TW201403679A - 半導體裝置及製造其之方法 - Google Patents
半導體裝置及製造其之方法 Download PDFInfo
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Abstract
本發明提供了一種具有針對金屬離子聚集的仿真主動區域的半導體裝置以及製造其之方法,其中該半導體裝置能夠防止由於金屬離子污染所致的裝置故障。該半導體裝置包括:在半導體基板中的隔離層所定義且以雜質離子佈植的主動區域,以及以雜質離子佈植的仿真主動區域,其中該仿真主動區域具有比在主動區域中的雜質的濃度還高的濃度,並且被配置為聚集金屬離子。
Description
本申請案宣告根據35 U.S.C.119(a)的2012年7月12日提交於韓國專利局的韓國申請案第10-2012-0076221號的優先權,其藉由參考方式將其全部內容併入於此。
本發明涉及一種半導體裝置和一種製造其之方法,更具體地,一種藉由形成用於聚集金屬離子的仿真主動區域以防止由於金屬離子污染所致的裝置故障的技術。
半導體積體電路的封裝技術中的三維(3D)堆疊技術已被開發,以減少電子裝置的尺寸,提高電子裝置的填充密度,並提高電子裝置的性能。3D堆疊封裝是一種堆疊具有相同的存儲容量的晶片的封裝,並通常稱作為堆疊晶片封裝。
堆疊晶片封裝技術具有由於簡化的製程和大規模生產所致的降低製造成本的優勢。然而,堆疊晶片封裝技術具有由於堆疊晶片的數量和晶片尺寸的增加所致的封裝內的電氣連接的空間缺乏的這樣的缺點。
也就是說,現有的堆疊晶片封裝被製造以具有一個結構,在該結構中,在複數個晶片在基板的晶片附著區域中配置的狀態下,各晶片的接合墊和基板的導電的電路圖案
透過導線電連接。因此,用於導線接合的空間和用於連接到導線的電路圖案的區是必要的,從而增加了半導體封裝的尺寸。
為了克服上述缺點,使用直通矽晶穿孔(TSV)的結構已被實施。在示範性封裝中,TSV被形成在晶片級的每個堆疊晶片中,然後晶片被堆疊在彼此的頂部且透過垂直TSV物理和電性連接。
然而,TSV被暴露以在諸如退火製程以及機械應力的隨後製程中加熱。當晶片被堆疊,接合製程可能會將半導體的下表面暴露於例如銅離子。然後離子可以遷移通過半導體以在主動區域中聚集。經聚集的金屬材料作為少數載子生成和複合中心而行動,導致漏電流,從而降低半導體封裝的電性特性。
一個以上的示範性實施例中係提供了一種具有用於金屬離子聚集的仿真主動區域的半導體裝置,以及製造其之方法。
根據示範性實施例的一態樣,提供了一種半導體裝置。半導體裝置可包括:複數個主動區域,其藉由在半導體基板中的隔離層所定義,並且以第一濃度的雜質離子佈植;以及仿真主動區域,其以高於第一濃度的雜質的第二濃度的雜質離子佈植,並且配置成聚集金屬離子。
在仿真主動區域中的經離子佈植的雜質的濃度是比在
主動區域中的雜質的濃度高至少1.2倍。當金屬離子是正離子時,在仿真主動區域中的雜質離子是P型,然而當金屬離子是負離子時,仿真主動區域中的雜質離子是N型。
P型雜質包括硼(B)並且N型雜質包括磷(P)或砷(As)。半導體裝置可以進一步包括形成在相對於仿真主動區域的第一側的第二側上的直通矽晶穿孔(TSV),其中TSV包括金屬離子。
仿真主動區域鄰近在外圍電路區中的主動區域。
半導體裝置可以進一步包括:位元線接觸,其設置在第一主動區域上;第一閘極,其設置在第二主動區域上;以及第二閘極,其設置在仿真主動區域上。
主動區域形成在仿真主動區域的第一和第二側處。形成在仿真主動區域的第一側上的主動區域係以N型雜質離子佈植,並且形成在仿真主動區域的第二側上的主動區域以P型雜質離子佈植。
形成在仿真主動區域的第一側上的主動區域包括N+接面區域,以及形成在仿真主動區域的第二側上的主動區域包括P+型區域。
根據示範性實施例的另一態樣,提供了一種製造半導體裝置的方法。該方法可以包括:形成藉由在半導體基板中的隔離層所定義的第一主動區域和複數個第二主動區域;將第一濃度的雜質離子佈植到第一主動區域;以及將第二濃度的雜質離子佈植到複數個第二主動區域。
將雜質離子佈植到複數個第二主動區域可以包括:將N
型雜質離子佈植到複數個第二主動區域的第一主動區域以形成N型阱;以及將P型雜質離子佈植到複數個第二主動區域的第二主動區域以形成P型阱。
該方法可以進一步包括在N型阱中佈植N型雜質離子以形成N+型接面區域;以及將P型雜質離子佈植至P型阱以形成P+型接面區域。
將雜質離子佈植至第一主動區域包括將N型雜質或P型雜質佈植到第一主動區域。P型雜質可以包括硼(B)並且N型雜質包括磷(P)或砷(As)。
該方法可以進一步包括在隔離層、第一主動區域和複數個第二主動區域的至少一者上依序堆疊多晶矽層、導電層、硬遮罩層,並且圖案化這些層以形成閘極結構。
該方法可以進一步包括在包含閘極結構的半導體基板上沉積層間絕緣層;蝕刻在複數個第二主動區域中的任何一者上的層間絕緣層,以形成位元線接觸孔;以及在位元線接觸孔中沉積導電材料。
該方法可以進一步包括在第一主動區域或複數個第二主動區域周圍形成直通矽晶穿孔(TSV)。
P型雜質離子被佈植在第一主動區域中。第二濃度是大於第二濃度至少1.2倍。根據本發明的示範性實施例的另一態樣,提供了一種半導體裝置。該半導體裝置可以包括:半導體基板,其包括主動區域和仿真主動區域;以及TSV,其貫通半導體基板。主動區域可以包括第一P型摻雜區域,並且仿真主動區域可以包括第二P型摻雜區域。第二摻雜
區域可以具有比第一P型摻雜區域的摻雜濃度還高的摻雜濃度。
第一摻雜區域和第二摻雜區域可以包括硼(B)摻雜的區域。
半導體基板可以進一步包括在主動區域和仿真主動區域之間配置的隔離層。
這些和其他特徵、態樣和實施例在下方名為“實施方式”的章節中描述。
在下文中,參照附圖示範性實施例將被更詳細的描述。
這裡所描述的示範性實施例參照了示範性實施例(和中間結構)的示意說明的橫截面說明。因此,作為例如製造技術及/或公差的結果的說明的形狀的變化是可以預期的。因此,示範性實施例不應該被解釋為限於這裡所說明的區域的特定形狀,但也可以包括例如由製造所致的形狀的偏差。在圖式中,為了清楚起見,可以誇大層和區域的長度和尺寸。在圖式中類似的參考符號表示相類似的元件。還應該理解的是,當層被稱作是在另一層或基板“上”時,它可以是直接在其他或基板上,或者也可以存在中間層。
在下文中,根據示範性實施例的一種半導體裝置及製造其之方法將參照圖1至圖2G而詳細描述。
圖1是說明根據示範性實施例的半導體裝置的橫截面
視圖。
根據一示範性實施例的半導體裝置包括:外圍電路區(i)和單元區域(ii)。在單元區域(ii)中,閘極119a形成在藉由在半導體基板101中的隔離層103a所定義的主動區域104上,並且N型雜質離子佈植到作為主動區域104的P型阱以形成N+型雜質佈植區域。位元線接觸形成在N+型雜質佈植區域上,並且位元線BL和金屬線M1和M2被形成為透過位元線接觸連接到N+型雜質佈植區域。
在外圍電路區域(i)中,藉由隔離層103所定義的以N型雜質離子佈植的主動區域105a、以P型雜質離子佈植的主動區域105b和以P型雜質離子佈植的仿真主動區域105c形成在半導體基板101上。在一實施例中,主動區域105b和仿真主動區域105c形成,使得佈植至仿真主動區域105c的雜質離子的濃度是高於佈植至主動區域105b和105a的雜質離子的濃度。
在實施例中,佈植到主動區域105b的P型雜質離子的濃度是3.0x1015/cm2至5.0x1016/cm2。實施例之間的特定類型和在主動區域中的離子的濃度可能會有所不同,這取決於例如半導體類型和半導體的面積。本發明並不限於特定的類型和在主動區域中的雜質離子的濃度。佈植至仿真主動區域105c的P型雜質離子的濃度是比佈植至主動區域105b的P型雜質離子的濃度高1.2倍和100倍之間。
用於形成堆疊晶片封裝的直通矽晶穿孔(TSV)200係形成在外圍電路區域(i)的一側處。圖1中所說明的示範
性實施例顯示了形成在外圍電路區域(i)的一側處的TSV 200,但在其它實施例中,TSV 200可以被形成在矽基板的任何部分上。在各種實施例中,TSV沉積在半導體中的固定間隔處,以均勻分佈在堆疊中的晶片之間的電力傳輸。
如上所討論的,仿真主動區域105c被摻雜以具有比相鄰的主動區域105b還高的雜質離子的濃度,並且可以相同類型的離子摻雜。因此,當銅離子污染物從TSV 200遷移時,銅離子被吸引和聚集在仿真主動區域105c中,從而防止在該位元線接觸處的故障。
聚集在仿真主動區域105c中的銅離子的原則現在將更加詳細的描述。
在半導體基板101中的矽(Si)是IV族元素,並且在填充可能為8個的外層價電子層中具有4個價電子。因此,在矽-矽(Si-Si)鍵中,每一個矽(Si)原子具有總共四個共價鍵,其中每個原子與其他原子的價電子層中的四個電子共享在外層價電子層中的四個電子。然而,身為III族元素的硼(B)具有三個價電子。在矽-硼(Si-B)鍵中,一個硼(B)原子形成針對三價的總共三個共價鍵。剩下的一個鍵不能形成共價鍵,因此,硼(B)是以來自矽(Si)的價電子單方面提供。換言之,硼離子創造在矽基質中的電洞。因此,在p型阱中的硼原子(B)具有負的離子(B-)狀態。
當正的銅離子(Cu++)被引入到包含帶負電荷的硼離子的基板時,正的銅離子可以被吸引到負的硼離子。如果電荷中的差異足夠大並且相鄰是足夠近的,帶正電的銅離
子(Cu++)遷移到帶負電荷的硼離子(B-)。
在一實施例中,在TSV和仿真主動區域之間的距離基於污染物的電荷和在仿真主動區域105c中的雜質濃度而確定。距離應是足夠於針對污染物的電荷和仿真主動區域互相作用。在其它實施例中,如果不知道精確的污染物的距離,仿真主動區域可被靠近主動區域來沉積,否則,可能有顯著的吸引污染物的風險。當仿真主動區域105c的雜質濃度和主動區域105b之間的差異較大時,仿真主動區域105c可以進一步遠離主動區域105b來沉積,然而如果雜質濃度之間的差異是小的,他們可以更靠近彼此來沉積。在一實施例中,主動區域105b和仿真主動區域105c的濃度差異和相鄰被確定,使得一種污染物被吸引到仿真主動區域105c而代替了主動區域105b。金屬離子透過上述的原則而被捕獲在以雜質摻雜的多晶矽層中。
圖1的實施例已經描述了具有以P型雜質佈植的仿真主動區域105b,以及聚集銅離子。然而,在其它實施例中,當銅離子以外的正金屬離子聚集時,仿真主動區域105b可以N型雜質摻雜。也就是說,在不同的實施例中,取決於待聚集的金屬離子的類型,不同種的雜質可以佈植至仿真主動區域。
圖2A到2G是說明製造根據示範性實施例的半導體裝置的方法的圖1的外圍電路區域(i)的放大的橫截面視圖。
如圖2A所示,在外圍電路區域(i)中,主動區域105a和105b以及仿真主動區域105c藉由在半導體基板101中的
隔離層103所定義。在一實施例中,仿真主動區域105c可以形成在主動區域105a和105b之間。
如圖2B所示,光阻圖案107形成在主動區域105a和105b和隔離層103上以暴露仿真主動區域105c。P型雜質透過離子佈植沉積到經暴露的仿真主動區域105c,以形成P型阱106。在各種實施例中,仿真主動區域105c中的雜質濃度可以比在後續製程中佈植的主動區域105b中的雜質濃度高1.2至100倍。
如圖2C所示,光阻圖案107隨後被移除。然後N型雜質藉由離子佈植佈植到主動區域105a,並且P型雜質被佈植到主動區域105b。
具體地,光阻層(未示出)形成在主動區域105b、仿真主動區域105c和隔離層103上,僅暴露主動區域105a。N型雜質佈植到主動區域105a以形成N型阱111a,然後N型雜質進一步被佈植到N型阱111a的上部以形成N+型離子佈植區域(N+型接面區域)111b,並且光阻層被移除。在一實施例中,N型雜質包括磷(P)或砷(As)。
接著,在光阻層(未示出)形成在主動區域105a、仿真主動區域105c和隔離層103上,僅暴露主動區域105b。P型雜質被佈植到主動區域105b以形成P型阱109a,然後P型雜質進一步佈植到P型阱109a的上部,以形成P+型離子佈植區域(P+型接面區域)109b。在一實施例中,將雜質離子佈植至主動區域105a和105b的製程可以以相反的順序執行。本發明並不受將離子佈植到主動區域105a和105b
或仿真主動區域105c的特定的順序所限制。
根據圖2D,閘極氧化物層(未示出)形成在主動區域105a和105b、仿真主動區域105c和隔離層103上。多晶矽層113、導電層115和用於閘極形成的硬遮罩層117依次堆疊在閘極氧化物層上。在一實施例中,多晶矽層113可以由多晶矽材料所形成。導電層115可由如鎢(W)、鈦(Ti)、鎳(Ni)、鋁(Al)或銅(Cu)的導電材料所形成。硬遮罩材料117可以由諸如氮化矽層Si3N4的氮化物的材料所形成。
如圖2E所示,進行蝕刻多晶矽層113、導電層115和硬遮罩層117使用作為蝕刻遮罩的光阻層(未顯示)來蝕刻,以形成閘極結構119。在圖中可以看出,閘極可以沉積在主動區域105a上方,並且閘極也可以沉積在仿真主動區域105c上方。在一實施例中,在主動區域105c上方沒有透過閘極的電性流動。
如圖2F所示,層間絕緣層121形成在包含閘極結構119的半導體基板的表面上,然後透過化學機械拋光(CMP)製程平面化。隨後,層間絕緣層121被蝕刻以暴露一部分的P+離子佈植區域109b,從而在離子佈植區域109b上方沉積位元線接觸孔123。在各種實施例中,層間絕緣層121可以包括氧化矽(SiO2)、硼磷矽酸鹽玻璃(boron phosphorus silicate glass,BPSG)、磷矽酸鹽玻璃(phosphorus silicate glass,PSG)、原矽酸四乙酯(tetra ethyl ortho silicate,TEOS)、未摻雜的矽酸鹽玻璃(undoped silicate glass,
USG)、旋塗式玻璃(spin on glass,SOG)、高密度等離子體(high density plasma,HDP)氧化物或是旋塗式介電質(spin on dielectric,SOD)。
如圖2G所示,將導電材料沉積以填充圖2F的位元線接觸孔123,從而形成位元線接觸125。
根據一示範性的製造半導體裝置的方法,包括比單元區域的主動區域還高的雜質離子的濃度的仿真主動區域105c形成在外圍電路區域中。諸如銅的被污染金屬離子被吸引到仿真主動區域,使得可以防止藉由諸如銅的被汙染金屬離子所致的在主動區域上的不利影響。
雖然示範性實施例已解釋關於移除由TSV所致的銅離子污染,其他實施例可以使用仿真主動區域以吸引源自其它來源的其他類型的污染物離子。進一步,可以根據特定類型的污染物而將不同類型的雜質(P型雜質或N型雜質)佈植至仿真主動區域。例如,當污染物是正的金屬離子時,將P型雜質佈植至仿真主動區域105c以形成P型阱。當被污染的金屬離子是負的離子時,將N型雜質佈植到仿真主動區域105c以形成N型阱。
上面的描述提供了一種結構和一種用於製造半導體的方法,其可具有一個以上的下述優點。
首先,在半導體裝置中的金屬離子污染物藉由仿真主動區域而聚集,防止不然將發生的裝置故障。
其次,從TSV引進的銅離子污染物藉由仿真主動區域而聚集。
雖然上面已經描述了某些實施例,這些實施例僅是做為本發明可以具體實現的方式的例子。因此,此處所描述的裝置和方法沒有根據所描述的實施例而限制。相反地,本文所述的系統和方法應該只受限於按照當採取結合上面的描述和附圖時所跟隨的申請專利範圍。
101‧‧‧基板
103‧‧‧隔離層
103a‧‧‧隔離層
104‧‧‧主動區域
105a‧‧‧主動區域
105b‧‧‧主動區域
105c‧‧‧仿真主動區域
106‧‧‧P型阱
107‧‧‧光阻圖案
109a‧‧‧P型阱
109b‧‧‧P+型離子佈植區域(P+型接面區域)
111a‧‧‧N型井
111b‧‧‧N+型離子佈植區域(N+型接面區域)
113‧‧‧多晶矽層
115‧‧‧導電層
117‧‧‧硬遮罩層
119‧‧‧閘極結構
119a‧‧‧閘極結構
121‧‧‧層間絕緣層
123‧‧‧位元線接觸孔
125‧‧‧位元線接觸
200‧‧‧直通矽晶穿孔(TSV)
本發明的揭露內容的標的中的上述和其它的態樣、特徵和優點將藉由結合附圖的下面詳細描述會更清楚地理解,其中:圖1是說明根據本發明的示範性實施例的半導體裝置的橫截面視圖;圖2A至2G是說明製造根據本發明的示範性實施例的半導體裝置的方法的橫截面視圖。
101‧‧‧基板
103‧‧‧隔離層
103a‧‧‧隔離層
104‧‧‧主動區域
105a‧‧‧主動區域
105b‧‧‧主動區域
105c‧‧‧仿真主動區域
106‧‧‧P型阱
109a‧‧‧P型阱
109b‧‧‧P+型離子佈植區域(P+型接面區域)
111a‧‧‧N型井
111b‧‧‧N+型離子佈植區域(N+型接面區域)
119‧‧‧閘極結構
119a‧‧‧閘極結構
121‧‧‧層間絕緣層
200‧‧‧直通矽晶穿孔(TSV)
Claims (20)
- 一種半導體裝置,包括:複數個主動區域,其藉由在半導體基板中的隔離層所定義,並且以第一濃度的雜質離子佈植;以及仿真主動區域,其以高於該第一濃度的雜質的第二濃度的雜質離子佈植,並且配置為聚集金屬離子。
- 根據申請專利範圍第1項的半導體裝置,其中在該仿真主動區域中的離子佈植的雜質的濃度是比在該主動區域中的雜質的濃度高至少1.2倍。
- 根據申請專利範圍第1項的半導體裝置,其中在該仿真主動區域中的雜質離子包括P型雜質或N型雜質。
- 根據申請專利範圍第1項的半導體裝置,其中當該金屬離子是正離子時,在該仿真主動區域中的雜質離子是P型,然而當該金屬離子是負離子時,在該仿真主動區域中的雜質離子是N型。
- 根據申請專利範圍第4項的半導體裝置,其中該P型雜質包含硼(B)並且該N型雜質包含磷(P)或砷(As)。
- 根據申請專利範圍第5項的半導體裝置,進一步包括形成在相對於該仿真主動區域的第一側的第二側上的直通矽晶穿孔(TSV),其中該TSV包含該金屬離子。
- 根據申請專利範圍第1項的半導體裝置,其中該仿真主動區域鄰近在外圍電路區中的主動區域。
- 根據申請專利範圍第1項的半導體裝置,進一步包括: 位元線接觸,其設置在第一主動區域上;第一閘極,其設置在第二主動區域上;以及第二閘極,其設置在該仿真主動區域上。
- 根據申請專利範圍第1項的半導體裝置,其中該主動區域形成在該仿真主動區域的第一和第二側處,其中形成在該仿真主動區域的第一側上的主動區域係以N型雜質離子佈植,並且形成在該仿真主動區域的第二側上的主動區域以P型雜質離子佈植。
- 根據申請專利範圍第9項的半導體裝置,其中形成在該仿真主動區域的第一側上的該主動區域包含N+接面區域,以及形成在該仿真主動區域的第二側上的該主動區域包含P+型區域。
- 一種製造半導體裝置的方法,該方法包括:形成藉由在半導體基板中的隔離層所定義的第一主動區域和複數個第二主動區域;將第一濃度的雜質離子佈植到該第一主動區域;以及將第二濃度的雜質離子佈植到該複數個第二主動區域。
- 根據申請專利範圍第11項的方法,其中將第二濃度的雜質離子佈植到該複數個第二主動區域包括:將N型雜質離子佈植到該複數個第二主動區域的第一主動區域以形成N型阱;以及將P型雜質離子佈植到該複數個第二主動區域的第二 主動區域以形成P型阱。
- 根據申請專利範圍第12項的方法,進一步包括:在該N型阱中佈植N型雜質離子以形成N+型接面區域;以及將P型雜質離子佈植至該P型阱中以形成P+型接面區域。
- 根據申請專利範圍第11項的方法,其中將雜質佈植至該第一主動區域包括將N型雜質或P型雜質佈植到該第一主動區域。
- 根據申請專利範圍第11項的方法,其中該仿真主動區域形成在外圍區域中。
- 根據申請專利範圍第11項的方法,進一步包括:在該隔離層、該第一主動區域和該複數個第二主動區域的至少一者上依序堆疊多晶矽層、導電層、硬遮罩層,並且圖案化這些層以形成閘極結構。
- 根據申請專利範圍第16項的方法,進一步包括:在包含該閘極結構的該半導體基板上沉積層間絕緣層;蝕刻在該複數個第二主動區域中的任何一者上的該層間絕緣層,以形成位元線接觸孔;以及在該位元線接觸孔中沉積導電材料。
- 根據申請專利範圍第11項的方法,進一步包括:在該第一主動區域或該複數個第二主動區域周圍形成直通矽晶穿孔(TSV)。
- 根據申請專利範圍第11項的方法,其中P型雜質離子被佈植在該第一主動區域中。
- 根據申請專利範圍第11項的方法,其中該第二濃度是大於該第二濃度至少1.2倍。
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