TW201401461A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW201401461A
TW201401461A TW102120256A TW102120256A TW201401461A TW 201401461 A TW201401461 A TW 201401461A TW 102120256 A TW102120256 A TW 102120256A TW 102120256 A TW102120256 A TW 102120256A TW 201401461 A TW201401461 A TW 201401461A
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passive device
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Shuo-Mao Chen
Der-Chyang Yeh
Li-Hsien Huang
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Taiwan Semiconductor Mfg
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Abstract

本發明提供一種半導體裝置，包括：一基板；一金屬墊，位於基板上；以及一鈍化保護層，部份位於金屬墊上。上述半導體裝置更包括一金屬柱，位於金屬墊上並電性連接至金屬墊；以及一被動裝置，包括一第一部份，與金屬柱齊高，其中被動裝置之第一部份係由相同於金屬柱的材料所組成。

Description

半導體裝置及其製造方法
本發明係有關於一種半導體裝置及其製造方法。
隨著半導體工藝的發展，半導體晶粒逐漸地變小。同時，必須整合更多的功能至半導體晶粒中。因此，在半導體晶粒中，必須有越來越多的輸入輸出(I/O)墊封裝於較小的範圍裡，且I/O墊的密度隨著時間快速的增加。因此，半導體晶粒的封裝變得更困難，其對封裝的產能造成不利的影響。
傳統的封裝技術可分成兩個類別。在第一類別中，在切割晶圓上的晶粒前進行封裝。這項封裝技術具有一些有利的特徵，例如高產能(throughput)與低成本。再者，底部封膠(underfill)或塑形(molding)元件的需求較少。然而，此封裝技術也有其缺點。如上述，晶粒的尺寸越來越小，僅可用扇入(fan-in)型封裝分別地封裝晶粒，其中各晶粒的I/O墊被限制到各個晶粒表面上的一個區域。在有限的晶粒範圍內，因為I/O墊之間距的限度，侷限了I/O墊的數量。若降低墊的間距，可能會存在焊錫橋(solder bridge)。此外，在固定球體尺寸的需求下，焊球具有一定的尺寸，這限制了在晶粒表面上可封裝的焊球數。
在另一類別的封裝中，封裝前從晶圓上切割晶 粒，且僅封裝“良品裸晶(known-good-dies)”。此封裝技術的一個有利特徵為形成扇出(fan-out)封裝的可能性，這代表晶粒上的I/O墊可被重新分佈(redistribute)至大於晶粒的範圍，因此，增加了封裝在晶粒表面上的I/O墊的數量。
本發明提供一種半導體裝置，包括：一基板；一金屬墊，位於基板上；一鈍化保護層，包括一部份位於金屬墊上；一金屬柱，位於金屬墊上並電性連接至金屬墊；以及一被動裝置，包括一第一部份與金屬柱齊高，其中被動裝置之第一部份係由相同於金屬柱的材料所組成。
本發明提供另一種半導體裝置，包括：一晶粒，包括：一半導體基板；一金屬墊，位於半導體基板上；一鈍化保護層，部份位於金屬墊上；以及一金屬柱，位於金屬墊上並延伸至鈍化保護層中；一塑形化合物，圍繞著(encircling)晶粒；一介電層，位於金屬柱、鈍化保護層、及塑形化合物之上；一後鈍化保護內連線線，位於介電層上，且其透過金屬柱與一導孔電性連接至金屬墊，導孔位於介電層中；以及一被動裝置，包括一第一部份位於鈍化保護層中以及一第二部份位於介電層上方。
本發明亦一種半導體裝置的製造方法，包括：形成一晶粒，其中晶粒之形成方法包括：形成一金屬墊於一半導體基板上；形成一鈍化保護層於半導體基板與金屬墊上；形成並電性連接一金屬柱至金屬墊上；以及在形成金屬柱的同時，形成一被動裝置之一第一部份；將晶粒貼附在一載體(carrier) 上；以及以一聚合物將晶粒塑形，其中聚合物圍繞著(encircle)晶粒。
20‧‧‧基板
22‧‧‧積體電路
24‧‧‧接合墊
26、28‧‧‧鈍化保護層
30、32‧‧‧金屬柱
28A、30A、32A、38A‧‧‧頂表面
36‧‧‧接著層
38‧‧‧塑形化合物
20B‧‧‧底表面
40‧‧‧介電層
34‧‧‧載體基板
42、44‧‧‧開口
46、50‧‧‧導孔
48‧‧‧後鈍化內連線
52‧‧‧後鈍化內連線元件
100‧‧‧晶粒
200‧‧‧積體被動裝置
300‧‧‧封裝體
第1~10圖係根據不同示範性實施例繪示出封裝體在製造的中間階段之剖面示意圖。
第11A-11B、12A-12B、13-14、15A-15B圖係根據實施例繪示出示範性積體被動裝置。
本說明書將根據第1~10圖敘述封裝體結構在不同的製造階段。以下將會配合圖式對本發明實施例作出詳述。本說明書儘可能地在圖式與說明書中使用相同的參考數字對應到相同或相似的部件。在圖式中，為了清楚及方便性，而擴大形狀及厚度。以下說明將特別針對本發明實施例之裝置或是其中元件的形成部分。可以理解的是未特別繪示或說明的元件可具有各種不同的型式。
本說明書全文中所提及關於”一實施例”的意思是指有關於本實施例中所提及特定的特徵(feature)、結構、或特色係包含於本發明的至少一實施例中。因此，本說明書全文中各處所出現的”一實施例中”用語所指的並不全然表示為相同的實施例。再者，特定的特徵、結構、或特色能以任何適當方式而與一或多個實施例作結合。可以理解的是以下的圖式並未依照比例繪示，而僅僅提供說明之用。
以下將敘述有關特定背景的實施例，即封裝體結 構包括整合被動裝置(integrated passive device,IPD)。亦適用於其它實施例，例如，需要額外的遮蔽層的封裝體結構。
請參照第1圖，其顯示晶粒100在製程的中間階段，包括基板20與接合墊24。基板20可為矽、鍺化矽、碳化矽、陶瓷基板、石英基板等、或上述之組合。基板20可包括大塊(bulk)矽、摻雜或未摻雜、或矽覆絕緣(silicon-on-insulator,SOI)基板的主動(active)層。可使用其他基板，包括多層(multi-layered)基板、梯度(gradient)基板、或混成定向(hybrid orientation)基板。
基板20可包括積體電路(integrated circuit)裝置22。此技藝人士應理解，可使用各種廣泛的積體電路裝置22(例如，電晶體、電容器、電阻器、或上述之組合等)以達成設計晶粒100的結構與功能上之需求。可使用任何適合的方法製造積體電路裝置22。
基板20亦可包括內連線(interconnect)結構(未顯示)。可在積體電路裝置22上形成內連線結構，內連線結構係設計用來連接不同的積體電路裝置22，以形成功能性電路。內連線結構可由介電層(例如，低介電常數材料)與導電層(例如，銅)交替形成，且可藉由任何適合的製程(例如，沉積、鑲嵌(damascene)、雙鑲嵌(dual damscene))形成。導電與介電層可包括金屬線與導孔(via)(未顯示)，以將積體電路裝置22電性連接至接合墊24。只有一部份的基板20繪示在圖中，如此將能充分的詳細敘述示範實施例。
在內連線結構上可形成接合墊24，且接合墊24與 內連線結構電性連接(未顯示)，以助於提供外部連線至積體電路裝置。接合墊24可包括鋁、銅、鎳等、或上述之組合。接合墊24的形成可透過使用沉積製程(例如，濺鍍)形成一材料層(未顯示)。之後，部份的材料層可透過適合的製程(例如微影遮罩(photolithographic masking)與蝕刻)移除而形成接合墊24。然而，可使用任何其他適合的製程形成接合墊24。接合墊24之厚度可介於約0.5~4 μm。
如第2圖所示，可在基板20與接合墊24之上形成第一鈍化保護層26。第一鈍化保護層26可由一或多種適合的介電材料製造，例如，氧化矽、氮化矽、低介電常數材料(例如，碳摻雜氧化物(carbon doped oxides))、極(extremely)低介電常數材料(例如，多孔碳摻雜二氧化矽(porous carbon doped silicon dioxide))、聚合物(例如，聚亞醯胺(polyimide))、防焊料(solder resist)、聚苯噁唑(polybenzoxazole,PBO))、苯並環丁烯(benzocyclobutene,BCB)、塑形化合物等、或上述之組合。可透過如化學氣相沉積(chemical vapor deposition,CVD)的製程形成第一鈍化保護層26，然而亦可使用任何合適的製程，且第一鈍化保護層26之後度介於約0.5~5 μm。一些實施例中，接合墊24之頂表面與第一鈍化保護層26之底表面本質上齊高。
第3圖繪示出在第一鈍化保護層26上之第二鈍化保護層的形成、在第一與第二鈍化保護層26與28中且電性連接至接合墊24之第一金屬柱(pillar)30的形成、以及在第一與第二鈍化保護層26與28中之第二金屬柱32的形成。在敘述中，第二金屬柱32又可的被稱為金屬柱重分佈線(pillar redistribution line,RDS)32。
在第一鈍化保護層上可形成第二鈍化保護層28。第二鈍化保護層28可由聚合物(例如，聚亞醯胺(polyimide))所組成。另外，第二鈍化保護層28可由相似於第一鈍化保護層26的材料所組成，例如，氧化矽、氮化矽、低介電常數材料、極(extremely)低介電常數材料、苯並環丁烯(benzocyclobutene,BCB)、聚苯噁唑(polybenzoxazole,PBO))等、或上述之組合。第二鈍化保護層28之厚度可介於約2~15 μm。
在形成第二鈍化保護層28之後，可在接合墊24上形成第一金屬柱(pillar)30，以透過第一及第二鈍化保護層26、28物理性與電性接觸到接合墊24。同時，可由形成第一金屬柱30的製程在第一鈍化保護層26上形成金屬柱重分佈線(RDL)32，以形成及/或連接到隨後形成的部份整合被動裝置(integrated passive device,IPD)200(在以下進一步討論)。
可藉由在第一與第二鈍化保護層26、28中形成開口進而形成第一金屬柱30與金屬柱RDL 32，開口可用，例如，蝕刻、研磨(milling)、雷射技術、或上述之組合等方式形成。可以保角(conformally)的方式在第二鈍化保護層28上與開口中沉積薄阻障(barrier)層(未顯示)，沉積的方式可包括CVD，原子層沉積(atomic layer deposition,ALD)等、或上述之組合。阻障層可包括氮化物或氮氧化物，例如氮化鈦、氮氧化鈦、氮化鉭、氮氧化鉭、氮化鎢、二氧化矽等、或上述之組合。可在薄阻障層上與開口中沉積導電材料。可由電化學電鍍(eletro-chemical plating)製程、CVD、ALD、物理氣相沉積 (physical vapor deposition,PVD)等、或上述之組合形成導電材料。導電材料可為銅、鎢、鋁、銀、金等、或上述之組合。接著，可圖案化導電材料以形成第一金屬柱30與金屬柱RDL 32。
在一實施例中，金屬柱30的頂表面30A大體上與第二鈍化保護層28之頂表面28A及金屬柱RDL 32之頂表面32A齊高。另一實施例中，金屬柱30之頂表面30A及/或金屬柱RDL 32之頂表面32A可低於第二鈍化保護層28之頂表面28A，且有薄薄的一部份的第二鈍化保護層28覆蓋著第一金屬柱30及/或金屬柱RDL 32。
第4圖繪示出將晶粒100固定至載體基板34。載體基板34可在隨後的加工步驟期間提供暫時的機械與結構支撐。可使用接著層36固定晶粒100至載體基板34。儘管只繪示出單一個晶粒100，本發明可有多個彼此相同的晶粒100置於載體基板34上。一實施例中，其中晶粒100包括基板20、及與基板20之底表面20B接觸的接著層36。一些實施例中，在相鄰的晶粒100之間留有間隔。在一實施例中，載體基板34可包括玻璃、氧化矽、氧化鋁等、或上述之組合。接著層可包括任何合適的接著劑，例如，紫外(ultraviolet,UV)膠，當暴露於紫外光時UV膠會失去其接著特性。
第5圖繪示出在晶粒100上塑形(molding)聚合物38。聚合物38可為塑形化合物，因此，儘管其可為其他材料所形成，以下仍可被稱為塑形化合物38。塑形化合物38可包括有機材料，例如環氧樹脂(epoxy)，其可填入晶粒100之間的間隔。塑形化合物38也覆蓋可晶粒100之頂表面。可進行硬化(curing) 製程以將塑形化合物38固化(solidify)。
又如第5圖所示，可在塑形化合物38上進行平坦化(planarization)製程(例如研磨(grinding))直到暴露出第一金屬柱30與金屬柱RDL 32，可能暴露出第二鈍化保護層28亦。因此，第二鈍化保護層28之頂表面28A、金屬柱30的頂表面30A大體上、金屬柱RDL 32之頂表面32A、塑形化合物38之頂表面38A大體上相互齊高。在本發明實施例中，其中第一金屬柱30及/或金屬柱RDL 32係嵌入(embedded)第二鈍化保護層28中，亦可研磨部份的第二鈍化保護層28。研磨後，在晶粒100上可能不再有塑形化合物38。在第5圖之結構的上視圖中，塑形化合物38可圍繞(encircled)晶粒100。
第6圖繪示出在塑形化合物38、第二鈍化保護層28、第一金屬柱30、及金屬柱RDL 32上方形成介電層40。介電層40可由一或多個合適的介電材料所形成，例如，氧化矽、氮化矽、低介電常數材料(例如，碳摻雜氧化物(carbon doped oxides))、極低介電常數材料(例如，多孔碳摻雜二氧化矽(porous carbon doped silicon dioxide))、聚合物(例如，聚亞醯胺(polyimide))、聚苯噁唑(polybenzoxazole,PBO))、苯並環丁烯(benzocyclobutene,BCB)等、或上述之組合。可透過如化學氣相沉積的製程形成介電層40，然而，可使用任何合適的製程。
形成介電層40之後，可形成穿透介電層40的開口40與44。開口42可形成於介電層40中以暴露出部份的金屬柱30。可藉由，例如，蝕刻、研磨(milling)、雷射技術、或上述之組合等方式形成開口42與44。可形成開口44以暴露出一或多 個部份的金屬柱RDL 32。一些實施例中，可同時形成開口42與44。
第7圖繪示出在開口42中形成導孔(via)46以及在開口44中形成導孔50。導孔46可在第一金屬柱30與隨後形成的後鈍化內連線(post-passivation interconnect,PPI)48(詳見第8圖)之間提供電性連接，而導孔50可在金屬柱RDL 32、後鈍化內連線48、以及後鈍化內連線元件52(詳見第8圖)之間提供電性連接。一實施例中，導孔46與50可包括銅、鎢、鋁、銀、金等、或上述之組合。一些實施例中，導孔46與50可包括上述的阻障層(關於第一金屬柱30與金屬柱RDL 32的段落)。一些實施例提供兩個以上的導孔50及一個以上的導孔46。第8圖繪示出在導孔46與50分別形成PPI 48與PPI元件52，導孔46與50分別電性連接著PPI 48與PPI元件52。一實施例中，儘管形成PPI 48與PPI元件52的材料必須不同於形成導孔46與50的材料，PPI 48與PPI元件52可包括相似於導孔46與50的材料，例如，銅、鎢、鋁、銀、金等、或上述之組合。可藉由形成光阻層54後將其圖案化，接著再形成PPI 48與PPI元件52，可藉由電化學電鍍製程、CVD、ALD、PVD等、或上述之組合形成PPI 48與PPI元件52。
第9圖繪示出在移除光阻層54後的示範性封裝體300，封裝體300包括積體被動裝置(IDP)200與晶粒100。金屬柱RDL 32、導孔50、及PPI元件52可組成IPD 200，IPD 200可為電阻器、電容器、電感器(inductor)、變壓器(transformer)、平衡器(balun)、帶線(strip line)、和共平面(co-planar)波導(waveguide)等。如第9圖所示，IPD 200可形成於晶粒100之上 並對準晶粒100。在另一實施例中，如第10圖的點狀矩形所示，IPD 200可形成於晶粒100與塑形化合物38兩者之上並對準兩者。一些實施例提供兩個以上的導孔50及一個以上的導孔46。如第11A、11B圖所示，一些實施例提供兩個或兩個以上的金屬柱RDL 32。
第11A~15B圖繪示出一些第9、10圖的示範性IPD 200。第11A~15B圖的IPD 200之製造方法可參照第1~10圖。每一IPD 200可有上導電層，上導電層包括PPI 48與PPI元件52、導孔46，而下導電層包括一或多個金屬柱RDL 32。一些IPD 200亦可包括一或多個導孔50，導孔50與導孔46位於同層。
第11A圖繪示出一示範性IPD 200之上視圖，IPD 200為金屬-氧化物-金屬(metal-oxide-metal,MOM)電容器。IPD 200包括第一多個電容指針(finger)48/52(上層)彼此內連線以形成電容器的一電容板，而第二多個電容指針32(下層)彼此內連線以形成電容器的另一電容板。第11B圖繪示出一示範性IPD 200之透視圖。第一多個電容指針48/52與第二多個電容指針32可透過部份的介電層40(未顯示於第11A圖與第11B圖中，請參照第9、10圖)彼此隔開，介電層40為電容絕緣體的一部份。
第12A圖與第12B圖根據一實施例繪示出IPD 200之透視圖，IPD 200為共平面波導。第12A圖中，IPD 200包括訊號線(PPI元件52中心)及在訊號線另一端的接地線(PPI元件52外圍)，訊號線與接地線互相平行。第12B圖中，訊號線與接電線可各自包括下部32、中部50、及上部52堆而形成厚導線。藉由堆疊32、50、及52可降低導線的電阻，因此，可提高第12B 圖中的共平面波導200之效能。
第13圖繪示出一示範性IPD 200之示意圖，IPD 200為微帶(micro-strip)導線，其包括作為接地板(ground plate)的金屬柱RDL 32以及作為訊號線的PPI元件52。訊號線與接地板可透過部份的介電層40(請參照第9、10圖)彼此隔開，介電層40為電容絕緣體的一部份。第14圖繪示出一示範性IPD 200之透視圖，IPD 200為帶線(strip line)且包括接合墊23、作為接地板的PPI元件52、金屬柱RDL 32、以及作為訊號線的第一金屬柱30。在此實施例中，接地板位於訊號線的上方與下方，並且接地板與訊號線由部份的介電層40及第一與第二鈍化保護層26、28彼此隔開。
第15A、15B圖繪示出一示範性IPD 200之透視圖，根據實施例，IPD 200為變壓器(transformer)或平衡器(balun)。第15A圖中，一或多個PPI元件52可作為變壓器或平衡器的線圈(coil)，且PPI 48及內(inner)線圈與金屬柱RDL 32內連線。第15B圖中，每一線圈可各自包括下部32、中部50、及上部52堆疊形成厚導線。藉由堆疊32、50、及52可降低導線的電阻，因此，可提高第15B圖中的變壓器或平衡器之效能。
藉由使用金屬柱RDL 32形成IPD 200，能更有效地利用封裝區域，且能改善IPD 200之效能。示範性IPD 200的形成不需要額外的遮罩(mask)與微影(lithography)步驟。再者，金屬柱RDL 32的使用可在封裝體300中容許新佈線的選擇，且金屬柱RDL 32可提供IPD 200或IPD 200下方虛置(dummy)金屬圖案的遮蔽。
然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。舉例來說，任何所屬技術領域中具有通常知識者可輕易理解此處所述的許多特徵、功能、製程及材料可在本發明的範圍內作更動。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
20‧‧‧基板
22‧‧‧積體電路
24‧‧‧接合墊
26、28‧‧‧鈍化保護層
30、32‧‧‧金屬柱
36‧‧‧接著層
38‧‧‧塑形化合物
40‧‧‧介電層
34‧‧‧載體基板
46、50‧‧‧導孔
48‧‧‧後鈍化內連線
52‧‧‧後鈍化內連線元件
100‧‧‧晶粒
200‧‧‧積體被動裝置
300‧‧‧封裝體

Claims (10)

  1. 一種半導體裝置，包括：一基板；一金屬墊，位於該基板上；一鈍化保護層，包括一部份位於該金屬墊上；一金屬柱，位於該金屬墊上並電性連接至該金屬墊；以及一被動裝置，包括一第一部份與該金屬柱齊高，其中該被動裝置之該第一部份係由相同於該金屬柱的材料所組成。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該被動裝置包括電阻器、電容器、誘導器(inductor)、變壓器(transformer)、共平面(co-planar)波導(waveguide)、帶線(strip-line)、或上述之組合。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該被動裝置之該第一部份包括一阻障(barrier)層、及位於該阻障層上方的一銅層。
  4. 如申請專利範圍第1項所述之半導體裝置，更包括一聚合物圍繞著該基板，且該聚合物與該基板齊高，其中該聚合物更包括有一部份與該金屬柱齊高，且其中該被動裝置包括一第二部份位於該聚合物上，且該第二部份對準該聚合物。
  5. 如申請專利範圍第4項所述之半導體裝置，更包括：一介電層，位於該金屬柱、該被動裝置之該第一部份、該鈍化保護層、與該聚合物上方；一第一導孔(via)，位於該介電層內；一後鈍化保護內連線(post-passivation interconnect,PPI) 線，位於該介電層上，其中該第一導孔係位於該PPI線與該金屬柱之間且該第一導孔互使該PPI線與該金屬柱內連線，且其中該被動裝置更包括一第三部份，與該PPI線齊高，其中該被動裝置之該第三部份係由相同於該PPI線的材料所形成；以及一第二導孔，位於該介電層中，其中該第二導孔係位於該被動裝置之該第一部份與該被動裝置之該第三部份之間且該第二導孔使該第三部份與該第一部份內連線，且其中該第二導孔包括該被動裝置的一第四部份。
  6. 一種半導體裝置，包括：一晶粒，包括：一半導體基板；一金屬墊，位於該半導體基板上；一鈍化保護層，部份位於該金屬墊上；一金屬柱，位於該金屬墊上並延伸至該鈍化保護層中；一塑形化合物，圍繞著(encircling)該晶粒；一介電層，位於該金屬柱、該鈍化保護層、及該塑形化合物之上；一後鈍化保護內連線線，位於該介電層上，且其透過該金屬柱與一導孔電性連接至該金屬墊，該導孔位於該介電層中；以及一被動裝置，包括一第一部份位於該鈍化保護層中以及一第二部份位於該介電層上方。
  7. 如申請專利範圍第6項所述之半導體裝置，其中該塑形化合 物包括：一底表面，與該半導體基板之一底表面齊高；以及一頂表面，與該鈍化保護層及該金屬柱之頂表面齊高。
  8. 一種半導體裝置的製造方法，包括：形成一晶粒，其中該晶粒之形成方法包括：形成一金屬墊於一半導體基板上；形成一鈍化保護層於該半導體基板與該金屬墊上；形成並電性連接一金屬柱至該金屬墊上；在形成該金屬柱的同時，形成一被動裝置之一第一部份；將該晶粒貼附在一載體(carrier)上；以及以一聚合物將該晶粒塑形，其中該聚合物圍繞著(encircle)該晶粒。
  9. 如申請專利範圍第8項所述之半導體裝置的製造方法，更包括：形成一介電層於該晶粒與該聚合物之上；形成多個第一開口於該介電層中，其中該些第一開口的其中之一暴露出該金屬柱，且其中該些第一開口的其中之一暴露出該被動裝置之該第一部份；形成一後鈍化保護內連線線於該介電層上，且該後鈍化保護內連線線透過該金屬柱與一第一導孔電性連接至該金屬墊，該第一導孔位於其中一個該些第一開口中；以及在形成該後鈍化保護內連線線的同時，形成該被動裝置的一第二部份於該介電層上。
  10. 如申請專利範圍第9項所述之半導體裝置的製造方法，其中 該被動裝置之該第二部份透過一第二導孔電性連接至該被動裝置的該第一部份，該第二導孔位於至少一個該些第一開口中。
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