TW201347122A - 晶片封裝體及其形成方法 - Google Patents

晶片封裝體及其形成方法 Download PDF

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TW201347122A
TW201347122A TW102116149A TW102116149A TW201347122A TW 201347122 A TW201347122 A TW 201347122A TW 102116149 A TW102116149 A TW 102116149A TW 102116149 A TW102116149 A TW 102116149A TW 201347122 A TW201347122 A TW 201347122A
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semiconductor substrate
chip package
layer
forming
conductive pad
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TW102116149A
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TWI529887B (zh
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Yu-Lung Huang
Tsang-Yu Liu
Shu-Ming Chang
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Xintec Inc
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Abstract

本發明一實施例提供一種晶片封裝體，包括：一半導體基底，具有一第一表面及一第二表面；一元件區，形成於該半導體基底之中；一介電層，設置於該半導體基底之該第一表面上；一導電墊結構，位於該介電層之中，且電性連接該元件區，該導電墊結構包括複數個導電墊層之堆疊結構；一支撐層，設置於該導電墊結構之一頂表面之上；以及一保護層，設置於該半導體基底之該第二表面上。

Description

晶片封裝體及其形成方法
本發明係有關於晶片封裝體及其形成方法，且特別是有關於以晶圓級封裝製程所形成之晶片封裝體。
電子產品持續有縮小化之需求。因此，晶片封裝體中之晶片的尺寸(例如，厚度)隨之縮小。
因此，業界亟需改良的晶片封裝技術以形成小晶片尺寸之晶片封裝體，並避免晶片於封裝製程中受損。
本發明一實施例提供一種晶片封裝體，包括：一半導體基底，具有一第一表面及一第二表面；一元件區，形成於該半導體基底之中；一介電層，設置於該半導體基底之該第一表面上；一導電墊結構，位於該介電層之中，且電性連接該元件區，該導電墊結構包括複數個導電墊層之堆疊結構；一支撐層，設置於該導電墊結構之一頂表面之上；以及一保護層，設置於該半導體基底之該第二表面上。
本發明一實施例提供一種晶片封裝體的形成方法，包括：提供一半導體基底，具有一第一表面及一第二表面，其中該半導體基底定義有至少一預定切割道，將該半導體基底劃分成複數個區域，該些區域分別形成有對應的一元件區，該半導體基底之該第一表面上，形成有一介電層，該介電層中具 有複數個導電墊結構，該些導電墊結構分別電性連接至對應的該元件區，且每一該些導電墊結構包括複數個導電墊層之堆疊結構；於每一該些導電墊結構之一頂表面上形成一支撐層；於該介電層上接合一承載基板；自該半導體基底之該第二表面薄化該半導體基底；在薄化該半導體基底之後，於該半導體基底之該第二表面上形成一保護層；於該保護層上設置一固定結構；在設置該固定結構後，移除該承載基板；在移除該承載基板後，於該介電層上設置一載體；在設置該載體後，移除該固定結構；以及沿著該至少一預定切割道進行一切割製程以於該載體上形成彼此分離之複數個晶片封裝體。
10‧‧‧晶片封裝體
100‧‧‧基底
101‧‧‧元件區
100a、100b‧‧‧表面
102‧‧‧介電層
104‧‧‧導電墊結構
104M1、104M2、104M3‧‧‧導電墊層
106‧‧‧支撐層
108‧‧‧黏著層
110‧‧‧承載基板
112‧‧‧孔洞
114、114a‧‧‧絕緣層
116‧‧‧導線層
118‧‧‧保護層
120‧‧‧導電凸塊
122‧‧‧固定結構
124‧‧‧載體
R‧‧‧區域
SC‧‧‧切割道
第1A-1K圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。
第2圖顯示根據本發明一實施例之晶片封裝體的剖面圖。
第3圖顯示根據本發明一實施例之半導體基底的上視圖。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於 一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。在圖式中，實施例之形狀或是厚度可能擴大，以簡化或是突顯其特徵。再者，圖中未繪示或描述之元件，可為所屬技術領域中具有通常知識者所知的任意形式。
本發明一實施例之晶片封裝體可用以封裝各種晶片。例如，其可用於封裝各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System；MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package；WSP)製程對影像感測元件、發光二極體(light-emitting diodes；LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)噴墨頭(ink printer heads)、或功率金氧半場效電晶體模組(power MOSFET modules)等半導體晶片進行封裝。
上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶 圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。在一實施中，上述切割後的封裝體係為一晶片尺寸封裝體(CSP；chip scale package)。晶片尺寸封裝體(CSP)之尺寸可僅略大於所封裝之晶片。例如，晶片尺寸封裝體之尺寸不大於所封裝晶片之尺寸的120%。
第1A-1K圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。如第1A圖所示，提供半導體基底100，其具有表面100a及表面100b。半導體基底100例如可為半導體晶圓，如矽晶圓。半導體基底100可定義有至少一預定切割道SC，其將半導體基底100劃分成複數個區域。第3圖顯示根據本發明一實施例之半導體基底的上視圖。如第3圖所示，半導體基底100可由所定義之預定切割道SC劃分成複數個區域R。區域R分別形成有對應的元件區101。元件區101中可形成有各種元件，例如(但不限於)光電元件，如影像感測元件。
半導體基底100之表面100a上，可形成有介電層102。介電層102中具有複數個導電墊結構104，這些導電墊結構104分別電性連接至對應的元件區101。在一實施例中，每一導電墊結構104可包括複數個導電墊層(例如，導電墊層104M1、104M2、及104M3)之堆疊結構。
接著，可於每一導電墊結構104之頂表面(例如，導電墊層104M3之頂表面)上形成支撐層106。在一實施例中，支撐層106之厚度係大於任一導電墊層(104M1、104M2、或104M3)之厚度。然應注意的是，在其他實施例中，支撐層106之厚度 可不大於任一導電墊層(104M1、104M2、或104M3)之厚度。支撐層106可增加導電墊結構104之結構強度。支撐層106之材質可例如為金屬、高分子、半導體、陶瓷、或前述之組合。支撐層106可位於介電層102之中。
在一實施例中，可移除部分的介電層102以使導電墊結構104之部分的頂表面露出。接著，可於露出的頂表面上形成材料層(例如，金屬層、高分子層、半導體層、陶瓷層、或前述之組合)以形成支撐層106。在另一實施例中，可在形成支撐層106之後，選擇性於支撐層106上形成介電材料以使介電層102具有大抵平坦的上表面。在一實施例中，支撐層106之材質相同於導電墊結構104。在另一實施例中，支撐層106之材質不同於導電墊結構104。在一實施例中，支撐層106可直接接觸導電墊結構104。支撐層106之面積可小於導電墊結構104之頂表面的面積。
接著，如第1B圖所示，於介電層102上接合承載基板110。例如，可以黏著層108將承載基板110接合於介電層102上。承載基板110例如為半導體基板、玻璃基板、高分子基板、金屬基板、或前述之組合。接著，以承載基板110為支撐，自半導體基底100之表面100b薄化半導體基底100。適合的薄化製程可包括機械研磨、化學機械研磨、蝕刻、或前述之組合。可將半導體基底100之厚度薄化至介於約50微米至約150微米之間。或者，薄化後之半導體基底100之厚度可介於約20微米至約250微米之間。
如第1C圖所示，接著可選擇性自半導體基底100之 表面100b移除部分的半導體基底100以形成朝導電墊結構104延伸之複數個孔洞112(其中，圖式僅顯示其中一孔洞112)。在一實施例中，可以蝕刻製程形成朝導電墊結構104延伸之孔洞112，其可露出導電墊結構104上之介電層102。接著，可進一步蝕刻移除所露出之介電層102而使導電墊結構104露出。在一實施例中，可透過蝕刻製程條件之調整，使孔洞112之側壁傾斜於半導體基底100之表面100b，且使孔洞112之接近表面100b的下口徑小於孔洞112之接近表面100a的上口徑。即，孔洞112之口徑可由洞口(鄰接表面100b處)朝孔洞112之底部遞增。然應注意的是，本發明實施例不限於此。在其他實施例中，孔洞112之側壁可大抵垂直於表面100b。或者，孔洞112之口徑可由洞口(鄰接表面100b處)朝孔洞112之底部遞減。以下之敘述，將以孔洞112之口徑可由洞口(鄰接表面100b處)朝孔洞112之底部遞增的情形為例。
如第1D圖所示，可於半導體基底100之表面100b及孔洞112之側壁上形成絕緣層114。絕緣層114可覆蓋表面100b、孔洞112之側壁、及導電墊結構104。在一實施例中，絕緣層114之厚度可由孔洞112之洞口(鄰接表面100b處)朝導電墊結構104遞減。
如第1E圖所示，為了後續形成與導電墊結構104電性連接之導線層，需移除孔洞112底部之絕緣層114而使導電墊結構104露出。在一實施例中，由於絕緣層114於孔洞112之洞口厚度較大，其本身可作為遮罩。因此，可在不於絕緣層114上另外設置圖案化遮罩的情形下，直接對絕緣層114進行蝕刻 製程而形成具有露出導電墊結構104之絕緣層114a。絕緣層114a之厚度係小於絕緣層114。由於絕緣層114於孔洞112底部處之厚度較薄，因此即使孔洞112底部處之導電墊結構104露出，孔洞112之側壁上仍有絕緣層114a保留。
接著，如第1F圖所示，於半導體基底100之表面100b上形成複數個導線層116(其中，圖式僅顯示其中一導線層116)。導線層116分別延伸於對應的孔洞112的側壁上而分別電性連接對應的導電墊結構104。在一實施例中，可於絕緣層114a上形成晶種層。接著，於晶種層上形成圖案化遮罩層以擋住不需形成導線層之區域。接著，於露出的晶種層上以電鍍、化鍍、或前述之組合沉積導電材料。接著，移除圖案化遮罩層，並進行蝕刻製程，使所沉積之導電材料薄化，並蝕刻移除原由圖案化遮罩層所覆蓋之晶種層而形成導線層116。
應注意的是，孔洞112與導線層116之形成並非必須。可透過其他的導電結構形成與導電墊結構104之電性連接。
接著，於半導體基底之表面100b上形成保護層118。在一實施例中，保護層118未將孔洞112填滿而留下孔洞。在另一實施例中，保護層118可將孔洞112完全填滿。在一實施例中，可移除部份的保護層118以形成露出導線層116之複數個開口。接著，可於露出之導線層116上形成穿過保護層118之導電凸塊120。導電凸塊120可電性接觸對應的導線層116。
如第1G圖所示，可於保護層118上設置固定結構122。在形成有導電凸塊120的實施例中，導電凸塊120可穿入固定結構122。固定結構122例如是UV膠帶。
如第1H圖所示，在設置固定結構122後，可移除承載基板110及黏著層108。
如第1I圖所示，在移除承載基板110後，可於介電層102上設置載體124。載體124例如為薄膜框載體，其具有UV膠帶，可黏附所形成之晶片封裝體。
如第1J圖所示，在設置載體124後，可移除固定結構122。在一實施例中，可對固定結構122照射光線(例如，UV光)以移除固定結構122。接著，可沿著預定切割道SC進行切割製程以於載體124上形成彼此分離之複數個晶片封裝體10。第2圖顯示根據本發明一實施例之晶片封裝體的剖面圖，其顯示類似於第1J圖之結構。
如第1K圖所示，在一實施例中，可將晶片封裝體10自載體124取下。例如，可切穿載體124而取下晶片封裝體10。在一實施例中，可預先對載體124之相應於切割道SC的部分照射UV光，接著切穿載體124。載體124可包括UV膠帶，於照射UV光後，可硬化而易於切割。接著，可移除晶片封裝體10上之殘餘UV膠帶。晶片封裝體10可包括半導體基底100，其具有表面100a及表面100b、形成於半導體基底100中之元件區101、設置於半導體基底100之表面100a上之介電層102、位於介電層102中且電性連接元件區101之導電墊結構104、設置於導電墊結構104之頂表面上之支撐層106、以及設置於半導體基底100之表面100b上之保護層118。
在本發明實施例中，晶片封裝體10中之半導體基底100因運作需求而薄化。在此情形下，所形成之支撐層106可 增加導電墊結構104之結構強度，可避免薄化後之晶片封裝體10受損。此外，在一實施例中，由於孔洞112之口徑自洞口朝導電墊結構104遞增，可至少減少一道絕緣層之圖案化製程。除了製程成本與時間可減少外，還能減少形成晶片封裝體10所需之製程(包含運送)，可有效減低晶片封裝體10於製程過程中受損之風險。
本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧晶片封裝體
100‧‧‧基底
101‧‧‧元件區
100a、100b‧‧‧表面
102‧‧‧介電層
104‧‧‧導電墊結構
106‧‧‧支撐層
112‧‧‧孔洞
114a‧‧‧絕緣層
116‧‧‧導線層
118‧‧‧保護層
120‧‧‧導電凸塊

Claims (22)

  1. 一種晶片封裝體，包括：一半導體基底，具有一第一表面及一第二表面；一元件區，形成於該半導體基底之中；一介電層，設置於該半導體基底之該第一表面上；一導電墊結構，位於該介電層之中，且電性連接該元件區，該導電墊結構包括複數個導電墊層之堆疊結構；一支撐層，設置於該導電墊結構之一頂表面之上；以及一保護層，設置於該半導體基底之該第二表面上。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該支撐層直接接觸該導電墊結構之該頂表面。
  3. 如申請專利範圍第1項所述之晶片封裝體，其中該支撐層之面積小於該導電墊結構之該頂表面的面積。
  4. 如申請專利範圍第1項所述之晶片封裝體，其中該支撐層之材質包括金屬。
  5. 如申請專利範圍第1項所述之晶片封裝體，更包括一導電凸塊，該導電凸塊設置於該半導體基底之該第二表面上，且穿過該保護層，其中該導電凸塊電性連接該導電墊結構。
  6. 如申請專利範圍第5項所述之晶片封裝體，更包括：一孔洞，自該半導體基底之該第二表面朝該導電墊結構延伸；一導線層，設置於該孔洞之側壁上，且電性連接該導電墊結構及該導電凸塊；以及 一絕緣層，設置於該導線層與該半導體基底之間。
  7. 如申請專利範圍第6項所述之晶片封裝體，其中該孔洞之接近該第二表面的一下口徑小於該孔洞之接近該第一表面的一上口徑。
  8. 如申請專利範圍第1項所述之晶片封裝體，其中該半導體基底之一厚度介於50微米至150微米之間。
  9. 如申請專利範圍第1項所述之晶片封裝體，其中該支撐層位於該介電層之中。
  10. 如申請專利範圍第1項所述之晶片封裝體，其中該介電層具有大抵平坦之一上表面。
  11. 如申請專利範圍第1項所述之晶片封裝體，其中該支撐層之厚度大於任一該些導電墊層之厚度。
  12. 一種晶片封裝體的形成方法，包括：提供一半導體基底，具有一第一表面及一第二表面，其中該半導體基底定義有至少一預定切割道，以將該半導體基底劃分成複數個區域，該些區域分別形成有對應的一元件區，該半導體基底之該第一表面上，形成有一介電層，該介電層中具有複數個導電墊結構，該些導電墊結構分別電性連接至對應的該元件區，且每一該些導電墊結構包括複數個導電墊層之堆疊結構；於每一該些導電墊結構之一頂表面上形成一支撐層；於該介電層上接合一承載基板；自該半導體基底之該第二表面薄化該半導體基底；在薄化該半導體基底之後，於該半導體基底之該第二表面 上形成一保護層；於該保護層上設置一固定結構；在設置該固定結構後，移除該承載基板；在移除該承載基板後，於該介電層上設置一載體；在設置該載體後，移除該固定結構；以及沿著該至少一預定切割道進行一切割製程以於該載體上形成彼此分離之複數個晶片封裝體。
  13. 如申請專利範圍第12項所述之晶片封裝體的形成方法，其中形成該支撐層的步驟包括：移除部分的該介電層以使每一該些導電墊結構之部分的該頂表面露出；以及於露出的該些頂表面上形成一材料層以形成該些支撐層。
  14. 如申請專利範圍第13項所述之晶片封裝體的形成方法，更包括在形成該些支撐層之後，於該些支撐層上形成一介電材料以使該介電層具有一大抵平坦的上表面。
  15. 如申請專利範圍第12項所述之晶片封裝體的形成方法，更包括於該半導體基底之該第二表面上設置複數個導電凸塊，其中該些導電凸塊穿過該保護層，且分別電性連接該對應的該些導電墊結構。
  16. 如申請專利範圍第15項所述之晶片封裝體的形成方法，其中該些導電凸塊穿入該固定結構。
  17. 如申請專利範圍第15項所述之晶片封裝體的形成方法，更包括：在薄化該半導體基底之後，且在形成該保護層之前，自該 半導體基底之該第二表面移除部分的該半導體基底以形成朝該些導電墊結構延伸之複數個孔洞；於該半導體基底之該第二表面及該些孔洞之側壁上形成一絕緣層；以及於該半導體基底之該第二表面上形成複數個導線層，該些導線層分別延伸於對應的該些孔洞的側壁上而分別電性連接對應的該些導電墊結構。
  18. 如申請專利範圍第17項所述之晶片封裝體的形成方法，其中在形成該些導電凸塊之後，該些導電凸塊分別電性接觸對應的該些導線層。
  19. 如申請專利範圍第17項所述之晶片封裝體的形成方法，該孔洞之接近該第二表面的一下口徑小於該孔洞之接近該第一表面的一上口徑。
  20. 如申請專利範圍第12項所述之晶片封裝體的形成方法，其中移除該固定結構之步驟包括對該固定結構照射一UV光線。
  21. 如申請專利範圍第12項所述之晶片封裝體的形成方法，更包括將該些晶片封裝體自該載體取下。
  22. 如申請專利範圍第12項所述之晶片封裝體的形成方法，其中該支撐層之厚度大於任一該些導電墊層之厚度。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105895613A (zh) * 2015-02-16 2016-08-24 精材科技股份有限公司 晶片封装体及其制造方法
TWI634625B (zh) * 2015-11-13 2018-09-01 台灣積體電路製造股份有限公司 晶片封裝體及其形成方法
US10615220B2 (en) 2015-03-31 2020-04-07 Hamamatsu Photonics K.K. Semiconductor device and manufacturing method thereof
TWI702655B (zh) * 2016-04-13 2020-08-21 日商濱松赫德尼古斯股份有限公司 半導體裝置及其製造方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8987851B2 (en) * 2012-09-07 2015-03-24 Mediatek Inc. Radio-frequency device package and method for fabricating the same
TWI566353B (zh) * 2013-08-21 2017-01-11 精材科技股份有限公司 半導體結構及其製造方法
CN109742064B (zh) * 2015-04-27 2021-06-11 精材科技股份有限公司 晶片封装体及其制造方法
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CN107507815A (zh) * 2016-06-14 2017-12-22 中芯国际集成电路制造(上海)有限公司 焊垫结构及csp封装方法
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US20210246015A1 (en) * 2020-02-06 2021-08-12 Advanced Semiconductor Engineering, Inc. Sensor device package and method for manufacturing the same
US20210335660A1 (en) * 2020-04-24 2021-10-28 Nanya Technology Corporation Semiconductor structure having void between bonded wafers and manufacturing method tehreof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7294565B2 (en) * 2003-10-01 2007-11-13 International Business Machines Corporation Method of fabricating a wire bond pad with Ni/Au metallization
US20100206737A1 (en) * 2009-02-17 2010-08-19 Preisser Robert F Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv)
JP5535765B2 (ja) * 2009-06-01 2014-07-02 日本特殊陶業株式会社 セラミックコンデンサの製造方法
TWI473223B (zh) * 2009-08-19 2015-02-11 Xintec Inc 晶片封裝體及其製造方法
US8779452B2 (en) * 2010-09-02 2014-07-15 Tzu-Hsiang HUNG Chip package
US8742564B2 (en) * 2011-01-17 2014-06-03 Bai-Yao Lou Chip package and method for forming the same
US9553040B2 (en) * 2012-03-27 2017-01-24 Mediatek Inc. Semiconductor package

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105895613A (zh) * 2015-02-16 2016-08-24 精材科技股份有限公司 晶片封装体及其制造方法
TWI607539B (zh) * 2015-02-16 2017-12-01 精材科技股份有限公司 晶片封裝體及其製造方法
US10615220B2 (en) 2015-03-31 2020-04-07 Hamamatsu Photonics K.K. Semiconductor device and manufacturing method thereof
US10622403B2 (en) 2015-03-31 2020-04-14 Hamamatsu Photonics K.K. Semiconductor device manufacturing method
US10622402B2 (en) 2015-03-31 2020-04-14 Hamamatsu Photonics K.K. Semiconductor device
TWI634625B (zh) * 2015-11-13 2018-09-01 台灣積體電路製造股份有限公司 晶片封裝體及其形成方法
US10269717B2 (en) 2015-11-13 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method for chip package
TWI702655B (zh) * 2016-04-13 2020-08-21 日商濱松赫德尼古斯股份有限公司 半導體裝置及其製造方法

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