TW201340313A - 鰭式場效電晶體及形成鰭式場效電晶體之應力結構的方法 - Google Patents

鰭式場效電晶體及形成鰭式場效電晶體之應力結構的方法 Download PDF

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TW201340313A
TW201340313A TW101129465A TW101129465A TW201340313A TW 201340313 A TW201340313 A TW 201340313A TW 101129465 A TW101129465 A TW 101129465A TW 101129465 A TW101129465 A TW 101129465A TW 201340313 A TW201340313 A TW 201340313A
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field effect
layer
effect transistor
fin field
superlattice layer
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TWI478335B (zh
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Yi-Jing Lee
You-Ru Lin
Cheng-Tien Wan
Cheng-Hsien Wu
Chih-Hsin Ko
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Taiwan Semiconductor Mfg
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Abstract

一種鰭式場效電晶體，包括一超晶格層和應變層(strained layer)，超晶格層係被一基底支撐，應變層位於超晶格層上，且提供一閘極通道，超晶格層係提供閘極通道應力。在一實施例中，超晶格層係由堆疊不同的矽鍺合金或堆疊其它III-V族半導體材料形成。

Description

鰭式場效電晶體及形成鰭式場效電晶體之應力結構的方法
本發明係有關於一種半導體元件及其製造方法，特別是有關於一種鰭式場效電晶體及其製造方法。
半導體元件係用於許多電子元件，例如電腦、手機或其它電子元件。半導體元件包括積體電路，其中積體電路係藉由沉積許多型態的材料薄膜，且圖案化材料薄膜，形成於半導體晶圓上。積體電路包括場效電晶體(field effect transistor，簡稱FET)，場效電晶體例如為金氧半導體場效電晶體(MOSEFT)。
半導體工業之目標之一是持續的微縮尺寸和增加各場效電晶體的速度。為達到此目標，鰭式場效電晶體(fin field effect transistor，簡稱FinFET)或多閘極電晶體會使用次32奈米之電晶體節點技術。舉例來說，鰭式場效電晶體不僅改善了面積密度，也改善了閘極控制通道的能力。
在最近這幾年中，鰭式場效電晶體係包括應力結構(stressor)以改善效能。在一些情形下，應力結構係經由單層磊晶製程，使用矽鍺(SiGe)成長製程形成。應力結構可使用高鍺百分比之矽鍺，或進行高溫退火製程釋力(relax)。漸變鍺百分比之矽鍺磊晶層可用來提供應變。
根據上述，本發明提供一種鰭式場效電晶體，包括：一超晶格(superlattice)層，被一基底支撐；一應變層(strained layer)位於超晶格層上，且提供一閘極通道，超晶格層係提 供閘極通道應力。
本發明另提供一種鰭式場效電晶體，包括：一超晶格(superlattice)層，被一基底支撐；一淺溝槽隔離區，密封超晶格層；一應變層(strained layer)位於超晶格層上，且提供一閘極通道，超晶格層係提供閘極通道應力；及一閘極堆疊，形成於應變層上方。
本發明另一種形成鰭式場效電晶體之應力結構(stressor)的方法，包括：建構一超晶格(superlattice)層於一基底上；及形成一應變層(strained layer)於超晶格層上，應變層提供一閘極通道，超晶格層係提供閘極通道應力。
為讓本發明之特徵能更明顯易懂，下文特舉實施例，並配合所附圖式，作詳細說明如下：
以下詳細討論實施本發明之實施例。可以理解的是，實施例提供許多可應用的發明概念，其可以較廣的變化實施。所討論之特定實施例僅用來發明使用實施例的特定方法，而不用來限定發明的範疇。
本揭示在以下的文字敘述會描述較佳的實施範例(亦即鰭式場效電晶體(FinFET)或金氧半導體(MOS)場效電晶體)，然而，本發明亦可應用於其它積體電路、電子結構或其它類似的元件。
第1圖顯示一鰭式場效電晶體元件10之三維立體圖。鰭式場效電晶體(FinFET)元件10包括提供張應變至閘極通道之閘極應力結構，其係減少或消除發射堆疊錯誤 (emitting stacking fault)，提供有效的磊晶釋力，且可用作一虛擬基底。如第1圖所示，鰭式場效電晶體(FinFET)元件10包括一基底12、一超晶格(superlattice)層14(或稱超晶格結構)、一應變層16和一閘極堆疊18。
第1圖的基底12可由矽或其它適合的半導體材料形成。如圖所示，基底12一般位於淺溝槽隔離(shallow trench isolation，簡稱STI)區20下，如此基底12可以支撐淺溝槽隔離區20。在一實施例中，基底12鰭部分係向上突出至淺溝槽隔離區20中。
請再參照第1圖，超晶格層14一般是以基底12支撐。在一實施例中，如第1圖所示，超晶格層14係位於基底12之鰭部分22上。在另一實施例中，超晶格層14可建構於基底12之頂部表面上，而不是鰭部分22上。如以下將會更詳盡描述的，超晶格層14用作鰭式場效電晶體(FinFET)元件10之閘極應力結構。
超晶格層14一般是以交錯的方式堆疊不同的半導體材料形成。如第1圖所示，超晶格層14包括一第一半導體材料24和一第二半導體材料26，在一實施例中，各第一和第二半導體材料24、26係以矽鍺合金形成。在一實施例中，各第一和第二半導體材料24、26係以III-V族半導體材料形成。在一實施例中，超晶格層14係完全的或大體上的鑲嵌於(或密封於)STI區20中。
請再參照第1圖，應變層16一般是由半導體材料形成。如第1圖所示，應變層16是從一第三半導體材料28形成。在一實施例中，第三半導體材料28是以矽鍺合金形 成。在一實施例中，第三半導體材料28是以III-V族半導體材料形成。在一實施例中，應變層16完全位於STI區20上方。換句話說，應變層16突出於STI區20上方。在一實施例中，第一和第三半導體材料24、28是由相同的半導體材料形成(例如相同的矽鍺合金)。
閘極堆疊18一般係形成於應變層16上方。如第1圖所示，閘極堆疊18係形成於部分之STI區20上方，沿著應變層16之頂部和側壁表面，且位於STI區20之相對應部分上。在一實施例中，閘極堆疊18大體上或完全的密封應變層16。在一實施例中，閘極堆疊18是由例如犧牲氧化層、高介電常數介電層和金屬層形成。
閘極堆疊18之介電部分可包括各種材料，例如氧化鉿(HfO2)、氧化鋯(ZrO2)或其它適合之高介電常數材料(亦即介電常數高於二氧化矽之材料)。應產品的速度和應用的需求，閘極堆疊18可選擇各種適合的厚度。在一實施例中，閘極堆疊18是由多晶矽形成。在一實施例中，閘極堆疊可由其它適合的金屬和介電材料形成。
請參照第2圖，揭示鰭式場效電晶體(FinFET)元件10更多的元件單元，例如鰭式場效電晶體元件10包括源極/汲極接觸30、鄰接閘極堆疊18之間隙壁32和一硬式罩幕34。如圖所示，源極/汲極接觸30係鑲嵌於應變層16中。源極/汲極接觸30亦位於鰭式場效電晶體(FinFET)元件10之閘極通道36(亦即電晶體通道)的相對側。在一實施例中，源極/汲極接觸30另可具有其它的定向或配置。
第1圖之閘極通道36係被超晶格層14施加應力(亦即 使超晶格層14於閘極通道36產生應力)。在一實施例中，超晶格層14產生拉應力於例如n通道NMOS矽鍺閘極通道36。在其它的實施例中，超晶格層14可以適合之材料或製程形成，以於閘極通道36產生其它型態的應力。在一實施例中，超晶格層14可提供壓應力至閘極通道36。除了提供應力至閘極通道36外，超晶格層14亦可抑制或防止發射堆疊錯誤(emitting stacking fault)。超晶格層14實際上提供堆疊錯誤鬆弛的磊晶(provide stacking fault free epitaxy)和有效的磊晶釋力(effective exitaxy relaxation)。在一實施例中，超晶格層14可視為虛擬基底閘極應力結構(virtual substrate gate stressor)。
請再參照第2圖，硬式罩幕層34係形成於閘極堆疊18下，在一實施例中，硬式罩幕層34是高介電常數材料形成。如第2圖所示，閘極間隙壁32係以其下之應變層16支撐。此外，各閘極間隙壁32係設置於源極/汲極接觸30和硬式罩幕層34之間。在一實施例中，閘極間隙壁32另可具有其它的定向或配置。在一實施例中，硬式罩幕層34、閘極間隙壁32或兩者可包括氧化物、氮化物、氮氧化物、高介電常數材料，例如Ta2O、Al203、HfO、SiTiO3、HfSiO、HfSiON、ZrSiON和上述之組合。
請參照第3圖，一穿透式電子顯微鏡照片38描繪鰭式場效電晶體(FinFET)元件10數個相鄰的鰭40。如圖所示，各鰭40包括一應變層16，位於(或堆疊於)超晶格層14上方。在一實施例中，超晶格層14係沉積於基底12之V形溝槽42中(或被V形溝槽支撐)。在一實施例中，超晶格層 14嚙合(engage)基底12之(111)表面44。
第4圖顯示第3圖之鰭式場效電晶體元件10之一個鰭40的穿透式電子顯微鏡照片。如第4圖所示，位於基底12上之超晶格層14係以交錯之矽鍺合金形成。在一實施例中，超晶格層14係以9個彼此堆疊之560℃ SiGe0.25和640℃ SiGe0.75形成。在一實施例中，可以更多或更少的材料帶(band)彼此堆疊或形成於另一層上。如第4圖所示，位於超晶格層14上的應變層16係由560℃ SiGe0.25形成。在一實施例中，其它半導體材料(例如III-V族半導體材料)(具有其它熔點，例如400℃和700℃之間)，可用來形成應變層16和超晶格層14(或混合入應變層16和超晶格層14)。
請參照第5圖，其顯示第3圖之鰭40應變分析的圖表48，如第5圖所示，圖表之垂直軸(y軸)提供相對於矽之晶格匹配百分比(Si%)50，此外，圖表48之水平軸(X軸)提供鰭40之位置。位置52代表沿著水平距離的點，而不是量測的特定單位(例如奈米)。如圖表48中各資料點54所揭示，位於位置0和位置60間全部鰭40相對於矽之晶格匹配百分比50係約在1和2之間。
第6圖揭示形成第1圖所示之鰭式場效電晶體元件10的方法56。在方塊58中，超晶格層14係建構於基底12上。在方塊60中，應變層16係形成於超晶格層14上。應變層16係提供閘極通道36應力(閘極通道36係以超晶格層14施加應力)。換句話說，超晶格層14係用作應力結構。
一種鰭式場效電晶體，包括：一超晶格(superlattice)層，被一基底支撐；一應變層(strained layer)位於超晶格層 上，且提供一閘極通道，超晶格層係提供閘極通道應力。
一種鰭式場效電晶體，包括：一超晶格(superlattice)層，被一基底支撐；一淺溝槽隔離區，密封超晶格層；一應變層(strained layer)位於超晶格層上，且提供一閘極通道，超晶格層係提供閘極通道應力；及一閘極堆疊，形成於應變層上方。
一種形成鰭式場效電晶體之應力結構(stressor)的方法，包括：建構一超晶格(superlattice)層於一基底上；及形成一應變層(strained layer)於超晶格層上，應變層提供一閘極通道，超晶格層係提供閘極通道應力。
雖然本發明之較佳實施例說明如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧鰭式場效電晶體元件
12‧‧‧基底
14‧‧‧超晶格層
16‧‧‧應變層
18‧‧‧閘極堆疊
20‧‧‧淺溝槽隔離區
22‧‧‧鰭部分
24‧‧‧第一半導體材料
26‧‧‧第二半導體材料
28‧‧‧第三半導體材料
30‧‧‧源極/汲極接觸
32‧‧‧間隙壁
34‧‧‧硬式罩幕
36‧‧‧閘極通道
38‧‧‧穿透式電子顯微鏡照片
40‧‧‧鰭
42‧‧‧V形溝槽
44‧‧‧表面
48‧‧‧圖表
50‧‧‧相對於矽晶格匹配
52‧‧‧位置
54‧‧‧資料點
56‧‧‧方法
58‧‧‧方塊
60‧‧‧方塊
第1圖顯示本發明一實施例具有超晶格層作為閘極通道應例結構之鰭式場效電晶體元件的三維立體圖。
第2圖顯示第1圖鰭式場效電晶體元件之剖面圖。
第3圖顯示一穿透電子顯微鏡影像，揭示類似於第1圖之鰭式場效電晶體元件之數個相鄰的鰭。
第4圖顯示穿透電子顯微鏡影像，揭示第3圖單一鰭之剖面。
第5圖顯示第3圖鰭應力分析之圖表。
第6圖顯示製作第1圖鰭式場效電晶體元件之流程圖。
10‧‧‧鰭式場效電晶體元件
12‧‧‧基底
14‧‧‧超晶格層
16‧‧‧應變層
18‧‧‧閘極堆疊
20‧‧‧淺溝槽隔離區
22‧‧‧鰭部分
24‧‧‧第一半導體材料
26‧‧‧第二半導體材料
28‧‧‧第三半導體材料

Claims (10)

  1. 一種鰭式場效電晶體，包括：一超晶格(superlattice)層，被一基底支撐；以及一應變層(strained layer)位於該超晶格層上，且提供一閘極通道，該超晶格層係提供該閘極通道應力。
  2. 如申請專利範圍第1項所述之鰭式場效電晶體，其中該超晶格層包括一第一矽鍺合金和一第二矽鍺合金。
  3. 如申請專利範圍第1項所述之鰭式場效電晶體，其中該超晶格層包括一第一III-V族半導體材料和一第二III-V族半導體材料。
  4. 如申請專利範圍第1項所述之鰭式場效電晶體，其中該超晶格層係位於該基底之一V形溝槽中。
  5. 如申請專利範圍第1項所述之鰭式場效電晶體，其中該超晶格層嚙合(engage)該基底之(111)表面。
  6. 如申請專利範圍第1項所述之鰭式場效電晶體，其中該超晶格層係鑲嵌於一淺溝槽隔離(STI)區中，且該應變層係突出(project)於該淺溝槽隔離區上。
  7. 如申請專利範圍第1項所述之鰭式場效電晶體，其中該應變層係以一閘極堆疊密封(encapsulate)。
  8. 一種形成鰭式場效電晶體之應力結構(stressor)的方法，包括：建構一超晶格(superlattice)層於一基底上；以及形成一應變層(strained layer)於該超晶格層上，該應變層提供一閘極通道，該超晶格層係提供該閘極通道應力。
  9. 如申請專利範圍第8項所述之形成鰭式場效電晶體 之應力結構的方法，更包括以交錯之第一III-V族半導體材料和第二III-V族半導體材料建構該超晶格層。
  10. 如申請專利範圍第8項所述之形成鰭式場效電晶體之應力結構的方法，更包括以交錯堆疊一第一矽鍺合金和一第二矽鍺合金建構該超晶格層。
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US20150162447A1 (en) 2015-06-11
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