TW201320201A - Method for manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

An objective of this invention is to provide a manufacturing method of SGT, which is a gate-last process, allowing parasitic capacitance between gate wiring and substrate to be reduced, and to provide a resultant SGT structure thereof. For attaining the above-described objective, this invention includes: a first step of forming a fin-shaped silicon layer on a silicon substrate, forming a first insulation film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on an upper part of the fin-shaped silicon layer; a step of implanting an impurity in an upper part of the pillar-shaped silicon layer, an upper part of the fin-shaped silicon layer and a lower part of the pillar-shaped silicon layer to form a diffusion layer after the above-described step; a step of creating a gate insulation film, a polysilicon gate electrode and a polysilicon gate wiring after the above-described step; a step of forming a silicide on an upper part of the diffusion layer on the upper part of the fin-shaped after the above-described step; a step of depositing an inter-layered insulation film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring after the above-described step; and a step of forming a contact after the above-described step.

Description

Semiconductor device manufacturing method and semiconductor device

The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device.

In semiconductor integrated circuits, in particular, integrated circuits using MOS transistors are constantly moving toward higher integration. Along with the above-described high integration, the MOS transistor used therein is also continuously fined to the nano-region. With the gradual miniaturization of the MOS transistor, there has been a problem that it is difficult to suppress the leakage current, and it is impossible to reduce the occupied area of the circuit in order to secure the required amount of current. In order to solve such problems, SGT (surrounding) in which a source, a gate, and a drain are disposed in a vertical direction with respect to a substrate and a gate surrounds the columnar semiconductor layer has been proposed. A gate transistor (around a gate transistor) (for example, Patent Document 1, Patent Document 2, and Patent Document 3).

By using a metal because the gate electrode does not use polysilicon, it is possible to suppress the depletion and reduce the resistance of the gate electrode. However, the step after forming the metal gate must be a manufacturing step that often takes into account metal contamination due to the metal gate.

In addition, in the conventional MOS transistor, in order to balance the metal gate process and the high-temperature process, a metal gate-gate formation process (non-patent) for forming a metal gate after a high-temperature process is used in an actual product. Document 1). After the polysilicon is used as a gate, after the interlayer insulating film is deposited, the polysilicon gate is exposed by chemical mechanical polishing, and the polysilicon gate is etched to deposit metal. Therefore, in order to also take care of the metal gate process in the SGT And high-temperature process, it must be used in the high-temperature process to form a metal gate after the metal gate formation process. In the SGT, since the upper portion of the columnar layer is located at a position higher than the gate, it is necessary to develop countermeasures in order to use the metal gate process.

Further, in order to reduce the parasitic capacitance between the gate wiring and the substrate, the first insulating film is used in the conventional MOS transistor. For example, a FINFET (Fin Field-effect transistor, FN Field Effect Transistor, Non-Patent Document 2) is formed by forming a first insulating film around one fin-shaped semiconductor layer and etching back the first insulating film. The film exposes the fin-shaped semiconductor layer to reduce parasitic capacitance between the gate wiring and the substrate. Therefore, in the SGT, it is necessary to use the first insulating film in order to reduce the parasitic capacitance between the gate wiring and the substrate. In the SGT, in addition to the fin-shaped semiconductor, there is a columnar semiconductor layer, so it is necessary to develop countermeasures for forming the columnar semiconductor layer.

[Previous Technical Literature] (Patent Literature)

(Patent Document 1): Japanese Patent Laid-Open No. 2-71556

(Patent Document 2): Japanese Patent Publication No. 2-188966

(Patent Document 3): Japanese Patent Laid-Open No. 3-145761

(Non-patent literature)

(Non-Patent Document 1): IEDM2007 IEDM2007 K. Mistry et. al, pp 247-250

(Non-Patent Document 2): IEDM2010 CC. Wu, et. al, 27.1.1-27.1.4.

Accordingly, an object of the present invention is to provide a SGT manufacturing method and a result thereof for reducing the parasitic capacitance between a gate wiring and a substrate and forming a process after the gate.

A method of manufacturing a semiconductor device according to the present invention includes: forming a fin-shaped germanium layer on a germanium substrate, forming a first insulating film around the fin-shaped germanium layer, and forming a columnar germanium layer on an upper portion of the fin-shaped germanium layer; a first step; the diameter of the columnar layer is the same as the width of the fin layer, and after the first step, the upper portion of the columnar layer, the upper portion of the fin layer, and the lower portion of the columnar layer a second step of forming a diffusion layer by implanting impurities; a third step of forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring after the second step; the gate insulating film covering the columnar crucible In the periphery and the upper portion of the layer, the polysilicon gate electrode covers the gate insulating film, and the upper surface of the polysilicon gate after the polysilicon gate electrode and the polysilicon gate wiring are formed on the diffusion layer above the columnar layer a higher position of the gate insulating film; and a fourth step of forming a germanide on the upper portion of the diffusion layer in the upper portion of the finned layer after the third step; After the fourth step, an interlayer insulating film is deposited to expose the polysilicon gate electrode and the polysilicon gate wiring, and after etching the polysilicon gate electrode and the polysilicon gate wiring, metal is deposited to form a metal gate electrode and a metal gate. In a fifth step of the pole wiring, the metal gate wiring extends in a direction orthogonal to the finned layer connected to the metal gate electrode, and after the fifth step, a sixth step of forming a contact portion, the pillar The diffusion layer on the upper portion of the crucible layer is directly connected to the contact portion.

Further, a first resist for forming a fin-shaped germanium layer is formed on the germanium substrate, and the germanium substrate is etched to form the fin-shaped germanium layer to remove the first resist; and the first layer is deposited around the fin-shaped layer The insulating film etches back the first insulating film to expose an upper portion of the fin-shaped germanium layer, forms a second resist so as to be orthogonal to the fin-shaped germanium layer, and etches the fin-shaped germanium layer to remove the second resist Thereby, the columnar tantalum layer is formed such that the portion in which the fin-shaped tantalum layer and the second resist are orthogonal to each other is the columnar tantalum layer.

In addition, the fin-shaped enamel layer formed on the ruthenium substrate, the first insulating film formed around the fin-shaped ruthenium layer, and the columnar ruthenium layer formed on the upper portion of the fin-shaped ruthenium layer are stacked. In the second oxide film, a first nitride film is formed on the second oxide film, and the first nitride film is etched and left in a side wall shape to implant impurities. A diffusion layer is formed on the upper portion of the columnar layer and the upper portion of the fin layer, and the first nitride film and the second oxide film are removed to perform heat treatment.

Further, the present invention includes a fin-shaped germanium layer formed on the germanium substrate, a first insulating film formed around the fin-shaped germanium layer, and a columnar germanium layer formed on the upper portion of the fin-shaped germanium layer; a diffusion layer of a lower portion of the ruthenium layer and a lower portion of the columnar ruthenium layer; and a structure of a diffusion layer formed on an upper portion of the columnar ruthenium layer, forming a gate insulating film, and depositing polysilicon to planarize the polysilicon The upper surface of the polysilicon is planarized so as to be higher than the gate insulating film on the diffusion layer on the upper portion of the columnar layer, and the second nitride film is deposited to form a polysilicon gate electrode and The third resist of the polysilicon gate wiring etches the second nitride film, etches the polysilicon to form the polysilicon gate electrode and the polysilicon gate wiring, and etches the gate insulating film to remove the third resist.

Further, the third nitride film is deposited, the third nitride film is etched and left in a side wall shape, and a metal is deposited to form a germanide on the upper portion of the diffusion layer on the upper portion of the fin layer.

Further, the fourth nitride film is deposited, the interlayer insulating film is deposited and planarized, and the polysilicon gate electrode and the polysilicon gate wiring are exposed, and the polysilicon gate electrode and the polysilicon gate wiring are removed, and the polysilicon is originally stored. A portion of the gate electrode and the polysilicon gate wiring is buried with a metal, and the metal is etched to expose a gate insulating film on the diffusion layer on the upper portion of the columnar layer to form a metal gate electrode and a metal gate wiring.

Further, the semiconductor device of the present invention has: a fin-shaped germanium layer formed on the germanium substrate; a first insulating film formed around the fin-shaped germanium layer; a columnar germanium layer formed on the fin-shaped germanium layer; wherein the diameter of the columnar germanium layer is a diffusion layer formed on the upper portion of the fin-shaped layer and the lower portion of the columnar layer; a diffusion layer formed on an upper portion of the columnar layer; formed on the upper portion of the fin layer a telluride on the upper portion of the diffusion layer; a gate insulating film formed around the columnar layer; a metal gate electrode formed around the gate insulating film; extending over and connected to the metal gate electrode a metal gate wiring in a direction in which the fin-shaped germanium layer is orthogonal; a contact portion formed on the diffusion layer formed on the upper portion of the columnar tantalum layer; a diffusion layer formed on an upper portion of the columnar tantalum layer and the contact portion Direct connection.

According to the present invention, it is possible to provide an SGT structure in which a method of manufacturing a SGT for reducing a parasitic capacitance between a gate wiring and a substrate and forming a gate after the gate and a result thereof.

Since the fin-shaped tantalum layer, the first insulating film, and the columnar tantalum layer formation system are based on a conventional FINFET manufacturing method, they can be easily formed.

In addition, in the past, a telluride was formed on the upper portion of the columnar layer, but many The deposition temperature of the wafer is higher than the temperature at which the germanide is formed, so the germanide must be formed after the formation of the polysilicon gate.

Therefore, if a telluride is to be formed on the upper portion of the mast, it is necessary to open a hole in the upper portion of the polysilicon gate electrode after forming the polysilicon gate, and form a germanium on the sidewall of the hole to form a germanium compound. The hole is buried in the insulating film, and there is a disadvantage that the number of processes is increased. Therefore, a diffusion layer is formed before the formation of the polysilicon gate electrode and the polysilicon gate wiring, and the columnar layer is covered by the polysilicon gate electrode, and only A telluride is formed on the upper portion of the finned layer, whereby a polysilicon is used as a gate, and after the interlayer insulating film is deposited, the polysilicon gate electrode is exposed by chemical mechanical polishing, and the polysilicon gate is etched, and the metal is deposited. Since the manufacturing method of the metal gate is conventionally formed, the metal gate SGT can be easily formed.

Hereinafter, the manufacturing steps for forming the SGT structure according to the embodiment of the present invention will be described with reference to Figs. 2 to 42.

First, a method of forming a fin-shaped tantalum layer on a tantalum substrate, forming a first insulating film around the fin-shaped tantalum layer, and forming a columnar tantalum layer on the upper portion of the fin-shaped tantalum layer is shown. As shown in FIG. 2, a first resist 102 for forming a fin-shaped germanium layer is formed on the germanium substrate 101.

As shown in FIG. 3, the germanium substrate 101 is etched to form a fin-shaped germanium layer 103. In this example, a fin layer is formed by using a resist as a mask, but a hard mask such as an oxide film or a nitride film may be used.

As shown in Fig. 4, the first resist 102 is removed.

As shown in FIG. 5, the first insulation is deposited around the finned layer 103. Film 104. As the first insulating film, an oxide film obtained by high-density plasma or an oxide film obtained by low-pressure chemical vapor deposition can also be used.

As shown in Fig. 6, the first insulating film 104 is etched back to expose the upper portion of the fin-shaped germanium layer 103. Up to now, it has been produced in the same manner as the fin-shaped layer of Patent Document 2.

As shown in FIG. 7, the second resist 105 is formed to be orthogonal to the fin-shaped germanium layer 103. The portion of the fin-shaped layer 103 that is orthogonal to the resist 105 is a portion that becomes a columnar layer. Since a linear resist can be used, the possibility of the resist falling down after patterning is low, and it becomes a stable precess.

As shown in Fig. 8, the fin layer 103 is etched. A portion of the finned layer 103 orthogonal to the second resist 105 is a columnar layer 106. Therefore, the diameter of the columnar layer 106 is the same as the width of the fin layer. On the other hand, a columnar layer 106 is formed on the upper portion of the finned layer 103, and a structure of the first insulating film 104 is formed around the fin layer 103.

As shown in Fig. 9, the second resist 105 is removed.

Next, a method for forming a diffusion layer by implanting impurities into the upper portion of the columnar ruthenium layer and the upper portion of the fin-shaped ruthenium layer and the lower portion of the columnar ruthenium layer in order to form a gate electrode is shown. As shown in Fig. 10, the second oxide film 107 is deposited to form the first nitride film 108. Thereafter, since the upper portion of the columnar layer is covered by the gate insulating film and the polysilicon gate electrode, a diffusion layer is formed on the upper portion of the columnar layer before being covered.

As shown in Fig. 11, the first nitride film 108 is etched and left as a sidewall.

As shown in Fig. 12, impurities such as arsenic, phosphorus, or boron are implanted, a diffusion layer 110 is formed on the upper portion of the columnar layer, and diffusion layers 109 and 111 are formed on the upper portion of the fin layer 103.

As shown in Fig. 13, the first nitride film 108 and the second oxide film 107 are removed.

The heat treatment was carried out as shown in Fig. 14. The diffusion layers 109 and 111 on the upper portion of the fin-shaped germanium layer 103 are in contact with each other to form the diffusion layer 112. In order to form "gate after formation" by the above steps, impurities are implanted into the upper portion of the columnar layer and the upper portion of the fin layer and the lower portion of the columnar layer to form diffusion layers 110 and 112.

Next, in order to form "gate after formation", a method of manufacturing a polysilicon gate electrode and a polysilicon gate wiring by polysilicon is shown. In order to form the "gate after the gate", it is necessary to expose the polysilicon gate electrode and the polysilicon gate wiring by chemical mechanical polishing after the interlayer insulating film is deposited. Therefore, it is necessary to use a columnar layer which is not caused by chemical mechanical polishing. The way the upper part is exposed.

As shown in Fig. 15, the gate insulating film 113 is formed, and the polysilicon 114 is deposited and planarized. The upper surface of the planarized polysilicon is higher than the gate insulating film 113 above the diffusion layer 110 on the upper portion of the columnar layer 106. Therefore, in order to form the "gate after the gate", after the interlayer insulating film is deposited, the polysilicon gate and the polysilicon gate wiring are exposed by chemical mechanical polishing, so that the columnar shape is not caused by chemical mechanical polishing. The way the upper part of the enamel layer is exposed.

Further, the second nitride film 115 is deposited. The second nitride film 115 is a film that prevents germanium formation on the upper portion of the polysilicon gate electrode and the polysilicon gate wiring when a germanide is formed on the upper portion of the fin layer.

As shown in Fig. 16, a third resist 116 for forming a polysilicon gate electrode and a polysilicon gate wiring is formed. It is preferable that the portion to be the gate wiring is orthogonal to the fin-shaped layer 103. This is to reduce the parasitic capacitance between the gate wiring and the substrate.

As shown in Fig. 17, the second nitride film 115 is etched.

As shown in Fig. 18, the polysilicon 114 is etched to form a polysilicon gate electrode 14a and a polysilicon gate wiring 114b.

As shown in Fig. 19, the gate insulating film 113 is etched.

As shown in Fig. 20, the third resist 116 is removed.

In the above procedure, a method of manufacturing a polysilicon gate electrode and a polysilicon gate wiring by polysilicon is shown in order to form "gate after formation". The upper surface of the polysilicon after forming the polysilicon gate electrode 114a and the polysilicon gate wiring 114b is higher than the gate insulating film 113 on the diffusion layer 110 on the upper portion of the columnar layer 106.

Next, a method of producing a telluride is shown on the upper portion of the finned layer. It is characterized in that no germanide is formed on the diffusion layer 110 on the upper portion of the polysilicon gate electrode 114a and the polysilicon gate wiring 114b and the upper portion of the columnar layer 106. If a telluride is to be formed on the diffusion layer 110 on the upper portion of the columnar layer 106, the manufacturing steps will be increased.

As shown in Fig. 21, the third nitride film 117 is deposited.

As shown in Fig. 22, the third nitride film 117 is etched and remains in a side wall shape.

As shown in Fig. 23, a metal such as nickel (Ni) or cobalt (Co) is deposited, and a telluride 118 is formed on the upper portion of the diffusion layer 112 on the upper portion of the fin-shaped layer 103. this When the polysilicon gate electrode 114a and the polysilicon gate wiring 114b are covered by the third nitride film 117 and the second nitride film 115, the diffusion layer 110 on the columnar layer 106 is composed of a gate insulating film 113 and a polysilicon. Since the gate electrode 114a and the polysilicon gate wiring 114b are covered, no germanide is formed.

The method for producing a telluride is formed on the upper portion of the fin-shaped layer by the above steps.

Next, after the interlayer insulating film is deposited, a polysilicon gate electrode and a polysilicon gate wiring are exposed by chemical mechanical polishing, and a polysilicon gate electrode and a polysilicon gate wiring are etched, and a metal gate is deposited.

As shown in Fig. 24, the fourth nitride film 140 is deposited to protect the germanide 118.

As shown in Fig. 25, the interlayer insulating film 119 is deposited and planarized by chemical mechanical polishing.

As shown in Fig. 26, the polysilicon gate electrode 114a and the polysilicon gate wiring 114b are exposed by chemical mechanical polishing.

As shown in Fig. 27, the polysilicon gate electrode 114a and the polysilicon gate wiring 114b are etched. It is preferred to use wet etching.

The metal 120 is deposited and planarized as shown in Fig. 28, and the metal 120 is buried in a portion having the polysilicon gate electrode 114a and the polysilicon gate wiring 114b. It is preferred to use atomic layer stacking.

As shown in Fig. 29, the metal 120 is etched to expose the gate insulating film 113 on the diffusion layer 110 on the upper portion of the columnar layer 106. A metal gate electrode 120a and a metal gate wiring 120b are formed. After showing the accumulation of interlayer insulating film, borrow A manufacturing method in which a polysilicon gate is exposed by chemical mechanical polishing, and a gate of a metal is deposited after etching a polysilicon gate.

Next, a manufacturing method for forming a contact is shown. Since the diffusion layer 110 on the upper portion of the columnar layer 106 is not formed with a germanide, the contact portion and the diffusion layer 110 on the upper portion of the columnar layer 106 are directly connected. As shown in Fig. 30, the interlayer insulating film 121 is deposited and planarized.

As shown in Fig. 31, a fourth resist 122 for forming a contact hole is formed in the upper portion of the columnar layer 106.

As shown in Fig. 32, the interlayer insulating film 121 is etched to form a contact hole 123.

As shown in Fig. 33, the fourth resist 122 is removed.

As shown in Fig. 34, a fifth resist 124 for forming a contact hole is formed on the metal gate wiring 120b and the fin-shaped germanium layer 103.

As shown in Fig. 35, the interlayer insulating films 121 and 119 are etched to form contact holes 125 and 126.

As shown in Fig. 36, the fifth resist 124 is removed.

As shown in Fig. 37, the nitride film 140 and the gate insulating film 113 are etched to expose the germanide 118 and the diffusion layer 110.

As shown in Fig. 38, metal is deposited to form contact portions 143, 127, 128. The manufacturing method for forming the contact portion is shown by the above steps. Since the diffusion layer 110 on the upper portion of the columnar layer 106 is not formed with a germanide, the contact portion 127 is directly connected to the diffusion layer 110 on the upper portion of the columnar layer 106.

Next, a manufacturing method for forming a metal wiring layer is shown.

As shown in Fig. 39, metal 129 is deposited.

As shown in Fig. 40, sixth resists 130, 131, and 132 for forming metal wiring are formed.

As shown in Fig. 41, the metal 129 is etched to form metal wirings 133, 134, and 135.

As shown in Fig. 42, the sixth resists 130, 131, 132 are removed.

The manufacturing method for forming the metal wiring layer is shown by the above steps.

The results of the above production method are shown in Fig. 1.

The structure has the following structure: a fin-shaped germanium layer 103 is formed on the substrate 101; a first insulating film 104 is formed around the fin-shaped germanium layer 103; and a columnar germanium layer 106 is formed on the fin-shaped germanium layer 103; The diameter of the columnar layer 106 is the same as the width of the fin layer 103; the diffusion layer 112 is formed on the upper portion of the fin layer 103 and the lower portion of the columnar layer 106; and the diffusion layer 110 is formed in the columnar layer An upper portion of 106; a germanide 118 formed on an upper portion of the diffusion layer 112 on the upper portion of the fin-shaped germanium layer 103; a gate insulating film 113 formed around the columnar layer 106; and a metal gate electrode 120a formed on the gate a periphery of the insulating film; a metal gate wiring 120b extending in a direction orthogonal to the fin-shaped germanium layer 103 connected to the metal gate electrode 120a; and a contact portion 127 formed on the diffusion layer 110; and the diffusion layer 110 is in contact with The portion 127 is a directly connected structure.

According to the above description, it is possible to provide an SGT structure in which the SGT manufacturing method and the result thereof are formed by reducing the parasitic capacitance between the gate wiring and the substrate, and forming a process after the gate.

101‧‧‧矽 substrate

102‧‧‧Resist

103‧‧‧Finned layer

104‧‧‧1st insulating film

105‧‧‧Resist

106‧‧‧ Columnar layer

107‧‧‧Oxide film

108‧‧‧Members that impede the implantation of impurities

109‧‧‧Diffusion layer

110‧‧‧Diffusion layer

111‧‧‧Diffusion layer

112‧‧‧Diffusion layer

113‧‧‧gate insulating film

114‧‧‧Polysilicon

114a‧‧‧Polysilicon gate electrode

114b‧‧‧Polysilicon gate wiring

115‧‧‧ nitride film

116‧‧‧Resist

117‧‧‧ nitride film

118‧‧‧ Telluride

119‧‧‧Interlayer insulating film

120‧‧‧Metal

120a‧‧‧Metal gate electrode

120b‧‧‧Metal gate wiring

121‧‧‧Interlayer insulating film

122‧‧‧Resist

123‧‧‧Contact hole

124‧‧‧Resist

125‧‧‧Contact hole

126‧‧‧Contact hole

127‧‧‧Contacts

128‧‧‧Contacts

129‧‧‧Metal

130‧‧‧Resist

131‧‧‧Resist

132‧‧‧Resist

133‧‧‧Metal wiring

134‧‧‧Metal wiring

135‧‧‧Metal wiring

140‧‧‧ nitride film

143‧‧‧Contacts

Fig. 1(a) is a plan view showing a semiconductor device of the present invention. Fig. 1(b) is a cross-sectional view taken along line X-X' of Fig. 1(a). Fig. 1(c) is a cross-sectional view taken along line Y-Y' of Fig. 1(a).

Fig. 2(a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 2(b) is a cross-sectional view taken along line X-X' of Fig. 2(a). Fig. 2(c) is a cross-sectional view taken along line Y-Y' of Fig. 2(a).

Fig. 3(a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 3(b) is a cross-sectional view taken along line X-X' of Fig. 3(a). Fig. 3(c) is a cross-sectional view taken along line Y-Y' of Fig. 3(a).

Fig. 4(a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 4(b) is a cross-sectional view taken along line X-X' of Fig. 4(a). Fig. 4(c) is a cross-sectional view taken along line Y-Y' of Fig. 4(a).

Fig. 5(a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 5(b) is a cross-sectional view taken along line X-X' of Fig. 5(a). Fig. 5(c) is a cross-sectional view taken along line Y-Y' of Fig. 5(a).

Fig. 6(a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 6(b) is a cross-sectional view taken along line X-X' of Fig. 6(a). Fig. 6(c) is a cross-sectional view taken along line Y-Y' of Fig. 6(a).

Fig. 7(a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 7(b) is a cross-sectional view taken along line X-X' of Fig. 7(a). Figure 7 (c) It is a sectional view of the Y-Y' line of Fig. 7(a).

Fig. 8(a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 8(b) is a cross-sectional view taken along line X-X' of Fig. 8(a). Fig. 8(c) is a cross-sectional view taken along line Y-Y' of Fig. 8(a).

Fig. 9(a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 9(b) is a cross-sectional view taken along line X-X' of Fig. 9(a). Fig. 9(c) is a cross-sectional view taken along line Y-Y' of Fig. 9(a).

Fig. 10 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 10(b) is a cross-sectional view taken along line X-X' of Fig. 10(a). Fig. 10(c) is a cross-sectional view taken along line Y-Y' of Fig. 10(a).

Fig. 11(a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 11(b) is a cross-sectional view taken along line X-X' of Fig. 11(a). Fig. 11(c) is a cross-sectional view taken along line Y-Y' of Fig. 11(a).

Fig. 12 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 12(b) is a cross-sectional view taken along line X-X' of Fig. 12(a). Fig. 12(c) is a cross-sectional view taken along line Y-Y' of Fig. 12(a).

Fig. 13(a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 13(b) is a cross-sectional view taken along line X-X' of Fig. 13(a). Fig. 13(c) is a cross-sectional view taken along line Y-Y' of Fig. 13(a).

Fig. 14(a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 14(b) is a cross-sectional view taken along line X-X' of Fig. 14(a). Fig. 14(c) is a cross-sectional view taken along line Y-Y' of Fig. 14(a).

Fig. 15(a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 15(b) is a cross-sectional view taken along line X-X' of Fig. 15(a). 15th Figure (c) is a cross-sectional view taken along line Y-Y' of Figure 15 (a).

Fig. 16(a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 16(b) is a cross-sectional view taken along line X-X' of Fig. 16(a). Fig. 16(c) is a cross-sectional view taken along line Y-Y' of Fig. 16(a).

Fig. 17 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 17(b) is a cross-sectional view taken along line X-X' of Fig. 17(a). Fig. 17 (c) is a cross-sectional view taken along line Y-Y' of Fig. 17 (a).

Fig. 18(a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 18(b) is a cross-sectional view taken along line X-X' of Fig. 18(a). Fig. 18(c) is a cross-sectional view taken along line Y-Y' of Fig. 18(a).

Fig. 19 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 19(b) is a cross-sectional view taken along line X-X' of Fig. 19(a). Fig. 19(c) is a cross-sectional view taken along line Y-Y' of Fig. 19(a).

Fig. 20 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 20(b) is a cross-sectional view taken along line X-X' of Fig. 20(a). Fig. 20(c) is a cross-sectional view taken along line Y-Y' of Fig. 20(a).

Fig. 21 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 21(b) is a cross-sectional view taken along line X-X' of Fig. 21(a). Fig. 21 (c) is a cross-sectional view taken along line Y-Y' of Fig. 21 (a).

Fig. 22 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 22(b) is a cross-sectional view taken along line X-X' of Fig. 22(a). Fig. 22 (c) is a cross-sectional view taken along line Y-Y' of Fig. 22 (a).

Fig. 23(a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 23(b) is a cross-sectional view taken along line X-X' of Fig. 23(a). 23rd Figure (c) is a cross-sectional view taken along line Y-Y' of Figure 23 (a).

Fig. 24(a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 24(b) is a cross-sectional view taken along line X-X' of Fig. 24(a). Fig. 24(c) is a cross-sectional view taken along line Y-Y' of Fig. 24(a).

Fig. 25(a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 25(b) is a cross-sectional view taken along line X-X' of Fig. 25(a). Fig. 25(c) is a cross-sectional view taken along line Y-Y' of Fig. 25(a).

Fig. 26(a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 26(b) is a cross-sectional view taken along line X-X' of Fig. 26(a). Fig. 26(c) is a cross-sectional view taken along line Y-Y' of Fig. 26(a).

Fig. 27 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 27(b) is a cross-sectional view taken along line X-X' of Fig. 27(a). Fig. 27(c) is a cross-sectional view taken along line Y-Y' of Fig. 27(a).

Fig. 28 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 28(b) is a cross-sectional view taken along line X-X' of Fig. 28(a). Fig. 28(c) is a cross-sectional view taken along line Y-Y' of Fig. 28(a).

Fig. 29 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 29 (b) is a cross-sectional view taken along the line X-X' of Fig. 29 (a). Fig. 29 (c) is a cross-sectional view taken along line Y-Y' of Fig. 29 (a).

Fig. 30 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 30(b) is a cross-sectional view taken along line X-X' of Fig. 30(a). Fig. 30(c) is a cross-sectional view taken along line Y-Y' of Fig. 30(a).

Fig. 31 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 31 (b) is a cross-sectional view taken along line X-X' of Fig. 31 (a). 31st Figure (c) is a cross-sectional view taken along line Y-Y' of Figure 31 (a).

Fig. 32 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 32(b) is a cross-sectional view taken along line X-X' of Fig. 32(a). Fig. 32 (c) is a cross-sectional view taken along line Y-Y' of Fig. 32 (a).

Fig. 33(a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 33(b) is a cross-sectional view taken along line X-X' of Fig. 33(a). Fig. 33(c) is a cross-sectional view taken along line Y-Y' of Fig. 33(a).

Figure 34(a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 34(b) is a cross-sectional view taken along line X-X' of Fig. 34(a). Fig. 34(c) is a cross-sectional view taken along line Y-Y' of Fig. 34(a).

Fig. 35 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 35(b) is a cross-sectional view taken along line X-X' of Fig. 35(a). Fig. 35(c) is a cross-sectional view taken along line Y-Y' of Fig. 35(a).

Fig. 36 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 36 (b) is a cross-sectional view taken along line X-X' of Fig. 36 (a). Fig. 36 (c) is a cross-sectional view taken along line Y-Y' of Fig. 36 (a).

Fig. 37 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 37(b) is a cross-sectional view taken along line X-X' of Fig. 37(a). Fig. 37 (c) is a cross-sectional view taken along line Y-Y' of Fig. 37 (a).

Fig. 38 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 38(b) is a cross-sectional view taken along line X-X' of Fig. 38(a). Fig. 38 (c) is a cross-sectional view taken along line Y-Y' of Fig. 38 (a).

Fig. 39 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 39 (b) is a cross-sectional view taken along line X-X' of Fig. 39 (a). 39th Figure (c) is a cross-sectional view taken along line Y-Y' of Figure 39 (a).

Fig. 40 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 40 (b) is a cross-sectional view taken along line X-X' of Fig. 40 (a). Fig. 40 (c) is a cross-sectional view taken along line Y-Y' of Fig. 40 (a).

Fig. 41 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 41 (b) is a cross-sectional view taken along line X-X' of Fig. 41 (a). Fig. 41 (c) is a cross-sectional view taken along line Y-Y' of Fig. 41 (a).

Fig. 42 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 42(b) is a cross-sectional view taken along line X-X' of Fig. 42(a). Fig. 42 (c) is a cross-sectional view taken along line Y-Y' of Fig. 42 (a).

Reason: The entire schema [Fig. 1 (a) to (c)] must be used to show the complete technical features.

101‧‧‧矽 substrate

103‧‧‧Finned layer

104‧‧‧1st insulating film

106‧‧‧ Columnar layer

110‧‧‧Diffusion layer

112‧‧‧Diffusion layer

113‧‧‧gate insulating film

117‧‧‧ nitride film

120‧‧‧Metal

120a‧‧‧Metal gate electrode

120b‧‧‧Metal gate wiring

121‧‧‧Interlayer insulating film

127‧‧‧Contacts

128‧‧‧Contacts

133‧‧‧Metal wiring

134‧‧‧Metal wiring

135‧‧‧Metal wiring

140‧‧‧ nitride film

143‧‧‧Contacts

Claims (7)

A method of manufacturing a semiconductor device, comprising: forming a fin-shaped germanium layer on a germanium substrate, forming a first insulating film around the fin-shaped germanium layer, and forming a columnar germanium layer on an upper portion of the fin-shaped germanium layer The first step; the diameter of the columnar layer is the same as the width of the fin layer, and after the first step, the upper portion of the columnar layer, the upper portion of the fin layer, and the columnar layer a second step of forming a diffusion layer by implanting impurities in the lower portion; a third step of forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring after the second step; the gate insulating film covering the columnar shape In the periphery and the upper portion of the germanium layer, the polysilicon gate electrode covers the gate insulating film, and the upper surface of the polysilicon gate after the polysilicon gate electrode and the polysilicon gate wiring are formed on the diffusion layer above the columnar layer a higher position of the upper gate insulating film; a fourth step of forming a germanide on the upper portion of the diffusion layer in the upper portion of the finned layer after the third step; and a fourth step after the step Film, the polysilicon gate electrode is exposed and the polysilicon gate wiring, etching the polysilicon gate electrode and the polycrystal a fifth step of depositing a metal to form a metal gate electrode and a metal gate wiring after the gate wiring; the metal gate wiring extending orthogonal to the finned layer connected to the metal gate electrode Direction; after the fifth step, the sixth step of forming the contact portion; and the diffusion layer on the upper portion of the columnar layer is directly connected to the contact portion. The method of manufacturing a semiconductor device according to claim 1, wherein a first resist for forming a fin-shaped germanium layer is formed on the germanium substrate, and the germanium substrate is etched to form the fin-shaped germanium layer, and the first layer is removed. a resisting agent; a first insulating film is deposited around the fin-shaped germanium layer, and the first insulating film is etched back to expose an upper portion of the fin-shaped germanium layer, and a second resistor is formed to be orthogonal to the fin-shaped germanium layer And etching the fin-shaped ruthenium layer to remove the second resist, thereby forming the columnar ruthenium layer such that a portion of the fin-shaped ruthenium layer and the second resist is a columnar ruthenium layer . The method of manufacturing a semiconductor device according to the first aspect of the invention, further comprising: forming a fin-shaped germanium layer formed on the germanium substrate, forming a first insulating film formed around the fin-shaped germanium layer, and forming the In the structure of the columnar tantalum layer in the upper portion of the fin-shaped layer, a second oxide film is deposited, a first nitride film is formed on the second oxide film, and the first nitride film is etched and left in a side wall shape. plant Into the impurity, a diffusion layer is formed on the upper portion of the columnar layer and the upper portion of the fin layer, and the first nitride film and the second oxide film are removed to perform heat treatment. The method of manufacturing a semiconductor device according to the first aspect of the invention, comprising: a fin-shaped germanium layer formed on a germanium substrate; and a first insulating film formed around the fin-shaped germanium layer; a columnar layer of the upper portion of the fin-shaped layer; a diffusion layer formed on an upper portion of the fin-shaped layer and a lower portion of the columnar layer; and a structure of a diffusion layer formed on an upper portion of the columnar layer Forming a gate insulating film and depositing polysilicon to planarize and stack the upper surface of the polysilicon which is flattened by the polysilicon to a position higher than the gate insulating film on the diffusion layer on the upper portion of the columnar layer a second resist film forming a third resist for forming a polysilicon gate electrode and a polysilicon gate wiring, etching the second nitride film, and etching the polysilicon to form the polysilicon gate electrode and the polysilicon gate Wiring, etching the gate insulating film to remove the third resist. The method of manufacturing a semiconductor device according to claim 4, wherein the third nitride film is deposited, the third nitride film is etched and left in a side wall shape, and the metal is deposited on the upper portion of the finned layer. The upper portion of the diffusion layer forms a telluride. The method of manufacturing a semiconductor device according to claim 5, wherein the fourth nitride film is deposited, the interlayer insulating film is deposited and planarized, and the polysilicon gate electrode and the polysilicon gate wiring are exposed and removed. The polysilicon gate electrode and the polysilicon gate wiring are buried in a portion of the polysilicon gate electrode and the polysilicon gate wiring, and the metal is etched to form a gate on the diffusion layer on the upper portion of the columnar layer The insulating film is exposed to form a metal gate electrode and a metal gate wiring. A semiconductor device comprising: a fin-shaped germanium layer formed on a germanium substrate; a first insulating film formed around the fin-shaped germanium layer; and a columnar germanium layer formed on the fin-shaped germanium layer; wherein The diameter of the columnar layer is the same as the width of the fin layer; the diffusion layer formed on the upper portion of the fin layer and the lower portion of the columnar layer; and the diffusion layer formed on the upper portion of the columnar layer; a telluride on an upper portion of the diffusion layer above the finned layer; a gate insulating film formed around the columnar layer; a gate electrode formed around the gate insulating film; extending and connecting a metal gate wiring in a direction orthogonal to the fin fin layer of the metal gate electrode; and a contact portion formed on the diffusion layer formed on the upper portion of the columnar layer; formed on the upper portion of the columnar layer The diffusion layer is directly connected to the aforementioned contact portion.