CN103201842A - Semiconductor device manufacturing method, and semiconductor device - Google Patents
Semiconductor device manufacturing method, and semiconductor device Download PDFInfo
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- CN103201842A CN103201842A CN2011800540678A CN201180054067A CN103201842A CN 103201842 A CN103201842 A CN 103201842A CN 2011800540678 A CN2011800540678 A CN 2011800540678A CN 201180054067 A CN201180054067 A CN 201180054067A CN 103201842 A CN103201842 A CN 103201842A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 73
- 239000004065 semiconductor Substances 0.000 title claims description 64
- 239000010410 layer Substances 0.000 claims abstract description 254
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 202
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 202
- 239000010703 silicon Substances 0.000 claims abstract description 202
- 229920005591 polysilicon Polymers 0.000 claims abstract description 113
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 112
- 238000000034 method Methods 0.000 claims abstract description 75
- 238000009792 diffusion process Methods 0.000 claims abstract description 61
- 239000002184 metal Substances 0.000 claims abstract description 55
- 229910052751 metal Inorganic materials 0.000 claims abstract description 55
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 27
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 26
- 239000011229 interlayer Substances 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 238000009826 distribution Methods 0.000 claims description 45
- 239000003795 chemical substances by application Substances 0.000 claims description 39
- 238000005530 etching Methods 0.000 claims description 35
- 150000004767 nitrides Chemical class 0.000 claims description 32
- 239000007943 implant Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 239000011469 building brick Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- -1 cobalt metals Chemical class 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Abstract
The present invention addresses the issue of reducing parasitic capacitance between gate wiring and a substrate, and providing a surrounding gate transistor (SGT) manufacturing method, which is a gate-last process, and a structure of the SGT obtained as a result of employing the method. The issue is solved by means of: a step wherein a fin-like silicon layer is formed on a silicon substrate, a first insulating film is formed at the periphery of the fin-like silicon layer, and a columnar silicon layer is formed on an upper portion of the fin-like silicon layer; a step wherein, after the previous step, a diffusion layer is formed by injecting an impurity into an upper portion of the columnar silicon layer, the upper portion of the fin-like silicon layer, and a lower portion of the columnar silicon layer; a step wherein, after the previous step, a gate insulating film, a polysilicon gate electrode and polysilicon gate wiring are formed; a step wherein, after the previous step, a silicide is formed on an upper portion of the diffusion layer on the upper portion of the fin-like silicon layer; a step wherein, after the previous step, an interlayer insulating film is deposited, the polysilicon gate electrode and the polysilicon gate wiring are exposed, the polysilicon gate electrode and the polysilicon gate wiring are etched, then, a metal is deposited, and a metal gate electrode and metal gate wiring are formed; and a step wherein, after the previous step, a contact is formed.
Description
Technical field
The present invention relates to a kind of manufacture method and semiconductor device of semiconductor device.
Background technology
In the semiconductor integrated circuit, the integrated circuit that especially uses MOS transistor is constantly to stride forward towards highly integrated.Be accompanied by above-mentioned highly integrated, be used in wherein MOS transistor also constantly granular to nano-area.Along with the continuous granular of MOS transistor, the problems such as occupied area that suppress leakage current (leak current), can't dwindle circuit in order to ensure the demand of the necessary magnitude of current have also appearred being difficult to.In order to solve these problems, motion has source electrode (source), grid (gate), drain electrode (drain) is disposed at the vertical direction with respect to substrate, and grid surrounds the SGT (surrounding gate transistor, all around gate transistor) (for example: patent documentation 1, patent documentation 2, patent documentation 3) of the structure of columnar semiconductor layers.
By not using polysilicon (polysilicon) to use metal (metal) in gate electrode, and can suppress vague and generalization and make the gate electrode low resistanceization.Yet the step after forming metal gates is necessary for the manufacturing step of often considering because of the metallic pollution due to the metal gates.
In addition, in MOS transistor in the past, in order to take into account metal gate process and high-temperature technology, so (gate-last) forms operation (non-patent literature 1) after making the metal gates of metal gates be used in high-temperature technology in the goods of reality after.Make grid with polysilicon, afterwards, after piling up interlayer dielectric, by cmp polysilicon gate is exposed, behind polysilicon grid etching, deposit.Therefore, in order in SGT, also to take into account metal gate process and high-temperature technology, so form operation after must being used in the metal gates that makes metal gates behind the high-temperature technology.In SGT, because the top of column silicon layer is positioned at the position high than grid, so in order to use metal gate process must discuss and formulate countermeasure.
In addition, in order to lower the parasitic capacitance between gate wirings and substrate, in MOS transistor in the past, be to use the 1st dielectric film.For example in FINFET (Fin Field-effect transistor, fin formula field-effect transistor, can be with reference to non-patent literature 2) in, be around 1 fin-shaped semiconductor layer, to form the 1st dielectric film, eat-back (etch back) the 1st dielectric film, expose the fin-shaped semiconductor layer, lower the parasitic capacitance between gate wirings and substrate.Therefore, in SGT, must use the 1st dielectric film in order to lower the parasitic capacitance between gate wirings and substrate.In SGT, except the fin-shaped semiconductor, columnar semiconductor layers is arranged still, so must discuss and formulate countermeasure in order to form columnar semiconductor layers.
(prior art document)
(patent documentation)
(patent documentation 1): Japanese kokai publication hei 2-71556 communique
(patent documentation 2): Japanese kokai publication hei 2-188966 communique
(patent documentation 3): Japanese kokai publication hei 3-145761 communique
(non-patent literature)
The international electronic building brick meeting of (non-patent literature 1): IEDM() 2007K.Mistry et.al, the 247-250 page or leaf.
The international electronic building brick meeting of (non-patent literature 2): IEDM() 2010CC.Wu, et.al, 27.1.1-27.1.4. chapter Festival.
Summary of the invention
(problem that invention institute desire solves)
At this, purpose of the present invention lowers the parasitic capacitance between gate wirings and substrate and is the structure of the manufacture method of the SGT that forms technology behind the grid and result's thereof SGT for providing a kind of.
(means of dealing with problems)
In order to reach described purpose, the manufacture method of semiconductor device of the present invention has:
On silicon substrate, form the fin-shaped silicon layer, around aforementioned fin-shaped silicon layer, form the 1st dielectric film,
Form the 1st step of column silicon layer in the top of aforementioned fin-shaped silicon layer;
The diameter of aforementioned column silicon layer is identical with the width of aforementioned fin-shaped silicon layer,
After aforementioned the 1st step,
In aforementioned column silicon layer top, aforementioned fin-shaped silicon layer top, and aforementioned column silicon layer bottom implant impurity and form the 2nd step of diffusion layer;
After aforementioned the 2nd step,
Make gate insulating film, polysilicon gate electrode, and the 3rd step of polysilicon gate distribution;
Aforementioned gate insulating film be cover aforementioned column silicon layer around and top, aforementioned polysilicon gate electrode is the cover gate dielectric film, and the upper surface of the polysilicon after aforementioned polysilicon gate electrode and aforementioned polysilicon gate distribution form is the higher position of aforementioned gate insulating film that is positioned on the aforementioned diffusion layer on more aforementioned column silicon layer top;
After aforementioned the 3rd step,
Form the 4th step of silicide in the aforementioned diffusion layer top on aforementioned fin-shaped silicon layer top;
After aforementioned the 4th step,
Pile up interlayer dielectric, expose aforementioned polysilicon gate electrode and aforementioned polysilicon gate distribution, behind the aforementioned polysilicon gate electrode of etching and the aforementioned polysilicon gate distribution, deposit, with the 5th step of formation metal gate electrode and metal gates distribution,
The aforementioned metal gate wirings is the direction that extends with the aforementioned fin-shaped silicon layer quadrature that is connected in the aforementioned metal gate electrode;
After aforementioned the 5th step,
Form the 6th step of contact site,
The aforementioned diffusion layer on aforementioned column silicon layer top and aforementioned contact site are for directly to be connected.
In addition, on silicon substrate, form in order to form the 1st of fin-shaped silicon layer and hinder agent,
The etching silicon substrate forms aforementioned fin-shaped silicon layer, to remove aforementioned the 1st resistance agent;
Around aforementioned fin-shaped silicon layer, pile up the 1st dielectric film, eat-back aforementioned the 1st dielectric film, the top of exposing aforementioned fin-shaped silicon layer, form the 2nd resistance agent in the mode with aforementioned fin-shaped silicon layer quadrature, the aforementioned fin-shaped silicon layer of etching, remove aforementioned the 2nd resistance agent, whereby, form aforementioned column silicon layer so that the part of aforementioned fin-shaped silicon layer and aforementioned the 2nd resistance agent quadrature becomes the mode of aforementioned column silicon layer.
In addition, be to have: be formed at fin-shaped silicon layer on the silicon substrate, be formed at the 1st dielectric film around the aforementioned fin-shaped silicon layer and be formed in the structure of column silicon layer on aforementioned fin-shaped silicon layer top,
Pile up the 2nd oxide-film, on aforementioned the 2nd oxide-film, form the 1st nitride film, aforementioned the 1st nitride film of etching and make its residual one-tenth sidewall shape, implant impurity, form diffusion layer in aforementioned column silicon layer top and aforementioned fin-shaped silicon layer top, remove aforementioned the 1st nitride film and aforementioned the 2nd oxide-film, heat-treat.
In addition, be to have: be formed at fin-shaped silicon layer on the silicon substrate, be formed at the 1st dielectric film around the aforementioned fin-shaped silicon layer and be formed at the column silicon layer on aforementioned fin-shaped silicon layer top; Be formed at the diffusion layer of the bottom of the top of aforementioned fin-shaped silicon layer and aforementioned column silicon layer; And be formed in the structure of diffusion layer on top of aforementioned column silicon layer,
Form gate insulating film, pile up polysilicon, so that the upper surface of the aforementioned polysilicon after the planarization becomes the mode of the higher position of aforementioned gate insulating film on the diffusion layer on more aforementioned column silicon layer top aforementioned polysilicon is carried out planarization, pile up the 2nd nitride film, to form in order to form the 3rd resistance agent of polysilicon gate electrode and polysilicon gate distribution, aforementioned the 2nd nitride film of etching, the aforementioned polysilicon of etching, to form aforementioned polysilicon gate electrode and aforementioned polysilicon gate distribution, the aforementioned gate insulating film of etching is to remove the 3rd resistance agent.
In addition, pile up the 3rd nitride film, aforementioned the 3rd nitride film of etching and make its residual one-tenth sidewall shape, deposit forms silicide with the top in the diffusion layer on fin-shaped silicon layer top.
In addition, pile up the 4th nitride film, pile up interlayer dielectric and make its planarization, polysilicon gate electrode and polysilicon gate distribution are exposed, remove aforementioned polysilicon gate electrode and aforementioned polysilicon gate distribution, imbed metal, the etching aforementioned metal in the former part that has aforementioned polysilicon gate electrode and aforementioned polysilicon gate distribution, gate insulating film on the diffusion layer on column silicon layer top is exposed, to form metal gate electrode, metal gates distribution.
In addition, semiconductor device of the present invention is to have:
Be formed at the fin-shaped silicon layer on the silicon substrate;
Be formed at the 1st dielectric film on every side of aforementioned fin-shaped silicon layer;
Be formed at the column silicon layer on the aforementioned fin-shaped silicon layer;
Wherein, the diameter of aforementioned column silicon layer is identical with the width of aforementioned fin-shaped silicon layer;
Be formed at aforementioned fin-shaped silicon layer top, and the diffusion layer of aforementioned column silicon layer bottom;
Be formed at the diffusion layer on aforementioned column silicon layer top;
Be formed at the silicide on top of the diffusion layer on aforementioned fin-shaped silicon layer top;
Be formed at the gate insulating film on every side of aforementioned column silicon layer;
Be formed at the metal gate electrode on every side of aforementioned gate insulating film;
Extend the metal gates distribution with the direction of the aforementioned fin-shaped silicon layer quadrature that is connected in the aforementioned metal gate electrode; And
Formed contact site on the diffusion layer that is formed at aforementioned column silicon layer top;
The diffusion layer that is formed at aforementioned column silicon layer top is directly to be connected with aforementioned contact site.
(invention effect)
According to the present invention, a kind of parasitic capacitance that lowers between gate wirings and substrate can be provided, and be the SGT structure that forms SGT manufacture method and the result thereof of technology behind the grid.
Because it is to have the manufacture method of FINFET now, so can easily form that fin-shaped silicon layer, the 1st dielectric film, column silicon layer form.
In addition, though formed silicide in column silicon layer top in the past, because the accumulation temperature of polysilicon is in order to forming the temperature height of silicide, so silicide must formation after forming polysilicon gate,
Therefore, if desire in silicon post top formation silicide, then need after forming polysilicon gate, in the perforate of the top of polysilicon gate electrode, after the sidewall in hole forms the sidewall of dielectric film, form silicide, imbed dielectric film in the hole of offering again, and have the shortcoming that what is called causes the technology number to increase, so before forming polysilicon gate electrode and polysilicon gate distribution, form diffusion layer, cover the column silicon layer with the polysilicon gate electrode, and only in fin-shaped silicon layer top formation silicide, whereby owing to can adopt with polysilicon and make grid, pile up interlayer dielectric afterwards after, by cmp the polysilicon gate electrode is exposed, behind the etching polysilicon gate, the manufacture method that forms behind the existing metal gates of deposit is so can easily form metal gates SGT.
Description of drawings
Fig. 1 (a) is the plane graph of semiconductor device of the present invention.Fig. 1 (b) is the profile of the X-X' line of Fig. 1 (a).Fig. 1 (c) is the profile of the Y-Y' line of Fig. 1 (a).
Fig. 2 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Fig. 2 (b) is the profile of the X-X' line of Fig. 2 (a).Fig. 2 (c) is the profile of the Y-Y' line of Fig. 2 (a).
Fig. 3 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Fig. 3 (b) is the profile of the X-X' line of Fig. 3 (a).Fig. 3 (c) is the profile of the Y-Y' line of Fig. 3 (a).
Fig. 4 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Fig. 4 (b) is the profile of the X-X' line of Fig. 4 (a).Fig. 4 (c) is the profile of the Y-Y' line of Fig. 4 (a).
Fig. 5 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Fig. 5 (b) is the profile of the X-X' line of Fig. 5 (a).Fig. 5 (c) is the profile of the Y-Y' line of Fig. 5 (a).
Fig. 6 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Fig. 6 (b) is the profile of the X-X' line of Fig. 6 (a).Fig. 6 (c) is the profile of the Y-Y' line of Fig. 6 (a).
Fig. 7 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Fig. 7 (b) is the profile of the X-X' line of Fig. 7 (a).Fig. 7 (c) is the profile of the Y-Y' line of Fig. 7 (a).
Fig. 8 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Fig. 8 (b) is the profile of the X-X' line of Fig. 8 (a).Fig. 8 (c) is the profile of the Y-Y' line of Fig. 8 (a).
Fig. 9 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Fig. 9 (b) is the profile of the X-X' line of Fig. 9 (a).Fig. 9 (c) is the profile of the Y-Y' line of Fig. 9 (a).
Figure 10 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 10 (b) is the profile of the X-X' line of Figure 10 (a).Figure 10 (c) is the profile of the Y-Y' line of Figure 10 (a).
Figure 11 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 11 (b) is the profile of the X-X' line of Figure 11 (a).Figure 11 (c) is the profile of the Y-Y' line of Figure 11 (a).
Figure 12 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 12 (b) is the profile of the X-X' line of Figure 12 (a).Figure 12 (c) is the profile of the Y-Y' line of Figure 12 (a).
Figure 13 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 13 (b) is the profile of the X-X' line of Figure 13 (a).Figure 13 (c) is the profile of the Y-Y' line of Figure 13 (a).
Figure 14 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 14 (b) is the profile of the X-X' line of Figure 14 (a).Figure 14 (c) is the profile of the Y-Y' line of Figure 14 (a).
Figure 15 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 15 (b) is the profile of the X-X' line of Figure 15 (a).Figure 15 (c) is the profile of the Y-Y' line of Figure 15 (a).
Figure 16 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 16 (b) is the profile of the X-X' line of Figure 16 (a).Figure 16 (c) is the profile of the Y-Y' line of Figure 16 (a).
Figure 17 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 17 (b) is the profile of the X-X' line of Figure 17 (a).Figure 17 (c) is the profile of the Y-Y' line of Figure 17 (a).
Figure 18 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 18 (b) is the profile of the X-X' line of Figure 18 (a).Figure 18 (c) is the profile of the Y-Y' line of Figure 18 (a).
Figure 19 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 19 (b) is the profile of the X-X' line of Figure 19 (a).Figure 19 (c) is the profile of the Y-Y' line of Figure 19 (a).
Figure 20 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 20 (b) is the profile of the X-X' line of Figure 20 (a).Figure 20 (c) is the profile of the Y-Y' line of Figure 20 (a).
Figure 21 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 21 (b) is the profile of the X-X' line of Figure 21 (a).Figure 21 (c) is the profile of the Y-Y' line of Figure 21 (a).
Figure 22 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 22 (b) is the profile of the X-X' line of Figure 22 (a).Figure 22 (c) is the profile of the Y-Y' line of Figure 22 (a).
Figure 23 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 23 (b) is the profile of the X-X' line of Figure 23 (a).Figure 23 (c) is the profile of the Y-Y' line of Figure 23 (a).
Figure 24 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 24 (b) is the profile of the X-X' line of Figure 24 (a).Figure 24 (c) is the profile of the Y-Y' line of Figure 24 (a).
Figure 25 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 25 (b) is the profile of the X-X' line of Figure 25 (a).Figure 25 (c) is the profile of the Y-Y' line of Figure 25 (a).
Figure 26 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 26 (b) is the profile of the X-X' line of Figure 26 (a).Figure 26 (c) is the profile of the Y-Y' line of Figure 26 (a).
Figure 27 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 27 (b) is the profile of the X-X' line of Figure 27 (a).Figure 27 (c) is the profile of the Y-Y' line of Figure 27 (a).
Figure 28 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 28 (b) is the profile of the X-X' line of Figure 28 (a).Figure 28 (c) is the profile of the Y-Y' line of Figure 28 (a).
Figure 29 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 29 (b) is the profile of the X-X' line of Figure 29 (a).Figure 29 (c) is the profile of the Y-Y' line of Figure 29 (a).
Figure 30 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 30 (b) is the profile of the X-X' line of Figure 30 (a).Figure 30 (c) is the profile of the Y-Y' line of Figure 30 (a).
Figure 31 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 31 (b) is the profile of the X-X' line of Figure 31 (a).Figure 31 (c) is the profile of the Y-Y' line of Figure 31 (a).
Figure 32 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 32 (b) is the profile of the X-X' line of Figure 32 (a).Figure 32 (c) is the profile of the Y-Y' line of Figure 32 (a).
Figure 33 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 33 (b) is the profile of the X-X' line of Figure 33 (a).Figure 33 (c) is the profile of the Y-Y' line of Figure 33 (a).
Figure 34 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 34 (b) is the profile of the X-X' line of Figure 34 (a).Figure 34 (c) is the profile of the Y-Y' line of Figure 34 (a).
Figure 35 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 35 (b) is the profile of the X-X' line of Figure 35 (a).Figure 35 (c) is the profile of the Y-Y' line of Figure 35 (a).
Figure 36 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 36 (b) is the profile of the X-X' line of Figure 36 (a).Figure 36 (c) is the profile of the Y-Y' line of Figure 36 (a).
Figure 37 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 37 (b) is the profile of the X-X' line of Figure 37 (a).Figure 37 (c) is the profile of the Y-Y' line of Figure 37 (a).
Figure 38 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 38 (b) is the profile of the X-X' line of Figure 38 (a).Figure 38 (c) is the profile of the Y-Y' line of Figure 38 (a).
Figure 39 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 39 (b) is the profile of the X-X' line of Figure 39 (a).Figure 39 (c) is the profile of the Y-Y' line of Figure 39 (a).
Figure 40 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 40 (b) is the profile of the X-X' line of Figure 40 (a).Figure 40 (c) is the profile of the Y-Y' line of Figure 40 (a).
Figure 41 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 41 (b) is the profile of the X-X' line of Figure 41 (a).Figure 41 (c) is the profile of the Y-Y' line of Figure 41 (a).
Figure 42 (a) is the plane graph of the manufacture method of semiconductor device of the present invention.Figure 42 (b) is the profile of the X-X' line of Figure 42 (a).Figure 42 (c) is the profile of the Y-Y' line of Figure 42 (a).
Wherein, description of reference numerals is as follows:
101 silicon substrates
102 resistance agent
103 fin-shaped silicon layers
104 the 1st dielectric films
105 resistance agent
106 column silicon layers
107 oxide-films
108 hinder the film that impurity is implanted
109 diffusion layers
110 diffusion layers
111 diffusion layers
112 diffusion layers
113 gate insulating films
114 polysilicons
114a polysilicon gate electrode
114b polysilicon gate distribution
115 nitride films
116 resistance agent
117 nitride films
118 silicides
119 interlayer dielectrics
120 metals
121 interlayer dielectrics
122 resistance agent
123 contact holes
124 resistance agent
125 contact holes
126 contact holes
127 contact sites
128 contact sites
129 metals
130 resistance agent
131 resistance agent
132 resistance agent
133 metal wirings
134 metal wirings
135 metal wirings
140 nitride films
143 contact sites
Embodiment
Below, the manufacturing step of constructing in order to the SGT that forms the invention process form is described with reference to Fig. 2 to Figure 42.
At first, be shown in and form the fin-shaped silicon layer on the silicon substrate, around the fin-shaped silicon layer, form the 1st dielectric film, form the manufacture method of column silicon layer in the top of fin-shaped silicon layer.As shown in Figure 2, on silicon substrate 101, form in order to form the 1st resistance agent (resist) 102 of fin-shaped silicon layer.
As shown in Figure 3, etching silicon substrate 101 forms fin-shaped silicon layer 103.Though form the fin-shaped silicon layer with the resistance agent as mask in this example, also can use hard mask (hard mask) such as oxide-film or nitride film.
As shown in Figure 4, remove the 1st resistance agent 102.
As shown in Figure 5, around fin-shaped silicon layer 103, pile up the 1st dielectric film 104.As the 1st dielectric film, also can use with high-density plasma oxide-film or the low pressure chemical gas phase pile up (chemical vapor deposition) and oxide-film.
As shown in Figure 6, eat-back the 1st dielectric film 104, the top of exposing fin-shaped silicon layer 103.Up to the present, be identical with the method for making of the fin-shaped silicon layer of patent documentation 2.
As shown in Figure 7, form the 2nd resistance agent 105 in the mode with fin-shaped silicon layer 103 quadratures.Fin-shaped silicon layer 103 is the part that becomes the column layer with the part of resistance agent 105 quadratures.Owing to can use the resistance agent of wire, so the possibility that the resistance agent is fallen down behind patterning is low, and become stable technology (precess).
As shown in Figure 8, etching fin-shaped silicon layer 103.The part of fin-shaped silicon layer 103 and the 2nd resistance agent 105 quadratures becomes column silicon layer 106.Therefore, the diameter of column silicon layer 106 is that to become the width of fin-shaped silicon layer identical.Be formed with column silicon layer 106 in the top of fin-shaped silicon layer 103 and become, and around fin-shaped silicon layer 103, be formed with the structure of the 1st dielectric film 104.
As shown in Figure 9, remove the 2nd resistance agent 105.
Secondly, show after becoming grid, to form, and be used to column silicon layer top and fin-shaped silicon layer top and column silicon layer bottom implant impurity and form the manufacture method of diffusion layer.As shown in figure 10, pile up the 2nd oxide-film 107, form the 1st nitride film 108.Afterwards because column silicon layer top covered by gate insulating film and polysilicon gate electrode, so before capped at column silicon layer top formation diffusion layer.
As shown in figure 11, etching the 1st nitride film 108, and make it remaining for the sidewall shape.
As shown in figure 12, implant impurity such as arsenic, phosphorus or boron, form diffusion layer 110 in column silicon layer top, form diffusion layer 109,111 in fin-shaped silicon layer 103 tops.
As shown in figure 13, remove the 1st nitride film 108 and the 2nd oxide-film 107.
Heat-treat as shown in figure 14.The diffusion layer 109, the 111st on fin-shaped silicon layer 103 tops, contact and become diffusion layer 112.In order to be made as " forming behind the grid " by above step, in column silicon layer top and fin-shaped silicon layer top and column silicon layer bottom implant impurity and form diffusion layer 110,112.
Secondly, show in order to be made as " forming behind the grid ", make the manufacture method of polysilicon gate electrode and polysilicon gate distribution with polysilicon.In order to be made as " forming behind the grid ", must after piling up interlayer dielectric, by cmp polysilicon gate electrode and polysilicon gate distribution be exposed, so must adopt the mode that does not cause column silicon layer top to be exposed because of cmp.
As shown in figure 15, form gate insulating film 113, pile up polysilicon 114, and make its planarization.The upper surface of the polysilicon after the planarization is to become the position higher than the gate insulating film 113 on the diffusion layer 110 on column silicon layer 106 tops.Whereby, become in order to be made as " forming behind the grid " after piling up interlayer dielectric, when by cmp polysilicon gate and polysilicon gate distribution being exposed, the mode that can column silicon layer top be exposed because of cmp not.
In addition, pile up the 2nd nitride film 115.The 2nd nitride film 115 is when forming silicide in fin-shaped silicon layer top, hinders the film that forms silicide in polysilicon gate electrode and polysilicon gate distribution top.
As shown in figure 16, form in order to form the 3rd resistance agent 116 of polysilicon gate electrode and polysilicon gate distribution.Be preferably and make the part and fin-shaped silicon layer 103 quadratures that becomes gate wirings.This is in order to lower the parasitic capacitance between gate wirings and substrate.
As shown in figure 17, etching the 2nd nitride film 115.
As shown in figure 18, etching polysilicon 114 forms polysilicon gate electrode 14a and polysilicon gate distribution 114b.
As shown in figure 19, the etching grid dielectric film 113.
As shown in figure 20, remove the 3rd resistance agent 116.
Show in order to be made as " forming behind the grid " by above step, and form the manufacture method of polysilicon gate electrode and polysilicon gate distribution with polysilicon.Forming the upper surface of the polysilicon behind polysilicon gate electrode 114a and the polysilicon gate distribution 114b, is to become the position higher than the gate insulating film 113 on the diffusion layer 110 on column silicon layer 106 tops.
Secondly, be shown in the manufacture method that silicide is formed at fin-shaped silicon layer top.It is characterized in that the diffusion layer 110 on polysilicon gate electrode 114a and polysilicon gate distribution 114b top and column silicon layer 106 tops does not form silicide.Then will increase manufacturing step if desire to form silicide in the diffusion layer 110 on column silicon layer 106 tops.
As shown in figure 21, pile up the 3rd nitride film 117.
As shown in figure 22, etching the 3rd nitride film 117 and residual one-tenth sidewall (side wall) shape.
As shown in figure 23, pile up nickel (Ni), cobalt metals such as (Co), silicide 118 is formed at the top of the diffusion layer 112 on fin-shaped silicon layer 103 tops.At this moment, polysilicon gate electrode 114a and polysilicon gate distribution 114b are covered by the 3rd nitride film 117, the 2nd nitride film 115, diffusion layer 110 on the column silicon layer 106 is covered by gate insulating film 113, polysilicon gate electrode 114a and polysilicon gate distribution 114b, does not therefore form silicide.
Be shown in the manufacture method that silicide is formed at fin-shaped silicon layer top by above step.
Secondly, behind the dielectric film, by cmp polysilicon gate electrode and polysilicon gate distribution are exposed between the display stack lamination, behind etching polysilicon gate electrode and the polysilicon gate distribution, the manufacture method that forms behind the grid of deposit.
As shown in figure 24, pile up the 4th nitride film 140 in order to protect silicide 118.
As shown in figure 25, pile up interlayer dielectric 119, the planarization by cmp.
As shown in figure 26, by cmp polysilicon gate electrode 114a and polysilicon gate distribution 114b are exposed.
As shown in figure 27, etching polysilicon gate electrode 114a and polysilicon gate distribution 114b.Be preferably the use wet etching.
As shown in figure 29, etching metal 120 exposes the gate insulating film 113 on the diffusion layer 110 on column silicon layer 106 tops.Form metal gate electrode 120a, metal gates distribution 120b.After having shown the accumulation interlayer dielectric, by cmp polysilicon gate is exposed, behind polysilicon grid etching, the manufacture method that forms behind the grid of deposit.
Secondly, show in order to form the manufacture method of contact site (contact).Because the diffusion layer 110 on column silicon layer 106 tops is not formed with silicide, is connected so contact site will become directly with the diffusion layer 110 on column silicon layer 106 tops.As shown in figure 30, pile up interlayer dielectric 121 and make it planarization.
As shown in figure 31, form in column silicon layer 106 tops in order to form the 4th resistance agent 122 of contact hole.
Shown in figure 32, etching interlayer dielectric 121 forms contact hole 123.
As shown in figure 33, remove the 4th resistance agent 122.
As shown in figure 34, on metal gates distribution 120b, fin-shaped silicon layer 103 forms in order to form the 5th resistance agent 124 of contact hole.
As shown in figure 35, etching interlayer dielectric 121,119 and form contact hole 125,126.
As shown in figure 36, remove the 5th resistance agent 124.
As shown in figure 37, etching nitride film 140 and gate insulating film 113 expose silicide 118 and diffusion layer 110.
As shown in figure 38, deposit is to form contact site 143,127,128.Show in order to form the manufacture method of contact site by above step.Because diffusion layer 110 on column silicon layer 106 tops is not formed with silicide, so the diffusion layer 110 on contact site 127 and column silicon layer 106 tops is directly to be connected.
Secondly, show in order to form the manufacture method of metallic wiring layer.
As shown in figure 39, deposit 129.
As shown in figure 40, form in order to form the 6th resistance agent 130,131,132 of metal wiring.
As shown in figure 41, etching metal 129 is to form metal wiring 133,134,135.
As shown in figure 42, remove the 6th resistance agent 130,131,132.
Show in order to form the manufacture method of metallic wiring layer by above step.
The Fig. 1 that the results are shown in above-mentioned manufacture method.
Become the structure that has with lower member:
Fin-shaped silicon layer 103 is formed on the substrate 101;
The 1st dielectric film 104, be formed at fin-shaped silicon layer 103 around;
The diameter of column silicon layer 106 is identical with the width of fin-shaped silicon layer 103;
And diffusion layer 110 is direct-connected structure with contact site 127.
According to above-mentioned explanation, the parasitic capacitance that lowers between gate wirings and substrate can be provided, and be the SGT structure that forms SGT manufacture method and the result thereof of technology behind the grid.
Claims (7)
1. the manufacture method of a semiconductor device is characterized in that, has following step Sudden:
On silicon substrate, form the fin-shaped silicon layer, around aforementioned fin-shaped silicon layer, form the 1st dielectric film,
Form the 1st step of column silicon layer in the top of aforementioned fin-shaped silicon layer;
The diameter of aforementioned column silicon layer is identical with the width of aforementioned fin-shaped silicon layer,
After aforementioned the 1st step,
In aforementioned column silicon layer top, aforementioned fin-shaped silicon layer top, and aforementioned column silicon layer bottom implant impurity and form the 2nd step of diffusion layer;
After aforementioned the 2nd step,
Make gate insulating film, polysilicon gate electrode, and the 3rd step of polysilicon gate distribution;
Aforementioned gate insulating film be cover aforementioned column silicon layer around and top, aforementioned polysilicon gate electrode is the cover gate dielectric film, and the upper surface of the polysilicon after aforementioned polysilicon gate electrode and aforementioned polysilicon gate distribution form is the higher position of aforementioned gate insulating film that is positioned on the aforementioned diffusion layer on more aforementioned column silicon layer top;
After aforementioned the 3rd step,
Form the 4th step of silicide in the aforementioned diffusion layer top on aforementioned fin-shaped silicon layer top;
After aforementioned the 4th step,
Pile up interlayer dielectric, expose aforementioned polysilicon gate electrode and aforementioned polysilicon gate distribution, behind the aforementioned polysilicon gate electrode of etching and the aforementioned polysilicon gate distribution, deposit is to form the 5th step of metal gate electrode and metal gates distribution;
The aforementioned metal gate wirings is the direction that extends with the aforementioned fin-shaped silicon layer quadrature that is connected in the aforementioned metal gate electrode;
After aforementioned the 5th step,
Form the 6th step of contact site;
The aforementioned diffusion layer on aforementioned column silicon layer top and aforementioned contact site are for directly to be connected.
2. the manufacture method of semiconductor device according to claim 1 is characterized in that,
Form on silicon substrate in order to form the 1st resistance agent of fin-shaped silicon layer, the etching silicon substrate forms aforementioned fin-shaped silicon layer, removes aforementioned the 1st resistance agent;
Around aforementioned fin-shaped silicon layer, pile up the 1st dielectric film, eat-back aforementioned the 1st dielectric film, the top of exposing aforementioned fin-shaped silicon layer, form the 2nd resistance agent in the mode with aforementioned fin-shaped silicon layer quadrature, the aforementioned fin-shaped silicon layer of etching, remove aforementioned the 2nd resistance agent, whereby, form aforementioned column silicon layer so that the part of aforementioned fin-shaped silicon layer and aforementioned the 2nd resistance agent quadrature becomes the mode of aforementioned column silicon layer.
3. the manufacture method of semiconductor device according to claim 1, it is characterized in that, have: be formed at fin-shaped silicon layer on the silicon substrate, be formed at the 1st dielectric film around the aforementioned fin-shaped silicon layer and be formed in the structure of column silicon layer on aforementioned fin-shaped silicon layer top
Pile up the 2nd oxide-film, on aforementioned the 2nd oxide-film, form the 1st nitride film, aforementioned the 1st nitride film of etching and make its residual one-tenth sidewall shape, implant impurity, form diffusion layer in aforementioned column silicon layer top and aforementioned fin-shaped silicon layer top, remove aforementioned the 1st nitride film and aforementioned the 2nd oxide-film, heat-treat.
4. the manufacture method of semiconductor device according to claim 1 is characterized in that, has: be formed at fin-shaped silicon layer on the silicon substrate, be formed at aforementioned fin-shaped silicon layer around the 1st dielectric film, be formed at the column silicon layer on aforementioned fin-shaped silicon layer top; Be formed at the diffusion layer of the bottom of the top of aforementioned fin-shaped silicon layer and aforementioned column silicon layer; And be formed in the structure of diffusion layer on top of aforementioned column silicon layer,
Form gate insulating film, pile up polysilicon, so that the upper surface of the aforementioned polysilicon after the planarization becomes the mode of the higher position of aforementioned gate insulating film on the diffusion layer on more aforementioned column silicon layer top aforementioned polysilicon is carried out planarization, pile up the 2nd nitride film, formation is in order to form the 3rd resistance agent of polysilicon gate electrode and polysilicon gate distribution, aforementioned the 2nd nitride film of etching, the aforementioned polysilicon of etching, form aforementioned polysilicon gate electrode and aforementioned polysilicon gate distribution, the aforementioned gate insulating film of etching is removed the 3rd resistance agent.
5. the manufacture method of semiconductor device according to claim 4 is characterized in that, piles up the 3rd nitride film, aforementioned the 3rd nitride film of etching and make its residual one-tenth sidewall shape, and deposit forms silicide in the top of the diffusion layer on fin-shaped silicon layer top.
6. the manufacture method of semiconductor device according to claim 5, it is characterized in that, pile up the 4th nitride film, pile up interlayer dielectric and with its planarization, polysilicon gate electrode and polysilicon gate distribution are exposed, remove aforementioned polysilicon gate electrode and aforementioned polysilicon gate distribution, imbed metal in the part that is aforementioned polysilicon gate electrode and aforementioned polysilicon gate distribution originally, the etching aforementioned metal, gate insulating film on the diffusion layer on column silicon layer top is exposed, form metal gate electrode, metal gates distribution.
7. semiconductor device is characterized in that having:
Be formed at the fin-shaped silicon layer on the silicon substrate;
Be formed at the 1st dielectric film on every side of aforementioned fin-shaped silicon layer;
Be formed at the column silicon layer on the aforementioned fin-shaped silicon layer;
Wherein, the diameter of aforementioned column silicon layer is identical with the width of aforementioned fin-shaped silicon layer;
Be formed at aforementioned fin-shaped silicon layer top, and the diffusion layer of aforementioned column silicon layer bottom;
Be formed at the diffusion layer on aforementioned column silicon layer top;
Be formed at the silicide on top of the diffusion layer on aforementioned fin-shaped silicon layer top;
Be formed at the gate insulating film on every side of aforementioned column silicon layer;
Be formed at the metal gate electrode on every side of aforementioned gate insulating film;
Extend the metal gates distribution with the direction of the aforementioned fin-shaped silicon layer quadrature that is connected in the aforementioned metal gate electrode; And
Formed contact site on the diffusion layer that is formed on aforementioned column silicon layer top;
The diffusion layer that is formed at aforementioned column silicon layer top directly is connected with aforementioned contact site.
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| PCT/JP2011/075789 WO2013069102A1 (en) | 2011-11-09 | 2011-11-09 | Semiconductor device manufacturing method, and semiconductor device |
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| JP (1) | JP5695745B2 (en) |
| KR (1) | KR20130110181A (en) |
| CN (1) | CN103201842A (en) |
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| CN101635309A (en) * | 2008-07-25 | 2010-01-27 | 海力士半导体有限公司 | All around gate type semiconductor device and method of manufacturing the same |
| CN101866857A (en) * | 2009-04-20 | 2010-10-20 | 日本优尼山帝斯电子株式会社 | Semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPWO2013069102A1 (en) | 2015-04-02 |
| JP5695745B2 (en) | 2015-04-08 |
| KR20130110181A (en) | 2013-10-08 |
| TW201320201A (en) | 2013-05-16 |
| WO2013069102A1 (en) | 2013-05-16 |
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