JP6368836B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device.

  Semiconductor integrated circuits, in particular integrated circuits using MOS transistors, are becoming increasingly highly integrated. Along with this high integration, the MOS transistors used therein have been miniaturized to the nano region. When the miniaturization of such a MOS transistor progresses, it is difficult to suppress the leakage current, and there is a problem that the occupied area of the circuit cannot be easily reduced due to a request for securing a necessary amount of current. In order to solve such a problem, a Surrounding Gate Transistor (hereinafter referred to as “SGT”) having a structure in which a source, a gate, and a drain are arranged in a direction perpendicular to a substrate and a gate electrode surrounds a columnar semiconductor layer is proposed. (For example, see Patent Document 1, Patent Document 2, and Patent Document 3).

In a conventional SGT manufacturing method, a silicon pillar in which a nitride film hard mask is formed in a columnar shape is formed using a mask for drawing a silicon pillar, and a silicon pillar is drawn using a mask for drawing a planar silicon layer. A planar silicon layer is formed at the bottom, and a gate wiring is formed using a mask for drawing the gate wiring (see, for example, Patent Document 4).
That is, a silicon pillar, a planar silicon layer, and a gate wiring are formed using three masks.

  Further, in a conventional MOS transistor, in order to achieve both a metal gate process and a high temperature process, a metal gate last process for creating a metal gate after a high temperature process is used in an actual product (Non-Patent Document 1). After forming a gate with polysilicon, an interlayer insulating film is deposited, then the polysilicon gate is exposed by chemical mechanical polishing, and after etching the polysilicon gate, a metal is deposited. Therefore, also in SGT, in order to make a metal gate process and a high temperature process compatible, it is necessary to use the metal gate last process which produces a metal gate after a high temperature process.

  In the metal gate last process, after a polysilicon gate is formed, a diffusion layer is formed by ion implantation. In SGT, since the upper part of the columnar silicon layer is covered with the polysilicon gate, a device is required.

When the silicon pillar is thinned, the density of silicon is 5 × 10 ²² pieces / cm ³ , so that it becomes difficult for impurities to exist in the silicon pillar.

In the conventional SGT, it has been proposed to determine the threshold voltage by changing the work function of the gate material by setting the channel concentration to a low impurity concentration of 10 ¹⁷ cm ⁻³ or less (see, for example, Patent Document 5). ).

  In the planar MOS transistor, the sidewall of the LDD region is formed of polycrystalline silicon having the same conductivity type as that of the low concentration layer, and the surface carrier of the LDD region is induced by the work function difference, so that the oxide film sidewall LDD type MOS It has been shown that the impedance of the LDD region can be reduced as compared with a transistor (for example, see Patent Document 6). The polycrystalline silicon sidewall is shown to be electrically insulated from the gate electrode. In the figure, it is shown that the polysilicon side wall and the source / drain are insulated by an interlayer insulating film.

  In order to reduce the parasitic capacitance between the gate wiring and the substrate, the conventional MOS transistor uses the first insulating film. For example, in FINFET (Non-patent Document 2), a first insulating film is formed around one fin-like semiconductor layer, the first insulating film is etched back, the fin-like semiconductor layer is exposed, and the gate wiring and the substrate The parasitic capacitance between them is reduced. Therefore, also in SGT, it is necessary to use the first insulating film in order to reduce the parasitic capacitance between the gate wiring and the substrate. In SGT, since there is a columnar semiconductor layer in addition to the fin-shaped semiconductor layer, a device for forming the columnar semiconductor layer is required.

JP-A-2-71556 Japanese Patent Laid-Open No. 2-188966 Japanese Patent Laid-Open No. 3-145761 JP 2009-182317 A JP 2004-356314 A JP 11-297984 A

IEDM2007 K. Mistry et.al, pp 247-250 IEDM2010 CC.Wu, et.al, 27.1.1-27.1.4.

  Therefore, a fin-like semiconductor layer, a columnar semiconductor layer, a gate electrode and a gate wiring are formed with two masks, and is a gate last process. An object of the present invention is to provide a method for manufacturing an SGT having a structure that functions as a p-type semiconductor layer or a p-type semiconductor layer, and an SGT structure obtained as a result.

  The method for manufacturing a semiconductor device of the present invention includes a first step of forming a fin-like semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-like semiconductor layer, and after the first step, A second step of forming a first dummy gate made of a columnar semiconductor layer and a first polysilicon; and after the second step, a second dummy gate is formed on a side wall of the first dummy gate and the columnar semiconductor layer. After the third step to be formed and after the third step, a sidewall made of a fifth insulating film is formed around the second dummy gate to form a sidewall made of a fifth insulating film. And a fourth step of forming a second diffusion layer under the columnar semiconductor layer and forming a compound of metal and semiconductor on the second diffusion layer, and depositing an interlayer insulating film after the fourth step And the second dummy gate and the first dashes. Exposing the upper part of the gate, removing the second dummy gate and the first dummy gate, and forming a first gate insulating film around the columnar semiconductor layer and inside the fifth insulating film; A fifth step of depositing a first metal and forming a gate electrode and a gate wiring; and after the fifth step, a second gate insulating film around the columnar semiconductor layer, on the gate electrode, and on the gate wiring A portion of the second gate insulating film on the gate wiring is removed, a second metal is deposited, etch back is performed, and the second gate insulating film on the columnar semiconductor layer is removed. Removing, depositing a third metal, and etching the third metal and a portion of the second metal so that the second metal surrounds the upper sidewall of the columnar semiconductor layer; The upper part of the first contact and the columnar semiconductor layer And a sixth contact for forming a second contact for connecting a portion and a third contact made of the second metal and the third metal formed on the gate wiring. .

  Further, in the second step, a second insulating film is formed around the fin-like semiconductor layer, the first polysilicon is deposited on the second insulating film and planarized, and the gate is formed. A second resist for forming a wiring and the columnar semiconductor layer is formed in a direction perpendicular to the direction of the fin-shaped semiconductor layer, and the first polysilicon, the second insulating film, and the fin The columnar semiconductor layer and the first dummy gate made of the first polysilicon are formed by etching the columnar semiconductor layer.

  In the third step, a fourth insulating film is formed around the columnar semiconductor layer and the first dummy gate, and second polysilicon is deposited around the fourth insulating film. Etching is performed to leave the first dummy gate and the side walls of the columnar semiconductor layer to form the second dummy gate.

  Further, in the fourth step, the fifth insulating film is formed around the second dummy gate, etched, left in a sidewall shape, and the side made of the fifth insulating film. Forming a wall; forming the second diffusion layer above the fin-like semiconductor layer and below the columnar semiconductor layer; and forming the metal-semiconductor compound on the second diffusion layer. .

  Further, in the fifth step, an interlayer insulating film is deposited and chemically mechanically polished to expose the second dummy gate and the upper portion of the first dummy gate, and the second dummy gate and the first dummy gate are exposed. The dummy gate is removed, the second insulating film and the fourth insulating film are removed, and a first gate insulating film is formed around the columnar semiconductor layer and inside the fifth insulating film, The first metal is deposited and etched back to form the gate electrode and the gate wiring.

  The method further includes depositing the first polysilicon on the second insulating film and planarizing, and then forming a third insulating film on the first polysilicon.

  The method further includes depositing a contact stopper film after the fourth step.

  The method further includes a step of removing the first gate insulating film after the fifth step.

  The metal work function of the first contact is between 4.0 eV and 4.2 eV.

  The metal work function of the first contact is between 5.0 eV and 5.2 eV.

  The semiconductor device of the present invention is formed on the fin-like semiconductor layer, the fin-like semiconductor layer formed on the semiconductor substrate, the first insulating film formed around the fin-like semiconductor layer, and the fin-like semiconductor layer. A columnar semiconductor layer, a first gate insulating film formed around the columnar semiconductor layer, a gate electrode made of metal formed around the first gate insulating film, and connected to the gate electrode A gate wiring made of a metal extending in a direction orthogonal to the fin-like semiconductor layer, the gate electrode, the first gate insulating film formed on the periphery and bottom of the gate wiring, and an outer side of the gate electrode The width of the gate wiring is the same as that of the second diffusion layer formed in the upper part of the fin-like semiconductor layer, the lower part of the columnar semiconductor layer, and the upper sidewall of the columnar semiconductor layer. Second game An insulating film; a first contact made of a second metal formed around the second gate insulating film; and a third metal connecting the upper portion of the first contact and the upper portion of the columnar semiconductor layer. And a third contact made of the second metal and the third metal formed on the gate wiring.

  Further, the width of the first contact in the direction perpendicular to the gate wiring is equal to the width of the third contact in the direction perpendicular to the gate wiring.

  Further, the width of the first contact in the direction perpendicular to the gate wiring is equal to the width of the gate wiring in the direction perpendicular to the gate wiring.

  Further, the width of the third contact in the direction perpendicular to the gate wiring is equal to the width of the gate wiring in the direction perpendicular to the gate wiring.

  Further, the width of the first contact in the direction perpendicular to the gate wiring is equal to the width of the second contact in the direction perpendicular to the gate wiring.

  The semiconductor device further includes the second gate insulating film formed around and at the bottom of the first contact.

  The work function of the second metal of the first contact is between 4.0 eV and 4.2 eV.

  The work function of the second metal of the first contact is between 5.0 eV and 5.2 eV.

  According to the present invention, a fin-like semiconductor layer, a columnar semiconductor layer, a gate electrode and a gate wiring are formed with two masks, and is a gate last process. It is possible to provide a method for manufacturing an SGT having a structure that functions as an n-type semiconductor layer or a p-type semiconductor layer by a function difference, and a structure of the SGT obtained as a result.

  A first step of forming a fin-like semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-like semiconductor layer; and after the first step, a columnar semiconductor layer and a first polysilicon are used. A second step of forming a first dummy gate; a third step of forming a second dummy gate on a sidewall of the first dummy gate and the columnar semiconductor layer after the second step; After the step, a sidewall made of a fifth insulating film is formed around the second dummy gate to form a sidewall made of a fifth insulating film, and a second portion is formed above the fin-like semiconductor layer and below the columnar semiconductor layer. A fourth step of forming a diffusion layer and forming a metal and semiconductor compound on the second diffusion layer; and after the fourth step, an interlayer insulating film is deposited, and the second dummy gate and the An upper portion of the first dummy gate is exposed, and the first dummy gate is exposed. The first dummy gate and the first dummy gate are removed, a first gate insulating film is formed around the columnar semiconductor layer and inside the fifth insulating film, a first metal is deposited, and etch back is performed. And the fifth step of forming the gate electrode and the gate wiring, and using the two masks, the fin-like semiconductor layer, the columnar semiconductor layer, the first dummy gate and the second gate electrode and the gate wiring later, A dummy gate can be formed, and the number of processes can be reduced.

  Misalignment between the columnar semiconductor layer and the gate wiring can be eliminated.

  In addition, the first dummy gate and the second dummy gate are made of polysilicon, and after that, an interlayer insulating film is deposited, and then the first dummy gate and the second dummy gate are exposed by chemical mechanical polishing. Since the conventional metal gate last manufacturing method of depositing metal after etching the gate can be used, the metal gate SGT can be easily formed.

  Further, after the fifth step, the exposed first gate insulating film is removed, and a second gate insulating film is deposited around the columnar semiconductor layer, the gate electrode, and the gate wiring, and the gate A part of the second gate insulating film on the wiring is removed, a second metal is deposited, etch back is performed, the second gate insulating film on the columnar semiconductor layer is removed, and a third A metal is deposited, and the third metal and a part of the second metal are etched, whereby the second metal surrounds the upper side wall of the columnar semiconductor layer, and the first contact A sixth step of forming a second contact connecting the upper portion and the upper portion of the columnar semiconductor layer, and a third contact made of the second metal and the third metal formed on the gate wiring; By having It is not necessary to form a diffusion layer on Jo semiconductor layer top. At the same time, a contact on the gate wiring can be formed.

  After the fifth step, a hole having the same shape as the gate electrode and the gate wiring remains above the gate electrode and the gate wiring. Therefore, the exposed first gate insulating film is removed, a second gate insulating film is deposited around the columnar semiconductor layer, the gate electrode, and the gate wiring, and a part of the first gate insulating film on the gate wiring is deposited. When the gate insulating film 2 is removed, the second metal is deposited, and etch back is performed, the metal is embedded in the hole having the same shape as the gate electrode and the gate wiring, and the second metal is formed into the columnar shape by self-alignment A first contact surrounding the upper sidewall of the semiconductor layer can be formed.

  In addition, since a part of the second gate insulating film on the gate wiring is removed, a third contact for the gate wiring can be formed at the same time, and the contact for the gate wiring can be easily made. Can be formed.

  If the metal gate last process is applied to SGT, the upper part of the columnar semiconductor layer is covered with the polysilicon gate, so that it is difficult to form a diffusion layer on the upper part of the columnar semiconductor layer. Therefore, a diffusion layer is formed on the columnar semiconductor layer before forming the polysilicon gate. On the other hand, in the present invention, the diffusion layer is not formed on the upper part of the columnar semiconductor layer, and the upper part of the columnar semiconductor layer can function as an n-type semiconductor layer or a p-type semiconductor layer depending on a work function difference between the metal and the semiconductor. Therefore, it is possible to reduce the step of forming the diffusion layer on the columnar semiconductor layer.

  The gate electrode and the gate wiring can be insulated from the columnar semiconductor layer and the fin-shaped semiconductor layer by the first gate insulating film formed around and at the bottom of the gate electrode and the gate wiring. .

  In order to form the first contact, the second contact, and the third contact by filling the hole having the same shape as the gate electrode and the gate wiring above the gate electrode and the gate wiring after the fifth step, The width of the first contact in the direction orthogonal to the gate wiring is equal to the width of the third contact in the direction orthogonal to the gate wiring. The width of the first contact in the direction perpendicular to the gate wiring is equal to the width of the gate wiring in the direction perpendicular to the gate wiring. In addition, the width of the third contact in the direction perpendicular to the gate wiring is equal to the width of the gate wiring in the direction perpendicular to the gate wiring. The width of the first contact in the direction perpendicular to the gate wiring is equal to the width of the second contact in the direction perpendicular to the gate wiring.

  Therefore, the first contact, the second contact, and the third contact can eliminate misalignment in the direction orthogonal to the gate wiring.

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  Below, the manufacturing process for forming the structure of SGT which concerns on embodiment of this invention is demonstrated with reference to FIGS.

  First, a first step of forming a fin-like semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-like semiconductor layer is shown. In this embodiment, the silicon substrate is used, but a semiconductor other than silicon can be used.

  As shown in FIG. 2, a first resist 102 for forming a fin-like silicon layer is formed on the silicon substrate 101.

  As shown in FIG. 3, the silicon substrate 101 is etched to form a fin-like silicon layer 103. Although the fin-like silicon layer is formed using a resist as a mask this time, a hard mask such as an oxide film or a nitride film may be used.

  As shown in FIG. 4, the first resist 102 is removed.

  As shown in FIG. 5, a first insulating film 104 is deposited around the fin-like silicon layer 103. An oxide film formed by high-density plasma or an oxide film formed by low-pressure CVD (Chemical Vapor Deposition) may be used as the first insulating film.

  As shown in FIG. 6, the 1st insulating film 104 is etched back and the upper part of the fin-like silicon layer 103 is exposed. The process up to here is the same as the manufacturing method of the fin-like silicon layer of Non-Patent Document 2.

  Thus, the first step of forming the fin-like silicon layer 103 on the silicon substrate 101 and forming the first insulating film 104 around the fin-like silicon layer 103 is shown.

  Next, a second insulating film is formed around the fin-shaped semiconductor layer, and first polysilicon is deposited and planarized on the second insulating film to form a gate wiring and a columnar semiconductor layer. The second resist is formed in a direction perpendicular to the direction of the fin-shaped semiconductor layer, and the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer are etched to form a columnar shape. A second step of forming a semiconductor layer and a first dummy gate made of the first polysilicon is shown.

  As shown in FIG. 7, a second insulating film 105 is formed around the fin-like silicon layer 103. The second insulating film 105 is preferably an oxide film.

  As shown in FIG. 8, a first polysilicon 106 is deposited on the second insulating film 105 and planarized.

  As shown in FIG. 9, a third insulating film 107 is formed on the first polysilicon 106. The third insulating film 107 is preferably a nitride film.

  As shown in FIG. 10, a second resist 108 for forming the gate wiring and the columnar silicon layer is formed in a direction perpendicular to the direction of the fin-shaped silicon layer 103.

  As shown in FIG. 11, by etching the third insulating film 107, the first polysilicon 106, the second insulating film 105, and the fin-like silicon layer 103, the columnar silicon layer 109 and the first silicon layer 109 are etched. A first dummy gate 106 made of one polysilicon is formed. At this time, when the second resist is removed during etching, the third insulating film 107 functions as a hard mask. When the second resist is not removed during etching, the third insulating film may not be used.

  As shown in FIG. 12, the second resist 108 is removed.

  As described above, the second insulating film is formed around the fin-like semiconductor layer, the first polysilicon is deposited and planarized on the second insulating film, and the gate wiring and the columnar semiconductor layer are formed. The second resist is formed in a direction perpendicular to the direction of the fin-shaped semiconductor layer, and the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer are etched to form a columnar shape. A second step of forming a semiconductor layer and a first dummy gate made of the first polysilicon is shown.

  Next, after the second step, a fourth insulating film is formed around the columnar semiconductor layer and the first dummy gate, and second polysilicon is deposited around the fourth insulating film. , Shows a third step of forming a second dummy gate by etching and remaining on the side walls of the first dummy gate and the columnar semiconductor layer.

  As shown in FIG. 13, a fourth insulating film 110 is formed around the columnar silicon layer 109 and the first dummy gate 106. The fourth insulating film 110 is preferably an oxide film.

  As shown in FIG. 14, second polysilicon 113 is deposited around the fourth insulating film 110.

  As shown in FIG. 15, the second polysilicon 113 is etched to remain on the side walls of the first dummy gate 106 and the columnar silicon layer 109, thereby forming the second dummy gate 113.

  As described above, after the second step, the fourth insulating film is formed around the columnar semiconductor layer and the first dummy gate, and the second polysilicon is deposited around the fourth insulating film. The third step of forming the second dummy gate by etching is left on the side walls of the first dummy gate and the columnar semiconductor layer.

  Next, a fifth insulating film is formed around the second dummy gate, etched, and left in a sidewall shape to form a sidewall made of the fifth insulating film, and the fin shape A fourth step is shown in which a second diffusion layer is formed on the upper part of the semiconductor layer and the lower part of the columnar semiconductor layer, and a compound of metal and semiconductor is formed on the second diffusion layer.

  As shown in FIG. 16, a fifth insulating film 114 is formed around the second dummy gate 113. The fifth insulating film 114 is preferably a nitride film.

  As shown in FIG. 17, the fifth insulating film 114 is etched and left in the shape of a sidewall to form a sidewall 114 made of the fifth insulating film.

  As shown in FIG. 18, impurities are introduced to form a second diffusion layer 115 above the fin-like silicon layer 103 and below the columnar silicon layer 109. In the case of an n-type diffusion layer, it is preferable to introduce arsenic or phosphorus. In the case of a p-type diffusion layer, it is preferable to introduce boron. Impurity introduction may be performed before the fifth insulating film is formed.

  As shown in FIG. 19, a metal-semiconductor compound 116 is formed on the second diffusion layer 115. At this time, a metal-semiconductor compound 117 is also formed on the second dummy gate 113.

  As described above, a fifth insulating film is formed around the second dummy gate, etched, and left in a sidewall shape to form a sidewall made of the fifth insulating film. A fourth step is shown in which a second diffusion layer is formed in the upper part of the semiconductor layer and the lower part of the columnar semiconductor layer, and a compound of metal and semiconductor is formed on the second diffusion layer.

  Next, after the fourth step, an interlayer insulating film is deposited, and the upper portions of the second dummy gate and the first dummy gate are exposed, and the second dummy gate and the first dummy gate are exposed. A fifth step of forming a first gate insulating film around the columnar semiconductor layer and inside the fifth insulating film, depositing a first metal, and forming a gate electrode and a gate wiring. Show.

  As shown in FIG. 20, a contact stopper film 118 is deposited, and an interlayer insulating film 119 is deposited. The contact stopper film 118 is preferably a nitride film. Further, when the contact hole etching can be controlled, the contact stopper film may not be used.

  As shown in FIG. 21, chemical mechanical polishing is performed to expose the upper portion of the second dummy gate and the first dummy gate. At this time, the metal-semiconductor compound 117 formed on the second dummy gate 113 is removed.

  As shown in FIG. 22, the second dummy gate 113 and the first dummy gate 106 are removed.

  As shown in FIG. 23, the second insulating film 105 and the fourth insulating film 110 are removed.

  As shown in FIG. 24, a first gate insulating film 120 is formed around the columnar silicon layer 109 and inside the fifth insulating film 114, and a first metal 121 is deposited. A gate electrode 121 a is formed around the columnar silicon layer 109. In addition, the gate wiring 121b is formed. The gate electrode 121a and the gate wiring 121b are insulated from the columnar silicon layer 109 and the fin-shaped silicon layer 103 by the first gate insulating film 120 formed around and at the bottom of the gate electrode 121a and the gate wiring 121b. Can do.

  As shown in FIG. 25, the first metal 121 is etched back to expose the upper portion of the columnar silicon layer 109.

  As described above, after the fourth step, an interlayer insulating film is deposited, and the upper portions of the second dummy gate and the first dummy gate are exposed, and the second dummy gate and the first dummy gate are exposed. A fifth step of forming a first gate insulating film around the columnar semiconductor layer and inside the fifth insulating film, depositing a first metal, and forming a gate electrode and a gate wiring. Indicated.

  Next, a second gate insulating film is deposited around the columnar semiconductor layer, on the gate electrode, and on the gate wiring, a part of the second gate insulating film on the gate wiring is removed, and a second gate insulating film is removed. Metal is deposited, etch back is performed, the second gate insulating film on the columnar semiconductor layer is removed, a third metal is deposited, and the third metal and a part of the second metal are deposited. Etching allows a second metal to surround the columnar semiconductor layer upper sidewall, a second contact connecting the upper portion of the first contact and the columnar semiconductor layer, and the gate wiring 6 shows a sixth step of forming a third contact made of the second metal and the third metal formed above.

  As shown in FIG. 26, the exposed first gate insulating film 120 is removed.

  As shown in FIG. 27, a second gate insulating film 123 is deposited around the pillar-shaped silicon layer 109 and on the gate electrode 121a and the gate wiring 121b.

  As shown in FIG. 28, a third resist 124 for removing a part of the second gate insulating film 123 on the gate wiring 121b is formed.

  As shown in FIG. 29, a part of the second gate insulating film 123 on the gate wiring 121b is removed.

  As shown in FIG. 30, the third resist 124 is removed.

  As shown in FIG. 31, the 2nd metal 125 is deposited. The metal work function of the second metal 125 is preferably between 4.0 eV and 4.2 eV when the transistor is n-type. The work function of the second metal 126 is preferably 5.0 eV to 5.2 eV when the transistor is p-type.

  As shown in FIG. 32, the second metal 125 is etched back to expose the second gate insulating film 123 on the columnar silicon layer 109.

  As shown in FIG. 33, the second gate insulating film 123 on the exposed columnar silicon layer 109 is removed.

  As shown in FIG. 34, a third metal 126 is deposited. The third metal may be the same metal as the second metal.

  As shown in FIG. 35, the 4th resist 127 for forming a contact hole is formed.

  As shown in FIG. 36, the interlayer insulating film 119 and the contact stopper film 118 are etched to form a contact hole 128.

  As shown in FIG. 37, the 4th resist 127 is removed.

  As shown in FIG. 38, the 4th metal 130 for metal wiring is deposited. At this time, a contact 129 is formed.

  As shown in FIG. 39, metal wiring is formed, and fifth resists 131, 132, and 133 for etching part of the third metal 126 and the second metal 125 are formed.

  As shown in FIG. 40, the 4th metal 130 is etched and the metal wiring 134, 135, 136 is formed. Further, by etching a part of the third metal 126 and the second metal 125, the second metal 125 surrounds the upper side wall of the columnar silicon layer 109, and the first contact 125a A second contact 126a connecting the upper portion and the upper portion of the columnar silicon layer 109, and a third contact 137 made of the second metal 125b and the third metal 126b formed on the gate wiring 121b are formed. Before the metal wiring is formed, part of the third metal 126 and the second metal 125 may be etched. Therefore, the first contact, the second contact, and the third contact can eliminate misalignment in the direction orthogonal to the gate wiring.

  A diffusion layer is not formed on the columnar silicon layer 109, but the columnar silicon layer upper portion can function as an n-type silicon layer or a p-type silicon layer depending on a work function difference between the second metal and silicon. Therefore, it is possible to reduce the step of forming the diffusion layer on the columnar silicon layer.

  As shown in FIG. 41, the fifth resists 131, 132, 133 are removed.

  As described above, the second gate insulating film is deposited around the columnar semiconductor layer, on the gate electrode, and on the gate wiring, and a part of the second gate insulating film on the gate wiring is removed, and the second gate insulating film is removed. Metal is deposited, etch back is performed, the second gate insulating film on the columnar semiconductor layer is removed, a third metal is deposited, and the third metal and a part of the second metal are deposited. Etching allows a second metal to surround the columnar semiconductor layer upper sidewall, a second contact connecting the upper portion of the first contact and the columnar semiconductor layer, and the gate wiring A sixth step of forming a third contact made of the second metal and the third metal formed thereon is shown.

  As described above, the fin-shaped semiconductor layer, the columnar semiconductor layer, the gate electrode and the gate wiring are formed with two masks, and is a gate last process, and the upper part of the columnar semiconductor layer is self-aligned by the work function difference between the metal and the semiconductor. A method for manufacturing an SGT having a structure that functions as an n-type semiconductor layer or a p-type semiconductor layer is shown.

A structure of a semiconductor device obtained by the manufacturing method is shown in FIG.
A fin-like silicon layer 103 formed on the silicon substrate 101, a first insulating film 104 formed around the fin-like silicon layer 103, and a columnar silicon layer 109 formed on the fin-like silicon layer 103. A first gate insulating film 120 formed around the columnar silicon layer 109, a gate electrode 121a made of metal formed around the first gate insulating film 120, and connected to the gate electrode 121a A gate wiring 121b made of a metal extending in a direction perpendicular to the finned silicon layer 103, and the gate electrode 121a and the first gate insulating film 120 formed around and at the bottom of the gate wiring 121b. Here, the width of the outside of the gate electrode 121a and the width of the gate wiring 121b are the same, and the fin-like silicon 103, a second diffusion layer 115 formed below the columnar silicon layer 109, a second gate insulating film 123 formed around the upper sidewall of the columnar silicon layer 109, and the second A first contact 125 a made of a second metal formed around the gate insulating film 123, and a second metal made of a third metal that connects the upper portion of the first contact 125 a and the upper portion of the columnar silicon layer 109. And a third contact 137 made of the second metal and the third metal formed on the gate wiring 121b.

  In order to form the first contact, the second contact, and the third contact by filling the hole having the same shape as the gate electrode and the gate wiring above the gate electrode and the gate wiring after the fifth step, The width of the first contact in the direction orthogonal to the gate wiring is equal to the width of the third contact in the direction orthogonal to the gate wiring. The width of the first contact in the direction perpendicular to the gate wiring is equal to the width of the gate wiring in the direction perpendicular to the gate wiring. In addition, the width of the third contact in the direction perpendicular to the gate wiring is equal to the width of the gate wiring in the direction perpendicular to the gate wiring. The width of the first contact in the direction perpendicular to the gate wiring is equal to the width of the second contact in the direction perpendicular to the gate wiring.

  Therefore, the first contact, the second contact, and the third contact can eliminate misalignment in the direction orthogonal to the gate wiring.

  In the present invention, the diffusion layer is not formed on the columnar silicon layer 109, and the columnar silicon layer 109 can function as an n-type silicon layer or a p-type silicon layer depending on a work function difference between the second metal 125 and silicon. it can. Therefore, it is possible to reduce the step of forming the diffusion layer on the columnar silicon layer.

  When the work function of the second metal 125 is between 4.0 eV and 4.2 eV, the work function of the n-type silicon is in the vicinity of 4.05 eV, so that the upper part of the columnar silicon layer 109 functions as n-type silicon. To do. In this case, as the second metal, for example, a compound of tantalum and titanium (TaTi) or tantalum nitride (TaN) is preferable.

  When the work function of the second metal 125 is between 5.0 eV and 5.2 eV, the work function of the p-type silicon is in the vicinity of 5.15 eV, so that the upper part of the columnar silicon layer 106 functions as p-type silicon. To do. In this case, for example, ruthenium (Ru) or titanium nitride (TiN) is preferable as the second metal.

  In addition, the gate electrode 121a and the gate wiring 121b include the columnar silicon layer 109, the fin-shaped silicon layer 103, and the first gate insulating film 120 formed around and at the bottom of the gate electrode 121a and the gate wiring 121b. Can be insulated from.

  Since it is formed by self-alignment, misalignment between the columnar silicon layer 109 and the gate wiring 121b can be eliminated.

  It should be noted that the present invention can be variously modified and modified without departing from the broad spirit and scope of the present invention. Further, the above-described embodiment is for explaining an example of the present invention, and does not limit the scope of the present invention.

For example, in the above embodiment, a method of manufacturing a semiconductor device in which p-type (including p ⁺ -type) and n-type (including n ⁺ -type) are opposite in conductivity type, and a semiconductor obtained thereby An apparatus is naturally included in the technical scope of the present invention.

101. Silicon substrate 102. First resist 103. Fin-like silicon layer 104. First insulating film 105. Second insulating film 106. First polysilicon, first dummy gate 107. Third insulating film 108. Second resist 109. Columnar silicon layer 110. Fourth insulating film 113. Second polysilicon, second dummy gate 114. Side wall 115. Made of fifth insulating film, fifth insulating film. Second diffusion layer 116. Compound of metal and semiconductor 117. Compound of metal and semiconductor 118. Contact stopper film 119. Interlayer insulating film 120. First gate insulating film 121. First metal 121a. Gate electrode 121b. Gate wiring 123. Second gate insulating film 124. Third resist 125. Second metal 125a. First contact 125b. Second metal 126. Third metal 126a. Second contact 126b. Third metal 127. Fourth resist 128. Contact hole 129. Contact 130. Fourth metal 131. Fifth resist 132. Fifth resist 133. Fifth resist 134. Metal wiring 135. Metal wiring 136. Metal wiring 137. Third contact

Claims (1)

A fin-like semiconductor layer formed on a semiconductor substrate;
A first insulating film formed around the fin-like semiconductor layer;
A columnar semiconductor layer formed on the fin-shaped semiconductor layer;
A first gate insulating film formed around the columnar semiconductor layer;
A gate electrode made of metal formed around the first gate insulating film;
A gate wiring made of a metal extending in a direction orthogonal to the fin-like semiconductor layer connected to the gate electrode;
A second gate insulating film formed around the upper sidewall of the columnar semiconductor layer;
A first contact made of a second metal formed around the second gate insulating film;
A third contact including the second metal formed on the gate wiring;
The second gate insulating film further formed under the first contact;
Have
The semiconductor device, wherein an upper portion of the first contact and an upper portion of the columnar semiconductor layer are electrically connected.

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