KR20130110181A - Method for manufacturing semiconductor device and semiconductor device - Google Patents

Method for manufacturing semiconductor device and semiconductor device Download PDF

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Publication number
KR20130110181A
KR20130110181A KR1020137011996A KR20137011996A KR20130110181A KR 20130110181 A KR20130110181 A KR 20130110181A KR 1020137011996 A KR1020137011996 A KR 1020137011996A KR 20137011996 A KR20137011996 A KR 20137011996A KR 20130110181 A KR20130110181 A KR 20130110181A
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silicon layer
fin
insulating film
forming
polysilicon gate
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KR1020137011996A
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Korean (ko)
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후지오 마스오카
히로키 나카무라
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유니산티스 일렉트로닉스 싱가포르 프라이빗 리미티드
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Publication of KR20130110181A publication Critical patent/KR20130110181A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)

Abstract

It is an object of the present invention to reduce the parasitic capacitance between the gate wiring and the substrate, and to provide a manufacturing method of the SGT which is the gate last process and the resulting SGT structure.
Forming a fin silicon layer on the silicon substrate, forming a first insulating film around the fin silicon layer, and forming a columnar silicon layer on the fin silicon layer; Forming a diffusion layer by implanting impurities into an upper part of the columnar silicon layer, an upper part of the fin silicon layer, and a lower part of the columnar silicon layer, and then forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring after the step; Forming a silicide on the diffusion layer above the fin-shaped silicon layer after the step; and depositing an interlayer insulating film after the step, exposing the polysilicon gate electrode and the polysilicon gate wiring, After etching the polysilicon gate electrode and the polysilicon gate wiring, the metal is withdrawn And solves the above problems by a process and a subsequent step of the process, it forms a contact form a metal gate electrode and the gate metal wiring.

Figure P1020137011996

Description

TECHNICAL MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device.

BACKGROUND OF THE INVENTION Semiconductor integrated circuits, particularly integrated circuits using MOS transistors, are becoming increasingly integrated. With this high integration, the MOS transistor used therein has been miniaturized to the nano-region. When the miniaturization of the MOS transistor proceeds, it is difficult to suppress the leakage current, and there is a problem that the occupied area of the circuit can hardly be reduced due to the request for securing the required amount of current. In order to solve such a problem, a SGT (Surrounding Gate Transistor) having a structure in which a source, a gate, and a drain are arranged in a vertical direction with respect to a substrate and the gate surrounds a columnar semiconductor layer has been proposed (for example, a patent document) 1, Patent Document 2, Patent Document 3).

By using metal instead of polysilicon for the gate electrode, depletion can be suppressed and the gate electrode can be made low in resistance. However, the subsequent process of forming the metal gate always needs to be a manufacturing process in consideration of metal contamination by the metal gate.

In addition, in the conventional MOS transistor, in order to make both the metal gate process and the high temperature process compatible, the metal gate last process of creating a metal gate after the high temperature process is used in actual products ( Non Patent Literature 1). After the gate is made of polysilicon, an interlayer insulating film is deposited thereafter, the polysilicon gate is exposed by chemical mechanical polishing, the polysilicon gate is etched, and the metal is deposited. Therefore, also in SGT, in order to make a metal gate process compatible with a high temperature process, it is necessary to use the metal gate last process which creates a metal gate after a high temperature process. In the SGT, since the upper portion of the pillar-shaped silicon layer is at a position higher than the gate, research for utilizing the metal gate last process is required.

Moreover, in order to reduce the parasitic capacitance between a gate wiring and a board | substrate, the 1st insulating film is used in the conventional MOS transistor. For example, in a FIN FET (Non-Patent Document 2), a first insulating film is formed around one fin semiconductor layer, the first insulating film is etched back, and the fin semiconductor layer is exposed to expose the gate. The parasitic capacitance between the wiring and the substrate is reduced. Therefore, also in SGT, it is necessary to use a 1st insulating film in order to reduce the parasitic capacitance between a gate wiring and a board | substrate. In SGT, since there is a columnar semiconductor layer in addition to the fin semiconductor layer, research for forming a columnar semiconductor layer is necessary.

(Prior art technical literature)

(Patent Literature)

Patent Document 1: Japanese Patent Laid-Open No. 2-71556

Patent Document 2: Japanese Patent Laid-Open No. 2-188966

Patent document 3: Unexamined-Japanese-Patent No. 3-145761

(Non-patent document)

Non-Patent Document 1: IEDM 2007 K.Mistry et.al, pp 247-250

Non-Patent Document 2: IEDM 2010 CC.Wu, et.al, 27.1.1-27.1.4.

Therefore, an object of the present invention is to reduce the parasitic capacitance between the gate wiring and the substrate, and to provide a manufacturing method of the SGT, which is a gate last process, and the resulting structure of the SGT.

A method of manufacturing a semiconductor device of the present invention includes:

Forming a fin silicon layer on a silicon substrate, forming a first insulating film around the fin silicon layer,

A first step of forming a columnar silicon layer on top of the fin silicon layer, the diameter of the columnar silicon layer being the same as the width of the fin silicon layer;

After the first step,

A second step of forming a diffusion layer by injecting impurities into the columnar silicon layer, the upper part of the fin silicon layer, and the lower part of the columnar silicon layer;

After the second process,

A third process of creating a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring, wherein the gate insulating film covers the periphery and the upper portion of the columnar silicon layer, the polysilicon gate electrode covers the gate insulating film, and the polysilicon The third process, wherein the upper surface of the polysilicon after the gate electrode and the polysilicon gate wiring is formed is higher than the gate insulating film on the diffusion layer above the columnar silicon layer;

After the third process,

A fourth step of forming a silicide on the diffusion layer on the fin silicon layer;

After the fourth process,

Depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and depositing metal to deposit the metal gate electrode and the metal gate wiring As a fifth process for forming, wherein said metal gate wiring extends in a direction orthogonal to said pinned silicon layer connected to said metal gate electrode, and

After the fifth process,

A sixth step of forming a contact, The sixth step of directly connecting the diffusion layer and the contact on the columnar silicon layer.

.

Furthermore, a first resist for forming a fin silicon layer on a silicon substrate is formed,

Etching a silicon substrate, forming the fin-like silicon layer, removing the first resist,

Depositing a first insulating film around the fin silicon layer, etching back the first insulating film, exposing an upper portion of the fin silicon layer, and forming a second resist to be orthogonal to the fin silicon layer, The columnar silicon layer is formed by etching the fin silicon layer and removing the second resist so that the portion where the fin silicon layer and the second resist are orthogonal is the columnar silicon layer. do.

Moreover, in the structure which has a fin silicon layer formed on the silicon substrate, the 1st insulating film formed around the said fin silicon layer, and the columnar silicon layer formed on the said fin silicon layer,

A second oxide film is deposited, a first nitride film is formed on the second oxide film, the first nitride film is etched, remains in a sidewall shape, impurities are implanted, and an upper portion of the pillar-shaped silicon layer and the fin shape are formed. A diffusion layer is formed on the silicon layer, the first nitride film and the second oxide film are removed, and heat treatment is performed.

Further, a fin silicon layer formed on the silicon substrate, a first insulating film formed around the fin silicon layer, a columnar silicon layer formed on the fin silicon layer,

A diffusion layer formed on an upper portion of the fin silicon layer and a lower portion of the columnar silicon layer;

Diffusion layer formed on top of the columnar silicon layer

In the structure having

Forming a gate insulating film, depositing polysilicon, planarizing the upper surface of the polysilicon after planarizing the polysilicon so as to be at a position higher than the gate insulating film on the diffusion layer above the columnar silicon layer, and depositing a second nitride film Forming a third resist for forming a polysilicon gate electrode and a polysilicon gate wiring, etching the second nitride film, and etching the polysilicon to form the polysilicon gate electrode and the polysilicon gate wiring; And etching the gate insulating film to remove the third resist.

In addition, a third nitride film is deposited, the third nitride film is etched to remain in a sidewall shape, metal is deposited, and silicide is formed on the upper part of the diffusion layer above the fin-like silicon layer.

In addition, a fourth nitride film is deposited, an interlayer insulating film is deposited and planarized, a polysilicon gate electrode and a polysilicon gate wiring are exposed, the polysilicon gate electrode and the polysilicon gate wiring are removed, and the polysilicon gate electrode is removed. And embedding a metal in a portion where the polysilicon gate wiring was present, etching the metal, and exposing a gate insulating film on the diffusion layer on the columnar silicon layer to form a metal gate electrode and a metal gate wiring.

In addition, the semiconductor device of the present invention,

A pin-shaped silicon layer formed on the silicon substrate,

A first insulating film formed around the fin silicon layer;

A columnar silicon layer formed on the fin silicon layer, the diameter of the columnar silicon layer being equal to the width of the fin silicon layer;

A diffusion layer formed on an upper portion of the fin silicon layer and a lower portion of the columnar silicon layer;

A diffusion layer formed on the columnar silicon layer;

A silicide formed on an upper portion of the diffusion layer on the fin silicon layer;

A gate insulating film formed around the columnar silicon layer;

A metal gate electrode formed around the gate insulating film,

A metal gate wiring extending in a direction orthogonal to the fin silicon layer connected to the metal gate electrode;

Has a contact formed on the diffusion layer formed on the columnar silicon layer,

The diffusion layer formed on the columnar silicon layer and the contact are directly connected.

According to the present invention, the parasitic capacitance between the gate wiring and the substrate can be reduced, and the manufacturing method of the SGT which is the gate last process and the resulting SGT structure can be provided.

Since the formation of the fin-like silicon layer, the first insulating film, and the pillar-like silicon layer is based on the conventional manufacturing method of the FIN FET, it can be easily formed.

In the past, silicide was formed on the columnar silicon layer, but since the deposition temperature of the polysilicon is higher than the temperature for forming the silicide, the silicide must be formed after the polysilicon gate is formed. If desired, after the polysilicon gate is formed, a number of manufacturing steps are performed in which a hole is formed in the upper portion of the polysilicon gate electrode, a sidewall of the insulating film is formed on the sidewall of the hole, and then silicide is formed and the insulating film is embedded in the drilled hole. Since there was a drawback of increasing the polysilicon gate electrode, the diffusion layer was formed before the polysilicon gate electrode and the polysilicon gate wiring were formed, the columnar silicon layer was covered with the polysilicon gate electrode, and the silicide was formed only on the fin silicon layer, thereby forming polysilicon. To write the gate, and that After depositing the interlayer insulating film, the conventional method for producing a metal gate last, which exposes the polysilicon gate by chemical mechanical polishing, etches the polysilicon gate, and deposits the metal, can be used. It can be formed easily.

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(A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention, (b) is sectional drawing in the X-X 'line | wire of (a), (c) is Y-Y of (a) It is sectional drawing in X-ray.
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(A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention, (b) is sectional drawing in the X-X 'line | wire of (a), (c) is Y-Y of (a) It is sectional drawing in X-ray.
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(A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention, (b) is sectional drawing in the X-X 'line | wire of (a), (c) is Y-Y of (a) It is sectional drawing in X-ray.
(A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention, (b) is sectional drawing in the X-X 'line | wire of (a), (c) is Y-Y of (a) It is sectional drawing in X-ray.
(A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention, (b) is sectional drawing in the X-X 'line | wire of (a), (c) is Y-Y of (a) It is sectional drawing in X-ray.
(A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention, (b) is sectional drawing in the X-X 'line of (a), (c) is Y-Y of (a). It is sectional drawing in X-ray.
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(A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention, (b) is sectional drawing in the X-X 'line of (a), (c) is Y-Y of (a). It is sectional drawing in X-ray.
(A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention, (b) is sectional drawing in the X-X 'line | wire of (a), (c) is Y-Y of (a) It is sectional drawing in X-ray.
(A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention, (b) is sectional drawing in the X-X 'line | wire of (a), (c) is Y-Y of (a) It is sectional drawing in X-ray.
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(A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention, (b) is sectional drawing in the X-X 'line | wire of (a), (c) is Y-Y of (a) It is sectional drawing in X-ray.
(A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention, (b) is sectional drawing in the X-X 'line | wire of (a), (c) is Y-Y of (a) It is sectional drawing in X-ray.

Hereinafter, the manufacturing process for forming the structure of SGT which concerns on embodiment of this invention is demonstrated with reference to FIGS.

A manufacturing method is described first in which a fin silicon layer is formed on a silicon substrate, a first insulating film is formed around the fin silicon layer, and a columnar silicon layer is formed on the fin silicon layer. As shown in FIG. 2, a first resist 102 for forming a fin silicon layer on the silicon substrate 101 is formed.

As shown in FIG. 3, the silicon substrate 101 is etched to form a fin silicon layer 103. This time, a fin silicon layer was formed using a resist as a mask, but a hard mask such as an oxide film or a nitride film may be used.

As shown in FIG. 4, the first resist 102 is removed.

As shown in FIG. 5, the first insulating film 104 is deposited around the fin silicon layer 103. As the first insulating film, an oxide film by high density plasma or an oxide film by low pressure chemical vapor deposition may be used.

As shown in FIG. 6, the first insulating film 104 is etched back to expose the upper portion of the fin silicon layer 103. Up to now, it is the same as the manufacturing method of the fin silicon layer of patent document 2. As shown in FIG.

As shown in FIG. 7, the second resist 105 is formed to be orthogonal to the fin silicon layer 103. The portion where the fin silicon layer 103 and the resist 105 are orthogonal is a portion which becomes a columnar silicon layer. Since the line-shaped resist can be used, the resist is unlikely to collapse after the pattern, resulting in a stable process.

As shown in FIG. 8, the fin silicon layer 103 is etched. The portion where the fin silicon layer 103 and the second resist 105 are orthogonal becomes the columnar silicon layer 106. Therefore, the diameter of the columnar silicon layer 106 becomes equal to the width of the fin silicon layer. The columnar silicon layer 106 is formed on the fin silicon layer 103, and the first insulating film 104 is formed around the fin silicon layer 103.

As shown in FIG. 9, the second resist 105 is removed.

Next, the manufacturing method for forming a diffusion layer by injecting an impurity into an upper part of a columnar silicon layer, an upper part of a fin type silicon layer, and a lower part of a columnar silicon layer for gate last is shown. As shown in FIG. 10, the 2nd oxide film 107 is deposited and the 1st nitride film 108 is formed. After that, since the upper portion of the columnar silicon layer is covered with the gate insulating film and the polysilicon gate electrode, a diffusion layer is formed over the columnar silicon layer before being covered.

As illustrated in FIG. 11, the first nitride film 108 is etched to remain in the sidewall shape.

As shown in FIG. 12, impurities such as arsenic, phosphorus, and boron are implanted to form the diffusion layers 110 on the columnar silicon layer and the diffusion layers 109 and 111 on the fin silicon layer 103.

As shown in FIG. 13, the first nitride film 108 and the second oxide film 107 are removed.

As shown in FIG. 14, heat treatment is performed. The diffusion layers 109 and 111 on the fin silicon layer 103 are in contact with each other to become the diffusion layer 112. In order to perform the gate last from the above, impurities were injected into the upper part of the columnar silicon layer, the upper part of the fin silicon layer, and the lower part of the columnar silicon layer to form the diffusion layers 110 and 112.

Next, in order to make a gate last, the manufacturing method which produces polysilicon gate electrode and polysilicon gate wiring from polysilicon is shown. Since the interlayer insulating film is deposited for the gate last, the polysilicon gate electrode and the polysilicon gate wiring are exposed by chemical mechanical polishing. Therefore, it is necessary to prevent the upper part of the columnar silicon layer from being exposed by chemical mechanical polishing. .

As shown in FIG. 15, the gate insulating film 113 is formed, and the polysilicon 114 is deposited and planarized. The upper surface of the polysilicon after planarization is set to a position higher than that of the gate insulating film 113 on the diffusion layer 110 on the columnar silicon layer 106. Thus, after the interlayer insulating film is deposited for the gate last, when the polysilicon gate electrode and the polysilicon gate wiring are exposed by chemical mechanical polishing, the upper part of the columnar silicon layer is not exposed by chemical mechanical polishing.

In addition, the second nitride film 115 is deposited. The second nitride film 115 is a film that inhibits the formation of silicide on the polysilicon gate electrode and the polysilicon gate wiring when silicide is formed on the fin silicon layer.

As shown in Fig. 16, a third resist 116 for forming a polysilicon gate electrode and a polysilicon gate wiring is formed. It is preferable that the part which becomes a gate wiring with respect to the fin silicon layer 103 orthogonally crosses. This is to reduce the parasitic capacitance between the gate wiring and the substrate.

As shown in FIG. 17, the second nitride film 115 is etched.

As shown in FIG. 18, the polysilicon 114 is etched to form the polysilicon gate electrode 114a and the polysilicon gate wiring 114b.

As shown in FIG. 19, the gate insulating film 113 is etched.

As shown in FIG. 20, the third resist 116 is removed.

In order to make a gate last by the above, the manufacturing method which forms a polysilicon gate electrode and a polysilicon gate wiring from polysilicon was shown. The upper surface of the polysilicon after the polysilicon gate electrode 114a and the polysilicon gate wiring 114b is formed is at a position higher than the gate insulating film 113 on the diffusion layer 110 above the columnar silicon layer 106.

Next, the manufacturing method which forms a silicide on the fin-like silicon layer is shown. Silicide is not formed on the polysilicon gate electrode 114a and the polysilicon gate wiring 114b and the diffusion layer 110 on the columnar silicon layer 106. If silicide is formed in the diffusion layer 110 on the columnar silicon layer 106, the manufacturing process increases.

As shown in FIG. 21, the 3rd nitride film 117 is deposited.

As shown in FIG. 22, the third nitride film 117 is etched to remain in the sidewall shape.

As shown in FIG. 23, metals such as nickel and cobalt are deposited, and the silicide 118 is formed on the upper part of the diffusion layer 112 on the upper portion of the fin silicon layer 103. At this time, the polysilicon gate electrode 114a and the polysilicon gate wiring 114b are covered with the third nitride film 117 and the second nitride film 115, and the diffusion layer 110 on the columnar silicon layer 106 is Since it is covered with the gate insulating film 113, the polysilicon gate electrode 114a, and the polysilicon gate wiring 114b, silicide is not formed.

As mentioned above, the manufacturing method which forms a silicide on the fin-like silicon layer upper part was shown.

Next, after depositing the interlayer insulating film, the polysilicon gate electrode and the polysilicon gate wiring are exposed by chemical mechanical polishing, the polysilicon gate electrode and the polysilicon gate wiring are etched, and then a gate last is prepared for depositing the metal. The method is shown.

As shown in FIG. 24, in order to protect the silicide 118, the 4th nitride film 140 is deposited.

As shown in FIG. 25, the interlayer insulation film 119 is deposited and planarized by chemical mechanical polishing.

As shown in FIG. 26, the polysilicon gate electrode 114a and the polysilicon gate wiring 114b are exposed by chemical mechanical polishing.

As shown in FIG. 27, the polysilicon gate electrode 114a and the polysilicon gate wiring 114b are etched. Wet etching is preferred.

As shown in FIG. 28, the metal 120 is deposited and planarized, and the metal 120 is embedded in the part where the polysilicon gate electrode 114a and the polysilicon gate wiring 114b existed. It is preferable to use atomic layer deposition.

As shown in FIG. 29, the metal 120 is etched to expose the gate insulating film 113 on the diffusion layer 106 on the columnar silicon layer 106. The metal gate electrode 120a and the metal gate wiring 120b are formed. After depositing an interlayer insulating film, the method of manufacturing the gate last which exposes a polysilicon gate by chemical mechanical polishing, etches a polysilicon gate, and deposits metal is shown.

Next, the manufacturing method for forming a contact is shown. Since no silicide is formed in the diffusion layer 110 on the columnar silicon layer 106, the contact and the diffusion layer 110 on the columnar silicon layer 106 are directly connected. As shown in FIG. 30, the interlayer insulation film 121 is deposited and planarized.

As shown in FIG. 31, the fourth resist 122 for forming a contact hole on the columnar silicon layer 106 is formed.

As shown in FIG. 32, the interlayer insulation film 121 is etched and the contact hole 123 is formed.

As shown in FIG. 33, the fourth resist 122 is removed.

As shown in FIG. 34, a fifth resist 124 is formed on the metal gate wiring 120b and on the fin silicon layer 103 to form contact holes.

As shown in FIG. 35, the interlayer insulating films 121 and 119 are etched to form contact holes 125 and 126.

As shown in Fig. 36, the fifth resist 124 is removed.

As shown in FIG. 37, the nitride film 140 and the gate insulating film 113 are etched to expose the silicide 118 and the diffusion layer 110.

As shown in FIG. 38, metal is deposited to form contacts 143, 127, and 128. As shown in FIG. The manufacturing method for forming a contact by the above was shown. Since no silicide is formed in the diffusion layer 110 on the columnar silicon layer 106, the contact 127 and the diffusion layer 110 on the columnar silicon layer 106 are directly connected.

Next, the manufacturing method for forming a metal wiring layer is shown.

As shown in FIG. 39, the metal 129 is deposited.

As shown in Fig. 40, sixth resists 130, 131, and 132 for forming metal wirings are formed.

As shown in FIG. 41, the metal 129 is etched to form metal wirings 133, 134, and 135.

As shown in FIG. 42, the sixth resists 130, 131, and 132 are removed.

The manufacturing method for forming a metal wiring layer by the above was shown.

The result of the said manufacturing method is shown in FIG.

A fin-shaped silicon layer 103 formed on the substrate 101,

A first insulating film 104 formed around the fin silicon layer 103,

A columnar silicon layer 106 formed on the fin silicon layer 103, the diameter of the columnar silicon layer 106 being the same as the columnar silicon layer 106, the same as the width of the fin silicon layer 103; ,

A diffusion layer 112 formed on the upper portion of the fin-shaped silicon layer 103 and the lower portion of the columnar silicon layer 106,

The diffusion layer 110 formed on the columnar silicon layer 106,

A silicide 118 formed on the diffusion layer 112 on the upper portion of the fin silicon layer 103,

A gate insulating film 113 formed around the columnar silicon layer 106,

A metal gate electrode 120a formed around the gate cutting film,

A metal gate wiring 120b extending in a direction orthogonal to the fin silicon layer 103 connected to the metal gate electrode 120a;

Having a contact 127 formed on the diffusion layer 110,

The diffusion layer 110 and the contact 127 are structured to directly connect.

As mentioned above, the parasitic capacitance between a gate wiring and a board | substrate can be reduced, and the manufacturing method of SGT which is a gate last process, and the structure of the resultant SGT can be provided.

101 silicon substrate 102 resist
103: fin-like silicon layer 104: first insulating film
105: resist 106: columnar silicon layer
107: oxide film 108: film inhibiting impurity implantation
109: diffusion layer 110: diffusion layer
111 diffusion layer 112 diffusion layer
113: gate insulating film 114: polysilicon
114a: Polysilicon Gate Electrode 114b: Polysilicon Gate Wiring
115: nitride film 116 resist
117: nitride film 118: silicide
119: interlayer insulating film 120: metal
121: interlayer insulating film 122: resist
123: contact hole 124: resist
125: contact hole 126: contact hole
127: contact 128: contact
129 metal 130 resist
131: resist 132: resist
133: metal wiring 134: metal wiring
135 metal wiring 140 nitride film
143: Contact

Claims (7)

Forming a fin silicon layer on the silicon substrate, forming a first insulating film around the fin silicon layer,
A first step of forming a columnar silicon layer on top of the fin silicon layer, the diameter of the columnar silicon layer being the same as the width of the fin silicon layer;
After the first step,
A second step of forming a diffusion layer by injecting impurities into the columnar silicon layer, the upper part of the fin silicon layer, and the lower part of the columnar silicon layer;
After the second process,
A third step of creating a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring, wherein the gate insulating film covers the periphery and the upper portion of the columnar silicon layer, the polysilicon gate electrode covers the gate insulating film, and the polysilicon gate An upper surface of the polysilicon after the electrode and the polysilicon gate wiring is formed, the third process being a position higher than the gate insulating film on the diffusion layer above the columnar silicon layer;
After the third process,
A fourth step of forming a silicide on the diffusion layer on the fin silicon layer;
After the fourth process,
An interlayer insulating film is deposited, the polysilicon gate electrode and the polysilicon gate wiring are exposed, the polysilicon gate electrode and the polysilicon gate wiring are etched, and then metal is deposited to deposit the metal gate electrode and the metal gate wiring. As a fifth process for forming, wherein said metal gate wiring extends in a direction orthogonal to said pinned silicon layer connected to said metal gate electrode, and
After the fifth process,
A sixth step of forming a contact, The sixth step of directly connecting the diffusion layer and the contact on the columnar silicon layer.
And a step of forming a semiconductor layer on the semiconductor substrate.
The method of claim 1,
Forming a first resist for forming a fin silicon layer on the silicon substrate, etching the silicon substrate, forming the fin silicon layer, removing the first resist,
Depositing a first insulating film around the fin silicon layer, etching back the first insulating film, exposing an upper portion of the fin silicon layer, and forming a second resist so as to be orthogonal to the fin silicon layer, The columnar silicon layer is formed by etching the fin silicon layer and removing the second resist so that the portion where the fin silicon layer and the second resist are orthogonal is the columnar silicon layer. The manufacturing method of the semiconductor device.
The method of claim 1,
In a structure having a fin silicon layer formed on a silicon substrate, a first insulating film formed around the fin silicon layer, and a columnar silicon layer formed on the fin silicon layer,
A second oxide film is deposited, a first nitride film is formed on the second oxide film, the first nitride film is etched, remains in a sidewall shape, impurities are implanted, and an upper portion of the pillar-shaped silicon layer and the fin shape are formed. A diffusion layer is formed over the silicon layer, the first nitride film and the second oxide film are removed, and a heat treatment is performed.
The method of claim 1,
A fin silicon layer formed on the silicon substrate, a first insulating film formed around the fin silicon layer, a columnar silicon layer formed on the fin silicon layer,
A diffusion layer formed on an upper portion of the fin silicon layer and a lower portion of the columnar silicon layer;
In a structure having a diffusion layer formed on top of the columnar silicon layer,
After forming a gate insulating film, depositing polysilicon, planarizing the polysilicon so that the upper surface of the polysilicon is higher than the gate insulating film on the diffusion layer above the columnar silicon layer, and depositing a second nitride film. Forming a third resist for forming a polysilicon gate electrode and a polysilicon gate wiring, etching the second nitride film, etching the polysilicon, forming the polysilicon gate electrode and the polysilicon gate wiring And etching the gate insulating film to remove the third resist.
5. The method of claim 4,
A method of manufacturing a semiconductor device, wherein a third nitride film is deposited, the third nitride film is etched, remains in a sidewall shape, metal is deposited, and silicide is formed on the diffusion layer above the fin silicon layer. .
The method of claim 5, wherein
A fourth nitride film is deposited, an interlayer insulating film is deposited and planarized, a polysilicon gate electrode and a polysilicon gate wiring are exposed, the polysilicon gate electrode and the polysilicon gate wiring are removed, and the polysilicon gate electrode and the A metal device is embedded in a portion where a polysilicon gate wiring has been used, the metal is etched, the gate insulating film on the diffusion layer on the columnar silicon layer is exposed, and the metal gate electrode and the metal gate wiring are formed. Manufacturing method.
A pin-shaped silicon layer formed on the silicon substrate,
A first insulating film formed around the fin silicon layer;
A columnar silicon layer formed on the fin silicon layer, the diameter of the columnar silicon layer being equal to the width of the fin silicon layer;
A diffusion layer formed on an upper portion of the fin silicon layer and a lower portion of the columnar silicon layer;
A diffusion layer formed on the columnar silicon layer;
A silicide formed on an upper portion of the diffusion layer on the fin silicon layer;
A gate insulating film formed around the columnar silicon layer;
A metal gate electrode formed around the gate insulating film,
A metal gate wiring extending in a direction orthogonal to the fin silicon layer connected to the metal gate electrode;
Has a contact formed on the diffusion layer formed on the columnar silicon layer,
The diffusion layer formed on the pillar-shaped silicon layer and the contact directly
A semiconductor device, characterized in that.
KR1020137011996A 2011-11-09 2011-11-09 Method for manufacturing semiconductor device and semiconductor device KR20130110181A (en)

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