JP5667699B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  Semiconductor integrated circuits, in particular, integrated circuits using MOS transistors, are becoming increasingly highly integrated. Along with this high integration, the MOS transistors used therein have been miniaturized to the nano region. As the miniaturization of MOS transistors progresses, there is a problem that it is difficult to suppress the leakage current, and the area occupied by the circuit cannot be easily reduced due to a request for securing a necessary amount of current. In order to solve such a problem, a Surrounding Gate Transistor (SGT) having a structure in which a source, a gate, and a drain are arranged in a vertical direction with respect to a substrate and the gate surrounds a columnar semiconductor layer has been proposed (for example, Patent Documents). 1, Patent Document 2, Patent Document 3).

  By using metal instead of polysilicon for the gate electrode, depletion can be suppressed and the resistance of the gate electrode can be reduced. However, the post-process after forming the metal gate must always be a manufacturing process that considers metal contamination by the metal gate.

  Further, in a conventional MOS transistor, in order to achieve both a metal gate process and a high temperature process, a metal gate last process for creating a metal gate after a high temperature process is used in an actual product (Non-Patent Document 1). After forming a gate with polysilicon, an interlayer insulating film is deposited, then the polysilicon gate is exposed by chemical mechanical polishing, and after etching the polysilicon gate, a metal is deposited. Therefore, also in SGT, in order to make a metal gate process and a high temperature process compatible, it is necessary to use the metal gate last process which produces a metal gate after a high temperature process. In SGT, since the columnar silicon layer is higher than the gate, it is necessary to devise for using the metal gate last process.

  In order to reduce the parasitic capacitance between the gate wiring and the substrate, the conventional MOS transistor uses the first insulating film. For example, in FINFET (Non-patent Document 2), a first insulating film is formed around one fin-like semiconductor layer, the first insulating film is etched back, the fin-like semiconductor layer is exposed, and the gate wiring and the substrate The parasitic capacitance between them is reduced. Therefore, also in SGT, it is necessary to use the first insulating film in order to reduce the parasitic capacitance between the gate wiring and the substrate. In SGT, since there is a columnar semiconductor layer in addition to the fin-shaped semiconductor layer, a device for forming the columnar semiconductor layer is required.

  On the other hand, a FINFET that forms two transistors from one dummy pattern is known (for example, Patent Document 4). Side walls are formed around the dummy pattern, and the substrate is etched using the side walls as a mask to form fins, thereby forming two transistors from one dummy pattern.

JP-A-2-71556 Japanese Patent Laid-Open No. 2-188966 Japanese Patent Laid-Open No. 3-145761 JP 2011-71235 A

IEDM2007 K. Mistry et.al, pp 247-250 IEDM2010 CC.Wu, et.al, 27.1.1-27.1.4.

  Accordingly, an object of the present invention is to provide a method for manufacturing an SGT in which two transistors are formed from one dummy pattern and a SGT structure as a result, which is a gate last process, reducing parasitic capacitance between the gate wiring and the substrate. And

A method for manufacturing a semiconductor device of the present invention includes:
A first fin-like silicon layer and a second fin-like silicon layer are formed on a substrate, and the first fin-like silicon layer and the second fin-like silicon layer are connected at respective ends to form a closed loop. A first insulating film is formed around the first fin-shaped silicon layer and the second fin-shaped silicon layer, and a first columnar silicon layer is formed on the first fin-shaped silicon layer. a first step of forming a second columnar silicon layer on the second fin-shaped silicon layer, the width of the first columnar silicon layer is equal to a width of the first fin shaped silicon layer The width of the second columnar silicon layer is the same as the width of the second fin-shaped silicon layer, and after the first step, the upper portion of the first columnar silicon layer and the first Fin-like silicon layer upper part and the first columnar silicon layer lower part Impurities are implanted to form a diffusion layer, and impurities are implanted into the second columnar silicon layer upper portion, the second fin-shaped silicon layer upper portion, and the second columnar silicon layer lower portion to form a diffusion layer. A step of forming a gate insulating film, a first polysilicon gate electrode, a second polysilicon gate electrode, and a polysilicon gate wiring after the second step; and The first columnar silicon layer and the second columnar silicon layer are covered with a periphery and an upper portion, the first polysilicon gate electrode and the second polysilicon gate electrode cover a gate insulating film, and the first polysilicon layer The upper surface of the polysilicon after forming the silicon gate electrode, the second polysilicon gate electrode and the polysilicon gate wiring is formed on the gate above the diffusion layer above the first columnar silicon layer. The diffusion layer above the first insulating layer and the gate insulating film above the diffusion layer above the second columnar silicon layer, and after the third step, above the first fin-like silicon layer A fourth step of forming silicide on the upper portion and the upper portion of the diffusion layer above the second fin-like silicon layer; and after the fourth step, an interlayer insulating film is deposited, and the first polysilicon gate is formed. Exposing the electrode, the second polysilicon gate electrode, and the polysilicon gate wiring, etching the first polysilicon gate electrode, the second polysilicon gate electrode, and the polysilicon gate wiring, and depositing a metal And a fifth step of forming a first metal gate electrode, a second metal gate electrode and a metal gate wiring, and the first metal gate electrode and the second metal gate electrode connected to the first metal gate electrode. A metal gate wiring extending in a direction orthogonal to the first fin-like silicon layer and the second fin-like silicon layer, the sixth step of forming a contact after the fifth step; The diffusion layer above the first columnar silicon layer and the contact are directly connected, and the diffusion layer above the second columnar silicon layer and the contact are directly connected. Features.

In the first step, a second oxide film is deposited on the substrate to form a dummy pattern, a first resist for forming the dummy pattern is formed, and the second oxidation film is formed. The film is etched to form a dummy pattern, the first resist is removed, a first nitride film is deposited, the first nitride film is etched and left in a sidewall shape, and the dummy pattern A first nitride film sidewall is formed around, the dummy pattern is removed, the substrate is etched using the first nitride film sidewall as a mask, and a closed loop is formed by connecting each end. A fin-like silicon layer and a second fin-like silicon layer are formed, a first insulating film is formed around the first fin-like silicon layer and the second fin-like silicon layer, and the first nitriding layer is formed. Sidewalls are removed, the first insulating film is etched back, and an upper portion of the first fin-like silicon layer and an upper portion of the second fin-like silicon layer are exposed, and the first fin-like silicon layer is exposed. And forming a second resist so as to be orthogonal to the second fin-shaped silicon, etching the first fin-shaped silicon layer and the second fin-shaped silicon layer, and removing the second resist By doing so, the first columnar silicon layer is formed so that a portion where the first fin-shaped silicon layer and the second resist are orthogonal to each other becomes the first columnar silicon layer, and the second fin-shaped silicon layer is formed. The second columnar silicon layer is formed so that a portion where the silicon layer and the second resist are orthogonal to each other becomes the second columnar silicon layer.

  In addition, after the first step, a second oxide layer is formed on the entire structure after the first step by depositing a third oxide film to form a second nitride film, and the second nitride layer. The film is etched and left in a sidewall shape, and impurities are implanted, and the first columnar silicon layer upper portion, the first fin-shaped silicon layer upper portion, the second columnar silicon layer upper portion, and the second fin-shaped A diffusion layer is formed on the silicon layer, the second nitride film and the third oxide film are removed, and heat treatment is performed.

  After the second step, in the third step, a gate insulating film is formed so as to surround the silicon pillar, polysilicon is deposited, and the upper surface of the polysilicon after planarization is the first step. Planarization is performed so as to be higher than the gate insulating film on the diffusion layer above the columnar silicon layer and higher than the gate insulating film on the diffusion layer above the second columnar silicon layer, and the third nitriding is performed. A film is deposited, a third resist for forming a first polysilicon gate electrode, a second polysilicon gate electrode, and a polysilicon gate wiring is formed, the third nitride film is etched, and the poly-silicon film is etched. Etching the silicon, forming the first polysilicon gate electrode, the second polysilicon gate electrode, and the polysilicon gate wiring; etching the gate insulating film; and And removing the resist.

  Further, a fourth nitride film is deposited on the entire structure after the third step, the fourth nitride film is etched, left in a sidewall shape, a metal is deposited, and the silicide is deposited on the first structure. It is characterized by being formed on the upper part of the diffusion layer above the fin-like silicon layer and the second fin-like silicon layer.

  Further, a fifth nitride film is deposited on the entire structure after the fourth step, an interlayer insulating film is deposited, planarized by chemical mechanical polishing, and the first polysilicon gate electrode and the first polysilicon film are formed by chemical mechanical polishing. 2 polysilicon gate electrodes and polysilicon gate wirings are exposed, the first polysilicon gate electrode and the second polysilicon gate electrode and the polysilicon gate wiring are etched, metal is deposited, and the first The metal is buried in a portion where the polysilicon gate electrode, the second polysilicon gate electrode, and the polysilicon gate wiring are present, the metal is etched, and gate insulation on the diffusion layer above the first columnar silicon layer is performed. Exposing the film and the gate insulating film on the diffusion layer above the second columnar silicon layer, the first metal gate electrode, the second metal gate electrode, and the metal gate; And forming a line.

  Also, a first fin-shaped semiconductor layer formed on the substrate and a second fin-shaped semiconductor layer formed on the substrate and connected to each end together with the first fin-shaped semiconductor layer to form a closed loop A first insulating film formed around the first fin-like semiconductor layer and the second fin-like semiconductor layer, and the first fin-like semiconductor layer formed on the first fin-like semiconductor layer. A first semiconductor layer having the same width as that of the fin-shaped semiconductor layer, and a second semiconductor layer formed on the second fin-shaped semiconductor layer and having the same width as that of the second fin-shaped semiconductor layer. A semiconductor layer, a diffusion layer formed above the first fin-shaped semiconductor layer and a lower portion of the first columnar semiconductor layer, a diffusion layer formed above the first columnar semiconductor layer, Formed above the second fin-like semiconductor layer and below the second columnar semiconductor layer A diffusion layer formed above the diffusion layer formed above the second columnar semiconductor layer, an upper portion of the first fin-like semiconductor layer, and an upper portion of the diffusion layer above the second fin-like semiconductor layer. A silicide formed, a gate insulating film formed around the first columnar semiconductor layer, a first metal gate electrode formed around the gate insulating film, and a second columnar semiconductor layer. A gate insulating film formed in the periphery, a second metal gate electrode formed in the periphery of the gate insulating film, and the first metal gate electrode connected to the first metal gate electrode and the second metal gate electrode A fin-shaped semiconductor layer, a metal gate wiring extending in a direction orthogonal to the second fin-shaped semiconductor layer, a contact formed on a diffusion layer formed on the first columnar semiconductor layer, Formed on top of second columnar semiconductor layer A contact formed on the diffusion layer, and the diffusion layer formed on the first columnar semiconductor layer and the contact are directly connected to each other and formed on the second columnar semiconductor layer. The diffusion layer and the contact are directly connected.

According to the present invention, there is provided a SGT manufacturing method in which two transistors are formed from one dummy pattern, and the resulting SGT structure is a gate last process, reducing parasitic capacitance between the gate wiring and the substrate. can do.
Based on the conventional method of manufacturing a FINFET in which a sidewall is formed around a dummy pattern, the substrate is etched using the sidewall as a mask, fins are formed, and two transistors are formed from one dummy pattern. Two SGTs can be easily formed from one dummy pattern.
In addition, conventionally, silicide is formed on the top of the columnar silicon layer. However, since the deposition temperature of polysilicon is higher than the temperature for forming silicide, the silicide must be formed after forming the polysilicon gate. If silicide is to be formed on the top of the pillar, after forming the polysilicon gate, a hole is formed in the upper portion of the polysilicon gate electrode, a sidewall of the insulating film is formed on the sidewall of the hole, silicide is then formed, and the hole is formed. Since there was a disadvantage of increasing the number of manufacturing steps to fill the insulating film, a diffusion layer was formed before forming the polysilicon gate electrode and polysilicon gate wiring, the columnar silicon layer was covered with the polysilicon gate electrode, and the silicide was finned By forming only on top of the silicon layer, the gate is made with polysilicon, and then the interlayer After depositing the edge film, the polysilicon gate is exposed by chemical mechanical polishing, and after the polysilicon gate is etched, metal can be deposited, so that a conventional metal gate last manufacturing method can be used. it can.

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  Below, the manufacturing process for forming the structure of SGT which concerns on embodiment of this invention is demonstrated with reference to FIGS.

  Forming a first fin-like silicon layer and a second fin-like silicon layer on a substrate; forming a first insulating film around the first fin-like silicon layer and the second fin-like silicon layer; A manufacturing method of forming a first columnar silicon layer on the first fin-shaped silicon layer and forming a second columnar silicon layer on the second fin-shaped silicon layer will be described. As shown in FIG. 2, a second oxide film 102 is deposited on the silicon substrate 101 to form a dummy pattern. A nitride film or a laminated film of an oxide film and polysilicon may be used.

  As shown in FIG. 3, a first resist 103 for forming a dummy pattern is formed.

  As shown in FIG. 4, the second oxide film 102 is etched to form a dummy pattern 102.

  As shown in FIG. 5, the first resist 103 is removed.

  As shown in FIG. 6, a first nitride film 104 is deposited.

  As shown in FIG. 7, the first nitride film 104 is etched and left in a sidewall shape. A first nitride film sidewall 104 was formed around the dummy pattern 102. The first fin-like silicon layer 105 and the second fin-like silicon layer 106 that are connected at the respective ends to form a closed loop are etched by etching the silicon using the formed first nitride film sidewall 104. Will be formed.

  As shown in FIG. 8, the dummy pattern 102 is removed.

  As shown in FIG. 9, the silicon substrate 101 is etched using the first nitride film side wall 104 as a mask, and the first fin-like silicon layer 105 and the second fin-like shape connected at each end to form a closed loop are formed. A silicon layer 106 is formed.

As shown in FIG. 10, a first insulating film 107 is formed around the first fin-like silicon layer 105 and the second fin-like silicon layer 106.
An oxide film formed by high-density plasma or an oxide film formed by low-pressure chemical vapor deposition may be used as the first insulating film.

  As shown in FIG. 11, the 1st nitride film side wall 104 is removed. If the first nitride film sidewall 104 is removed during silicon etching or oxide film deposition, this step is unnecessary.

  As shown in FIG. 12, the first insulating film 107 is etched back to expose the upper portion of the first fin-like silicon layer 105 and the upper portion of the second fin-like silicon layer 106.

As shown in FIG. 13, a second resist 108 is formed so as to be orthogonal to the first fin-like silicon layer 105 and the second fin-like silicon layer 106. A portion where the first fin-shaped silicon layer 105, the second fin-shaped silicon layer 106, and the second resist 108 are orthogonal to each other is a portion that becomes a columnar silicon layer. Since a line-shaped resist can be used, the possibility that the resist falls after patterning is low, and the process is stable.

  As shown in FIG. 14, the first fin-like silicon layer 105 and the second fin-like silicon layer 106 are etched. A portion where the first fin-like silicon layer 105 and the second resist 108 are orthogonally becomes the first columnar silicon layer 109. A portion where the second fin-shaped silicon layer 106 and the second resist 108 are orthogonal to each other becomes the second columnar silicon layer 110. Therefore, the diameter of the first columnar silicon layer 109 is the same as the width of the first fin-shaped silicon layer 105. The diameter of the second columnar silicon layer 110 is the same as the width of the second fin-shaped silicon layer 106.

  A first columnar silicon layer 109 is formed on top of the first fin-shaped silicon layer 105, a second columnar silicon layer 110 is formed on top of the second fin-shaped silicon layer 106, and the first fin-shaped silicon layer is formed. The first insulating film 107 is formed around the layer 105 and the second fin-shaped silicon layer 106.

  As shown in FIG. 15, the second resist 108 is removed.

Next, in order to obtain a gate last, an impurity is implanted into the upper part of the first columnar silicon layer 109, the upper part of the first fin-like silicon layer 105, and the lower part of the first columnar silicon layer 109 to form a diffusion layer. A manufacturing method for forming a diffusion layer by injecting impurities into the upper part of the columnar silicon layer 110, the upper part of the second fin-like silicon layer 106, and the lower part of the second columnar silicon layer 110 will be described.
As shown in FIG. 16, the 3rd oxide film 111 is deposited and the 2nd nitride film 112 is formed. Later, since the upper part of the columnar silicon layer is covered with the gate insulating film and the polysilicon gate electrode, a diffusion layer is formed on the upper part of the columnar silicon layer before being covered.

  As shown in FIG. 17, the second nitride film 112 is etched and left in a sidewall shape.

  As shown in FIG. 18, impurities such as arsenic, phosphorus, and boron are implanted, the diffusion layer 113 is formed on the first columnar silicon layer 109, the diffusion layers 115 and 116 are formed on the first fin-shaped silicon layer 105, and the second columnar shape is formed. A diffusion layer 114 is formed on the silicon layer 110 and diffusion layers 115 and 116 are formed on the second fin-like silicon layer 106.

  As shown in FIG. 19, the second nitride film 112 and the third oxide film 111 are removed.

  Heat treatment is performed as shown in FIG. The diffusion layers 115 and 116 on the first fin-shaped silicon layer 105 and the second fin-shaped silicon layer 106 are in contact with each other to form a diffusion layer 117. In order to obtain gate last as described above, impurities are implanted into the upper part of the first columnar silicon layer 109, the upper part of the first fin-like silicon layer 105, and the lower part of the first columnar silicon layer 109 to form diffusion layers 113 and 117, Diffusion layers 114 and 117 are formed by implanting impurities into the upper part of the second columnar silicon layer 110, the upper part of the second fin-like silicon layer 106, and the lower part of the second columnar silicon layer 110.

  Next, a manufacturing method for forming the first polysilicon gate electrode 119b, the second polysilicon gate electrode 119a, and the polysilicon gate wiring 119c using polysilicon in order to obtain the gate last will be described. Since the polysilicon gate electrode and the polysilicon gate wiring are exposed by chemical mechanical polishing after depositing an interlayer insulating film for gate last, it is necessary to prevent the upper portion of the columnar silicon layer from being exposed by chemical mechanical polishing. .

  As shown in FIG. 21, a gate insulating film 118 is formed, and polysilicon 119 is deposited and planarized. The upper surface of the polysilicon 119 after the planarization is higher than the gate insulating film 118 on the diffusion layer 113 above the first columnar silicon layer 109, and the gate insulation on the diffusion layer 114 above the second columnar silicon layer 110. The position is higher than the film 118. As a result, when the polysilicon gate electrode and the polysilicon gate wiring are exposed by chemical mechanical polishing after depositing an interlayer insulating film to form gate last, the upper part of the columnar silicon layer is not exposed by chemical mechanical polishing.

  A third nitride film 120 is deposited. When the silicide is formed on the first fin-like silicon layer 105 and the second fin-like silicon layer 106, the third nitride film 120 has a first polysilicon gate electrode 119b and a second polysilicon gate. This is a film that inhibits formation of silicide on the electrode 119a and the polysilicon gate wiring 119c.

  As shown in FIG. 22, the 3rd resist 121 for forming the 1st polysilicon gate electrode 119b, the 2nd polysilicon gate electrode 119a, and the polysilicon gate wiring 119c is formed. It is desirable that a portion serving as a gate wiring be orthogonal to the first fin-shaped silicon layer 105 and the second fin-shaped silicon layer 106. This is because the parasitic capacitance between the gate wiring and the substrate is reduced.

  As shown in FIG. 23, the third nitride film 120 is etched, the polysilicon 119 is etched, and a first polysilicon gate electrode 119b, a second polysilicon gate electrode 119a, and a polysilicon gate wiring 119c are formed. .

  As shown in FIG. 24, the gate insulating film 118 is etched.

As shown in FIG. 25, the 3rd resist 121 is removed.
Thus, a manufacturing method for forming the first polysilicon gate electrode 119b, the second polysilicon gate electrode 119a, and the polysilicon gate wiring 119c with polysilicon in order to obtain the gate last has been shown. The upper surface of the polysilicon after the formation of the first polysilicon gate electrode 119b, the second polysilicon gate electrode 119a, and the polysilicon gate wiring 119c is a gate insulating film on the diffusion layer 113 above the first columnar silicon layer 109. It is higher than 118 and higher than the gate insulating film 118 on the diffusion layer 114 above the second columnar silicon layer 110.

Next, a manufacturing method for forming silicide on the upper portion of the diffusion layer 117 above the first fin-like silicon layer 105 and the upper portion of the diffusion layer 117 above the second fin-like silicon layer 106 will be described.
The first polysilicon gate electrode 119b, the second polysilicon gate electrode 119a, the polysilicon gate wiring 119c, the diffusion layer 113 above the first columnar silicon layer 109, and the diffusion layer 114 above the second columnar silicon layer 110. This is characterized in that no silicide is formed. If silicide is formed on the diffusion layer 113 above the first columnar silicon layer 109 and the diffusion layer 114 above the second columnar silicon layer 110, the number of manufacturing steps increases.
As shown in FIG. 26, the 4th nitride film 122 is deposited.

  As shown in FIG. 27, the fourth nitride film 122 is etched and left in a sidewall shape.

As shown in FIG. 28, a metal such as nickel or cobalt is deposited, and a silicide 123 is formed on the diffusion layer 117 above the first fin-like silicon layer 105 and the second fin-like silicon layer 106. At this time, the first polysilicon gate electrode 119b, the second polysilicon gate electrode 119a, and the polysilicon gate wiring 119c are covered with the fourth nitride film 122 and the third nitride film 120, and the first columnar silicon is formed. The diffusion layer 113 on the layer 109 and the diffusion layer 114 on the second columnar silicon layer 110 include a gate insulating film 118, a first polysilicon gate electrode 119b, a second polysilicon gate electrode 119a, and a polysilicon gate wiring. Since it is covered with 119c, no silicide is formed.
The manufacturing method for forming silicide on the diffusion layer 117 above the first fin-like silicon layer 105 and the diffusion layer 117 above the second fin-like silicon layer 106 has been described above.

Next, an interlayer insulating film 125 is deposited, the first polysilicon gate electrode 119b, the second polysilicon gate electrode 119a, and the polysilicon gate wiring 119c are exposed, and the first polysilicon gate electrode 119b and the second polysilicon gate electrode 119b are exposed. After the polysilicon gate electrode 119a and the polysilicon gate wiring 119c are etched, a metal 126 is deposited to form a first metal gate electrode 126b, a second metal gate electrode 126a, and a metal gate wiring 126c. Indicates.
As shown in FIG. 29, in order to protect the silicide 123, a fifth nitride film 124 is deposited.

  As shown in FIG. 30, an interlayer insulating film 125 is deposited and planarized by chemical mechanical polishing.

  As shown in FIG. 31, the first polysilicon gate electrode 119b, the second polysilicon gate electrode 119a, and the polysilicon gate wiring 119c are exposed by chemical mechanical polishing.

  As shown in FIG. 32, the first polysilicon gate electrode 119b, the second polysilicon gate electrode 119a, and the polysilicon gate wiring 119c are etched. Wet etching is desirable.

  As shown in FIG. 33, a metal 126 is deposited and planarized, and the metal 126 is buried in the portion where the first polysilicon gate electrode 119b, the second polysilicon gate electrode 119a, and the polysilicon gate wiring 119c were present. It is preferred to use atomic layer deposition.

  As shown in FIG. 34, the metal 126 is etched, and the gate insulating film 118 on the diffusion layer 113 on the first columnar silicon layer 109 and the gate insulating film on the diffusion layer 114 on the second columnar silicon layer 110 are etched. 118 are exposed. A first metal gate electrode 126b, a second metal gate electrode 126a, and a metal gate wiring 126c are formed.

  An interlayer insulating film 125 is deposited, the first polysilicon gate electrode 119b, the second polysilicon gate electrode 119a, and the polysilicon gate wiring 119c are exposed, and the first polysilicon gate electrode 119b and the second polysilicon gate are exposed. A method of manufacturing a gate last is shown in which a metal 126 is deposited after etching the electrode 119a and the polysilicon gate wiring 119c to form a first metal gate electrode 126b, a second metal gate electrode 126a, and a metal gate wiring 126c. It was.

Next, a manufacturing method for forming contacts will be described. Since no silicide is formed in the diffusion layer 113 above the first columnar silicon layer 109 and the diffusion layer 114 above the second columnar silicon layer 110, the contact and the diffusion layer 113 above the first columnar silicon layer 109 are directly connected. The contact and the diffusion layer 114 on the second columnar silicon layer 110 are directly connected.
As shown in FIG. 35, an interlayer insulating film 127 is deposited and planarized.

  As shown in FIG. 36, the 4th resist 128 for forming a contact hole is formed in the 1st columnar silicon layer 109 upper part and the 2nd columnar silicon layer 110 upper part.

  As shown in FIG. 37, the interlayer insulating film 127 is etched to form contact holes 129.

  As shown in FIG. 38, the 4th resist 128 is removed.

  As shown in FIG. 39, a fifth resist 130 for forming contact holes is formed on the metal gate wiring 126 c and on the first fin-like silicon layer 105 and the second fin-like silicon layer 106.

  As shown in FIG. 40, the interlayer insulating films 127 and 125 are etched to form contact holes 131 and 132.

  As shown in FIG. 41, the 5th resist 130 is removed.

As shown in FIG. 42, the fifth nitride film 124 and the gate insulating film 118 are etched to expose the silicide 123 and the diffusion layers 113 and 114.

  As shown in FIG. 43, metal is deposited to form contacts 133, 134, and 135. Thus, a manufacturing method for forming a contact has been shown. Since no silicide is formed in the diffusion layer 113 above the first columnar silicon layer 109 and the diffusion layer 114 above the second columnar silicon layer 110, the contact 134 and the diffusion layer 113 above the first columnar silicon layer 109 are directly connected. The contact 134 and the diffusion layer 114 on the second columnar silicon layer 110 are directly connected.

Next, a manufacturing method for forming the metal wiring layer will be described.
As shown in FIG. 44, metal 136 is deposited.

  As shown in FIG. 45, sixth resists 137, 138, and 139 for forming metal wiring are formed.

  As shown in FIG. 46, the metal 136 is etched to form metal wirings 140, 141, 142.

As shown in FIG. 47, the sixth resists 137, 138, and 139 are removed.
Thus, a manufacturing method for forming a metal wiring layer has been shown.

The result of the manufacturing method is shown in FIG.
First fin-like silicon layer 105 formed on substrate 101, second fin-like silicon layer 106 formed on substrate 101, first fin-like silicon layer 105 and second fin-like silicon layer The layers 106 are connected at their respective ends to form a closed loop, and the first insulating film 107 formed around the first fin-like silicon layer 105 and the second fin-like silicon layer 106, and the first Of the first columnar silicon layer 109 formed on the fin-shaped silicon layer 105, the second columnar silicon layer 110 formed on the second fin-shaped silicon layer 106, and the first columnar silicon layer 109. width is the same as the width of the first fin shaped silicon layer 105, the width of the second columnar silicon layer 110 is the same as the width of the second fin-shaped silicon layer 106, a first fin-shaped silicon 105, a diffusion layer 117 formed below the first columnar silicon layer 109, a diffusion layer 113 formed above the first columnar silicon layer 109, and an upper portion of the second fin-shaped silicon layer 106. A diffusion layer 117 formed below the second columnar silicon layer 110, a diffusion layer 114 formed above the second columnar silicon layer 110, an upper portion of the first fin-shaped silicon layer 105, and a second layer. The silicide 123 formed on the diffusion layer 117 above the fin-like silicon layer 106, the gate insulating film 118 formed around the first columnar silicon layer 109, and the gate insulating film 118 are formed. The first metal gate electrode 126b, the gate insulating film 118 formed around the second columnar silicon layer 110, and the second metal formed around the gate insulating film 118 Extending in a direction perpendicular to the first fin-like silicon layer 105 and the second fin-like silicon layer 106 connected to the gate electrode 126a, the first metal gate electrode 126b, and the second metal gate electrode 126a. The metal gate wiring 126c, the contact 134 formed on the diffusion layer 113 formed on the first columnar silicon layer 109, and the diffusion layer 114 formed on the second columnar silicon layer 110. The diffusion layer 113 formed on the first columnar silicon layer 109 and the contact 134 are directly connected to each other, and the diffusion layer 114 formed on the second columnar silicon layer 110 and the contact 134 are connected to each other. And have a direct connection structure.
From the above, it is possible to provide an SGT manufacturing method in which two transistors are formed from one dummy pattern, and a SGT structure as a result, which is a gate last process by reducing the parasitic capacitance between the gate wiring and the substrate.

101. Silicon substrate 102. Second oxide film, dummy pattern 103. First resist 104. First nitride film, first nitride film sidewall 105. First fin-like silicon layer 106. Second fin-like silicon layer 107. First insulating film 108. Second resist 109. First columnar silicon layer 110. Second columnar silicon layer 111. Third oxide film 112. Second nitride film 113. Diffusion layer 114. Diffusion layer 115. Diffusion layer 116. Diffusion layer 117. Diffusion layer 118. Gate insulating film 119. Polysilicon 119a. Second polysilicon gate electrode 119b. First polysilicon gate electrode 119c. Polysilicon gate wiring 120. Third nitride film 121. Third resist 122. Fourth nitride film 123. Silicide 124. Fifth nitride film 125. Interlayer insulating film 126. Metal 126a. Second metal gate electrode 126b. First metal gate electrode 126c. Metal gate wiring 127. Interlayer insulating film 128. Fourth resist 129. Contact hole 130. Fifth resist 131. Contact hole 132. Contact hole 133. Contact 134. Contact 135. Contact 136. Metal 137. Sixth resist 138. Sixth resist 139. Sixth resist 140. Metal wiring 141. Metal wiring 142. Metal wiring

Claims (7)

A first fin-like silicon layer and a second fin-like silicon layer are formed on a substrate, and the first fin-like silicon layer and the second fin-like silicon layer are connected at respective ends to form a closed loop. A first insulating film is formed around the first fin-shaped silicon layer and the second fin-shaped silicon layer, and a first columnar silicon layer is formed on the first fin-shaped silicon layer. a first step of forming a second columnar silicon layer on the second fin-shaped silicon layer, the width of the first columnar silicon layer is equal to a width of the first fin shaped silicon layer The width of the second columnar silicon layer is the same as the width of the second fin-shaped silicon layer, and after the first step, the upper portion of the first columnar silicon layer and the first Fin-like silicon layer upper part and the first columnar silicon layer lower part Impurities are implanted to form a diffusion layer, and impurities are implanted into the second columnar silicon layer upper portion, the second fin-shaped silicon layer upper portion, and the second columnar silicon layer lower portion to form a diffusion layer. A step of forming a gate insulating film, a first polysilicon gate electrode, a second polysilicon gate electrode, and a polysilicon gate wiring after the second step; and The first columnar silicon layer and the second columnar silicon layer are covered with a periphery and an upper portion, the first polysilicon gate electrode and the second polysilicon gate electrode cover a gate insulating film, and the first polysilicon layer The upper surface of the polysilicon after forming the silicon gate electrode, the second polysilicon gate electrode and the polysilicon gate wiring is formed on the gate above the diffusion layer above the first columnar silicon layer. The diffusion layer above the first insulating layer and the gate insulating film above the diffusion layer above the second columnar silicon layer, and after the third step, above the first fin-like silicon layer A fourth step of forming silicide on the upper portion and the upper portion of the diffusion layer above the second fin-like silicon layer; and after the fourth step, an interlayer insulating film is deposited, and the first polysilicon gate is formed. Exposing the electrode, the second polysilicon gate electrode, and the polysilicon gate wiring, etching the first polysilicon gate electrode, the second polysilicon gate electrode, and the polysilicon gate wiring, and depositing a metal And a fifth step of forming a first metal gate electrode, a second metal gate electrode and a metal gate wiring, and the first metal gate electrode and the second metal gate electrode connected to the first metal gate electrode. A metal gate wiring extending in a direction orthogonal to the first fin-like silicon layer and the second fin-like silicon layer, the sixth step of forming a contact after the fifth step; The diffusion layer above the first columnar silicon layer and the contact are directly connected, and the diffusion layer above the second columnar silicon layer and the contact are directly connected. A method of manufacturing a semiconductor device. In the first step, a second oxide film is deposited on the substrate to form a dummy pattern, a first resist for forming the dummy pattern is formed, and the second oxide film is formed Etching to form a dummy pattern, removing the first resist, depositing a first nitride film, etching the first nitride film, leaving a sidewall, and surrounding the dummy pattern First nitride film sidewalls are formed, the dummy pattern is removed, the substrate is etched using the first nitride film sidewalls as a mask, and first fins connected at respective ends to form closed loops Forming a first silicon layer and a second fin-like silicon layer; forming a first insulating film around the first fin-like silicon layer and the second fin-like silicon layer; Removing the wall, said first insulating film is etched back to expose the top and the top of the second fin-shaped silicon layer of said first fin shaped silicon layer, said first fin shaped silicon layer A second resist is formed so as to be orthogonal to the second fin-shaped silicon, the first fin-shaped silicon layer and the second fin-shaped silicon layer are etched, and the second resist is removed. Thus, the first fin-like silicon layer is formed so that a portion where the first fin-like silicon layer and the second resist are orthogonal to each other becomes the first pillar-like silicon layer, and the second fin-like silicon is formed. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the second columnar silicon layer is formed so that a portion where the layer and the second resist are orthogonal to each other is the second columnar silicon layer.   After the first step, in the second step, a third oxide film is deposited on the entire structure after the first step, a second nitride film is formed, and the second nitride film is formed. Etching is performed to leave sidewalls, and impurities are implanted, and the first columnar silicon layer upper portion, the first fin-shaped silicon layer upper portion, the second columnar silicon layer upper portion, and the second fin-shaped silicon layer 2. The method of manufacturing a semiconductor device according to claim 1, wherein a diffusion layer is formed on the upper portion, the second nitride film and the third oxide film are removed, and heat treatment is performed.   After the second step, in the third step, a gate insulating film is formed so as to surround the silicon pillar, polysilicon is deposited, and the upper surface of the polysilicon after planarization is the first step. Planarization is performed so as to be higher than the gate insulating film on the diffusion layer above the columnar silicon layer and higher than the gate insulating film on the diffusion layer above the second columnar silicon layer, and the third nitriding is performed. A film is deposited, a third resist for forming a first polysilicon gate electrode, a second polysilicon gate electrode, and a polysilicon gate wiring is formed, the third nitride film is etched, and the poly-silicon film is etched. Etching the silicon, forming the first polysilicon gate electrode, the second polysilicon gate electrode, and the polysilicon gate wiring; etching the gate insulating film; and The method of manufacturing a semiconductor device according to claim 1, characterized in that the removal of resist.   A fourth nitride film is deposited on the entire structure after the third step, the fourth nitride film is etched, left in a sidewall shape, a metal is deposited, and silicide is formed into a first fin shape. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is formed on the diffusion layer above the silicon layer and the second fin-like silicon layer.   A fifth nitride film is deposited on the entire structure after the fourth step, an interlayer insulating film is deposited, planarized by chemical mechanical polishing, and the first polysilicon gate electrode and the second second electrode are formed by chemical mechanical polishing. A polysilicon gate electrode and a polysilicon gate wiring are exposed, the first polysilicon gate electrode, the second polysilicon gate electrode and the polysilicon gate wiring are etched, a metal is deposited, and the first polysilicon gate electrode is etched. A portion of the silicon gate electrode, the second polysilicon gate electrode, and the polysilicon gate wiring embedded in the metal; the metal is etched; and a gate insulating film on the diffusion layer above the first columnar silicon layer; The gate insulating film on the diffusion layer above the second columnar silicon layer is exposed, and the first metal gate electrode, the second metal gate electrode, and the metal gate wiring are exposed. The method of manufacturing a semiconductor device according to claim 5, characterized in that the formed. A first fin-like semiconductor layer formed on the substrate; and a second fin-like semiconductor layer formed on the substrate and connected to each end together with the first fin-like semiconductor layer to form a closed loop; A first insulating film formed around the first fin-shaped semiconductor layer and the second fin-shaped semiconductor layer; and the first fin formed on the first fin-shaped semiconductor layer. A first columnar semiconductor layer having the same width as the width of the semiconductor layer, and a second column formed on the second fin-shaped semiconductor layer and having the same width as the width of the second fin-shaped semiconductor layer. A columnar semiconductor layer; a diffusion layer formed above the first fin-shaped semiconductor layer; a lower layer formed on the first columnar semiconductor layer; a diffusion layer formed above the first columnar semiconductor layer; An upper part of the second fin-like semiconductor layer and a lower part of the second columnar semiconductor layer A diffusion layer formed; a diffusion layer formed above the second columnar semiconductor layer; an upper portion of the first fin-like semiconductor layer; and an upper portion of the diffusion layer above the second fin-like semiconductor layer. A silicide formed on the first columnar semiconductor layer, a first gate insulating film formed around the first columnar semiconductor layer, a first metal gate electrode formed around the first gate insulating film, wherein the second gate insulating film formed around the second columnar semiconductor layer, and a second metal gate electrode formed around the second gate insulating film, and the first metal gate electrode A first fin-like semiconductor layer connected to a second metal gate electrode; a metal gate wiring extending in a direction perpendicular to the second fin-like semiconductor layer; and an upper portion of the first columnar semiconductor layer A contact formed on the formed diffusion layer, and the second A contact formed on the diffusion layer formed on the top of the columnar semiconductor layer, the diffusion layer formed on the top of the first columnar semiconductor layer and the contact are directly connected, and the second columnar A diffusion layer formed on a semiconductor layer and the contact are directly connected to each other.

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