TW201309616A - In-Ga-Sn系氧化物燒結體 - Google Patents
In-Ga-Sn系氧化物燒結體 Download PDFInfo
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- TW201309616A TW201309616A TW101130510A TW101130510A TW201309616A TW 201309616 A TW201309616 A TW 201309616A TW 101130510 A TW101130510 A TW 101130510A TW 101130510 A TW101130510 A TW 101130510A TW 201309616 A TW201309616 A TW 201309616A
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- sintered body
- oxide
- oxide sintered
- film
- thin film
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Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- C04B35/00—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
- C04B35/01—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics
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- C04B35/00—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
- C04B35/01—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics
- C04B35/453—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics based on zinc, tin, or bismuth oxides or solid solutions thereof with other oxides, e.g. zincates, stannates or bismuthates
- C04B35/457—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics based on zinc, tin, or bismuth oxides or solid solutions thereof with other oxides, e.g. zincates, stannates or bismuthates based on tin oxides or stannates
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- C—CHEMISTRY; METALLURGY
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- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B35/00—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
- C04B35/622—Forming processes; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
- C04B35/626—Preparing or treating the powders individually or as batches ; preparing or treating macroscopic reinforcing agents for ceramic products, e.g. fibres; mechanical aspects section B
- C04B35/62605—Treating the starting powders individually or as mixtures
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- C04B35/62675—Thermal treatment of powders or mixtures thereof other than sintering characterised by the treatment temperature
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- C04B35/6455—Hot isostatic pressing
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- C04B37/023—Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles characterised by the interlayer used
- C04B37/026—Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles characterised by the interlayer used consisting of metals or metal salts
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Abstract
本發明之氧化物燒結體以下述區域(A)及(B)中所包含之原子比含有In、Ga、Sn及Zn。區域(A) 0.38≦In/(In+Ga+Sn)<0.70 0.05<Ga/(In+Ga+Sn)<0.40 0.20<Sn/(In+Ga+Sn)≦0.50 0.00≦Zn/(In+Ga+Sn+Zn)<0.05 區域(B) 0.25≦In/(In+Ga+Sn)<0.69 0.20≦Ga/(In+Ga+Sn)≦0.55 0.11<Sn/(In+Ga+Sn)≦0.20 0.00≦Zn/(In+Ga+Sn+Zn)<0.05
Description
本發明係關於一種氧化物燒結體、濺鍍靶、氧化物半導體薄膜、薄膜電晶體等。
含有氧化銦之非晶質之氧化物膜由於具有可見光穿透性,且具有自導電體起至半導體、絕緣體為止之廣泛電氣特性,故而作為透明導電膜或薄膜電晶體(TFT,Thin Film Transistor)等中使用之半導體膜而受到關注。
作為氧化物膜之成膜方法,正研究濺鍍、PLD(Pulsed Laser Deposition,脈衝雷射沈積)、蒸鍍等物理性成膜或溶膠凝膠法等化學性成膜,但作為可於相對較低溫度下大面積地均勻地成膜之方法,正以濺鍍法、PLD法、電子束蒸鍍法等物理性成膜為中心進行研究。
於以物理性成膜法形成氧化物薄膜時,為了均勻地、穩定地、高效地、且以較高成膜速度進行成膜,通常使用包含氧化物燒結體之靶。
尤其是若將包含氧化物燒結體之靶應用於濺鍍法中,則由於量產性優異故而可用於平面顯示器等大面積之用途中。
包含氧化銦及氧化鋅之各種氧化物半導體受到關注,最近正研究將使用包含氧化銦、氧化鎵及氧化鋅之靶製作之非晶質氧化物半導體膜作為薄膜電晶體之半導體層而驅動的方法。
然而,大量含有氧化鋅之非晶質氧化物半導體膜具有可以有機酸系蝕刻液(例如草酸蝕刻液)進行濕式蝕刻之優點,但另一方面,亦存在易溶於無機酸系濕式蝕刻液(例如磷酸/硝酸/乙酸之混酸濕式蝕刻液)中而與Mo(鉬)或Al(鋁)等之濕式蝕刻之選擇比較小的問題。
又,含有氧化鋅之非晶質氧化物半導體膜存在於以乾式蝕刻進行圖案化時蝕刻速度較慢之課題。
為解決該等課題,正研究於氧化銦、氧化鎵及氧化鋅中添加氧化錫而成之氧化物半導體膜、及用以製作其之濺鍍靶(專利文獻1)。
然而,該濺鍍靶存在應管理之元素數較多而製造步驟或品質管理複雜之問題。
又,存在於Si基板等含Si層上製作各種元件時,鋅擴散至含Si層內而使元件特性劣化之問題,可應用之元件構成受到限制。
又,正關於包含氧化銦、氧化鎵及氧化錫之氧化物薄膜及用以製作其之靶進行研究(專利文獻2、3)。
然而,該研究係以透明導電膜為目的,並未進行製作氧化物半導體膜、尤其是薄膜電晶體之研究或適合之性狀之研究。又,組成比並不適合薄膜電晶體之製作。
又,揭示有可於稱為T相(T phase)之區域中合成Ga3-xIn5+xSn2O16所示之化合物(非專利文獻1),但並未進行以該晶型為主成分之靶之研究或對於薄膜電晶體製作之應用等。
專利文獻1:國際公開第2008/139654號說明書
專利文獻2:國際公開第2009/128424號說明書
專利文獻3:日本專利特開2000-77358號公報
非專利文獻1: D. D. Edwards et. al., Appl. Phys. Lett. 70 (13), (1997) 1706
本發明之目的在於提供一種可製作適於圖案化步驟之氧化物半導體膜之氧化物燒結體。又,本發明之目的在於提供一種可製作遷移率較高之TFT之氧化物燒結體。
本發明者反覆銳意研究,結果發現,可藉由含有氧化錫、氧化鋅之含量較少或不含氧化鋅之組成(實質上包含氧化銦、氧化鎵及氧化錫之組成)之氧化物燒結體靶,而不增加元素數地製作對無機酸系濕式蝕刻液(例如磷酸/硝酸/乙酸之混酸濕式蝕刻液)具耐性之氧化物半導體膜。
又,發現,可藉由該靶而製作顯示與包含氧化銦、氧化鎵及氧化鋅之半導體膜相同特性之半導體膜,且可製作遷移率較高之薄膜電晶體。進而發現,藉由選定氧化錫之組成比,亦可提高乾式蝕刻時之選擇比。
本發明者進而發現一種以Ga3-xIn5+xSn2O16(式中,X為0~1)所示之晶體結構之化合物為主成分之燒結體,且發現,藉由以Ga3-xIn5+xSn2O16所示之晶體結構之化合物為主成分,而獲得具有適合作為靶之特性之氧化物燒結體,
即,若以該燒結體為靶而製作薄膜電晶體,則獲得遷移率較高之薄膜電晶體。
根據本發明,可提供以下之氧化物燒結體等。
1.一種氧化物燒結體,其係以下述區域(A)及(B)中所包含之原子比含有In、Ga、Sn及Zn:
區域(A)
0.38≦In/(In+Ga+Sn)<0.70
0.05<Ga/(In+Ga+Sn)<0.40
0.20<Sn/(In+Ga+Sn)≦0.50
0.00≦Zn/(In+Ga+Sn+Zn)<0.05
區域(B)
0.25≦In/(In+Ga+Sn)<0.69
0.20≦Ga/(In+Ga+Sn)≦0.55
0.11<Sn/(In+Ga+Sn)≦0.20
0.00≦Zn/(In+Ga+Sn+Zn)<0.05。
2.如1之氧化物燒結體,其中於上述區域(A)中,In、Ga及Sn之原子比滿足下式,且除不可避免地含有之雜質以外不含Zn:0.10<Ga/(In+Ga+Sn)<0.30
0.20<Sn/(In+Ga+Sn)≦0.30。
3.如1之氧化物燒結體,其中於上述區域(B)中,In、Ga及Sn之原子比滿足下式,且除不可避地含有之雜質以外不含Zn:0.20≦Ga/(In+Ga+Sn)≦0.30。
4.如1至3中任一項之氧化物燒結體,其含有Ga3-xIn5+xSn2O16(式中,X為0~1)所示之晶體結構之化合物作為主成分。
5.如4之氧化物燒結體,其實質上含有Ga3-xIn5+xSn2O16(式中,X為0~1)所示之晶體結構之化合物。
6.如4或5之氧化物燒結體,其內部與表面之晶體結構實質上相同。
7.如1至6中任一項之氧化物燒結體,其具有圓筒狀之形狀。
8.一種濺鍍靶,其使用如1至7中任一項之氧化物燒結體。
9.一種氧化物半導體薄膜,其係使用如8之濺鍍靶以濺鍍法形成而獲得。
10.一種薄膜電晶體,其含有如9之氧化物半導體薄膜作為通道層。
11.一種顯示裝置,其係具備如10之薄膜電晶體而成。
根據本發明,可提供一種可製作適於圖案化步驟之氧化物半導體膜之氧化物燒結體。又,根據本發明,可提供一種可製作遷移率較高之TFT之氧化物燒結體。
本發明之氧化物燒結體包含銦元素(In)、鎵元素(Ga)及錫元素(Sn),且包含少量鋅(Zn)或不含鋅(Zn)。具體而言,該等元素之原子比係選自下述區域(A)及區域(B)。
區域(A)
0.38≦In/(In+Ga+Sn)<0.70 (1)
0.05<Ga/(In+Ga+Sn)<0.40 (2)
0.20<Sn/(In+Ga+Sn)≦0.50 (3)
0.00≦Zn/(In+Ga+Sn+Zn)<0.05 (4)
區域(B)
0.25≦In/(In+Ga+Sn)<0.69 (5)
0.20≦Ga/(In+Ga+Sn)≦0.55 (6)
0.11<Sn/(In+Ga+Sn)≦0.20 (7)
0.00≦Zn/(In+Ga+Sn+Zn)<0.05 (8)
藉由滿足區域(A)或(B),而可提高氧化物燒結體之相對密度,又,可製成顏色不均較少而外觀良好之氧化物燒結體。
藉由使用滿足區域(A)之氧化物燒結體,而獲得氫氟酸(無機酸系濕式蝕刻液)耐性較高之氧化物薄膜。因此,薄膜電晶體之製造步驟之選擇項擴大,可製作電晶體特性良好之薄膜電晶體。
藉由滿足區域(B),而獲得電阻更低之氧化物燒結體,可製作電晶體特性良好之薄膜電晶體。
較佳為,於區域(A)及(B)中,In、Ga及Sn之原子比滿足下式,且除不可避免地含有之雜質以外不含Zn。
0.10<Ga/(In+Ga+Sn)<0.30
0.20<Sn/(In+Ga+Sn)≦0.30
又,較佳為,於區域(A)及(B)中,In、Ga及Sn之原子比滿足下式,且除不可避免地含有之雜質以外不含Zn。
0.20≦Ga/(In+Ga+Sn)≦0.30
區域(A)較佳為下式(1')、(9)及(10),進而較佳為下式
(1")、(11)及(12),尤佳為下式(1''')、(13)及(14)。
0.40≦In/(In+Ga+Sn)<0.70 (1')
0.07<Ga/(In+Ga+Sn)<0.40 (9)
0.20<Sn/(In+Ga+Sn)≦0.30 (10)
0.41≦In/(In+Ga+Sn)<0.70 (1")
0.10<Ga/(In+Ga+Sn)<0.30 (11)
0.20<Sn/(In+Ga+Sn)≦0.30 (12)
0.41≦In/(In+Ga+Sn)<0.66 (1''')
0.15<Ga/(In+Ga+Sn)<0.30 (13)
0.21≦Sn/(In+Ga+Sn)≦0.30 (14)
區域(B)較佳為下式(5')、(15)及(7),進而較佳為下式(5")、(16)及(7),尤佳為下式(5''')、(17)及(7)。
0.36≦In/(In+Ga+Sn)<0.69 (5')
0.20≦Ga/(In+Ga+Sn)<0.45 (15)
0.11<Sn/(In+Ga+Sn)≦0.20 (7)
0.46≦In/(In+Ga+Sn)<0.69 (5")
0.20≦Ga/(In+Ga+Sn)<0.35 (16)
0.11<Sn/(In+Ga+Sn)≦0.20 (7)
0.50≦In/(In+Ga+Sn)<0.69 (5''')
0.20≦Ga/(In+Ga+Sn)≦0.30 (17)
0.11<Sn/(In+Ga+Sn)≦0.20 (7)
若於上述範圍內,則可製作遷移率等電晶體特性良好之薄膜電晶體。
又,使用上述範圍內之燒結體製作之氧化物薄膜可以有
機酸系蝕刻液(例如草酸蝕刻液)進行濕式蝕刻,且不易溶於無機酸系濕式蝕刻液(例如磷酸/硝酸/乙酸之混酸濕式蝕刻液)中,因此可增大與電極中使用之Mo(鉬)或Al(鋁)等之濕式蝕刻之選擇比。
於本發明之氧化物燒結體中,區域(A)及(B)中之Zn之原子比較佳為滿足下式(18),更佳為滿足下式(19),進而較佳為滿足下式(20),尤佳為除不可避免地含有之雜質以外不含Zn。
0.00≦Zn/(In+Ga+Sn+Zn)<0.05 (18)
0.00≦Zn/(In+Ga+Sn+Zn)<0.01 (19)
0.00≦Zn/(In+Ga+Sn+Zn)<0.001 (20)
藉由減少Zn之含量,而可獲得表面與內部之性狀(晶體結構、電阻)之差別較少(實質上相同)之燒結體。再者,所謂「實質上相同」,係指對表層及自表層磨削1 mm之內部部分分別實施晶體結構分析及表面電阻測定,於晶體結構分析上獲得相同之圖案,於表面電阻測定上獲得±10%之測定值。
又,於製作燒結體時,即便於高溫下進行燒結,表面部分之變質亦較少,其結果為,可使磨削厚度變薄,即便不磨削而僅研磨,表面之性狀亦可穩定,因此可降低成本。
再者,於本發明中,氧化物燒結體中所含有之金屬元素亦可實質上僅為In、Ga及Sn。此處,於本申請案中,所謂「實質上」,係指作為靶之效果係源於構成上述氧化物燒結體之金屬元素之組成,或構成氧化物燒結體之金屬氧化
物之95重量%以上100重量%以下(較佳為98重量%以上100重量%以下,尤佳為99.99重量%以上100.00重量%以下)為上述金屬元素之氧化物。
進而,本發明之氧化物燒結體亦可含有通常可獲得之原料於精製步驟上不可避免地含有之元素或於製程上不可避免地混入之雜質。上述元素或上述雜質較佳為相對於總構成成分為10 ppm以下。
本發明之氧化物燒結體中所含有之各元素之原子比可利用電感耦合電漿發光分析裝置(ICP-AES,Inductively Coupled Plasma-Atomic Emission Spectrometer)定量分析含有元素而求出。
具體而言,使用ICP-AES之分析中,當以噴霧器使溶液試樣成為霧狀而導入至氬電漿(約6000~8000℃)中時,試樣中之元素吸收熱能而被激發,軌道電子自基態移動至較高能階之軌道上。該軌道電子以10-7~10-8秒左右移動至更低能階之軌道上。此時將能量之差以光之形式放射而發光。該光顯示元素固有之波長(譜線),因此可藉由譜線之有無而確認元素之存在(定性分析)。
又,各譜線之大小(發光強度)與試樣中之元素數成比例,因此可藉由與已知濃度之標準溶液進行比較而求出試樣濃度(定量分析)。
由定性分析確定所含有之元素後,由定量分析求出含量,並根據該結果求出各元素之原子比。
本發明之氧化物燒結體較佳為含有Ga3-xIn5+xSn2O16(式
中,X為0~1)所示之晶體結構之化合物。
作為Ga3-xIn5+xSn2O16所示之晶體結構之化合物,可列舉Ga2In6Sn2O16或Ga2.4In5.6Sn2O16等,只要為Ga3-xIn5+xSn2O16所示之晶體結構之化合物,則並無限制。
是否為Ga3-xIn5+xSn2O16所示之晶體結構之化合物係根據以下情況來判斷:參照JCPDS(Joint Committee of Powder Diffraction Standards,粉末繞射標準聯合委員會)卡而與Ga2In6Sn2O16(JCPDS卡:51-0205)或Ga2.4In5.6Sn2O16(JCPDS卡:51-0204)一致,或以相同圖案進行波峰移動。
當以後述之X射線繞射對本發明之氧化物燒結體進行分析時,較佳為於(1)30.0~32.0°、(2)35.0~37.0°、(3)51.0~53.0°及(4)60.5~63.0°之範圍內存在波峰。
更佳為於(1)30.5~31.5°、(2)35.5~36.5°、(3)51.5~52.5°及(4)61.0~62.5°之範圍內存在波峰。
本發明之氧化物燒結體較理想為上述Ga3-xIn5+xSn2O16所示之晶體結構之化合物為主成分或第二成分,尤其理想為主成分。
若以Ga3-xIn5+xSn2O16所示之晶體結構之化合物為主成分,則以該氧化物燒結體為靶製作之薄膜電晶體可成為遷移率較高者。
是否為主成分或第二成分係根據利用後述之X射線繞射而獲得之波峰之高度而進行判斷。具體而言,所謂主成分,係最大波峰強度最高者,所謂第二成分,係最大波峰強度次於主成分而較高者。
本發明之氧化物燒結體較理想為實質上包含上述Ga3-xIn5+xSn2O16所示之晶體結構之化合物。「實質上包含上述Ga3-xIn5+xSn2O16所示之晶體結構之化合物」係根據如下情況來判斷:X射線繞射之光譜中鑑定為上述晶體之波峰的面積相對於整個光譜之面積占90%以上。
X射線繞射之測定條件係例如如下所述。
裝置:Rigaku(股)製造之Ultima-III
X射線:Cu-Kα射線(波長1.5406 Å,利用石墨單色器而單色化)
2θ-θ反射法,連續掃描(1.0°/分鐘)
採樣間隔:0.02°
狹縫DS、SS:2/3°、RS:0.6 mm
再者,若以晶體結構X射線繞射圖案來判斷結構,則氧過剩或不足(氧缺損)亦不要緊。即,可遵循化學計量比,亦可偏離化學計量比。又,較佳為存在氧缺損。若氧過剩,則有製靶時電阻過高之虞。
本發明之氧化物燒結體適於濺鍍靶。以下,對本發明之氧化物燒結體及濺鍍靶之製造方法進行說明。
本發明之濺鍍靶(氧化物燒結體)可藉由包括下述(a)~(e)步驟之製法而獲得。
(a)混合原料化合物粉末而製備混合物之步驟,
(b)使上述混合物成形而製備平均厚度5.5 mm以上之成形體之步驟,
(c)將上述成形體於1280℃以上1520℃以下燒結2小時以上
96小時以下之步驟
(d)研磨燒結體之表面之步驟
(e)將燒結體黏合於襯板之步驟
調配步驟係使濺鍍靶之原料即金屬氧化物混合之必需步驟。
使用銦化合物之粉末、鎵化合物之粉末、錫化合物之粉末及鋅化合物之粉末等粉末作為原料。作為銦之化合物,例如可列舉氧化銦、氫氧化銦等。作為錫、鎵及鋅之化合物,例如可列舉各自之氧化物、氫氧化物等。作為各自之化合物,就燒結之容易度、副產物殘留之難度而言,較佳為氧化物。
又,原料之純度通常為2 N(99質量%)以上,較佳為3 N(99.9質量%)以上,尤佳為4 N(99.99質量%)以上。若純度低於2 N,則有耐久性降低,用於液晶顯示器時雜質進入液晶側而產生殘像之虞。
較佳為,將金屬氧化物等靶之製造中使用之原料混合,使用通常之混合粉碎機例如濕式球磨機或珠磨機或超音波裝置,均勻地混合、粉碎。
本發明中,亦可於原料之成形前設置預燒步驟。預燒步驟係視需要而設置之於獲得濺鍍靶之原料即化合物之混合物後將該混合物進行預燒的步驟。
藉由預燒,而容易提高所獲得之燒結體之密度,較佳,但有成本上升之虞。因此,更佳為不進行預燒而提高密
度。
於預燒步驟中,較佳為將原料混合物於500~1200℃下進行1~100小時熱處理。未達500℃或未達1小時之熱處理存在銦化合物、鎵化合物、錫化合物及鋅化合物之熱分解不充分之情形。
另一方面,於熱處理條件超過1200℃之情形或超過100小時之情形時,存在產生粒子之粗大化之情形。
預燒尤佳為於800~1200℃之溫度範圍內實施2~50小時。
再者,此處所獲得之預燒物較佳為於下述成形步驟及煅燒步驟之前進行粉碎。
成形步驟係將原料混合物(於設置有上述預燒步驟之情形時為預燒物)加壓成形而製成成形體之必需步驟。藉由該步驟而成形為作為靶而較佳之形狀,例如圓筒形。圓筒形與平板形相比利用效率較高,因此較佳。於設置有預燒步驟之情形時,將所獲得之預燒物之細粉末進行造粒後,可成形為所需之形狀。
成形體之平均厚度較佳為5.5 mm以上,更佳為6 mm以上,進而較佳為8 mm以上,尤佳為12 mm以上。若為5.5 mm以上,則可期待膜厚方向之溫度梯度減少,難以產生表面與深部之晶型組合之變動。
作為本步驟中可使用之成形處理,例如可列舉:加壓成形(單軸加壓)、模具成形、澆鑄成形、射出成形等。為獲得燒結密度較高之燒結體(靶),較佳為以冷均壓(CIP,
Cold Isostatic Pressure)等進行成形。
又,亦可設置於加壓成形(單軸加壓)後再以冷均壓(CIP)、熱均壓(HIP,Hot Isostatic Pressure)等進行成形等2階段以上之成形步驟。
於使用冷均壓或均壓加壓裝置之情形時,較佳為以接觸壓力300~4000 kgf/cm2保持0.5~60分鐘,更佳為以接觸壓力350~3000 kgf/cm2保持2~30分鐘。
若為上述範圍內,則可期待成形體內部之組成不均等減少而均勻化。若接觸壓力未達30 kgf/cm2,則有燒結後之密度不提高或電阻變高之虞。若接觸壓力超過4000 kgf/cm2,則有裝置過大而不經濟之虞。若保持時間未達0.5分鐘,則有燒結後之密度不提高或電阻變高之虞。若超過60分鐘,則有過於耗費時間而不經濟之虞。
再者,成形處理亦可使用聚乙烯醇或甲基纖維素、聚蠟、油酸等成形助劑。
燒結步驟係煅燒上述成形步驟中所獲得之成形體之必需步驟。
作為燒結條件,較佳為於含氧氣之環境、氧氣環境或氧氣加壓下進行。若於不含氧氣之環境下進行燒結,則存在無法充分提高所獲得之靶之密度,無法充分抑制濺鍍時產生異常放電的情形。
至燒結溫度為止之升溫速度較佳為3℃/分鐘以下,更佳為2.5℃/分鐘以下,尤佳為1.5℃/分鐘以下。若升溫速度超
過3℃/分鐘,則有表面與深部之晶型組合發生變動之虞。一般認為其原因在於,升溫時於靶之厚度方向上產生溫度不均等。
再者,亦可於升溫過程中嘗試停止升溫並保持特定溫度而以2階段以上進行燒結。
燒結溫度較佳為1280℃以上1520℃以下,更佳為1300℃以上1500℃以下,更佳為1320℃以上1480℃以下。
燒結時間較佳為2小時以上96小時以下,更佳為4小時以上48小時以下,尤佳為6小時以上24小時以下。
冷卻時之降溫速度通常為4℃/分鐘以下,較佳為2℃/分鐘以下,更佳為1℃/分鐘以下,進而較佳為0.8℃/分鐘以下,尤佳為0.5℃/分鐘以下。若為4℃/分鐘以下,則容易獲得本發明之晶型。又,於降溫時不易產生裂痕。
於本發明中,為了整體性降低上述燒結步驟中所獲得之燒結體之體電阻,亦可設置還原處理步驟。作為還原方法,例如可列舉利用還原性氣體之方法或利用真空煅燒或惰性氣體之還原等。
於利用還原性氣體之還原處理之情形時,可使用氫氣、甲烷、一氧化碳或該等氣體與氧氣之混合氣體等。
於利用惰性氣體中之煅燒之還原處理的情形時,可使用氮氣、氬氣或該等氣體與氧氣之混合氣體等。
再者,於本發明中,較佳為不進行還原處理。若進行還原處理,則有產生或增大表面部與深部之電阻值差異之虞。
磨削(加工)步驟係將以上述方式燒結而獲得之燒結體切削加工成適合裝著於濺鍍裝置之形狀的步驟。於本發明中,亦可將上述步驟(c)中所獲得之燒結體之表面磨削0.1 mm以上。
磨削後,亦可研磨燒結體而提高表面之平滑性。該研磨(鏡面加工)可使用機械研磨、化學研磨、機械化學研磨(機械研磨與化學研磨之併用)等已知之研磨技術。
例如,可藉由如下方式而獲得:以固定研磨粒拋光機(拋光液:水)拋光至#2000以上,或於以游離研磨粒研磨(研磨材:SiC膏等)進行研磨後再將研磨材換成金剛石膏而進行研磨。此種研磨方法並無特別限制。
黏合步驟係將磨削後之燒結體黏合於襯板上之步驟。
再者,磨削步驟後之氧化物燒結體之清潔處理中可使用鼓風或流水洗淨等。於以鼓風去除異物時,若以集塵機自噴嘴之對面側進行吸氣則可更有效地去除。再者,由於鼓風或流水洗淨存在侷限,故亦可進而進行超音波洗淨等。該超音波洗淨中,於頻率25~300 KHz之間使其多重振動而進行之方法較為有效。例如,可於頻率25~300 KHz之間,每25 KHz進行12種頻率之多重振動而進行超音波洗淨。
包含本發明之氧化物燒結體之濺鍍靶較佳為氧化物燒結體部分之密度為5.5 g/cm3以上,更佳為6.0 g/cm3以上,進而較佳為6.3 g/cm3以上,尤佳為6.6 g/cm3以上。
又,較佳為,氧化物燒結體之相對密度為85%以上。若氧化物燒結體之相對密度為85%以上,則用作濺鍍靶時產生破裂或裂痕之虞減少。又,成膜速度加快。
又,較佳為,於氧化物燒結體內部,粒徑2 μm以上之氧化鎵之凝聚部分之數為10個/8100 μm2以下。
使用本發明之濺鍍靶而獲得之氧化物半導體薄膜可較佳地用於各種半導體元件。尤其是可較佳地用於薄膜電晶體之半導體層、氧化物薄膜層等,其中尤佳為半導體層。
以下,作為半導體元件之例,對薄膜電晶體進行說明。
作為薄膜電晶體之一例,將實施例中所製作之薄膜電晶體之概略剖面圖示於圖1。該薄膜電晶體係通道阻斷型(逆交錯型薄膜電晶體)。該薄膜電晶體係於基板10及閘極絕緣膜30之間挾持有閘電極20,且於閘極絕緣膜30上積層有通道層(氧化物半導體)40作為活性層。進而,以覆蓋半導體膜40之端部附近之方式分別設置有源電極50及汲電極52。於由半導體膜40、源電極50及汲電極52包圍之部分形成有蝕刻阻斷層(保護膜)60。
可使用本技術領域中公知者,並無特別限制。例如,可使用矽酸鹼系玻璃、無鹼玻璃、石英玻璃等玻璃基板,矽基板、丙烯酸系樹脂、聚碳酸酯、聚萘二甲酸乙二酯(PEN,Polyethylene Naphthalate)等樹脂基板,聚對苯二甲酸乙二酯(PET,Polyethylene Terephthalate)、聚醯胺等高分子膜基材等。
半導體層例如可藉由使用本發明之濺鍍靶形成薄膜而製作。亦可以使用2種以上之不同組成之靶之共濺鍍法、PLD法(脈衝雷射沈積法)、溶膠凝膠法等而形成。使用本發明之濺鍍靶易於工業化,因此較佳。
於該情形時,半導體層較佳為非晶質膜。藉由為非晶質膜,而可改善與絕緣膜或保護層之密接性,且可容易地獲得大面積下亦均勻之電晶體特性。此處,藉由X射線晶體結構分析而可確認半導體層是否為非晶質膜。於無法觀測到明確之波峰之情形時,為非晶質。再者,非晶質中亦可含有微晶。
薄膜電晶體亦可具有半導體之保護層。形成半導體之保護層之材料並無特別限制。可於不失去本發明之效果之範圍內任意選擇通常所使用者。例如,可使用SiO2、SiNx、Al2O3、Ta2O5、TiO2、MgO、ZrO2、CeO2、K2O、Li2O、Na2O、Rb2O、Sc2O3、Y2O3、Hf2O3、CaHfO3、PbTi3、BaTa2O6、SrTiO3,AlN等。其中,較佳為使用SiO2、SiNx、Al2O3、Y2O3、Hf2O3、CaHfO3,更佳為SiO2、SiNx、Y2O3、Hf2O3、CaHfO3,尤佳為SiO2、Y2O3、Hf2O3、CaHfO3等氧化物。該等氧化物之氧數並不一定與化學計量比一致(例如,可為SiO2亦可為SiOx)。又,SiNx亦可含有氫元素。
此種保護膜亦可為積層有不同之2層以上之絕緣膜的結
構。
形成閘極絕緣膜之材料亦並無特別限制,可任意選擇通常所使用者。例如,可使用SiO2、SiNx、Al2O3、Ta2O5、TiO2、MgO、ZrO2、CeO2、K2O、Li2O、Na2O、Rb2O、Sc2O3、Y2O3、Hf2O3、CaHfO3、PbTi3、BaTa2O6、SrTiO3,AlN等。其中,較佳為使用SiO2、SiNx、Al2O3、Y2O3、Hf2O3、CaHfO3,更佳為SiO2、SiNx、Y2O3、Hf2O3、CaHfO3。該等氧化物之氧數並不一定與化學計量比一致(例如,可為SiO2亦可為SiOx)。又,SiNx亦可含有氫元素。
此種閘極絕緣膜亦可為積層有不同之2層以上之絕緣膜的結構。又,閘極絕緣膜可為結晶質、多結晶質、非晶質之任一者,較佳為易於工業化製造之多結晶質或非晶質。
又,閘極絕緣膜亦可使用聚(4-乙烯酚)(PVP,Poly(4-Vinylphenol))、聚對二甲苯等有機絕緣膜。進而,閘極絕緣膜亦可具有無機絕緣膜及有機絕緣膜之2層以上積層結構。
形成閘電極、源電極及汲電極之各電極之材料並無特別限制,可於不失去本發明之效果之範圍內任意選擇通常所使用者。
例如,可使用氧化銦錫(ITO,Indium Tin Oxide)、氧化銦鋅、ZnO、SnO2等透明電極,或Al、Ag、Cr、Ni、
Mo、Au、Ti、Ta、Cu等金屬電極,或包含其等之合金金屬電極。
薄膜電晶體之各構成構件(層)可以本技術領域內公知之方法而形成。具體而言,作為成膜方法,可使用噴霧法、浸漬法、CVD(Chemical Vapor Deposition,化學氣相沈積)法等化學成膜方法,或濺鍍法、真空蒸鍍法、離子電鍍法、脈衝雷射沈積法等物理成膜方法。由於易於控制載子密度及易於提高膜質,故較佳為使用物理成膜方法,由於生產性較高,故更佳為使用濺鍍法。
可藉由各種蝕刻法使所形成之膜圖案化。
半導體層較佳為使用本發明之靶並藉由DC(Direct Current,直流)或AC(Alternating Current,交流)濺鍍而進行成膜。藉由使用DC或AC濺鍍,與RF(射頻,Radio Frequency)濺鍍之情形相比,可減少成膜時之損傷。因此,薄膜電晶體中可期待遷移率提高等效果。
又,本發明中較佳為,於形成半導體層及半導體之保護層後,於70~350℃下進行熱處理。若低於70℃,則有所獲得之電晶體之熱穩定性或耐熱性降低、遷移率降低、S值增大、或閾值電壓升高之虞。另一方面,若高於350℃,則有無法使用無耐熱性之基板、或花費熱處理用之設備費用之虞。
熱處理較佳為於惰性氣體中於氧分壓為10-3 Pa以下之環境下進行,或於以保護層覆蓋半導體層後進行。若為上述條件下,則再現性提高。
關於上述薄膜電晶體,較佳為遷移率為3 cm2/Vs以上,更佳為6 cm2/Vs以上,尤佳為10 cm2/Vs以上。若為3 cm2/Vs以上,則開關速度加快,可期待用於4K2K等大畫面高精細之顯示器。
開關比(on/off ratio)通常較佳為108以上,更佳為109以上,尤佳為1010以上。若開關比較高,則圖像之明暗變得清晰而可期待畫質之提高。
斷態電流通常為50 pA以下,較佳為10 pA以下,更佳為5 pA以下,尤佳為1 pA以下。若斷態電流為50 pA以下,則漏電流較少而於用於顯示器之TFT之情形時可期待提高畫質。
閾值電壓(Vth,Voltage Threshold)通常為-1.0~3.0 V,較佳為-0.5~2.0 V,更佳為-0.2~1.0 V,尤佳為0~0.5 V。若閾值電壓處於上述範圍內,則可降低驅動電壓而可減少消耗電力。
使用In2O3(BET(布厄特,Brunauer Emmett Teller)表面積28.5 m2/g)、Ga2O3(BET表面積15.3 m2/g)、SnO2(BET表面積58 m2/g)作為起始原料。以金屬元素之原子比為In:Ga:Sn=50:20:30之方式稱量該等原料。其後,相對於原料粉末總量添加1 wt%硬脂酸,使用行星式球磨機混合、粉碎8小時。
於混合、粉碎後,通過篩子使粒度一致,製成造粒粉末。將所獲得之造粒粉末填充至模具中,並藉由單軸加壓機進行加壓成形。再者,此時之接觸壓力設為120 kgf/cm2,保持時間設為2分鐘。其後,利用CIP(均壓加壓裝置)進行加壓。接觸壓力設為390 kgf/cm2,保持5分鐘。獲得密度3.5(g/cm3)之成形體。
其後,將所獲得之成形體於以下燒結條件下利用燒結爐進行燒結,而獲得密度6.0(g/cm3)之燒結體。
室溫~400℃:以0.5℃/分鐘進行升溫
400℃~800℃:以2℃/分鐘進行升溫
800℃~1400℃:以1℃/分鐘進行升溫
1400℃(燒結溫度):保持10小時
1400℃~室溫:自然冷卻
燒結環境:大氣下
以下述方法對所獲得之氧化物燒結體進行評價。
原子組成比:藉由ICP-AES分析原子比。
X射線繞射測定(XRD,X Ray Diffraction):於下述條件下直接測定氧化物燒結體及其切割片。
.裝置:Rigaku(股)製造之Ultima-III
.X射線:Cu-Kα射線(波長1.5406 Å,利用石墨單色器而單色化)
.2θ-θ反射法,連續掃描(1.0°/分鐘)
.採樣間隔:0.02°
.狹縫DS、SS:2/3°、RS:0.6 mm
密度(g/cm3):根據尺寸及質量進行計算。
外觀(顏色不均):於北窗日光下,自距離50 cm之位置目視燒結體,以下述方式進行評價。
A:幾乎不存在顏色不均
B:存在少許顏色不均
C:存在顏色不均
又,於燒結體中存在顏色不均之情形時,有例如於使用靶時難以判斷其狀態之虞。
燒結體之組成比與原料之組成比(原子比)一致。
將X射線繞射測定(XRD)之結果示於圖2。根據XRD、WPF(Whole Pattern Fitting,全譜擬合)及裏特沃爾德分析(Rietveld Analysis)之結果可知,所獲得之燒結體中Ga2In6Sn2O16所示之晶體結構之化合物為99.2%,實質上包含Ga3-xIn5+xSn2O16。
以金屬元素之原子比為In:Ga:Sn=50:30:20之方式稱量原料,除此以外以與實施例1相同之方式製作燒結體,並進行評價。成形體及燒結體之密度分別為3.2(g/cm3)、5.7(g/cm3)。
將X射線繞射測定(XRD)之結果示於圖3。根據XRD、WPF(全譜擬合)及裏特沃爾德分析之結果可知,所獲得之燒結體中,Ga2In6Sn2O16所示之晶體結構之化合物為
95.0%,實質上包含Ga3-xIn5+xSn2O16所示之晶體結構之化合物。
將以單軸加壓機進行加壓成形時之接觸壓力設為400 kgf/cm2,將CIP(均壓加壓裝置)加壓時之接觸壓力設為2000 kgf/cm2,除此以外以與實施例1相同之方式製作氧化物燒結體。將氧化物燒結體之表面磨削0.5 mm後進行研磨、鼓風,並進而進行3分鐘超音波洗淨。其後,利用銦焊而黏合於無氧銅製襯板上,製成靶。
使用已完成之濺鍍靶,製作圖1之通道阻斷型薄膜電晶體(逆交錯型薄膜電晶體)。
基板10係使用玻璃基板(Corning 1737)。首先,藉由電子束蒸鍍法於基板10上依序積層厚度10 nm之Mo、厚度80 nm之Al及厚度10 nm之Mo。使用光微影法及剝離法於閘電極20上形成積層膜。
藉由TEOS(Tetra Ethyl Ortho Silicate,正矽酸四乙酯)-CVD法於閘電極20及基板10上形成厚度200 nm之SiO2膜,形成閘極絕緣層30。再者,閘極絕緣層之成膜亦可利用濺鍍法,但較佳為利用TEOS-CVD法或PE(Plasma-Enhanced,電漿加強)CVD法等CVD法而形成。濺鍍法有斷態電流升高之虞。
繼而,藉由磁控RF濺鍍,而於全壓0.6 Pa、氧氣20%、
氬氣80%之條件下,使用(1)中所製作之靶,形成厚度50 nm之半導體膜40(通道層)。其後,於大氣中以300℃進行60分鐘熱處理。
藉由濺鍍法於半導體膜40上堆積SiO2膜作為蝕刻阻斷層60(保護膜)。再者,保護膜之成膜方法亦可為CVD法。
藉由光微影法及蝕刻法,將所堆積之氧化物半導體膜及保護膜加工成適當大小。
於形成蝕刻阻斷層60後,依序積層厚度5 nm之Mo、厚度50 nm之Al及厚度5 nm之Mo,藉由光微影法及濕式蝕刻而形成源電極50及汲電極52。
其後,於大氣中以300℃進行60分鐘熱處理,製作通道長度為20 μm、通道寬度為20 μm之電晶體。
薄膜電晶體之遷移率(場效遷移率(μ))、開關比、閾值電壓(V)係使用半導體參數分析儀(Keithley 4200),於室溫、遮光環境下進行測定。
使用已完成之濺鍍靶,於玻璃基板上濺鍍形成50 nm之薄膜。
將薄膜於加熱至30℃之磷酸-硝酸-乙酸(PAN,phosphoric,acetic and nitric acid)之混酸中浸漬特定時間,實施膜厚測定。將該操作重複3次以上,以浸漬時間為橫軸,以自初始膜厚減少之膜厚為縱軸,以其斜率作為蝕刻速度。
如表所示般變更原料之金屬元素之原子比,除此以外以與實施例3相同之方式製作、評價靶及TFT。
本發明之氧化物燒結體可用於薄膜電晶體之製作。
以上已對本發明之實施形態及/或實施例進行一些詳細說明,從業者容易實質上不脫離本發明之新穎之教示及效果,而於該等作為例示之實施形態及/或實施例中添加較多之變更。因此,該等較多之變更包含於本發明之範圍內。
將本說明書中記載之文獻及作為本案之巴黎公約優先權之基礎之日本申請說明書之內容全部引用於此。
10‧‧‧基板
20‧‧‧閘電極
30‧‧‧閘極絕緣層
40‧‧‧半導體膜
50‧‧‧源電極
52‧‧‧汲電極
60‧‧‧蝕刻阻斷層(保護膜)
圖1係使用本發明之濺鍍靶製作之TFT之一例的概略剖面圖。
圖2係實施例1中所製作之燒結體之X射線繞射測定(XRD)之結果。
圖3係實施例2中所製作之燒結體之XRD之結果。
Claims (11)
- 一種氧化物燒結體,其係以下述區域(A)及(B)中所包含之原子比而含有In、Ga、Sn及Zn:區域(A)0.38≦In/(In+Ga+Sn)<0.70 0.05<Ga/(In+Ga+Sn)<0.40 0.20<Sn/(In+Ga+Sn)≦0.50 0.00≦Zn/(In+Ga+Sn+Zn)<0.05 區域(B)0.25≦In/(In+Ga+Sn)<0.69 0.20≦Ga/(In+Ga+Sn)≦0.55 0.11<Sn/(In+Ga+Sn)≦0.20 0.00≦Zn/(In+Ga+Sn+Zn)<0.05。
- 如請求項1之氧化物燒結體,其中In、Ga及Sn之原子比滿足下式,且除不可避免地含有之雜質以外不含Zn:0.10<Ga/(In+Ga+Sn)<0.30 0.20<Sn/(In+Ga+Sn)≦0.30。
- 如請求項1之氧化物燒結體,其中In、Ga及Sn之原子比滿足下式,且除不可避地含有之雜質以外不含Zn:0.20≦Ga/(In+Ga+Sn)≦0.30。
- 如請求項1至3中任一項之氧化物燒結體,其含有Ga3-xIn5+xSn2O16(式中,X為0~1)所示之晶體結構之化合物作為主成分。
- 如請求項4之氧化物燒結體,其實質上含有Ga3-xIn5+xSn2O16(式中,X為0~1)所示之晶體結構之化合物。
- 如請求項4之氧化物燒結體,其內部與表面之晶體結構實質上相同。
- 如請求項1至3中任一項之氧化物燒結體,其具有圓筒狀之形狀。
- 一種濺鍍靶,其使用如請求項1至7中任一項之氧化物燒結體。
- 一種氧化物半導體薄膜,其係使用如請求項8之濺鍍靶並以濺鍍法形成而獲得。
- 一種薄膜電晶體,其含有如請求項9之氧化物半導體薄膜作為通道層。
- 一種顯示裝置,其係具備如請求項10之薄膜電晶體而成。
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CN104425623B (zh) * | 2013-09-09 | 2017-09-05 | 元太科技工业股份有限公司 | 薄膜晶体管 |
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CN106489209A (zh) * | 2014-09-02 | 2017-03-08 | 株式会社神户制钢所 | 薄膜晶体管 |
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