TW201244045A - Semiconductor substrate, semiconductor device and method for making a semiconductor substrate - Google Patents

Abstract

This invention provides a semiconductor substrate having: a base substrate of which the entire surface or a part of the surface is a silicon crystal surface, a hindrance member positioned on the base substrate, the hindrance member having an opening reaching the silicon crystal surface and adapted to hinder the growth of the crystal, a first crystal layer positioned on the silicon crystal surface exposed through the opening of the hindrance member, a pair of first metal layers positioned on the first crystal layer and arranged to separate from each other and a pair of second metal layers positioned on the first crystal layer and arranged to separate from each other, a first shortest line connecting respective pair of first metal layers, and a second shortest line connecting respective pair of second metal layers. The first shortest line and the second shortest line are in a crossing relation or in the relation of a twisted position.

Description

201244045 VI. Description of the Invention: TECHNICAL FIELD The present invention relates to a semiconductor substrate, a semiconductor device, and a method of manufacturing a semiconductor substrate. [Prior Art] Patent Document 1 describes an integrated hybrid magnetic sensor. The materials constituting the sensing portion of the magnetic sensor are described as InSb, InAs, GaSb,

GaAs, GaAsSb, InAsSb, InGaAs, InGaSb, InGaAsSb, InP, InGaP, InAsP, InGaAsP, InN, GaN, and InGaN o [Prior Art Document] (Patent Document) Patent Document 1: Japanese Patent Laid-Open Publication No. 2004-158668 】 (Problem to be Solved by the Invention) A semiconductor substrate suitable for manufacturing a Hall element having sufficient sensitivity is being sought. There is less chance of using a Hall element of a p-type carrier than a Hall element of an n-type carrier. This is considered to be due to the fact that the mobility of the p-type carrier is not very high. If the Hall element of the p-type carrier is provided, a complementary circuit can be formed together with the Hall element of the n-type carrier, and a circuit with rich variability can be constructed. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor substrate suitable for manufacturing a Hall element having a p-type carrier having sufficient sensitivity. Means for Solving the Problems In order to solve the above problems, a first aspect of the present invention provides a semiconductor substrate having: a base substrate 324031 in which all or a part of the surface is a ruthenium crystal surface;

S 201244045 plate; a substrate on the base substrate having an opening reaching the crystal surface of the stone and blocking the growth of the junction; a first crystal layer located above the crystal surface exposed by the opening; a first metal layer disposed on the layer and separated from each other, located on the second crystal layer, and separated from each other to be disposed adjacent to the second metal layer; wherein the first shortest line connecting the pair of first metal layers - The second shortest line connecting the second metal layers is a positional relationship of intersection, relationship, or skew. ^ The shape of the crystal layer is quadrilateral when viewed from the upper side. At this time, the direction of the first shortest line is used. It is preferable that the direction of the first diagonal line of the first crystal layer on the upper side is equal to the direction of the second diagonal line, and the direction of the second diagonal line is equal to the direction of the second diagonal line, and the second diagonal line is The aforementioned i-th diagonal in the i-th crystal layer is different from the side. The first crystal layer is a p-type semiconductor. The crystal layer is preferably ^<1). A second crystal layer composed of a mi-group compound semiconductor may be formed between the first crystal layer and the i-th metal layer or the second metal layer. In addition, the broken crystal surface at the bottom of the mouth refers to the crystal surface exposed by the opening σ. According to a second aspect of the present invention, there is provided a semiconductor device comprising the semiconductor substrate ’ The crystal layer serves as a carrier moving layer, a pair of first metal layers serves as a pair of main current electrodes, and a pair of second metal layers serves as a Hall element for the counter electrode. The obstructing body may have another opening at a position different from the opening of the Hall element. In this case, the semiconductor device may have the first crystal layer located at the other opening and the first crystal layer located at the other opening as the active layer. The active component, and the Hall component and the active component are interconnected by wires located on the obstructing body. Alternatively, the obstructing body may have other openings at a position different from the opening of the Hall 70 member. In this case, the semi-conductive 324031 201244045 body device may have the i-th crystal layer located at the other opening, and is located at the other. The other crystal layer formed on the crystal layer, the other crystal layer as the active element of the active layer, and the Hall element and the active element can be connected to each other by the wiring on the β-barrier. According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor substrate, which has the steps of: forming a barrier on a base substrate having all or part of a surface of a crystal surface; a step of forming an opening reaching the crystal plane of the crucible; a step of forming the first "grain layer" by epitaxial growth on the surface of the crystal surface exposed by the opening; and the obstructing body and the first crystal a step of forming a metal layer on the upper surface of the layer; and a step of patterning the metal layer to form a pair of main current electrodes and a pair of detecting electrodes. In the step of forming a pair of main current electrodes and a pair of detecting electrodes, A pair of main current electrodes are formed such that a linear direction connecting the respective electrodes of the main current electrode and a linear direction connecting the respective electrodes of the detecting electrode are in an intersecting relationship or a skewed positional relationship [Embodiment] Fig. 1A shows a plane of a semiconductor substrate 1A. The 帛ib diagram shows a cross section of the semiconductor substrate 100. The interception shown in Fig. 1B is shown in the figure. The semiconductor substrate 1A has a base substrate 102, an inhibitor 1〇4, a first crystal layer 1〇6, a pair of i-th metal layers 11〇, and a pair of second metal layers 112. All or part of the surface of the substrate 102 is a stone crystal surface i〇2a. The substrate of all or part of the surface of the crystal surface may be ♦ substrate or s〇i 324031

S 6 201244045 (Silicon on Insulator: substrate on the insulating layer). The base substrate 102 is preferably a ruthenium-based plate. When the base substrate 1 〇 2 is used as a substrate in which all or a part of the surface is a crystallization crystal, it is not necessary to use a high-priced compound semiconductor crystal substrate. In addition, since the base substrate 1 〇 2 uses the shi shi substrate, it is possible to use a conventional manufacturing apparatus and an existing process used in the wafer process, and a large diameter can be used as compared with the compound semiconductor substrate. The substrate can reduce the manufacturing cost of the semiconductor substrate 100. The obstruction body 104 is located on the base substrate 102 and has an opening σ 104a reaching the 矽 crystal plane l 〇 2a. The inhibitor 1〇4 system hinders crystal growth. The hindrance body 1〇4 may be exemplified by oxidized oxidized stone, cerium nitride, oxynitride, or oxidized. The size of the open-mouth purchase is preferably _ phantom m, more preferably 5 to 50/zra, and particularly preferably 3 〇 (four). Here, when the base substrate 102 which is exposed by the opening is square, the "size of the opening" is the length of the side, 2 is the length of the short side when the square is square, and the length of the short axis when the area is elliptical, The area is the diameter when it is circular. 102a^ The layer 1〇6 is located in the crystal surface exposed by the opening 1〇4& preferably, the crystal layer 1〇6 is preferably composed of (10) coffee, and the Sir X ei:X (〇^ X<1) is composed. For example, the first crystal layer 106 may have a composition of two: lC, SiCGn 1 crystal layer 106, more preferably "the inner portion of the e, the crucible layer 1〇6 is formed in the small opening 104a of 3〇_ or less, and the i L 4 defect is small. Most of them can be formed without defects. As a result, the quality is improved as follows: 曰 is the quality of 〇6 'while' when the first crystal layer 106 is shaped with the smear S, 'the second crystal layer has fewer or no defects, σ The quality of the crystal layer m曰曰 layer 106 can be directly grown on the surface of the radish crystal 324031 201244045 surface 1〇2a, or can be grown through the Si buffer layer or the SiGe buffer layer. The first crystal layer 106 is the base of the barrier body 104. The opposite surface of the surface where the substrate 102 is in contact protrudes. That is, the thickness of the first crystal layer 1〇6 is larger than the thickness of the inhibitor 104. The first crystal layer 1〇6 is on the surface that is in contact with the inhibitor 104 and A metal contact surface that is in contact with the pair of first metal layers 110 or the pair of second metal layers 112 is provided between the opposite surfaces of the surfaces on which the base substrate 102 is in contact with each other. The metal contact faces may be opposite to the first crystal faces 1〇6. The lamination direction is inclined. The metal contact surface may have a surface parallel to the surface in contact with the first crystal layer 1〇6 and the obstruction body 104. And a surface parallel to the surface in contact with the first crystal layer ι6 and the base substrate 102. The first crystal layer 106 may be recessed on the opposite surface of the surface in contact with the base substrate 102 of the inhibitor 1〇4. That is, the thickness of the second crystal layer 1〇6 may be smaller than the thickness of the inhibitor 104. In this case, the first crystal layer 1〇6 is attached to the surface that is in contact with the inhibitor 104 and the base substrate 1〇2. The opposite side of the surface has a metal contact surface that is in contact with the pair of first metal layers 110 or the pair of second metal layers 112. The first crystal layer 106 can be formed as a p-type semiconductor. a Hall element constituting a P-type carrier. The pair of first metal layers 110 are located on the first crystal layer 1〇6, and the first metal layers 110 are disposed apart from each other. The pair of second metal layers 112 are located at the first stage. The second metal layer 112 is disposed apart from each other on the crystal layer 106. The second shortest line 112a that connects the first shortest line 110a' and the pair of second metal layers 112, respectively, to which the pair of first metal layers 110 are connected is The relationship between intersections or skews. That is, the 1st shortest line

324031 S 201244045 110a and the second shortest line 112a may be in a relationship intersecting on the same plane, and the first shortest line lla and the second shortest line 112a may be independent of each other and not parallel to each other, and are skewed. . With such a relationship, when either of the pair of first metal layers 110 and the pair of second metal layers 112 is used as the main current electrode and the other is used as the detecting electrode, the semiconductor substrate 100 has van der Pauw. The function of the Hall element of the type. The metal layer is, for example, a single layer of Au, AuGe, or Ni or a laminate of two or more of these. Further, the first shortest line 11a and the second shortest line 112a preferably intersect at an angle of slightly 90 as viewed from above the plane on which the first metal layer 11 or the second metal layer U2 is formed. The second shortest line 11〇a and the second shortest line n2a are slightly 90. The second metal layer 11A and the second metal layer 112 are disposed at an angle to each other, whereby the magnetic detection sensitivity at the time of forming the Hall element can be improved. The shape of the first crystal layer 106 as seen from above is, for example, a quadrangle. The shape of the first crystal layer 106 as viewed from above may be square. For example, the direction of the i-th shortest line 11〇a connected to each of the pair of first metal layers 110 is equal to the two diagonal lines of the second crystal layer 1〇6 viewed from above. 1 diagonal direction. The direction 'the direction of the second shortest line 112a to which the pair of second metal layers 112 are connected is equal to the second angle different from the β-th angle of the two diagonal lines of the first crystal layer 1G6 as viewed from above. The direction of the diagonal. For example, the first metal layer 110 and the second metal layer 112 have a quadrangular shape as viewed from above. The shape of the 帛1 metal layer 11G and the second metal layer 112 as viewed from above may be square. From the top, the area where each of the genus layer 110 and the second metal layer 112 overlaps the ith crystal layer 〇6 is a quadrangle. The i-th crystal layer 1〇6, the i-th metal layer 11〇, and the second metal layer 112 have a square shape as viewed from above, and each of the first metal layer 110 and the second metal layer 112 and the first crystal layer are viewed from above. The area where 1〇6 overlaps may be square. In the above configuration, a region in which each of the first metal layer 110 and the second metal layer 112 overlaps with the first crystal layer 106 is formed in a quadrangular region of the four corners of the i-th crystal layer 1〇6. The pair of second metal layer 11A and the pair of second metal layers 112 can be easily formed by the quadrangular region formed at the four corners of the first crystal layer 1〇6 and the inhibitor 104' even if the first crystal layer 1 is 6 μm. The first metal layer 110 and the second metal layer 112 are formed. In the semiconductor device, the semiconductor substrate 1 described above has a j-th crystal layer as a carrier transfer layer, a pair of second metal layers 11 as a pair of main electric/melon electrodes, and a pair of second metal layers 112 as one. The function of the Hall element of the detection electrode. Further, the other semiconductor substrates described below also have a function as a Hall element. According to the semiconductor substrate 100, - on the first! Among the metal layer 11A and the pair of second metal layers 110, the first shortest line 110a to which the pair of first metal layers (10) are connected and the second shortest line U2a to which the second metal layer 112 is connected are intersecting relationship st The skewed positional relationship can thus constitute a Hall 7G piece in a semiconductor device. Then, since the Hall element has a p-type carrier, it can constitute a P-type Hall element. Again, because of the first! The crystal quality of the crystal layer 1G6 is good, so the P-type Laizhi (4) component can also achieve high sensitivity. Fig. 2 and Fig. 3 show a section of 324031 201244045 in the manufacturing process of the semiconductor substrate 1A. As shown in Fig. 2, an obstruction body 104 is formed on the base substrate 102, and an opening 104a reaching the crucible crystal plane l2a is formed on the obstruction body 104. Next, as shown in Fig. 3, a first crystal layer 106 composed of SixGei-x (0Sχ<1) is formed by the crystal growth method on the dream crystal plane 102a exposed by the opening 1 〇 4a. . The epitaxial growth of the first crystal layer 106 and the second crystal layer 202 to be described later can be performed by a CVD (Chemical Vapor Deposition) method or a MOCVD (Metal Organic Chemical Vapor Deposition) method. In the CVD method, GeH4 (stane) can be used as the Ge source, SiH decane can be used as the Si source, or Si2H6 (dioxane) can be used. In the M0CVD method, a Ge source can use tBuGe (tertiary butyl decane), a Si source can use TMeSi (tetradecyl decane), an In source can use TMIn (tridecyl indium), and a Ga source can use TMGa (three oxime). Glycerium), A1 source can use TMA1 (tridecyl aluminum), As source can use AsH3 (胂), P source can use PH3 (phosphine), N source can use leg (ammonia), Sb source can use TMSb (three曱基锑). Hydrogen can be used as the carrier gas. The reaction temperature is preferably from 300 ° C to 11 Torr. The range of (: is preferably in the range of 450 ° C to 750 ° C. The preferred reaction temperature varies depending on the composition of the crystal formed by epitaxial growth. It can be controlled by appropriately selecting the reaction time. The thickness of the epitaxial growth layer is formed. After the first crystal layer 106 is formed, a film is formed on the upper surface of the inhibitor 1〇4 and the first crystal layer 106, and the metal layer is patterned to form a pair of first metal layers. 110 and a pair of second metal layers 112. Thus, the semiconductor substrate 1A shown in Figs. 1A and 1B can be formed. Further, the first crystal layer is preferably annealed. By annealing, 324031 11 201244045 is obtained. The i-th crystal layer having a good crystal quality is 1〇6. In addition, an insulator may be buried in the trace of etching (patterning) of the metal layer. In this case, the insulator may be yttrium oxide, tantalum nitride, hafnium oxynitride, or oxidation. Fig. 4 shows a cross section of the semiconductor substrate 200. The semiconductor substrate 200 has a second crystal layer 2〇2 in addition to the member of the semiconductor substrate 1. The second crystal layer 202 is located in the first crystal layer ι6 and Between the first metal layer u〇 or the second metal layer 112. The second crystal 202 is composed of a Π-V group compound semiconductor. The second crystal layer 202 may be composed of InGaAlAsPNSb, preferably InGaAlAsP. Examples of the second crystal layer 202 include GaAs, InSb, InAs, GaP, and InP. GaN, InN, A1N, etc. The second crystal layer 202 is formed on the i-th crystal layer 106 having good crystallinity, so that crystal defects are few, and many of them can be formed without defects. The second crystal layer 202 is preferably formed with the first crystal. Layer 1 〇6 is lattice-matched (1 att ice-matched) or pseudo-lattice matching. By performing lattice matching or pseudo-lattice matching with the first crystal layer 106 having good crystallinity, the second crystallinity can be obtained. The crystal layer 202. When the first crystal layer 1〇6 is Ge, the second crystal layer 202 is preferably GaAs, InGaAs, InGaAsP or InGaAsN which is lattice-matched or pseudo-lattice matched to the first crystal layer 1〇6. When the crystal layer 106 is Ge, the second crystal layer 202 may be a crystal which is lattice-matched or pseudo-lattice-matched with GaAs. The first crystal layer 106 made of Ge is annealed, thereby making it high-quality. The second crystal layer 202 formed on the Ge crystal is preferably a higher quality crystal, and is preferred. The layer 202 can be two crystal layers which are mutually different compositions. By making the energy gaps of the two crystal layers different from each other, two crystals can be obtained 12 324031

The interface of the S 201244045 layer forms a hetero barrier. The heterogeneous barrier is used as a boundary, and the layer that produces the carrier and the layer that moves the carrier can be separated. So you can • get a higher carrier movement rate. As a result, a Huerle component with improved sensitivity can be obtained. The second crystal layer 202 may be composed of three or more crystal layers. A quantum well can be formed from the three or more crystal layers, and a higher mobility can be obtained even if the concentration of the impurity atoms of the quantum well layer is lowered. This makes it possible to obtain a Hall element with improved sensitivity. The mobility of the conventional p-type carrier is not high, but according to the present invention, the Hall element having a very p-type carrier mobility can be obtained. Therefore, the complementary type circuit can be constructed by combining the Hall element of the p-type carrier and the Hall element of the n-type carrier. Fig. 5 shows a cross section of the semiconductor substrate 300. In the semiconductor substrate 3, the "obstruction body 104" has another opening 104b at a position different from the opening i?4a of the Hall element, and has a first crystal layer 106 inside the other opening i?4b. Further, the other crystal layer 108 formed on the first crystal layer 106 of the other opening i 〇 4b and the other crystal layer 302 are formed as active layers to form an active element. Next, the Hall element and the active element are connected to each other by a wiring 304 located on the blocking body 104. The wiring 304 is separated by the insulating layer 306' from the first crystal layer 1〇6 and other crystal layers 108 located in the other openings i〇4b. The active device may be, for example, a HEMT (High Electron Mobility Transistor). For example, when the second crystal layer ι〇6 is Ge, the crystal layer 1〇8 is i_GaAs (pure gallium arsenide), and the crystal layer 3〇2 324031 13 201244045 is n-AlGaAsOi type gallium arsenide aluminum, a crystal layer can be formed. 1〇8 and crystal layer 302 are used as the active layer of HEMT. In addition, the active component can be exemplified by HBT (Heter〇juncti〇nBip〇lar·Transistor. Heterojunction bipolar transistor). For example, the i-th crystal layer 106 forms Ge, and three or more crystal layers are laminated on the first crystal layer 1〇6. For example, on the first crystal layer 丨06, n-GaAs (sub-c〇llect〇r layer) n-GaAs (high impurity concentration n-type gallium arsenide) and a drain layer n-GaAs ( N-type gallium arsenide), p+-GaAs in the underlying layer (p-type gallium arsenide with high impurity concentration), n-InGaP (n-type indium gallium phosphide) in the emitter layer, and sub-emitter layer n+_GaAs (n-type deuterated gallium with high impurity indifference) and ηΜη_ (n-type stone indium gallium) of the emitter electrodeless layer can be formed as an active component function. In other words, the 汲 can include a human 汲 layer composed of n+ GaAs, a drain layer composed of n-GaAs, a base layer composed of p+ GaAs, and an emitter composed of n-InGaP. The layer, the sub-emitter layer composed of n+_GaAs, and the HBT of the emitter drain layer composed of n-InGaAs. Other active components include HFET (Hetero-Field Effect Transistor). There are also cases where other crystal layers are not present on the first crystal layer 1〇6 of the other openings l〇4b. At this time, the second crystal layer 1〇6 can serve as an active layer of the active element. For example, the conductivity of the first crystal layer 106 can be adjusted by the introduction of the impurity atoms, and the FET (Fleid Effect Transistor) which forms the channel of the J-th crystal layer 1〇6 can be formed. In this case, the i, , and "b" layers 106 include Ge and p-type Ge. By making the first crystal layer 1 〇 6 324031

S 14 2〇1244045

A P-type FET can be formed as an active element for the P-type P w '. An n-channel type mosfet dtal 〇 〇 yj 欵 cle cle S S S S S 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底 基底Metal - can constitute a CMOSFET (Complementary MOSFET, complementary NMOS, first semiconductor field effect transistor). At this time, the ?-type MOSFET on the base substrate 102 and the p-channel type M?SFE:T on the first crystal layer are connected to each other by the wiring 304. When the CMOS transistor is formed as the main piece, it is preferable because the Hall element and the CMOS device (CM0SFE1T) can be integrated with the cmIs to make the device smaller. In addition, make a combination of Hall element arrays. The unit of the device is arranged in the plane, thereby forming a magnetic sensor

In the combination of the Hall element formed by Ge and the CMOS device, a Ge layer selectively grown in the same manner as the device can be used as the p-type channel. Since the Ge P type carrier has a high mobility, it is also possible to speed up the CMOS device, which is preferable. Furthermore, since the CMOS device consumes less power, it is preferable. When the active device (for example, CMOS converter) and the Hall device composed of Ge jin are formed by the selective growth method, the growth of Ge and the subsequent heating are preferably performed so as not to cause the existing active device (for example, on the base substrate 102). The temperature of the range of thermal deterioration of the n-channel type MOSFET is performed. It can be applied to a magnetic head or the like by using such a device in which a Hall element is combined with an active element. Further, the first crystal layer 1〇6 located at the opening 104a and the first crystal layer 1〇6 located at the opening 104b can be simultaneously formed by the same epitaxial growth step. When the first crystal layer 1〇6 is simultaneously formed by the same crystal growth step, the steps of forming the Hall element and the active element can be simplified, and the manufacturing can be reduced to 324031 15 201244045. According to the semiconductor substrate 300, active elements such as a Hall element and a transistor can be integrated on the single base substrate 1A2. For example, the λ number of the Hall element is used for the purpose of amplifying an active element such as a transistor. The Hall element is constructed to have a plurality of the above Hall elements on a single base substrate 1〇2. Further, the active element of the Hall element and the transistor shown in Fig. 5 can have a plurality of active elements on the single base substrate 1〇2. (Example) A oxidized stone layer was formed by thermal oxidation on a stone substrate, and an open π of 3 () / ζ π ϋ (square of the side length) was formed on the oxidized stone layer by photolithography and (10). . The opening of the μ crystal growth method forms a Ge layer of thickness _. The Ge layer was annealed for 10 cycles by a cyclic annealing method in which a two-stage annealing of 800 t and 68 〇〇 c was repeated. Further, the Ti layer and the Au layer were each formed into a Ti layer having a thickness of 1 〇〇 Α and a thickness of 2500 A by vacuum deposition. The metal layer is patterned to form a main current electrode and a detecting electrode. Fig. 6 is a photomicrograph of the component (4) observed from above. A and C are electrodes for current, and ... are detection electrodes. The respective metal layers are separated from each other8. Figure 7 shows the current-voltage characteristics of the fabricated (four) pieces. No observation of the characteristics of Xiao (SehQttky), but observing Oum (10) mie). As a result of the fabrication of the Hall element, the resistivity is 2.00 ± 0.05 [Qm], the Hall coefficient is 〇〇 6 〇 ± 〇〇〇 5, and the mobility is 303 ± 13 [cin2 / TS] ' Carrier density For h 〇 ± 〇 · lxi 〇 2D [cm_3]. 324031 201244045 In addition, a device in which a Hall element and a CUSFET as an active element are integrally formed on the same substrate can be manufactured by the following method. In other words, a portion of the Si substrate is formed to form a substrate of an n-channel type MOSFET, and an insulating layer composed of S i 〇 2 covers the surface of the substrate. The formation of the p-channel type MOSFET and the formation of Si 〇 2 at the Hall element are performed by photolithography, and the Si substrate is exposed to form an opening. Mounting the substrate on the CVD device and

Gelh is used as a raw material to selectively grow Ge in the opening, followed by annealing for improving the crystal quality. An electrode is formed on the Ge crystal of the portion where the Hall element should be formed by a steaming method. On the other hand, an oxide layer serving as a gate insulating layer is formed on the Ge crystal to be formed into a p-type portion, and the respective elements are connected by wiring. By the above, the Hall element and the CMOS element can be formed on the same substrate as a whole. In addition, the middle layer of this specification

When the first element such as the Ihe code is located on the second element (Qn), 'except for the second element directly on the second element', it is also included between the second element and the f 2 element with a == indirectly The situation on the second element. In addition, by exposing the crystal surface, it means the bottom of the opening. [Simple description of the figure] 8. The sun surface. The first, first, and first drawings show the plane of the semiconductor substrate. 1B shows a cross section of the semiconductor substrate 1A. 2 is a view showing a manufacturing process of a semiconductor substrate 1 . 3 shows a cross section of the semiconductor substrate 200 during the manufacturing process of the semiconductor substrate 100. The figure 5 shows the wearing surface of the semiconductor substrate 300. Cross section. Cross section. 324031 17 201244045 Fig. 6 is a photomicrograph showing a semiconductor substrate of the embodiment. Fig. 7 is a graph showing the current-voltage characteristics of the Hall element of the embodiment. [Description of main components] 100, 200, 300 Semiconductor substrate 102 Base substrate 102a 矽 Crystal plane 104 Obstruction body 104a, 104b Opening 106 First crystal layer 108 Crystal layer 110 First metal layer 110a First shortest line 112 Second metal layer 112a second shortest line 202 second crystal layer 302 crystal layer 304 wiring 306 insulating layer 324031 18

Claims (1)

201244045 » VII. Patent application scope: 1. A semiconductor substrate having: w a base substrate having all or part of a surface of a crystal surface; _ located on the base substrate, having an opening reaching the aforementioned crystal plane, and obstructing a first crystal layer located on the first crystal layer exposed by the opening; One of the second metal layers is disposed on the first crystal layer, and the second shortest line connecting the first shortest line and the pair of second metal layers respectively connected to the pair of first metal layers is The relationship between intersections or skews. 2. The semiconductor substrate according to claim 1, wherein the shape of the first crystal layer viewed from the upper side is a quadrangle, and the direction of the first shortest line and the first one seen from the upper side. The direction of the first diagonal line of the crystal layer is equal; the direction of the second shortest line is equal to the direction of the second diagonal line, and the second diagonal line is the same as that of the first crystal layer seen from the upper side The first diagonal is different. 3. The semiconductor substrate according to claim 1, wherein the first crystal layer is a p-type semiconductor. 4. The semiconductor substrate according to claim 1, wherein the first crystal layer of the above-mentioned 324031 1 201244045 is composed of SixGei-x (〇$x<l). 5. The semiconductor substrate according to claim 2, wherein the first crystal layer and the first metal layer or the second metal layer are made of a bismuth-V compound semiconductor. The second crystal layer. A semiconductor device having a semiconductor substrate according to claim j, comprising: the second germanium crystal layer as a carrier moving layer, and the pair of second metal layers as a pair of main currents The electrode is a Hall element in which a pair of second metal layers are used as a pair of detecting electrodes. 7. The semiconductor device according to claim 6, wherein the obstructing body has another opening at a position different from the opening of the Hall element, and further includes: the first one located in the other opening The crystal layer and the active element of the first crystal layer located in the other opening are used as an active layer, and the Hall element and the active element are connected to each other by a wiring located on the inhibitor. 8. The semiconductor device according to claim 6, wherein the obstructing body has another opening at a position different from the opening of the Hall element, and further includes: the first one located in the other opening a crystal layer, another crystal layer of 324031 S 201244045 formed on the first crystal layer of the other opening, and an active element having the other crystal layer as an active layer, wherein the Hall element and the active element are located in the foregoing hindrance The wiring on the body is connected to each other. A method of manufacturing a semiconductor substrate, comprising the steps of: forming a barrier on a base substrate having all or one of a surface of a ruthenium crystal surface; forming a pre-escape sand on the hindering body a step of forming an opening of the surface; a step of forming a first crystal layer by the crystal growth method; and forming a first crystal layer on the upper surface of the inhibitor and the first crystal layer; and forming the metal layer Layer patterning 'steps of forming a pair of detection electrodes. U-electrode and -10· As claimed in the patent application, the manufacturing method of the first ten (fourth) riding, the formation of a pair of main current electrode steps, so that Yu, +, the direction of the detection electrode in the straight line direction and the aforementioned - pair The linear direction in which the respective electrodes of the detecting electrodes are connected is a relationship of intersections & the electrodes are connected to each other to the main current electrode and the pair of detecting electrodes. Way of relationship, shape 324031 3