TW201227855A - Method for mounting semiconductor element, and mounted product - Google Patents
Method for mounting semiconductor element, and mounted product Download PDFInfo
- Publication number
- TW201227855A TW201227855A TW100143300A TW100143300A TW201227855A TW 201227855 A TW201227855 A TW 201227855A TW 100143300 A TW100143300 A TW 100143300A TW 100143300 A TW100143300 A TW 100143300A TW 201227855 A TW201227855 A TW 201227855A
- Authority
- TW
- Taiwan
- Prior art keywords
- insulating resin
- resin layer
- bump
- substrate
- semiconductor element
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 90
- 238000000034 method Methods 0.000 title claims abstract description 67
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- VZSRBBMJRBPUNF-UHFFFAOYSA-N 2-(2,3-dihydro-1H-inden-2-ylamino)-N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]pyrimidine-5-carboxamide Chemical compound C1C(CC2=CC=CC=C12)NC1=NC=C(C=N1)C(=O)NCCC(N1CC2=C(CC1)NN=N2)=O VZSRBBMJRBPUNF-UHFFFAOYSA-N 0.000 description 2
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- AFCARXCZXQIEQB-UHFFFAOYSA-N N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]-2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidine-5-carboxamide Chemical compound O=C(CCNC(=O)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F)N1CC2=C(CC1)NN=N2 AFCARXCZXQIEQB-UHFFFAOYSA-N 0.000 description 2
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- PXKLMJQFEQBVLD-UHFFFAOYSA-N bisphenol F Chemical compound C1=CC(O)=CC=C1CC1=CC=C(O)C=C1 PXKLMJQFEQBVLD-UHFFFAOYSA-N 0.000 description 2
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- ZCUJYXPAKHMBAZ-UHFFFAOYSA-N 2-phenyl-1h-imidazole Chemical compound C1=CNC(C=2C=CC=CC=2)=N1 ZCUJYXPAKHMBAZ-UHFFFAOYSA-N 0.000 description 1
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- 239000005977 Ethylene Substances 0.000 description 1
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- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 241000935974 Paralichthys dentatus Species 0.000 description 1
- LGRFSURHDFAFJT-UHFFFAOYSA-N Phthalic anhydride Natural products C1=CC=C2C(=O)OC(=O)C2=C1 LGRFSURHDFAFJT-UHFFFAOYSA-N 0.000 description 1
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- 244000007853 Sarothamnus scoparius Species 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
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- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 150000008064 anhydrides Chemical class 0.000 description 1
- 125000003118 aryl group Chemical group 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- JHIWVOJDXOSYLW-UHFFFAOYSA-N butyl 2,2-difluorocyclopropane-1-carboxylate Chemical compound CCCCOC(=O)C1CC1(F)F JHIWVOJDXOSYLW-UHFFFAOYSA-N 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
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- 238000011109 contamination Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
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- ZLNQQNXFFQJAID-UHFFFAOYSA-L magnesium carbonate Chemical compound [Mg+2].[O-]C([O-])=O ZLNQQNXFFQJAID-UHFFFAOYSA-L 0.000 description 1
- 239000001095 magnesium carbonate Substances 0.000 description 1
- 229910000021 magnesium carbonate Inorganic materials 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- FPYJFEHAWHCUMM-UHFFFAOYSA-N maleic anhydride Chemical compound O=C1OC(=O)C=C1 FPYJFEHAWHCUMM-UHFFFAOYSA-N 0.000 description 1
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- 239000011733 molybdenum Substances 0.000 description 1
- CJRQAPHWCGEATR-UHFFFAOYSA-N n-methyl-n-prop-2-ynylbutan-2-amine Chemical compound CCC(C)N(C)CC#C CJRQAPHWCGEATR-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29075—Plural core members
- H01L2224/2908—Plural core members being stacked
- H01L2224/29082—Two-layer arrangements
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
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- H—ELECTRICITY
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Description
201227855 、發明說明: 【發明所屬之技術分野】 本發明係關於半導體元件之封裝方法及封裝體。 【先前技術】 作為將1C晶片等之半導體元件與印刷電路板(PCB) 等之基板連接的方法之一有覆晶(flip chip)工法。此覆晶 工法係使前述1C晶片中的凸塊(bump )與前述PCB中的 電路對向,使直接接觸或間隔導電性粒子而接觸的同時, 藉由加熱加壓而作電氣的連接。
一直以來,間隔著前述導電性粒子的連接係使用異方 性導電膜(ACF ; Anisotropic Conductive Film )。就此 ACF 而言,一般使用環氧樹脂系之接著劑層中使導電性粒子分 散者,例如,於前述1C晶片及前述基板之間配置前述ACF, 加熱押壓時,由於前述導電性粒子被包夾於前述1C晶片之 凸塊及前述基板中的電極之間而壓擠,實現了前述1C晶片 的凸塊與前述電極之電氣連接。 近年來,伴隨電子機器的小型化及高機能化,經由半 導體裝置的高集聚化,加速了 1C晶片之凸塊間空間的狹距 化及凸塊面積的狹小化。 然而,前述導電性粒子之粒子徑有2μιη左右的限度, 藉由異方性導電膜的接著係有其侷限的。 因此,作為可對應凸塊間空間的狹距化及凸塊面積的 狹小化的連接法,正關注於將前述1C晶片中的凸塊與前述 201227855 基板中的電路間隔者非導電性膜(NCF : Non Conductive Film)加以接著的NCF接合法。此NCF接合法並未使用前 述導電性粒子,而係使用金凸塊(stud bump )作為前述1C 晶片的凸塊來使用,於前述1C晶片與前述基板壓著時,藉 由前述金凸塊會與前述基板接觸,藉由壓擠,使前述1C晶 片與前述基板直接接合。 於前述NCF接合法,將前述1C晶片與前述基板壓著 後,又於壓著時’藉由加熱,使前述]SfCF硬化,而實現接 著及1C晶片與基板之黏接。 然而’未高精密度地控制壓著條件時,前述1C晶片的 凸塊會過度壓擠,鄰接的凸塊間會產生接觸,而有發生導 通不良,即有所謂會產生短路的問題。尤其,產生凸塊間 空間的狹距化的問題係為顯著。 就改良導通的技術而§ ’已揭示於JC晶片的電極使用 球形接頭(joint ball),間隔著二層構造的NCF,而將1C 晶片與基板接合的方法(參照專利文獻1)。於此提議的技 術’為了將前述NCF作成二層構造,於前述NCF之厚度 方向,形成於單一種環氧樹脂組成物中含有無機質填充劑 及不含有無機質填充劑的層。 然而’此挺案之技術有無法防止凸塊過度壓擠的問題。 又,已揭示使用可溶性聚醯亞胺的組成為相異的二層 構造的接著片的NCF接合方法(參照專利文獻2 )。 此提案之技術會降低切割時的破裂、缺損、剝離等之 缺點’雖可減少經切削粉所致的污染,但是於無法防止凸 201227855 塊過度壓擠的有問題。 為了防止壓著時凸塊過度壓擠,亦考量使NCF於某程 度硬化,於將NCF變硬的狀態下將凸塊壓著,但於如此情 形,有所謂NCF之接著性變低的問題。 因此,目前正冀求防止由於凸塊過度壓擠所致的導通 不良,同時提供接著性良好的半導體元件之封裝方法、及 由該半導體元件之封裝方法所獲得的封裝體。 [先前技術文獻] [專利文獻] [專利文獻1]特開平10-289969號公報 [專利文獻2]特開2009-21562號公報 【發明内容】 [發明概要] [發明所欲解決的課題] 本發明係以解決向來的前述諸問題,並達成以下目的 為課題。即,本發明係以防止凸塊過度壓擠所致的導通不 良〔短路(short)〕,同時提供接著性良好的半導體元件之 封裝方法、及藉由該半導體元件之封裝方法所獲得的封裝 體為目的。 [用以解決課題的手段] 作為用以解決前述課題的手段如下。即, <1> 一種半導體元件之封裝方法,其特徵為包含下 列步驟: 5 201227855 積層物製作步驟,其係於形成凸塊的半導體元件之具 有前述凸塊的面上,依序製作積層硬化的第一絕緣性樹脂 層、未硬化之第二絕緣性樹脂層的積層物; 配置步驟,其係於具有電極的基板上,配置前述積層 物使前述基板之具有前述電極的面與前述第二絕緣性樹脂 層成為對向, 接續步驟,其係將前述半導體元件加熱及押壓,使前 述第二絕緣性樹脂層硬化的同時,將前述凸塊與前述基板 之前述電極作電氣接續。 <2>如前述<1>記載之半導體元件之封裝方法,其 中第二絕緣性樹脂層之硬化溫度(T2)與第一絕緣性樹脂 層之硬化溫度(Τ!)之差(T2-TJ為20t以上。 <3>如前述< 1>或<2>項記載之半導體元件之封 裝方法,於積層物製作步驟,未硬化的第二絕緣性樹脂層 被積層於硬化的第一絕緣性樹脂層上。 <4>如前述<1>至<3>項中任一項記載之半導體 元件之封裝方法,其中凸塊為銲錫球(soldering ball)。 <5> —種封裝體,其特徵為其係藉由前述< 1>至< 4>項中任一項記載之半導體元件之封裝方法而獲得。 [發明之效果] 依據本發明,可解決向來之前述諸問題,達成前述目 的之防止凸塊過度壓擠所致的導通不良〔短路(short)〕, 同時提供接著性良好的半導體元件之封裝方法、及藉由該 半導體元件之封裝方法所獲得的封裝體。 201227855 【實施方式】 [用以實施發明之形態] (半導體元件之封裝方法、及封裝體) 本發明之半導體元件之封裝方法至少包含積層物製作 步驟、配置步驟、連接步驟,更視需要包含其他步驟。 本發明之封裝體係藉由本發明之前述半導體元件之封 裝方法而獲得。 <積層物製作步驟> 就前述積層物製作步驟而言,只要於具有形成凸塊的 半導體元件之前述凸塊的面上,依序製作積層硬化的第一 絕緣性樹脂層、及未硬化的第二絕緣性樹脂層的積層物的 步驟即可,並未特別限定,可因應目的加以適當選擇。 就前述積層物製作步驟而言,例如,可舉例於前述半 導體元件之具有前述凸塊的面上,形成未硬化之第一絕緣 性樹脂層後,於未硬化之第一絕緣性樹脂層上,積層未硬 化之第二絕緣性樹脂層,再使前述未硬化之第一絕緣性樹 脂層硬化的步驟。又,於此時,前述未硬化之第二絕緣性 樹脂層並未硬化。 又,例如,可舉例於前述半導體元件之具有前述凸塊 的面上,形成未硬化之第一絕緣性樹脂層後,使前述未硬 化之第一絕緣性樹脂層硬化,於此硬化的第一絕緣性樹脂 層上,積層未硬化之第二絕緣性樹脂層的步驟。 -半導體元件- 就前述半導體元件而言,只要形成前述凸塊的半導體 201227855 特別限定’可因應目的加以適宜選擇,例 ,日日體咖输)、半導體開關元件(thyri (chode)等。又,前述半導體元件係經 )-= 之各半導體元件的集合體,即,可為各::::則 半導體晶圓。 #體讀形成的 就前述凸塊而言,並未特別限定,可因應目 宜選擇,例如’可舉例金凸塊、銲錫球等。例如,前^ j可使用金屬電線而形成。例如,前述銲錫球可藉由於 ^導體凡件之電極-邊併用超音波一邊加熱及加麗而固定 來形成。此等中,就前述凸塊而言,銲錫球為較佳。 就前述凸塊之平均高度而言,並未特別限定,可因應 目的加以適宜選擇,例如,可舉例1一〜。並中, 塊之高度’換言之,係指自成為凸塊的突起的前述 半導體,件面的最大高度。前述凸塊之平均高度係將前述 凸塊之南度於任意50點測量之平均値。 就前述凸塊之平均間距(凸塊間距離)而言’並未特 別限定’可因應目的加以適宜選擇,例如,可舉例%卿〜 150μιη。 前述凸塊之平均間距係將前述凸塊之間距於任意20點 測量之際之平均値。 其中關於剛述凸塊的高度、及前述凸塊之間距使用 圖式加以説明。第1圖係形成凸塊2的半導體元件1之概 略剖面圖。於第1圖’前述凸塊2之高度⑻為成為凸塊 201227855 的突起之最大高度。又,前述凸塊2之間距(L)為鄰接的 前述凸塊之中心間距離。 於前述半導體元件之封裝方法,因可防止前述凸塊於 必要程度以上壓擠,即使如上述之凸塊間距離短,即所謂 的狹間距,亦不會引起短路,且可將半導體元件於基板上 封裝。 -第一絕緣性樹脂層、及第二絕緣性樹脂層- 就前述第一絕緣性樹脂層及前述第二絕緣性樹脂層之 材質而言,並未特別限定,可因應目的加以適宜選擇,例 如,至少含有硬化性樹脂、硬化劑、無機填充劑,更因應 需要,可舉例含有其他成分的絕緣性之材質。 --硬化性樹脂— 就前述硬化性樹脂而言,並未特別限定,可因應目的 加以適宜選擇,例如,可舉例環氧樹脂、苯氧樹脂等。 就前述環氧樹脂而言,例如,可舉例雙酚A型環氧樹 脂、雙盼F型環氧樹脂、紛-紛搭清漆(phenol-novolac)型 環氧樹脂等。 就前述絕緣性樹脂層中前述硬化性樹脂之含量而言, 並未特別限定,可因應目的加以適當選擇,但20質量%〜 40質量%為較佳。 前述含量低於20質量%時,作為接著層之性能有時會 降低,超過40質量%時,有時會對連接信賴性有不良影響。 --硬化劑一 就前述硬化劑而言,並未特別限定,可因應目的加以 201227855 / j如,可舉例°米唾系硬化劑、酸酐系硬化劑、 聚酿胺^硬化劑、_硬化劑、聚硫醇(PGly_aptan) 糸硬 有機過氧化物系硬化劑、陰離子系硬化劑、陽 離子系硬化劑等。此笙, 等T使用早獨1種,亦可併用2種 以上。 就則述咪啥系硬化劑而言,例如, 2-苯基咪唑等。 午』τ丞矿生 丁戚就酐系硬化劑而言,例如’可舉例酞酸酐、順 丁烯二酸酐等。 j⑽系硬化劑而言’例如’可舉例盼祕清漆等。 疣引述有機過氧化物系硬化劑而言,例如 桂酿基過氧化物、丁基過氧化物、节基過氧化物、二月桂 醯基:氧化物、二丁基過氧化物、节基過氧化物、過氧化 一石反酸Sa、苄醯基過氧化物等。 前述陰離子系硬化劑而言,例如,可舉例有機胺類等。 前述陽離子系硬化劑而言,例如,可舉例錄鹽、鏽鹽 (omum salt )、鋁螯合劑等。 就則述絕緣性樹脂層中的前述硬化劑之含量而言,並 未特別限定,可因應目的加以適當選擇,但i質量 質置%為較佳。 —無機填充劑一 就前述無機填充劑而言,並未特別限定,可因應目的 加以適宜轉,例如,可舉㈣氧㈣、氫氧傾、碳酸 鈣、碳酸鎂、矽酸鈣、矽酸鎂、酸化鈣、酸化鎂、氧化鋁 10 201227855 粉末、石夕石、氮化鋁、氮化蝴粉末、鋁硼酸晶鬚(aluminum boric acid whisker)等。此等可使用單獨1種,亦可併用2 種以上。 就前述絕緣性樹脂層中的前述無機填充劑之含量而 言’並未特別限定’可因應目的加以適當選擇,但30質量 %〜70質量。/。為較佳。 前述含量低於30質量%時,尺寸安定性會降低,超過 70質量%時,薄膜狀態的維持會變困難。 --其他成分一 就前述其他成分而言,並未特別限定,可因應目的加 以適宜選擇,例如’可舉例應力缓和劑、軟化劑、促進劑、 老化防止劑、著色劑(顔料、染料)、離子捕集劑(ion catcher ) 等。 …應力緩和劑-一 就前述應力缓和劑而言,例如,可舉例PB (聚丁二烯 橡膠)、丙烯酸系橡膠、丙烯腈(acrylonitrile)橡膠、EVA (乙烯•乙酸乙蛾酯共聚合樹脂)、橡膠變性環氧樹脂等。 此等可使用單獨1種,亦可併用2種以上。 就前述絕緣性樹脂層中的前述應力緩和劑之含量而 言,並未特別限定,巧"因應目的加以適當選擇,但5質量 %〜30質量%為較值。 就前述第一絕緣性樹脂層、及前述第二絕緣性樹脂層 之形成方法而言,迆未特別限定,可因應目的加以適宜選 擇,例如,可舉例將含有前述硬化性樹脂、前述硬化劑、 201227855 前述無機填充劑、及溶劑等的絕緣性樹脂層用組成物加以 塗布而形成的方法。 就前述塗布方法而言,例如,可舉例旋轉塗布法(spin coat )、流延法(casting )、微凹版塗布法(microgravure coat )、凹版塗布法(gravure coat )、刮刀塗布法(knife coat )、棒塗布法(bar coat )、輭i塗布法(roll coat )、線棒 塗布法(wire bar coat )、浸潰塗布法(dip coat )、喷塗法(spray coat)等。 又,可舉例於具有脫模性(mold release)的PET (聚 對苯二甲酸乙二醇醋(polyethylene terephthalate))薄膜等 之脫模薄膜上塗布前述絕緣性樹脂層用組成物而形成絕緣 性樹脂薄膜後,藉由將該絕緣性樹脂薄膜貼附於前述半導 體元件而形成的方法。 就前述第一絕緣性樹脂層之平均厚度而言,並未特別 限定,可因應目的加以適當選擇,但5μιη以上為較佳。前 述平均厚度低於5μιη時’接著力會降低而不佳。 又,就前述第一絕緣性樹脂層之平均厚度而言,較前 述凸塊的平均高㈣倍更大者為較佳,車交3/5倍更大為 更佳》前述平均厚度為倍以下時’因凸塊過度壓擠而 有產生短路(導通不良)的情形。 就前述第二絕緣性樹脂層之平均厚度而言,並未特別 限定,可因應目的加以適當選擇,但以上為較佳。前 述平均厚度低於5μιη時’接著力會降低而不佳。 又,就前述第二絕緣性樹脂層之平均厚度之而言,較 12 201227855 前述凸塊之平均高度的1/2 者 借更j者為較佳,較2/5倍更小 時之凸塊壓擠的情形。 ’,、'、忐控制K者 於前述積層物製作步驟,前述第—絕緣性樹脂會硬
At於本《明’所明「硬化」係指硬化率超過5G%的狀 悲。 又’於前述制物製作步驟,前述第二絕緣性樹脂層 係未硬化’但財發明,所「未魏」係指魏率為㈣ 以下的狀態。 前述硬化率可藉由以下方法而求得。 於對象的絕緣性樹脂層之測量,係藉由示差掃瞒敎量 計進行示差掃瞄熱量測量,來測量發熱量u)。又,為'與 前述測量對象之絕緣性樹脂層相同的組成,且於熱累積 (heat history)低於硬化溫度(未暴露於硬化溫度^的 熱)的絕緣性樹脂層,藉由示差掃瞄熱量計進行示差掃瞄 熱量測量,來測量發熱量(J〇)。而且,可藉由下式:硬: 率(%) =〔(VJ!) /Jo〕X100〕而求得硬化率(%)。 其中,就示差掃瞄熱量測量中的測量條件而言,例如, 可舉例測量試料的質量為l〇mg,升溫速度為1〇〇c/分鐘, 測量溫度為25°C〜200。(:。 就前述第二絕緣性樹脂層之硬化溫度(T2)與前述第 —絕緣性樹脂層之硬化溫度(T!)的差(Τ^Τ〗)而言,並 未特別限定,可因應目的加以適當選擇,但2〇°c以上為較 佳。前述差(L-Td低於2(TC時,第一絕緣性樹脂層未充 13 201227855 分發揮作為支柱的機能,成為壓著時發生短路(導通不良) 的原因。 本文中,前述硬化溫度係指以流變儀(Rheometer )法 測量未硬化之絕緣性樹脂時,顯示最低融熔黏度的溫度。 前述硬化溫度亦可稱為硬化開始溫度。 藉由前述流變儀法的測量可使用例如流變儀(ARES, ΤΑ Instruments 公司),以升溫速度 5°C/min、頻率 lrad/sec 的條件的來進行。 前述積層物製作步驟可為製作於各半導體元件所形成 的半導體晶圓之前述半導體元件具有前述凸塊的面上依序 積層硬化的第一絕緣性樹脂層、及未硬化之第二絕緣性樹 脂層的積層物之步驟。於此情形,前述積層物製作步驟之 後,藉由進行切割步驟,可獲得於經個片化的前述半導體 元件上依序積層硬化的第一絕緣性樹脂層、及未硬化之第 二絕緣性樹脂層的積層物。 <配置步驟> 就前述配置步驟而言,只要於具有電極的基板上,以 前述基板之具有前述電極的面與前述第二絕緣性樹脂層為 對向的方式來配置前述積層物的步驟即可,並未特別限 定,可因應目的加以適當選擇。 _基板_ 就前述基板而言,只要具有電極的基板即可,並未特 別限定,可因應目的加以適宜選擇,例如,可舉例玻璃環 氧基板、硬性基板、撓性電路板等。 14 201227855 <連接步驟> 就前述連接步驟而言,只要將前述半導體元件加熱及 押壓,使前述第二絕緣性樹脂層硬化的同時,將前述凸塊 與前述基板之前述電極作電氣連接的步驟即可,並未特別 限定,可因應目的加以適當選擇。 就前述加熱及押壓的方法而言,並未特別限定,可因 應目的加以適宜選擇,例如,可舉例藉由具備加熱機構的 押壓構件來進行的方法。就具備前述加熱機構的押壓構件 而言,例如,可舉例加熱扣(button )。 就前述押壓構件之先端形狀而言,並未特別限定,可 因應目的加以適宜選擇,例如,可舉例平面狀、曲面狀等。 又,前述先端形狀為曲面狀的情形,可沿著前述曲面狀來 押壓。 就前述加熱之溫度而言,只要前述第二絕緣性樹脂層 會硬化的溫度即可,並未特別限定,可因應目的加以適當 選擇,但100°C〜300°c為較佳。 就前述押壓之壓力而言,並未特別限定,可因應目的 加以適當選擇。 就前述加熱及押壓之時間而言,並未特別限定,可因 應目的加以適宜選擇,例如,可舉例1秒〜300秒。 藉由前述加熱,前述第二絕緣性樹脂層會硬化,而前 述半導體元件與前述基板被接著的同時,藉由前述押壓, 進行前述半導體元件之前述凸塊、與前述基板之前述電極 的接觸並作電氣的連接。前述加熱及押壓之際,前述第一 15 201227855 絕緣性樹脂層已經硬化後,藉由此經硬化的前述第一絕緣 性樹脂層,可防止由於押壓所致的前述凸塊的過度壓擠。 又,經由此方式,可防止由於鄰接的前述凸塊間之接觸所 致的導通不良。 其中,使用圖式說明前述半導體元件之封裝方法之一 例。 由第2A圖至第2E圖,顯示前述半導體元件之封裝方 法,其中作為前述積層物製作步驟,係使用於前述半導體 元件之具有前述凸塊的面上,形成未硬化之第一絕緣性樹 脂層後,於此未硬化的第一絕緣性樹脂層上,積層未硬化 之第二絕緣性樹脂層,使前述未硬化之第一絕緣性樹脂層 硬化的步驟。 第2A圖係凸塊2所形成的半導體元件1之概略剖面 圖。首先,於前述半導體元件1之具有前述凸塊2的面上, 依序積層未硬化之第一絕緣性樹脂層3a、及未硬化之第二 絕緣性樹脂層4a (第2B圖)。接著,於前述未硬化之第一 絕緣性樹脂層3a會硬化且前述未硬化之第二絕緣性樹脂層 4a並未硬化的加熱溫度下將其加熱,使前述未硬化之第一 絕緣性樹脂層3a硬化,於硬化的第一絕緣性樹脂層3b,獲 得積層物(第2C圖)。接著,於具有電極6的基板5上, 使前述基板5之具有前述電極6的面與前述未硬化之第二 絕緣性樹脂層4a成為對向的方式配置前述積層物(第2D 圖)。又,於此配置之際,前述未硬化之第二絕緣性樹脂層 4a與前述基板5亦可接續。接著,藉由具備加熱裝置的押 16 201227855 壓構件7,將前述半導體元件1加熱及押壓,使前述未硬化 之第二絕緣性樹脂層4a硬化,作成經硬化的第二絕緣性樹 脂層4b,同時將前述凸塊2與前述電極6作電氣連接(第 2L·圖)。經由以上步驟獲得接合體。 又,於第3A圖至第3F圖呈示前述半導體元件之封裝 方法,係使用作為前述積層物製作步驟,於前述半導體元 件之具有前述凸塊的面上,形成未硬化的第一絕緣性樹脂 層後,使前述未硬化之第一絕緣性樹脂層硬化,於此硬化 的第一絕緣性樹脂層上,積層未硬化之第二絕緣性樹脂層 的步驟的前述半導體元件之封裝方法。 第3A圖係形成凸塊2的半導體元件1之概略剖面圖。 首先,於前述半導體元件1之具有前述凸塊2的面上,形 成未硬化之第一絕緣性樹脂層3a (第3B圖)。接著,將其 加熱,使前述未硬化之第一絕緣性樹脂層硬化,作成硬化 的第一絕緣性樹脂層3b,而獲得積層物(第3C圖)。接著, 於前述硬化的第一絕緣性樹脂層3b上,形成未硬化之第二 絕緣性樹脂層4a,獲得積層物(第3D圖)。接著,於具有 電極6的基板5上,於前述基板5之具有前述電極6的面 配置前述積層物使與前述未硬化之第二絕緣性樹脂層4a成 為對向(第3E圖)。又,於此配置之際,前述未硬化之第 二絕緣性樹脂層4a與前述基板5接續為宜。其次,前述半 導體元件1藉由具備加熱裝置的押壓構件7加以加熱及押 壓,使前述未硬化之第二絕緣性樹脂層4a硬化,作成硬化 的第二絕緣性樹脂層4b的同時,將前述凸塊2與前述基板 17 201227855 5之如述電極6竹雷名、由/ 作冤軋連接(第3F圖)。經由上述獲得接 合體。 [實施例] 1" 、, °先明本發明之實施例,但本發明並未限定於此 等實施例。又,「彳八.. 知」係表示質量份。 (製造例1 ) <、、邑緣性樹脂薄膜之製作> 調製含有下矣]μ _ 务、〇π 衣1所不摻合量的絕緣性樹脂用組成物, 藉由塗布◎將該絕緣性樹脂用組成物塗布於脫模薄膜上, & 70 烘箱除去有機溶媒,製作具有指定厚度 的絕緣性樹脂薄膜。 [表1]
表1中各摻合之數値之單位為「質量份」 表1中,雙盼八型環氧樹脂為JR-828 (三菱化學公司 ^ )陽離子系硬化劑為San_AidSi•狐(三新化♦公司製, 芳香無疏鹽)。陰離子系硬化劑為咖継PN-23 (味之素 ne Techno λ 司製)。盼系硬化劑為 τ〇2ΐ3ι (IC A 司製)丙烯酸橡膠為 S(}_p_3 (Nagase ChemteX 公司製)。石夕石為(龍森公司製)。 201227855 表1中之「硬化溫度」為獲得的絕緣性樹脂薄膜之硬 化溫度。此硬化溫度係表示以流變儀法測量之際之最低融 熔黏度的溫度。以前述流變儀法之測量係使用流變儀 (ARES,TA Instruments 公司),於升溫速度 5t:/min、頻 率lrad/sec、25°C〜250°C之條件下進行。 (實施例1) <半導體元件之封裝> -半導體元件之準備- 準備 貝用 1C 晶片(Sony Chemical & Information 股 伤有限公司製’大小0.3mm><6.3mm、厚度0.2mm、錫焊凸 塊(Solder bump)、凸塊平均高度35陣、凸塊平均間距 85μιη) ° -積層物製作步驟- 於前述評價用1C晶片之具有凸塊的面上,貼附摻合1 之絕緣性樹脂薄膜(厚度25μπι),形成未硬化之第一絕緣 性樹脂層。接著,於前述未硬化之第一絕緣性樹脂層上, 貼附摻合4之絕緣性樹脂薄膜(厚度1〇μιη),形成未硬化 之第二絕緣性樹脂層。之後,於100°C經加熱30分鐘,使 前述第一絕緣性樹脂層硬化,獲得積層物。前述加熱後之 前述第一絕緣性樹脂層之硬化率為100% (硬化狀態),前 述第二絕緣性樹脂層之硬化率為40% (未硬化狀態)。 _配置步驟- 接者,於具有電極的基板(玻璃彡哀氧基板)上,配置 前述積層物使前述基板之具有前述電極的面與前述未硬化 19 201227855 之第二絕緣性樹脂層成為對向。 -連接步驟- 接著,前述評價用1C晶片藉由覆晶扣(flip chip buttom) ( FCB3,Panasonic Factory Solutions 公司製,具備 加熱裝置的押壓構件),以30秒、250°C加熱及以50N/IC 押壓,使前述未硬化之第二絕緣性樹脂層硬化,作成經硬 化的第二絕緣性樹脂層的同時,使前述凸塊與前述電極作 電氣連接。 <測量> -硬化率- 硬化率係由以下方法求得。 於測量對象之絕緣性樹脂層,藉由示差掃瞄熱量計 (DSC 9100,TA Instruments公司製)進行示差掃瞄熱量測 量,測量發熱量(J!)。又,與前述測量對象之絕緣性樹脂 層相同的組成,於且熱累積低於硬化溫度(未成為硬化溫 度以上的熱)絕緣性樹脂層,藉由示差掃瞄熱量計進行示 差掃瞄熱量測量’測量發熱量(JG )。而且,藉由下式:硬 化率(%) =〔(Jo-Ji) /J〇〕xlOO〕求得硬化率(%)。 其中,示差掃瞄熱量測量中的測量條件係測量試料之 質量為10mg,升溫速度為10°C/分鐘,測量溫度為25°C〜 200〇C。 <評價> -凸塊評價- 藉由SEM ( S-3000>vi,日立製作所公司製)測量凸塊 20 201227855 以下述評價基準加 的壓擠率,再測量鄰接的凸塊的導通 以评價。結果示於表2-1。 〇 :凸塊壓擠率為50%以下,且導通〇κ △:凸塊壓擠率超過50%,但導通為οκ x :凸塊壓擠率超過50%,或導通不_ 其中,凸塊壓擠率係指以下式求得之値. =擠率W =〔〔(封裝前之凸塊平均高度)_(封 Ί 塊平均面度)〕/ (封裳前之凸塊平均高度)〕 χΙΟΟ 其中,導通OK係指鄰接的凸塊彼此未接觸,且無導 通。導通不良係指鄰接的凸塊彼此有接觸,有導通。其中, 以4端子法測量之際,為㈣以上且〇 2Ω以下判斷導通 為良好’低於ο.1Ω時會發生短路(sh〇rt),㈣〇 2Ω時未 充分連接。 -接著性- 基於下述基準,藉由目視評價壓著時之接合體。評價 結果示於表2-1。 0:壓著時可與基板接合 Χ:壓著時無法與基板接合 -連接信賴性_ 藉由數位萬用表(digital multimeter) ( Fluke公司製, F1uke-ll5)測量電阻値,依據下述評價基準加以評價。結 果示於表2-1。 :0.1Ω〜0.2Ω :低於0.1Ω、或大於0.2Ω 21 201227855 (實施例2〜13、比較例1〜23 ) 將於實施例1之第一絕緣性樹脂層、及第二絕緣性樹 脂層之摻合、及厚度、以及積層物製作步驟中的加熱溫度 替換為表2-1〜表2-3所示者之外,與實施例1同樣地進行 半導體元件之封裝,進行測量、及評價。結果示於表2-1 〜表2-3。 (實施例14) <半導體元件之封裝> -半導體元件之準備_ 準備评價用 1C 晶片(Sony Chemical & Information 股 知有限公司製’大小6.3mm><6.3mm、厚度0.2mm、錫焊凸 塊、凸塊平均高度35μιη、凸塊平均間距85μιη)。 -積層物製作步驟― 於前述評價用1C晶片之具有凸塊的面上,貼附摻合2 之絕緣性樹脂薄膜(厚度25μιη),形成未硬化之第一絕緣 性樹脂層。接著,經由將此等於150°C加熱30分鐘,使前 述第一絕緣性樹脂層硬化。接著,於前述硬化的第一絕緣 性樹脂層上’貼附摻合3之絕緣性樹脂薄膜(厚度ΙΟμιη), 獲得形成未硬化之第二絕緣性樹脂層的積層物。獲得的積 層物中的前述第一絕緣性樹脂層之硬化率為1〇〇%(硬化狀 態)°前述第二絕緣性樹脂層之硬化率為〇% (未硬化狀 態)。 \ -配置步驟- 其次’於具有電極的基板(玻璃環氧基板)上,配置 22 201227855 前述積層物使前述基板之具有前述電極的面與前述未硬化 之第二絕緣性樹脂層成為對向。 -連接步驟- 其次,將前述評價用1C晶片經由覆晶扣(FCB3, Panasonic Factory Solutions 公司製)於 250°C加熱、及以 50N/IC押壓30秒,使前述未硬化之第二絕緣性樹脂層硬 化,作成硬化的第二絕緣性樹脂層的同時,使前述凸塊與 前述電極作電氣連接。 與實施例1同樣地進行測量、及評價。結果示於表2-4。 (實施例15、及16) 除了將實施例14之第一絕緣性樹脂層、及第二絕緣性 樹脂層之摻合替換為表2-4所示者之外,與實施例14同樣 地進行半導體元件之封裝,進行測量、及評價。結果示於 表 2-4。 [表 2-1] i f施例 1 2 3 4 5 6 7 8 9 10 11 12 13 第一 絶緣性樹脂層 摻合例 1 1 1 1 2 2 2 2 3 3 3 4 4 硬化溫度 (°C ) 70 70 70 70 80 80 80 80 90 90 90 100 100 厚度 (μιη) 25 25 25 25 25 25 25 25 25 25 25 25 25 第二 絶緣性樹脂層 摻合例 4 5 6 3 3 4 5 6 4 5 6 5 6 硬化溫度 (°C) 100 110 120 90 90 100 110 120 100 110 120 110 120 厚度 (μπι) 10 10 10 10 10 10 10 10 10 10 10 10 10 積層物製作步驟中的加熱溫度 (°c) 100 100 100 100 100 100 100 100 110 110 110 120 120 積層物製作步驟 後之硬化率 (%) 第一絶緣性樹脂層 100 100 100 100 75 75 75 75 75 75 75 75 75 第二絶緣性樹脂層 40 30 20 50 50 40 30 20 50 40 30 50 40 接續步驟中的加熱溫度 (°c) 250 250 250 250 250 250 250 250 250 250 250 250 250 凸塊評價 〇 〇 〇 Δ Δ 〇 〇 〇 Δ 〇 〇 Δ 〇 接著性 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 接續信賴性 85°C85%RH、500hr後 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 23 201227855 [表 2_2]
比較例 1 2 3 4 5 6 7 8 9 10 11 12 第一 梦合例 1 1 2 2 3 3 3 4 4 4 4 5 絶緣性樹脂層 硬化溫度 ΓΟ 70 70 80 80 90 90 90 100 100 100 100 110 厚度 (μπι) 25 25 25 25 25 25 25 25 25 25 25 25 第二 步合例 1 2 1 2 1 2 3 1 2 3 4 1 絶緣性樹脂層 硬化溫度 (°C) 70 80 70 80 70 80 90 70 80 90 100 70 積層 5:度 (μπι) 10 10 10 10 10 10 10 10 10 10 10 10 的加熱溫度 (°C) 100 100 100 100 1⑻ 100 110 100 1⑻ 100 120 100 積層物製作步驟 後之硬仆座 第一絶緣性樹脂層 100 100 75 75 50 50 75 20 20 50 75 30 (%) 第二絶緣性樹脂層 100 75 100 75 100 75 75 100 75 75 75 100 少驟 度(。〇 250 250 250 250 250 250 250 250 250 250 250 250 口观旰頂 X X X X X X X X X X X X 接者性 X X X X X X X X X X X X 接躓信賴性 85〇C85%RH 、500hr後 X X X X X X X X X X X X
[表 2-31
比較例 13 14 15 16 17 18 19 20 21 22 23 第一 絶緣性樹脂層 摻合例 5 5 5 5 5 6 6 6 6 6 6 硬化温度 (°C) 110 110 110 110 110 120 120 120 120 120 120 厚度 (μΓΠ) 25 25 25 25 25 25 25 25 25 25 25 第二 絶緣性樹脂層 摻合例 2 3 4 5 6 1 2 3 4 5 6 硬化温度 (°c) 80 90 100 110 120 70 80 90 100 110 120 厚度 (μπι) 10 10 10 10 10 10 10 10 10 10 10 積層物製作步級Φ 的加熱溫度 (°C) 100 110 120 130 130 100 100 110 120 130 130 積層物作製步驟 後之硬化率 (%) 第一絶緣性樹脂層 30 40 50 50 50 20 20 30 40 40 40 第二絶緣性樹脂層 75 75 75 50 40 100 75 75 75 50 40 接績步驟中的加熱溫度) 250 250 250 250 250 250 250 250 250 250 250 凸塊評價 X X X X X X X X X X X 接著性 X X X X X X X X X X X 接續信賴性 85°C85%RH、500hr後 X X X X X X X X X X X 24 201227855 [表 2-4] 實施例 14 15 16 第一 絶緣性樹脂層 摻合例 2 3 4 硬化溫度 (°C) 80 90 100 厚度 (μΠ〇 25 25 25 積層物製作步驟中的加熱溫度 (°c) 150 150 150 第二 絶緣性樹脂層 摻合例 3 4 5 硬化溫度 (°c) 90 100 110 厚度 (μιη) 10 10 10 積層物製作步驟 後之硬化率 (%) 第一絶緣性樹脂層 100 100 100 第二絶緣性樹脂層 0 0 0 接續步驟中的加熱溫度 (°c) 250 250 250 凸塊評價 〇 〇 〇 接著性 〇 〇 〇 接續信賴性 85°C85%RH、500hr後 〇 〇 〇 於實施例1〜13、及比較例1〜23之凸塊評價之結果, 與硬化溫度之關係整理於表3。 [表3]
第一絶緣性樹脂層之硬化溫度 70°C 80°C 90°C loot 110°C 120°c 第 絶 緣 性 樹 脂 層 之 硬 化 温 度 70°C X X X X X X 80°C X X X X X X 90°C Δ Δ X X X X loot: 〇 〇 Δ X X X 110°C 〇 〇 〇 Δ X X 120°C 〇 〇 〇 〇 X X 由表2-1〜表2-3及表3之結果,實施例1〜13之藉由 本發明之半導體元件之製造方法所獲得的封裝體,因連接 時第一絕緣性樹脂層會硬化,可防止由於凸塊壓擠所致的 25 201227855 =通不=短路)。又,接著性、連接信賴性亦為良好。尤 於—絕緣性樹脂層之硬化溫度 樹脂層之硬化溫度(Τι)之# 丁、第、、'邑緣性 η /n( 1、及13 ’凸塊壓擠率為5〇%以 且亦無導通不良(短路),係㈣地良好。 又由表2-4之結果,實施例14〜16之藉由本發明之 半導體元狀製造方法所獲得的㈣體,因將第―絕緣性 樹脂層硬化後積層第二絕緣性樹脂層,即使接近硬化严 度’凸塊壓擠率為50%以下,且亦無導通不良(短路),係 非常地良好。 另一方面,藉由比較例1〜23之半導體元件之製造方 法所獲得的封裝體,於凸塊評價、接著性、及連接信賴性 任-者皆«由本發日狀半導體元件之製造方法所獲得的 封裝體為差。 [產業上之可利用性] 本發明之半導體元件之封裝方法可防止由於凸塊過度 壓擠所致的導通不良〔短路(sh〇rt)〕,同時因接著性良好, 了適合使用於凸塊之間距為狹間距的半導體元件的封裝。 【圖面簡單説明】 第1圖係呈示半導體元件之一例的概略剖面圖。 第2A圖係呈示本發明的半導體元件之封裝方法之一 例的概略剖面圖。 第2B圖係呈示本發明的半導體元件之封裝方法之一 26 201227855 例的概略剖面圖。 第2C圖係呈示本發明的半導體元件之封裝方法之一 例的概略剖面圖。 第2D圖係呈示本發明的半導體元件之封裝方法之一 例的概略剖面圖。 第2E圖係呈示本發明的半導體元件之封裝方法之一 -例的概略剖面圖。 第3A圖係呈示本發明的半導體元件之封裝方法之其 他例的概略剖面圖。 第3B圖係呈示本發明的半導體元件之封裝方法之其 他例的概略剖面圖。 第3C圖係呈示本發明的半導體元件之封裝方法之其 他例的概略剖面圖。 第3D圖係呈示本發明的半導體元件之封裝方法之其 他例的概略剖面圖。 .第3E圖係呈示本發明的半導體元件之封裝方法之其 他例的概略剖面圖。 第3F圖係呈示本發明的半導體元件之封裝方法之其 他例的概略剖面圖。 【元件符號説明】 1 半導體元件 2 凸塊 3a 未硬化之第一絕緣性樹脂層 27 201227855 3b 硬化的第一絕緣性樹脂層 4a 未硬化之第二絕緣性樹脂層 4b 硬化的第二絕緣性樹脂層 5 基板 6 電極 7 押壓構件 H 高度 L 間距 28
Claims (1)
- 201227855 七、申請專利範圍: 1. 一種半導體元件之封裝方法,其係包含下列步驟: 積層物製作步驟,其係於形成凸塊的半導體元件之具有前 述凸塊的面上,依序製作積層硬化的第一絕緣性樹脂層、 未硬化之第二絕緣性樹脂層的積層物; 配置步驟,其係於具有電極的基板上,配置前述積層物使 前述基板之具有前述電極的面與前述第二絕緣性樹脂層 成為對向; 連接步驟,其係加熱及押壓前述半導體元件,使前述第二 絕緣性樹脂層硬化的同時,將前述凸塊與前述基板之前述 電極作電氣連接。 2. 如申請專利範圍第1項記載之半導體元件之封裝方法,其 中第二絕緣性樹脂層之硬化溫度(T2)與第一絕緣性樹脂 層之硬化溫度(Τ〗)的差(T2-T丨)為2(TC以上。 3. 如申請專利範圍第1項記載之半導艟元件之封裝方法,其 中於積層物製作步驟中,未硬化之第二絕緣性樹脂層係被 積層於硬化的第一絕緣性樹脂層上。 4. 如申請專利範圍第1項記載之半導體元件之封裝方法,其 中凸塊為鮮錫球(soldering ball)。 _ 5. —種封裝體,其係為該封裝體係藉由半導體元件之封裝方 法所獲得,其中該半導體元件之封裝方法包含: 積層物製作步驟,其係於形成凸塊的半導體元件之具有前 述凸塊的面上,依序製作積層硬化的第一絕緣性樹脂層、 未硬化之第二絕緣性樹脂層的積層物; 29 201227855 配置步驟,其係於具有電極的基板上,配置前述積層物使 前述基板之具有前述電極的面與前述第二絕緣性樹脂層 成為對向, 連接步驟,其係加熱及押壓前述半導體元件,使前述第二 絕緣性樹脂層硬化的同時,將前述凸塊與前述基板之前述 電極作電氣連接。 30
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US6924171B2 (en) * | 2001-02-13 | 2005-08-02 | International Business Machines Corporation | Bilayer wafer-level underfill |
JP2002299378A (ja) * | 2001-03-30 | 2002-10-11 | Lintec Corp | 導電体付接着シート、半導体装置製造方法および半導体装置 |
WO2009001264A1 (en) * | 2007-06-27 | 2008-12-31 | Koninklijke Philips Electronics N.V. | Light output device |
JP5004351B2 (ja) * | 2007-11-30 | 2012-08-22 | 信越化学工業株式会社 | 半導体装置の製造方法 |
US7951648B2 (en) * | 2008-07-01 | 2011-05-31 | International Business Machines Corporation | Chip-level underfill method of manufacture |
-
2010
- 2010-12-07 JP JP2010272226A patent/JP2012124244A/ja active Pending
-
2011
- 2011-11-08 WO PCT/JP2011/075677 patent/WO2012077447A1/ja active Application Filing
- 2011-11-25 TW TW100143300A patent/TW201227855A/zh unknown
Also Published As
Publication number | Publication date |
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JP2012124244A (ja) | 2012-06-28 |
WO2012077447A1 (ja) | 2012-06-14 |
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