201218886 六、發明說明： 【發明所屬之技術領域】 尤其涉及一種電路板製作 [0001]本發明涉及電路板製造技術 方法。 [先前技術] 剛衫訊、通訊及消費性電子產業中，電路板為所有電子 產亡不可或缺之基本構成要件。隨著電子產品往小型化 Γ7速化方向發|冑路板亦從單面電路板往雙面電路 板、多層電路板方向發展。多層電频由於具有較多佈 線面積與較高裝配密度而得到廣泛_，請參^aka— hash1，A.等人於1992年發表於_ Trans. on201218886 VI. Description of the Invention: [Technical Field of the Invention] In particular, the present invention relates to a method of manufacturing a circuit board. [Prior Art] In the shirt, communications and consumer electronics industries, circuit boards are an essential component of all electronic survival. With the miniaturization of electronic products, the direction of the 7-speed circuit is also moving from a single-sided circuit board to a double-sided circuit board and a multilayer circuit board. Multilayer RF is widely used due to its large wiring area and high assembly density. Please refer to ^aka-hash1, A. et al., published in 1992 on _ Trans. on
Components, Packacri j , ^ging, and ManufacturingComponents, Packacri j , ^ging, and Manufacturing
Technology 之文獻 «„ ·,, 又馱 Hlgh density ffiultilayer printed circuit hr, a 4： „ oard for UITAC M〜880”。並且 ，電路板不僅要為電；；吳此也μ & €子兀15件提供電氣連接以及必要之 機械支撐’還要具有更多之功能:。 [0003] 厚銅線路板之線路厚度較大，因而具有能夠提供大電流 、將電源集成、散熱性良好、控制特性阻抗等特性 製作厚銅線路板之線路時，—般亦採用先前技術中之圖 像轉移技術一次餘刻成形。亦即’在銅箱表面形成圖荦 化之先阻層，然後通過鋪刻液敍刻去除暴露出之銅荡 ，最後未祕刻之銅箱即構成線路。在先前技術製作厚 銅線路板之方法中，存在以下兩個問題。第―，銅蚀刻 液之㈣為各向同性，因而在銅_液自銅《面向下 餘刻之壯中’還會私側面之鋼㈣，即㈣光阻下方 099136852 表單編號A0101 第 頁/共33頁 0992064362-0 201218886 之銅箔。在銅箔厚度較小之線路板中，由於蝕刻之時間 較短，因此側面侵蚀之情況益不會對線路造成影響。然 而，在厚銅線路板中，由於銅箔之厚度較大’需要扠長 之姓刻時間，從而會加重侧面侵#之情況，造成線路上 方之寬度變小，嚴重地甚至可能蝕穿線路上部，從而造 成光阻脫離於鋼羯層，如此則會造成整個銅箔均被蝕刻 而不能構成線路。第二，由於蝕刻之過程中’在蝕刻銅 箔而在銅箔中形成凹陷之後，反應後之銅蝕刻液會易於 聚集於這些凹陷之中，從而阻止未反應之銅蝕刻液進入 凹陷之中’繼續向下钕刻凹陷下之銅。亦即，“水池效 應”會嚴重影響厚銅線路板中線路之製作，使得越下方 之銅被姓刻地越少。即，使得線路之形狀變成梯形，使 得相鄰兩條線路越遠離光阻層之線距越小，甚至可能造 成相鄰兩條線路相連接。以上兩個問題趣彩響了厚鋼線 路板之製作良率》 闺有紐此’有必要提供—種可具有較高製作良率之電路 板製作方法。 【發明内容】 [0005] [0006] 099136852 从》'肘U貫施例說明一種電路板製作方法。 一種電路板製作方法，包括步驟：提供電路基板，所述 電路基板具有銅箔層，所述铜 ΜΨ , ^ + /白層之厚度大於或等於100 銅歸具有第-綠路區、靠近第—線路區之 區以及位於第一線路區與第二線路區之間之姓 刻s，U及通過兩次以上之蝕 — d工序去除敍刻區之銅箔 層。母二人蝕刻之前，在銅箔層 表面形成圖案化之光阻層 第5頁/共33頁 表單編號A0101 0992064362-0 201218886 ’以遮蔽第一線路區之銅箔層與第二線路區之銅箱層， 並暴露出蝕刻區之銅箔層；每次蝕刻蝕刻區之銅$層時 ’蝕刻深度在50微米至75微米之間；每次餘刻之後^去 除圖案化之光阻層’從而在去除蝕刻區之銅箱層後 得第一線路區構成第一線路，使得第二線路區構成第二 線路。 [0007] [0008] 本技術方案之電路板製作方法中，採用兩次以上之蝕刻 工序製作線路，相較於採用一次蝕刻工序製作線路之方 法而言，可以降低銅蝕刻液各向同性之蝕刻與水池效靡 對線路形狀之影響，可以保證線路之形狀及尺寸，·: 電路板之線路製作具有較高之良率。本技術方案之電= 板製作方法可以獲得線寬較為一致之線路，戍者戈了、 獲得形狀更接近長方形之線路。具體而言，在線路厚产 在100微米以上時，通過兩次以上之蝕刻工序可以掣作出 線路各處之線寬差值在5 0微米以下之線路。並且、 姓刻工序非常成熟，成林較低，因此，g卩使採用兩次 以上之侧工序製作線路’峡不會影響電路板製作之 成本與效率。 【實施方式】 下面將結合附圖及實施例，對本技術方 茶钕供之電路板 製作方法作進一步之詳細說明。 [0009] 本技術方案實施方式提供之電路板製作方法， 包括步驟 [0010] 099136852 第一步，請參閱圖1 ’提供電路基板1〇。 所迷電路基板10 包括基底層11及貼合於基底層丨丨表面 表單編號A_1 » —白增12。所述 第6頁/共33頁 0992064362-0 201218886 ❹ 基底層11可以為僅包括絕緣層，還可以為包括至少一層 絕緣層與至少一層導電層之結構。亦即，電路基板1〇可 為單面覆鋼基材，亦可為雙面覆銅基材，還可為多層電 路基材。所述多層電路基材係指已形成内層線路，尚未 製作外層線路之基板。在本實施例中，所述電路基板10 為單面覆鋼基材，即基底層11為絕緣層。所述絕緣層之 材料為硬性材料，如環氧樹脂、玻纖布等’但亦可為柔 &材料’例如聚醯亞胺（Polyimide，ΡΙ)、聚乙烯對 本一甲酸乙二醇醋（p〇iyethylene Terephthalate， ET)、聚萘二曱酸乙二醇龜(p〇iyethyiene naphtha late ’ pen) 等 。所述銅箱層 般為電 鍍銅箔 、壓 延銅、名或者為包括壓延銅揭與電解銅络之複合結構。銅 泊層12之厚度大於或等於1〇〇微米，一般來說可以在 140微米至25〇微米之間。 [0011] 〇 所述銅落層12用於形成導電線路，因此，銅簿㈣包括 複數用於形成祕之線㈣減麟去狀軸區。在 本實施例中，以_層12包括兩個線路區與三個餘刻區 為例進行制。脚，在本實施财，⑽層η包括第 一線路區121、第二線路F 9 ^ 緣峪& 122、第一蝕刻區123、第二 姓刻£ 12 4及第三钱刻p· 1 9 q ήί·、+、哲 习£125。所述第一線路區121位於 第一钮刻區123與第二蚀刻區124之間，所述第—_區 123位於第一線路區121與第二線路區122之間，所述第 二線路區122位於第_餘刻區123與第三蚀刻區出之間 0 [0012] 第一/通過兩_人以上之钱刻工序去除第一餘刻區123、 099136852 表單編號Α0101 第7頁/共33頁 0992064362-0 201218886 第二蝕刻區124及第三蝕刻區125之銅箔層12，每次蝕刻 之蝕刻深度為50微米至75微米。 [0013] 在本實施例中，銅箔層12之厚度為210微米，通過三次蝕 刻工序去除第一蝕刻區123、第二蝕刻區124及第三蝕刻 區125之銅箔層12。以下對第一次蝕刻工序、第二次蝕刻 工序及第三次蝕刻工序進行具體說明。 [0014] 請參閱圖2至圖5，第一次蝕刻工序可以包括以下步驟： [0015] 首先，請參閱圖2，在銅箔層12表面形成第一光阻層21。 所述第一光阻層21可通過在銅箔層12表面塗覆液態光阻 油墨之方法形成。 [0016] 其次，通過曝光、顯影工藝去除部分第一光阻層21，以 形成圖案化之第一光阻層21，如圖3所示。圖案化之第一 光阻層21遮蔽第一線路區121之銅箔層12與第二線路區 122之銅箔層12，並暴露出第一蝕刻區123、第二蝕刻區 124及第三蝕刻區125之銅箔層12。 [0017] 再次，通過銅蝕刻液第一次蝕刻暴露出之第一蝕刻區123 、第二蝕刻區124及第三蝕刻區125之銅箔層12，直至第 一蝕刻區123、第二蝕刻區124及第三蝕刻區125之銅箔 層12被蝕刻掉50微米至75微米。所述銅蝕刻液可以為氯 化銅系蝕刻液、氣化鐵系蝕刻液、硫酸/過氧化氫系蝕刻 液。 [0018] 在第一次蝕刻之過程中，銅蝕刻液基本上會自銅箔層1 2 之表面向下蝕刻，銅箔層12被蝕刻掉之厚度即為蝕刻深 度。在本實施例中，第一次蝕刻之蝕刻深度為70微米。 099136852 表單編號A0101 第8頁/共33頁 0992064362-0 201218886 由於蝕刻之各向同性，因此’在第一線路區121與第二線 路區122中，靠近第一#刻區123、第二蚀刻區124及第 三蚀刻區1 2 5之銅箔層12可能有少部分亦被姓刻掉。蚀刻 之後’在第一線路區121形成第一凸起131，在第二線路 區122形成第二凸起132 ’在第一餘刻區123形成第一開 口 141 ’在第二姓刻區124形成第二開口 142，在第三敍 刻區125形成第三開口 143 ’如圖4所示。由於水池效應， 第一凸起131之橫截面與第二凸起132之橫截面均基本近 Ο [0019] [0020] [0021] ❹ [0022] 似於梯形，而第二開口 142之橫截面基本為倒梯形。 .. 最後’請參閱圖5 ’第一次蝕刻後，去除圖案化之第一光 阻層21。第一光阻層21可以採用強鹼液溶解之方法去除 第一次蝕刻工序之後可進行第二次蝕刻工序，第二次蝕 刻工序可採用近似於第一次蝕刻工序之步驟如圖6至圖 Θ所示： 首先，請參閱圖6，在銅箔層12表面形成第二光阻層22。 即，第二光阻層22分佈在第一開口 141之底面、第一凸起 131之表面、第二凸起〗32之表面、第二開口 142之底面 以及第三開口 143之底面。第二光阻層22亦可為液態光阻 油墨。 其次，通過曝光、顯影工藝去除部分第二光阻層22，以 形成圖案化之第二光阻層22，如圖7所示。圖案化之第二 光阻層22遮蔽第-線路區121之射|層12之表面與第二線 路區122之銅騎12之表面，並暴露出第-⑽區123、 099136852 表單編號A0101 第9頁/共33頁 0992064362-0 201218886 第二蝕刻區124及第三蝕刻區 ^ ^ 125之銅箔層12。亦郎，岡 案化之第二光阻層22遮蔽第—n 圖 凸起1 31之表面與第_凸起 132之表面，並暴露出第I” 第-凸起 142之底面以及第三開口 i43 〈底面。 [0023] 、叫刈暴露出之第一蝕刻 、第二蝕刻區124及第三蝕刻F19c; 區125之銅箔層12， —蝕刻區123、第二蝕刻區12 且芏乐 二次 第二餘刻區1 2 5之銅箔 層12被蝕刻掉50微米至75微半。+ v、°在本實施例中，第 蝕刻之蝕刻深度亦為70微米。 [0024] [0025] [0026] 在第二次#刻後，在第-線路區121形成連接於第_凸起 m下方之第三凸起133,在第二線路區122形成連接於 第二凸起132下方之第四凸起134 ’在第一餘刻區123形 成連通於第一開口 141下方之第四開口 144，在第二蝕刻 區124形成連通於第二開口 142下方之第五開口145，在 第三蝕刻區125形成連通於第三開口 143下方之第六開口 ，如圖8所示。第三凸起133之橫載面近似於梯形，第 四凸起134之橫截面亦近似於梯形。 另外’由於蝕刻之各向同性，因此，在第一線路區121與 第二線路區122中，靠近第一餘刻區123、第二钱刻區 124及第三蝕刻區125之銅箔層12可能有少部分亦被蝕刻 掉’從而第一凸起131與第三凸起133之連接處可能存在 —突刺，在第二凸起132與第四凸起134之連接處可能亦 存在一突刺。 最後，請參閱圖9，去除圖案化之第二光阻層22。 099136852 表單蝙號A0101 第10頁/共33頁 0992064362-0 201218886 [0027] [0028] Ο [0029] Ο [0030] [0031] 第二次蝕刻工序之後可進行第三次蝕刻工序，第三次蝕 刻工序可採用近似於第一次蝕刻工序之步驟，如圖10至 圖13所示： 首先，請參閱圖10，在銅箔層12表面形成第三光阻層23 即’第三光阻層23分佈在第四開口 144之底面、第一凸 起Ϊ31與第三凸起133之表面、第二凸起132與第四凸起 以4之表面、第五開口 ι45之底面以及第六開口 ι46之底 面。第三光阻層23亦可為液態光阻油墨。 其次，通過曝光、顯影工序去除部分第三光阻層23，以 形成圖案化之第三光阻層23，如圖u所示。圖案化之第 三光阻層23遮蔽第一線路區121之銅箔層丨2之表面與第二 線路區122之鋼箔層12之表面，並暴露出第一蝕刻區123 、第二蝕刻區124及第三蝕刻區125之鋼箔層12。亦即， 圖案化之第三光阻層23遮蔽第一凸起131之表面、第二凸 起132之表面、第三凸起133之表面及第四凸起134之表 面’並暴露出第四開口 14 4之底面、第五開口 14 5之底面 以及第六開口 146之底面。 再次，通過銅敍刻液第三次蝕刻暴露出之第一触刻區123 、第二钮刻區124及第三飯刻區125之銅箔層12，直至第 一餘刻區123、第二蝕刻區丨24及第三蝕刻區125之銅箔 層12被完全蝕刻去除，從而暴露出第一蝕刻區123、第二 蝕刻區124及第三蝕刻區125相對應之基底層丨丨。在本實 施例中，第三次蝕刻之蝕刻深度亦為7〇微米。 在第二次餘刻後’在第—線路區121形成連接於第三凸起 099136852 表單編號Α0101 第11頁/共33頁 0992064362-0 201218886 133下方之第五凸起135 ’在第二線路區i22形成連接於 第四凸起m下方之第六&起136,在第一蚀刻區123形 成連通於第四P和144下方之第七開口147，在第二_ 區124形成連通於第五開口 145下方之第八開口 148，在 第二蚀刻區125形成連通於第六開口丨46下方之第九開口 149，如圖12所示。第五凸起135之橫截面近似於梯形， 第六凸起136之橫截面亦近似於梯形。第-凸起131、第 =凸起133及第五凸起135依次連接，構成第一線路15。 弟一凸起132、第四凸起134及第六凸起136依次連接， 構成第二線路16。第—線路15與第二線路i 6被第一開口 141第四開口 144及第七開口 147連通構成之間隔空間 17分隔開。 [0032] [0033] [0034] 另外，由於蝕刻之各向同性，因此在第一線路區121與第 二線路區122中，靠近第—⑽區123、第二㈣區124 及第三細1m 12 5之㈣層12可能有少部分亦減刻掉， 從而第五凸起135與第三凸起133之連接處可能存在—突 刺，在第六凸起136與第四凸考134之連接處可能亦存在 一突刺。 最後，請參閱圖13，去除圖案化之第三光阻層23。如此 ，即可獲得具有基底層11及形成在基底層11表面之第一 線路15與第二線路16之電路板1〇〇。 第一線路15具有與基底層11接觸之第一底面κι、與第一 底面151相對之第一頂面152以及兩個連接在第一底面 151與第—頂面152之間之第一側面153。第一底面151之 寬度與第一頂面152之寬度相近。基本上，第一底面i5i 099136852 表單編號A0101 第12頁/共33頁 0992064362- 201218886 [0035] [0036] Ο [0037] 與第一頂面152之高度大於或等於100微米，第一底面 151之寬度與第一頂面152之寬度之差值小於或等於50微 米。或者說，第一線路15靠近基底層11之線寬與遠離基 底層11之線寬之差值小於或等於50微米。 第二線路16具有與基底層11接觸之第二底面161、與第二 底面161相對之第二頂面162以及兩個連接在第二底面 161與第二頂面162之間之第二側面163。第二底面161之 寬度與第二頂面162之寬度相近。基本上，第二底面161 與第二頂面162之高度大於或等於100微米，第二底面 161之寬度與第二頂面162之寬度之差值小於或等於50微 米。或者說，第二線路16靠近基底層11之線寬與遠離基 底層11之線寬之差值小於或等於50微米。整條第二線路 16之線寬較為一致。 整條第一線路15之線寬較為一致，整條第二線路16之線 寬亦較為一致，從而，第一線路15與第二線路16之間之 線距亦基本較為一致。一般來說，第一線路15與第二線 路16之厚度在100微米以上，第一線路15與第二線路16 之線寬均在100微米以上，第一線路15與第二線路16之線 距亦均在10 0微米以上。 本實施例中，每個第一側面153及每個第二側面163均具 有兩個突刺。本領域技術人員可以理解，在多次蝕刻形 成第一線路15與第二線路16之過程中，可以選擇適當之 銅蝕刻液，並控制蝕刻條件與蝕刻時間，從而避免在線 路側面形成突刺。另外，即使如本實施例所示，形成了 侧面具有突刺之第一線路15與第二線路16，但由於突刺 099136852 表單編號Α0101 第13頁/共33頁 0992064362-0 201218886 十分微小，因而並不會對第—線路15與第：線路& 輸性能造成影響。如果對線路之形狀存在要求，可以、雨 過後續磨刷、舰之方法去除存在於㈣側面 [0038] 本實施例中係通過三次㈣工序製作厚度為川微米 -線路15與第二線路16為例進行說明電路板之製作方去 。本領域技術人員可以理解，當銅箱層12之厚度為复他 數值時，即第—線路15與第二線路如厚“其他數值 時，可以通過其他絲之_卫序製作。❹，當鋼落 層12之厚度為100微米至15G微米時，可以通過兩次餘 工序製作形成第-線路15與第二線路16 ;當㈣層以 厚度為15〇«至22Q微米時，可以通過三次㈣工序彭 作形成第一線路15與第二線路16 ;當_12之厚度為 220微米至29G微米時，可以通過四次⑽工序製作形成 第一線路15與第二線路16。在製作線路時，僅需使得第 一次蚀刻之㈣深度為5G微米至75微米，當第__次餘刻 後蝕刻區剩餘之_層12之厚度小於或掌於75微求時： 第二次蚀刻即可完全去除㈣區之銅猪層12 ;當第一次 餘刻後㈣區之㈣㈣之剩餘厚度大於75微米時，第 二次蚀刻去除5G微米至75微米之似彳區之銅騎η ;當 第二次_後刻區_之_層12之厚度小於或等於 =米時，第三次_即可完全去除㈣區之㈣層η ，當第二次㈣後_區之㈣層12之剩餘厚度大於75 微f時’則需要第三次，第四次乃至更多次之㈣工序 方能完全去除關區之_層12 m欠㈣時， 銅羯層12之蝕刻深度均為50微米至75微米。 099136852 表單編號A01G1 第丨4頁/共33頁 0992064362-0 201218886 [0039] 需要說明，本實施例中僅以製作兩條線路’即第—線路 15與第二線路16為例說明製作電路板之方法。事實上， 在製作電路板時，線路之數量不限，可以為一條或兩條 以上，一般來說，為十條以上。 [0040] ❹ 本技術方案之製作電路板1〇〇之方法中，採用兩次以上之 蝕刻工序製作線路，相較於採用一次蝕刻工序製作線路 之方法而言’可以降低銅钱刻液各向同性之钱刻與水池 效應對線路形狀之影響，可以保證線路之形狀及尺寸， 使得電路板100之線路製作具有較高之良率。本技術方案 之電路板製作方法可以獲#線寬較為一致之線路，或者 說可以獲得形狀更接近長方形之線路。具艟而言，在線 路厚度在100微米以上時，通過兩次以上之姓刻工序可以 製作出線路各處之線寬差值在50微米以下之線路。並且 ，由於蝕刻工序非常成熟，成本亦較低，因此，即使採 用兩次以上之敍刻工序製作線路’亦並不會影響電路板 製作之成本與效率。 ❹ [0041] 綜上所述，本發明確已符合發明專利之要件，遂依法提 出專利申請。惟，以上所述者僅為本發明之較佳實施方 式，自不能以此限制本案之申請專利範圍。舉凡熟悉本 案技藝之人士援依本發明之精神所作之等效修飾或B ，皆應涵蓋於以下申請專利範圍内。 [圖式簡單說明】 [0042]圖1為本技術方案實施例提供之電路基板之剖視示音圖。 [0043] 099136852 圖2為本技術方案實蘭提供之在電路基板表面形成第一 光p且層之剖視示意圖° 0992064362-0 表單煸號A0101 第15頁/共33頁 201218886 [0044] 圖3為本技術方案實施例提供之在圖案化第一光阻層後之 剖視示意圖。 [0045] 圖4為本技術方案實施例提供之第一次蝕刻電路基板後之 剖視示意圖。 [0046] 圖5為本技術方案實施例提供之去除第一光阻層後之剖視 示意圖。 [0047] 圖6為本技術方案實施例提供之在電路基板表面形成第二 光阻層之剖視示意圖。 [0048] 圖7為本技術方案實施例提供之在圖案化第二光阻層後之 剖視示意圖。 [0049] 圖8為本技術方案實施例提供之第二次蝕刻電路基板後之 刮視示意圖。 [0050] 圖9為本技術方案實施例提供之去除第二光阻層後之剖視 示意圖。 [0051] 圖10為本技術方案實施例提供之在電路基板表面形成第 三光阻層之剖視示意圖。 [0052] 圖11為本技術方案實施例提供之在圖案化第三光阻層後 之剖視示意圖。 [0053] 圖1 2為本技術方案實施例提供之第三次蝕刻電路基板後 之剖視示意圖。 [0054] 圖13為本技術方案實施例提供之去除第三光阻層後之剖 視示意圖。 099136852 表單編號A0101 第16頁/共33頁 0992064362-0 201218886 【主要元件符號說明】 [0055] 電路基板：10 [0056] 基底層：11 [0057] 銅箔層：12 [0058] 第一線路區：121 [0059] 第二線路區：122 [0060] 第一蝕刻區：123 〇 [0061] 第二蝕刻區：124 [0062] 第三蝕刻區：125 [0063] 第一光阻層：21 [0064] 第一凸起：131 [0065] 第二凸起：132 [0066] 第一開口 ： 141 〇 [0067] 第二開口 ： 142 [0068] 第三開口 ： 143 [0069] 第二光阻層：22 [0070] 第三凸起：133 [0071] 第四凸起：134 [0072] 第四開口 ： 14 4 [0073] 第五開口 ： 145 099136852 表單編號A0101 第17頁/共33頁 0992064362-0 201218886 [0074] 第六開口 ： 146 [0075] 第三光阻層：23 [0076] 第五凸起： 135 [0077] 第六凸起： 136 [0078] 第七開口 ： 147 [0079] 第八開口 ： 148 [0080] 第九開口 ： ：149 [0081] 第一線路： ：15 [0082] 第二線路： ：16 [0083] 間隔空間： ：17 [0084] 第一底面： ：151 [0085] 第一頂面： ：152 [0086] 第一側面 :153 [0087] 第二底面 ：161 [0088] 第二頂面 ：162 [0089] 第二侧面 :163 099136852 表單編號A0101 第18頁/共33頁 0992064362-0Technology's literature «„ ·,, 驮Hlgh density ffiultilayer printed circuit hr, a 4: „ oard for UITAC M~880”. And, the circuit board must not only be electricity;; Wu also μ & €子兀15 Provides electrical connections and the necessary mechanical support's to have more features: [0003] Thick copper circuit boards have large thicknesses, which provide high current, integrated power, good heat dissipation, control characteristic impedance, etc. When the characteristics of the thick copper circuit board are made, the image transfer technology of the prior art is also used for one-time forming, that is, 'the first resist layer is formed on the surface of the copper box, and then the engraving liquid is engraved through the paving liquid. The exposed copper slab is removed, and the copper box that is not secretly formed constitutes a line. In the prior art method of manufacturing a thick copper circuit board, there are the following two problems. First, the copper etchant (4) is isotropic, thus In the copper _ liquid from the copper "face to the next moment of the strong" will also be private side of the steel (four), that is, (four) under the photoresist 099136852 Form No. A0101 page / a total of 33 page 0992064362-0 201218886 copper foil. In copper foil In a circuit board with a small degree, since the etching time is short, the side etching may not affect the line. However, in the thick copper circuit board, since the thickness of the copper foil is large, the last name of the fork is required. Engraving time, which will increase the side intrusion #, resulting in a smaller width above the line, and may even erode through the upper part of the line, causing the photoresist to break away from the steel layer, thus causing the entire copper foil to be etched. It is impossible to form a line. Second, since the copper etchant after the etching forms a recess in the copper foil after etching, the copper etching solution after the reaction tends to accumulate in the recesses, thereby preventing the unreacted copper etching liquid from entering. In the depression, 'continue to engrave the copper under the depression. That is, the "pool effect" will seriously affect the production of the lines in the thick copper circuit board, so that the lower copper is less engraved by the surname. The shape becomes trapezoidal, so that the distance between the adjacent two lines is farther away from the photoresist layer, and even the adjacent two lines may be connected. The above two questions are interesting to the thick steel line. The production yield of the board is not necessary. It is necessary to provide a circuit board manufacturing method which can have a high production yield. [Abstract] [0005] [0006] 099136852 A method of manufacturing a circuit board, comprising the steps of: providing a circuit substrate, wherein the circuit substrate has a copper foil layer, and the thickness of the copper ΜΨ, ^ + / white layer is greater than or equal to 100 copper has a first green road The zone, the zone adjacent to the first line zone, and the surname s, U between the first line zone and the second line zone, and the copper foil layer of the etched zone are removed by two or more etch-d processes. Before the mother etches, a patterned photoresist layer is formed on the surface of the copper foil layer. Page 5 of 33 Form No. A0101 0992064362-0 201218886 'To shield the copper foil layer of the first line region from the copper of the second line region a box layer, and exposing the copper foil layer of the etched region; each etching the copper layer of the etched region 'etching depth between 50 micrometers and 75 micrometers; removing the patterned photoresist layer after each moment After removing the copper box layer of the etched area, the first line area constitutes the first line, such that the second line area constitutes the second line. [0008] In the circuit board manufacturing method of the present technical solution, the circuit is formed by using two or more etching processes, and the isotropic etching of the copper etching solution can be reduced compared with the method of fabricating the circuit by using one etching process. The effect of the pool effect on the shape of the line can ensure the shape and size of the line. · The circuit board production has a high yield. The electric=board manufacturing method of the technical solution can obtain a line with a relatively uniform line width, and the latter can obtain a line with a shape closer to a rectangular shape. Specifically, when the line thickness is more than 100 μm, the line having a line width difference of less than 50 μm across the line can be made by two or more etching processes. Moreover, the process of surname engraving is very mature and the forest is low. Therefore, the production of the line by the side process of more than two processes does not affect the cost and efficiency of circuit board production. [Embodiment] Hereinafter, a method for manufacturing a circuit board provided by the present technology will be further described in detail with reference to the accompanying drawings and embodiments. [0009] A circuit board manufacturing method provided by an embodiment of the present invention includes a step [0010] 099136852. In the first step, please refer to FIG. 1 'providing a circuit substrate 1 〇. The circuit board 10 includes a base layer 11 and a surface attached to the base layer. Form No. A_1 » - Bai Zeng 12. The 6th page/total 33 page 0992064362-0 201218886 基底 The base layer 11 may include only an insulating layer, and may also be a structure including at least one insulating layer and at least one conductive layer. That is, the circuit board 1 can be a single-sided steel-clad substrate, a double-sided copper-clad substrate, or a multilayer circuit substrate. The multilayer circuit substrate refers to a substrate on which an inner layer wiring has been formed, and an outer layer wiring has not been formed. In the embodiment, the circuit substrate 10 is a single-sided steel-coated substrate, that is, the base layer 11 is an insulating layer. The material of the insulating layer is a hard material, such as epoxy resin, fiberglass cloth, etc. 'but can also be a soft & material 'such as polyimide (Polyimide, ΡΙ), polyethylene to the original glycol vinegar ( P〇iyethylene Terephthalate, ET), polyethylene naphthalate (p〇iyethyiene naphtha late ' pen), etc. The copper box layer is typically an electroplated copper foil, a rolled copper, or a composite structure comprising a rolled copper strip and an electrolytic copper strip. The copper layer 12 has a thickness greater than or equal to 1 micron and can generally be between 140 and 25 microns. [0011] The copper falling layer 12 is used to form a conductive line, and therefore, the copper book (4) includes a plurality of lines for forming a secret line (4). In the present embodiment, the _ layer 12 includes two line regions and three residual regions as an example. In the present implementation, the (10) layer η includes a first line region 121, a second line F 9 ^ edge amp & 122, a first etched region 123, a second surname £12 4, and a third money engraved p·1 9 q ήί·, +, 哲习£125. The first line region 121 is located between the first button region 123 and the second etch region 124, and the first _ region 123 is located between the first line region 121 and the second line region 122, the second line The area 122 is located between the first _ etched area 123 and the third etched area. [0012] First, the first remaining area 123, 099136852 is removed by the process of two or more people. Form No. Α0101 Page 7 / Total Page 33, 0992064362-0 201218886 The copper foil layer 12 of the second etched region 124 and the third etched region 125 has an etch depth of 50 micrometers to 75 micrometers per etch. In the present embodiment, the thickness of the copper foil layer 12 is 210 micrometers, and the copper foil layer 12 of the first etching region 123, the second etching region 124, and the third etching region 125 is removed by a three etching process. The first etching step, the second etching step, and the third etching step will be specifically described below. Referring to FIG. 2 to FIG. 5, the first etching process may include the following steps: [0015] First, referring to FIG. 2, a first photoresist layer 21 is formed on the surface of the copper foil layer 12. The first photoresist layer 21 can be formed by applying a liquid photoresist ink to the surface of the copper foil layer 12. [0016] Next, a portion of the first photoresist layer 21 is removed by an exposure and development process to form a patterned first photoresist layer 21, as shown in FIG. The patterned first photoresist layer 21 shields the copper foil layer 12 of the first wiring region 121 and the copper foil layer 12 of the second wiring region 122, and exposes the first etching region 123, the second etching region 124, and the third etching. The copper foil layer 12 of the region 125. [0017] Again, the copper etch layer 12 of the first etched region 123, the second etched region 124, and the third etched region 125 is exposed by the copper etching solution for the first time, until the first etched region 123 and the second etched region The copper foil layer 12 of the 124 and third etched regions 125 is etched away from 50 microns to 75 microns. The copper etching solution may be a copper chloride etching solution, a vaporized iron based etching solution, or a sulfuric acid/hydrogen peroxide based etching solution. [0018] During the first etching, the copper etching solution is substantially etched downward from the surface of the copper foil layer 12, and the thickness of the copper foil layer 12 is etched away to be the etching depth. In this embodiment, the first etching has an etch depth of 70 microns. 099136852 Form No. A0101 Page 8 of 33 0992064362-0 201218886 Due to the isotropy of the etch, 'in the first line region 121 and the second line region 122, close to the first #刻区123, the second etched region 124 and the third etched zone 1 2 5 of the copper foil layer 12 may have a small portion that is also erased by the surname. After etching, a first protrusion 131 is formed in the first line region 121, and a second protrusion 132' is formed in the second line region 122. The first opening 141' is formed in the first remaining region 123. The second opening 142 forms a third opening 143' in the third scribe region 125 as shown in FIG. Due to the pool effect, the cross section of the first protrusion 131 and the second protrusion 132 are substantially close to each other. [0020] [0021] [0022] Like a trapezoid, and the cross section of the second opening 142 Basically inverted trapezoidal. .. Finally, please refer to Figure 5, after the first etching, the patterned first photoresist layer 21 is removed. The first photoresist layer 21 can be removed by a strong alkali solution to remove the first etching process, and the second etching process can be performed by a step similar to the first etching process. Θ: First, referring to FIG. 6, a second photoresist layer 22 is formed on the surface of the copper foil layer 12. That is, the second photoresist layer 22 is distributed on the bottom surface of the first opening 141, the surface of the first protrusion 131, the surface of the second protrusion 32, the bottom surface of the second opening 142, and the bottom surface of the third opening 143. The second photoresist layer 22 can also be a liquid photoresist ink. Next, a portion of the second photoresist layer 22 is removed by an exposure and development process to form a patterned second photoresist layer 22, as shown in FIG. The patterned second photoresist layer 22 shields the surface of the first layer region 121 from the surface of the layer 12 and the surface of the copper pad 12 of the second line region 122, and exposes the -(10) region 123, 099136852 Form No. A0101 No. 9 Page / Total 33 pages 0992064362-0 201218886 The second etched region 124 and the third etched region ^ 125 of the copper foil layer 12. Also, the second photoresist layer 22 of the gangs masks the surface of the n-th projection 1 31 and the surface of the first protrusion 132, and exposes the bottom surface of the first I-th projection 142 and the third opening. I43 <bottom surface. [0023], the first etching exposed, the second etching region 124 and the third etching F19c; the copper foil layer 12 of the region 125, the etching region 123, the second etching region 12 and the second etching region The second foil region 1225 of the copper foil layer 12 is etched away from 50 micrometers to 75 microseconds. + v, ° In this embodiment, the etching depth of the etch is also 70 micrometers. [0025] [0026] After the second time, a third protrusion 133 connected under the first protrusion m is formed in the first line region 121, and a second connection is formed in the second line region 122 below the second protrusion 132. The fourth protrusion 134' forms a fourth opening 144 communicating with the lower side of the first opening 141 in the first residual region 123, and forms a fifth opening 145 under the second opening 142 in the second etching region 124, in the third etching. The region 125 forms a sixth opening connected to the lower side of the third opening 143, as shown in Fig. 8. The cross surface of the third protrusion 133 is approximately trapezoidal, and the fourth protrusion 134 The cross section is also approximately trapezoidal. In addition, due to the isotropy of the etching, in the first line region 121 and the second line region 122, the first remaining region 123, the second engraved region 124, and the third etched region are adjacent. A portion of the copper foil layer 12 of 125 may be etched away 'so that there may be a spur at the junction of the first protrusion 131 and the third protrusion 133, at the junction of the second protrusion 132 and the fourth protrusion 134 There may also be a spike. Finally, please refer to Figure 9, removing the patterned second photoresist layer 22. 099136852 Form bat number A0101 Page 10 of 33 page 0992064362-0 201218886 [0027] [0029] [0031] After the second etching step, a third etching step may be performed, and the third etching step may be performed in a step similar to the first etching step, as shown in FIGS. 10 to 13: First, please Referring to FIG. 10, a third photoresist layer 23 is formed on the surface of the copper foil layer 12, that is, 'the third photoresist layer 23 is distributed on the bottom surface of the fourth opening 144, the surface of the first bump 31 and the third bump 133, and the second The protrusion 132 and the fourth protrusion have a surface of 4, a bottom surface of the fifth opening ι45, and a sixth opening The third photoresist layer 23 may also be a liquid photoresist ink. Next, a portion of the third photoresist layer 23 is removed by an exposure and development process to form a patterned third photoresist layer 23, as shown in FIG. The patterned third photoresist layer 23 shields the surface of the copper foil layer 2 of the first wiring region 121 and the surface of the steel foil layer 12 of the second wiring region 122, and exposes the first etching region 123 and the second The steel foil layer 12 of the etched region 124 and the third etched region 125. That is, the patterned third photoresist layer 23 shields the surface of the first protrusion 131, the surface of the second protrusion 132, the surface of the third protrusion 133, and the surface of the fourth protrusion 134 and exposes the fourth The bottom surface of the opening 14 4, the bottom surface of the fifth opening 14 5 and the bottom surface of the sixth opening 146. Thirdly, the first etched region 123, the second button region 124 and the third rice layer 125 of the copper foil layer 12 are exposed by the copper etchant for the third etching, until the first residual region 123, the second The copper foil layer 12 of the etched region 24 and the third etched region 125 is completely etched away to expose the corresponding underlying layer 丨丨 of the first etched region 123, the second etched region 124, and the third etched region 125. In this embodiment, the etching depth of the third etching is also 7 Å. After the second remaining moment, 'in the first line area 121 is formed to be connected to the third protrusion 099136852 Form No. Α0101 Page 11 / Total 33 Page 0992064362-0 201218886 133 Below the fifth protrusion 135 'In the second line area I22 forms a sixth & 136 connected under the fourth protrusion m, a seventh opening 147 which is connected to the lower side of the fourth P and 144 in the first etching region 123, and a fifth connection 147 in the second _ region 124. An eighth opening 148 below the opening 145 forms a ninth opening 149 in communication with the sixth opening 丨 46 in the second etched region 125, as shown in FIG. The cross section of the fifth protrusion 135 is approximately trapezoidal, and the cross section of the sixth protrusion 136 is also approximately trapezoidal. The first protrusions 131, the = protrusions 133, and the fifth protrusions 135 are sequentially connected to constitute the first line 15. A protrusion 132, a fourth protrusion 134 and a sixth protrusion 136 are sequentially connected to form a second line 16. The first line 15 and the second line i 6 are separated by a space 17 formed by the fourth opening 144 of the first opening 141 and the seventh opening 147. [0033] In addition, due to the isotropy of the etching, in the first line region 121 and the second line region 122, close to the first (10) region 123, the second (four) region 124, and the third thin 1 m. 12 (4) layer 12 may have a small portion also reduced, so that there may be a spur at the junction of the fifth protrusion 135 and the third protrusion 133, at the junction of the sixth protrusion 136 and the fourth convex 134 There may also be a spur. Finally, referring to FIG. 13, the patterned third photoresist layer 23 is removed. Thus, the circuit board 1 having the base layer 11 and the first line 15 and the second line 16 formed on the surface of the base layer 11 can be obtained. The first line 15 has a first bottom surface κι in contact with the base layer 11, a first top surface 152 opposite to the first bottom surface 151, and two first side surfaces 153 connected between the first bottom surface 151 and the first top surface 152. . The width of the first bottom surface 151 is similar to the width of the first top surface 152. Basically, the first bottom surface i5i 099136852 Form No. A0101 Page 12 / Total 33 Page 0992064362 - 201218886 [0036] [0037] The height of the first top surface 152 is greater than or equal to 100 microns, and the first bottom surface 151 The difference between the width and the width of the first top surface 152 is less than or equal to 50 microns. In other words, the difference between the line width of the first line 15 near the base layer 11 and the line width away from the base layer 11 is less than or equal to 50 μm. The second line 16 has a second bottom surface 161 in contact with the base layer 11 , a second top surface 162 opposite to the second bottom surface 161 , and two second side surfaces 163 connected between the second bottom surface 161 and the second top surface 162 . . The width of the second bottom surface 161 is similar to the width of the second top surface 162. Basically, the height of the second bottom surface 161 and the second top surface 162 is greater than or equal to 100 microns, and the difference between the width of the second bottom surface 161 and the width of the second top surface 162 is less than or equal to 50 micrometers. Alternatively, the difference between the line width of the second line 16 adjacent to the base layer 11 and the line width away from the base layer 11 is less than or equal to 50 microns. The line width of the entire second line 16 is relatively uniform. The line width of the entire first line 15 is relatively uniform, and the line width of the entire second line 16 is also relatively uniform, so that the line spacing between the first line 15 and the second line 16 is substantially uniform. Generally, the thickness of the first line 15 and the second line 16 is 100 μm or more, and the line widths of the first line 15 and the second line 16 are both 100 μm or more, and the line distance between the first line 15 and the second line 16 is Also above 10 microns. In this embodiment, each of the first side 153 and each of the second side 163 has two spurs. Those skilled in the art will appreciate that during the multiple etching to form the first line 15 and the second line 16, an appropriate copper etchant can be selected and the etching conditions and etching time can be controlled to avoid the formation of spurs on the sides of the line. In addition, even as shown in the present embodiment, the first line 15 and the second line 16 having the spurs on the side are formed, but the spur 099136852 form number Α0101 page 13/33 page 0992064362-0 201218886 is very small, and thus is not It will affect the performance of the first line 15 and the line: line & If there is a requirement for the shape of the line, it may be removed by rain, and the method of removing the ship may be present on the side of (4). [0038] In this embodiment, the thickness is made by the third (four) process, and the thickness of the line is 15 and the line 15 and the second line 16 are For example, let's explain how to make a circuit board. Those skilled in the art can understand that when the thickness of the copper box layer 12 is a complex value, that is, when the first line 15 and the second line are thick, "other values can be made by other wires." When the thickness of the falling layer 12 is 100 micrometers to 15 micrometers, the first line 15 and the second line 16 can be formed by two remaining processes; when the thickness of the (four) layer is 15 〇 « to 22 Q micron, the process can be passed through three (four) steps. Peng made the first line 15 and the second line 16; when the thickness of _12 is 220 micrometers to 29G micrometers, the first line 15 and the second line 16 can be formed by four (10) processes. The thickness of the first etching (4) is required to be 5G micrometers to 75 micrometers. When the thickness of the remaining layer 12 of the etched area after the __th residual is less than or less than 75 microseconds: the second etching can be completely removed. (4) The copper pig layer of the area 12; when the remaining thickness of (4) (4) of the (4) area is greater than 75 microns after the first remnant, the second etching removes the copper riding η of 5G micron to 75 micron; _After the engraved area _ _ layer 12 thickness is less than or equal to = m, the third time _ Fully remove the (four) layer η of the (four) zone. When the remaining thickness of the (four) layer 12 of the second (four) zone is greater than 75 microf, then the third, fourth or even more (four) processes are required to be completely removed. The etch depth of the copper ruthenium layer 12 is 50 micrometers to 75 micrometers when the layer is 12 m owed (four). 099136852 Form No. A01G1 Page 4 of 33 pages 0992064362-0 201218886 [0039] Need to explain, this implementation In the example, the method of making a circuit board is described by taking two lines, that is, the first line 15 and the second line 16. As an example, when the circuit board is made, the number of lines may be one or more. In general, there are more than ten. [0040] In the method of fabricating a circuit board according to the present invention, a circuit is formed by using two or more etching processes, compared to a method of fabricating a circuit by using one etching process. 'It can reduce the influence of the isotropic money engraving and the pool effect on the shape of the circuit, and can ensure the shape and size of the circuit, so that the circuit of the circuit board 100 has a high yield. The circuit board manufacturer of the technical solution It is possible to obtain a line with a relatively uniform line width, or a line having a shape closer to a rectangle. In the case of a line having a thickness of 100 μm or more, it is possible to create a line by two or more times. Lines with a line width difference of less than 50 microns. And because the etching process is very mature and the cost is low, even if the circuit is made by using more than two or more steps, it will not affect the cost and efficiency of board manufacturing.综 [0041] In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and the application of the case cannot be limited thereby. Patent scope. Equivalent modifications or B in accordance with the spirit of the present invention by those skilled in the art should be covered by the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0042] FIG. 1 is a cross-sectional view of a circuit board provided by an embodiment of the present technical solution. [0043] FIG. 2 is a cross-sectional view showing the formation of the first light p on the surface of the circuit substrate and the layer provided by the real solution of the present invention. 0992064362-0 Form No. A0101 Page 15 / Total 33 pages 201218886 [0044] A schematic cross-sectional view of the embodiment of the present technical solution after patterning the first photoresist layer. 4 is a cross-sectional view showing the first etching of a circuit substrate according to an embodiment of the present application. 5 is a cross-sectional view of the first photoresist layer after removing the first photoresist layer according to an embodiment of the present disclosure. 6 is a cross-sectional view showing a second photoresist layer formed on a surface of a circuit substrate according to an embodiment of the present disclosure. FIG. 7 is a cross-sectional view showing the second photoresist layer after patterning according to an embodiment of the present disclosure. 8 is a schematic view showing the second etching of the circuit substrate after the embodiment of the present application. 9 is a cross-sectional view of the second photoresist layer after removing the second photoresist layer according to an embodiment of the present application. FIG. 10 is a cross-sectional view showing a third photoresist layer formed on a surface of a circuit substrate according to an embodiment of the present disclosure. FIG. 11 is a cross-sectional view of the third photoresist layer after patterning according to an embodiment of the present disclosure. FIG. 12 is a cross-sectional view showing the third etching of the circuit substrate according to the embodiment of the present application. FIG. 13 is a schematic cross-sectional view of the third photoresist layer after removing the third photoresist layer according to an embodiment of the present disclosure. 099136852 Form No. A0101 Page 16 of 33 0992064362-0 201218886 [Description of Main Component Symbols] [0055] Circuit Substrate: 10 [0056] Base Layer: 11 [0057] Copper Foil Layer: 12 [0058] First Line Area :121 [0059] Second line region: 122 [0060] First etched region: 123 〇 [0061] Second etched region: 124 [0062] Third etched region: 125 [0063] First photoresist layer: 21 [ 0064] First protrusion: 131 [0065] Second protrusion: 132 [0066] First opening: 141 〇 [0067] Second opening: 142 [0068] Third opening: 143 [0069] Second photoresist layer :22 [0070] Third protrusion: 133 [0071] Fourth protrusion: 134 [0072] Fourth opening: 14 4 [0073] Fifth opening: 145 099136852 Form number A0101 Page 17 / Total 33 page 0992064362- 0 201218886 [0074] sixth opening: 146 [0075] third photoresist layer: 23 [0076] fifth bump: 135 [0077] sixth bump: 136 [0078] seventh opening: 147 [0079] Eight openings: 148 [0080] Ninth opening: :149 [0081] First line: :15 [0082] Second line: :16 [0083] Space: 17 [0084] First bottom surface: : 151 [0085] First top surface: : 152 [0086] First side: 153 [0087] Second bottom surface: 161 [0088] Second top surface: 162 [0089] Second Side: 163 099136852 Form No. A0101 Page 18 of 33 0992064362-0