TWI420993B - Method for manufacturing printed circuit board - Google Patents

Description

Circuit board manufacturing method

The present invention relates to circuit board manufacturing technology, and in particular, to a circuit board manufacturing method.

In the information, communications and consumer electronics industries, circuit boards are an essential component of all electronic products. With the development of electronic products in the direction of miniaturization and high speed, circuit boards have also evolved from single-sided circuit boards to double-sided circuit boards and multilayer circuit boards. Multilayer boards are widely used due to their large wiring area and high assembly density. Please refer to Takahashi, A. et al., 1992, IEEE Trans.on Components, Packaging, and Manufacturing Technology, "High Density Layer printed". Circuit board for HITACM~880”. Moreover, the board not only needs to provide electrical connections for electronic components and the necessary mechanical support, but also has more functions.

Thick copper circuit boards have a large thickness, and thus have the characteristics of being able to provide a large current, integrating power, good heat dissipation, and controlling characteristic impedance. In the production of thick copper circuit boards, the image transfer technique of the prior art is generally used for one etching. That is, a patterned photoresist layer is formed on the surface of the copper foil, and then the exposed copper foil is removed by etching with a copper etching solution, and finally the copper foil which is not etched constitutes a wiring. In the prior art method of manufacturing a thick copper wiring board, there are the following two problems. First, the etching of the copper etching solution is isotropic, so that the copper etching solution is etched downward from the surface of the copper foil. In the process, it will also erode the copper foil on the side, that is, the copper foil under the photoresist. In a circuit board having a small copper foil thickness, since the etching time is short, the side etching does not affect the wiring. However, in a thick copper circuit board, since the thickness of the copper foil is large, a long etching time is required, which may aggravate the side erosion, causing the width above the line to become small, and may even seriously erode the upper portion of the line. The photoresist is caused to detach from the copper foil layer, which causes the entire copper foil to be etched and cannot form a line. Secondly, after the etching process, after the copper foil is etched to form a recess in the copper foil, the copper etching solution after the reaction is likely to accumulate in the recesses, thereby preventing the unreacted copper etching liquid from entering the recess. Continue to etch down the copper under the recess. That is, the "pool effect" can seriously affect the fabrication of the lines in the thick copper circuit board, so that the lower copper is etched less. That is, the shape of the line is made trapezoidal, so that the distance between the adjacent two lines farther from the photoresist layer is smaller, and even the adjacent two lines may be connected. Both of these issues have affected the production yield of thick copper circuit boards.

In view of this, it is necessary to provide a circuit board manufacturing method which can have a high manufacturing yield.

A method of fabricating a circuit board will be described below by way of example.

A circuit board manufacturing method comprising the steps of: providing a circuit substrate, wherein the circuit substrate has a copper foil layer, the copper foil layer has a thickness greater than or equal to 100 micrometers, and the copper foil layer has a first line region and is close to the first line a second line region of the region and an etch region between the first line region and the second line region; and removing the copper foil layer of the etched region by two or more etching processes. Before each etching, a patterned photoresist layer is formed on the surface of the copper foil layer to shield the copper foil layer of the first wiring region and the copper foil layer of the second wiring region And exposing the copper foil layer of the etched region; each etching the copper foil layer of the etched region, the etching depth is between 50 micrometers and 75 micrometers; the patterned photoresist layer is removed after each etching, thereby removing the etching After the copper foil layer of the region, the first line region constitutes the first line, such that the second line region constitutes the second line.

In the circuit board manufacturing method of the technical solution, the circuit is formed by using two or more etching processes, and the isotropic etching and pool effect of the copper etching solution can be reduced compared with the method of fabricating the circuit by using one etching process. The influence of the circuit can ensure the shape and size of the circuit, so that the circuit board production has a high yield. The circuit board manufacturing method of the present technical solution can obtain a line having a relatively uniform line width, or a line having a shape closer to a rectangle. Specifically, when the line thickness is 100 μm or more, a line having a line width difference of 50 μm or less across the line can be produced by two or more etching processes. Moreover, since the etching process is very mature and the cost is low, even if the circuit is fabricated by using two or more etching processes, the cost and efficiency of the board manufacturing are not affected.

10‧‧‧ circuit board

11‧‧‧ basal layer

12‧‧‧copper layer

121‧‧‧First line area

122‧‧‧Second line area

123‧‧‧First etching zone

124‧‧‧Second etched area

125‧‧‧ Third etching zone

21‧‧‧First photoresist layer

131‧‧‧First bulge

132‧‧‧second bulge

141‧‧‧ first opening

142‧‧‧ second opening

143‧‧‧ third opening

22‧‧‧Second photoresist layer

133‧‧‧3rd bulge

134‧‧‧fourth bulge

144‧‧‧fourth opening

145‧‧‧ fifth opening

146‧‧‧ sixth opening

23‧‧‧ Third photoresist layer

135‧‧‧5th bulge

136‧‧‧ sixth bulge

147‧‧‧ seventh opening

148‧‧‧ eighth opening

149‧‧‧ ninth opening

15‧‧‧First line

16‧‧‧second line

17‧‧‧Interval space

151‧‧‧ first bottom surface

152‧‧‧ first top surface

153‧‧‧ first side

161‧‧‧second bottom surface

162‧‧‧Second top

163‧‧‧ second side

FIG. 1 is a cross-sectional view of a circuit substrate according to an embodiment of the present technical solution.

2 is a schematic cross-sectional view showing a first photoresist layer formed on a surface of a circuit substrate according to an embodiment of the present disclosure.

FIG. 3 is a cross-sectional view of the first photoresist layer after patterning according to an embodiment of the present disclosure.

FIG. 4 is a cross-sectional view showing the first etching of the circuit substrate provided by the embodiment of the present technical solution.

FIG. 5 is a cross-sectional view of the first photoresist layer after removing the first photoresist layer according to an embodiment of the present disclosure.

FIG. 6 is a cross-sectional view showing a second photoresist layer formed on a surface of a circuit substrate according to an embodiment of the present disclosure.

FIG. 7 is a schematic cross-sectional view of the embodiment of the present invention after the second photoresist layer is patterned.

FIG. 8 is a cross-sectional view showing the second etching of the circuit substrate according to the embodiment of the present application.

FIG. 9 is a cross-sectional view showing the second photoresist layer removed after the embodiment of the present invention is removed.

FIG. 10 is a cross-sectional view showing a third photoresist layer formed on a surface of a circuit substrate according to an embodiment of the present disclosure.

FIG. 11 is a cross-sectional view showing the third photoresist layer after patterning according to an embodiment of the present disclosure.

FIG. 12 is a cross-sectional view showing the third etching of the circuit substrate according to the embodiment of the present application.

FIG. 13 is a cross-sectional view of the third photoresist layer after removing the third photoresist layer according to an embodiment of the present disclosure.

The method for fabricating the circuit board provided by the technical solution will be further described in detail below with reference to the accompanying drawings and embodiments.

The circuit board manufacturing method provided by the embodiment of the present technical solution includes the following steps: First, referring to FIG. 1, the circuit substrate 10 is provided. The circuit substrate 10 includes a base layer 11 and a copper foil layer 12 bonded to the surface of the base layer 11. The base layer 11 may include only an insulating layer, and may also be a structure including at least one insulating layer and at least one conductive layer. That is, the circuit substrate 10 may be a single-sided copper-clad substrate, a double-sided copper-clad substrate, or a multilayer circuit substrate. The multilayer circuit substrate refers to a substrate on which an inner layer line has been formed, and an outer layer line has not been formed. In the embodiment, the circuit substrate 10 is a single-sided copper-clad substrate, that is, the base layer 11 is an insulating layer. The material of the insulating layer is a hard material, such as an epoxy resin, a fiberglass cloth, etc., but may also be a flexible material, such as Polyimide (PI), polyethylene terephthalate (Polyethylene). Terephthalate, PET), polyethylene naphthalate (PEN), and the like. The copper foil layer 12 is generally an electroplated copper foil, a rolled copper foil or a composite structure including a rolled copper foil and an electrolytic copper foil. The thickness of the copper foil layer 12 is greater than or equal to 100 microns and, in general, may be between 140 microns and 250 microns.

The copper foil layer 12 is used to form a conductive trace. Therefore, the copper foil layer 12 includes a plurality of wiring regions for forming a wiring and a plurality of etching regions to be removed. In the present embodiment, the copper foil layer 12 includes two line regions and three etching regions as an example for description. That is, in the present embodiment, the copper foil layer 12 includes a first wiring region 121, a second wiring region 122, a first etching region 123, a second etching region 124, and a third etching region 125. The first line region 121 is located between the first etch region 123 and the second etch region 124. The first etch region 123 is located between the first line region 121 and the second line region 122, and the second line region 122 is located between the first etched region 123 and the third etched region 125.

In the second step, the copper foil layer 12 of the first etched region 123, the second etched region 124, and the third etched region 125 is removed by two or more etching processes, and the etching depth is etched from 50 micrometers to 75 micrometers per etching.

In the present embodiment, the thickness of the copper foil layer 12 is 210 micrometers, and the copper foil layer 12 of the first etching region 123, the second etching region 124, and the third etching region 125 is removed by a three-time etching process. Hereinafter, the first etching step, the second etching step, and the third etching step will be specifically described.

Referring to FIG. 2 to FIG. 5 , the first etching process may include the following steps: First, referring to FIG. 2 , a first photoresist layer 21 is formed on the surface of the copper foil layer 12 . The first photoresist layer 21 can be formed by applying a liquid photoresist ink to the surface of the copper foil layer 12.

Next, a portion of the first photoresist layer 21 is removed by an exposure and development process to form a patterned first photoresist layer 21, as shown in FIG. The patterned first photoresist layer 21 shields the copper foil layer 12 of the first wiring region 121 and the copper foil layer 12 of the second wiring region 122, and exposes the first etching region 123, the second etching region 124, and the third etching. The copper foil layer 12 of the region 125.

Again, the copper etch layer 12 of the first etched region 123, the second etched region 124, and the third etched region 125 is exposed to the first etched region 123, the second etched region 124, and the first etched region by a copper etchant. The copper foil layer 12 of the triple etched region 125 is etched away from 50 microns to 75 microns. The copper etching solution may be a copper chloride-based etching solution, a ferric chloride-based etching solution, or a sulfuric acid/hydrogen peroxide-based etching solution.

During the first etching, the copper etching solution is substantially etched downward from the surface of the copper foil layer 12, and the thickness of the copper foil layer 12 is etched away to be the etching depth. In this embodiment The etching depth of the first etching was 70 microns. Due to the isotropy of the etch, in the first line region 121 and the second line region 122, the copper foil layer 12 adjacent to the first etch region 123, the second etch region 124, and the third etch region 125 may have a small portion. Also etched away. After the etching, a first bump 131 is formed in the first wiring region 121, a second bump 132 is formed in the second wiring region 122, a first opening 141 is formed in the first etching region 123, and a second opening is formed in the second etching region 124. The opening 142 forms a third opening 143 in the third etched region 125, as shown in FIG. Due to the pool effect, the cross section of the first protrusion 131 and the second protrusion 132 are substantially similar to the trapezoid, and the second opening 142 has a substantially inverted cross section.

Finally, referring to FIG. 5, after the first etching, the patterned first photoresist layer 21 is removed. The first photoresist layer 21 can be removed by a method of dissolving a strong alkali solution.

A second etching process may be performed after the first etching process, and a second etching process may be performed similar to the first etching process, as shown in FIGS. 6 to 9 : First, please refer to FIG. 6 , in the copper foil A second photoresist layer 22 is formed on the surface of the layer 12. That is, the second photoresist layer 22 is distributed on the bottom surface of the first opening 141, the surface of the first protrusion 131, the surface of the second protrusion 132, the bottom surface of the second opening 142, and the bottom surface of the third opening 143. The second photoresist layer 22 can also be a liquid photoresist ink.

Next, a portion of the second photoresist layer 22 is removed by an exposure and development process to form a patterned second photoresist layer 22, as shown in FIG. The patterned second photoresist layer 22 shields the surface of the copper foil layer 12 of the first wiring region 121 and the surface of the copper foil layer 12 of the second wiring region 122, and exposes the first etching region 123 and the second etching region 124. And a copper foil layer 12 of the third etched region 125. That is, the patterned second photoresist layer 22 shields the first protrusion 131 The surface and the surface of the second protrusion 132 expose the bottom surface of the first opening 141, the bottom surface of the second opening 142, and the bottom surface of the third opening 143.

Again, the copper etch layer 12 of the first etched region 123, the second etched region 124, and the third etched region 125 is exposed through the copper etchant for a second time, until the first etched region 123, the second etched region 124, and the first etched region The copper foil layer 12 of the triple etched region 125 is etched away from 50 microns to 75 microns. In this embodiment, the etching depth of the second etching is also 70 micrometers.

After the second etching, a third protrusion 133 connected under the first protrusion 131 is formed in the first line region 121, and a fourth protrusion 134 connected under the second protrusion 132 is formed in the second line region 122. Forming a fourth opening 144 under the first opening 141 in the first etched region 123, forming a fifth opening 145 under the second opening 142 in the second etched region 124, and forming a communication in the third etched region 125 The sixth opening 146 below the third opening 143 is as shown in FIG. The cross section of the third protrusion 133 is approximately trapezoidal, and the cross section of the fourth protrusion 134 is also approximately trapezoidal.

In addition, since the etching is isotropic, in the first line region 121 and the second line region 122, the copper foil layer 12 adjacent to the first etching region 123, the second etching region 124, and the third etching region 125 may have A small portion is also etched away, so that there may be a spur at the junction of the first protrusion 131 and the third protrusion 133, and a spur may also exist at the junction of the second protrusion 132 and the fourth protrusion 134.

Finally, referring to FIG. 9, the patterned second photoresist layer 22 is removed.

A third etching process may be performed after the second etching process, and a third etching process may be performed in a step similar to the first etching process, as shown in FIGS. 10 to 13 : First, please refer to FIG. 10 , in the copper foil A third photoresist layer 23 is formed on the surface of the layer 12. That is, the first The three photoresist layers 23 are distributed on the bottom surface of the fourth opening 144, the surfaces of the first protrusions 131 and the third protrusions 133, the surfaces of the second protrusions 132 and the fourth protrusions 134, the bottom surface of the fifth opening 145, and the sixth The bottom surface of the opening 146. The third photoresist layer 23 can also be a liquid photoresist ink.

Next, a portion of the third photoresist layer 23 is removed by an exposure and development process to form a patterned third photoresist layer 23, as shown in FIG. The patterned third photoresist layer 23 shields the surface of the copper foil layer 12 of the first wiring region 121 and the surface of the copper foil layer 12 of the second wiring region 122, and exposes the first etching region 123 and the second etching region 124. And a copper foil layer 12 of the third etched region 125. That is, the patterned third photoresist layer 23 shields the surface of the first protrusion 131, the surface of the second protrusion 132, the surface of the third protrusion 133, and the surface of the fourth protrusion 134, and exposes the fourth The bottom surface of the opening 144, the bottom surface of the fifth opening 145, and the bottom surface of the sixth opening 146.

Again, the copper etch layer 12 of the first etched region 123, the second etched region 124, and the third etched region 125 is exposed through the copper etching solution for a third time, until the first etched region 123, the second etched region 124, and the first etched region The copper foil layer 12 of the triple etched region 125 is completely etched away to expose the base layer 11 corresponding to the first etched region 123, the second etched region 124, and the third etched region 125. In this embodiment, the etching depth of the third etching is also 70 μm.

After the third etching, a fifth protrusion 135 connected under the third protrusion 133 is formed in the first line region 121, and a sixth protrusion 136 connected under the fourth protrusion 134 is formed in the second line region 122. Forming a seventh opening 147 under the fourth opening 144 in the first etched region 123, forming an eighth opening 148 under the fifth opening 145 in the second etched region 124, and forming a communication in the third etched region 125 Below the sixth opening 146 The ninth opening 149 is as shown in FIG. The cross section of the fifth protrusion 135 is approximately trapezoidal, and the cross section of the sixth protrusion 136 is also approximately trapezoidal. The first protrusions 131, the third protrusions 133, and the fifth protrusions 135 are sequentially connected to constitute the first line 15. The second protrusion 132, the fourth protrusion 134, and the sixth protrusion 136 are sequentially connected to constitute the second line 16. The first line 15 and the second line 16 are separated by a space 17 formed by the first opening 141, the fourth opening 144, and the seventh opening 147.

In addition, since the etching is isotropic, the copper foil layer 12 adjacent to the first etching region 123, the second etching region 124, and the third etching region 125 may be less in the first wiring region 121 and the second wiring region 122. The portion is also etched away, so that there may be a spur at the junction of the fifth protrusion 135 and the third protrusion 133, and there may also be a spur at the junction of the sixth protrusion 136 and the fourth protrusion 134.

Finally, referring to FIG. 13, the patterned third photoresist layer 23 is removed. Thus, the circuit board 100 having the base layer 11 and the first line 15 and the second line 16 formed on the surface of the base layer 11 can be obtained.

The first line 15 has a first bottom surface 151 in contact with the base layer 11, a first top surface 152 opposite to the first bottom surface 151, and two first side surfaces 153 connected between the first bottom surface 151 and the first top surface 152. . The width of the first bottom surface 151 is similar to the width of the first top surface 152. Basically, the height of the first bottom surface 151 and the first top surface 152 is greater than or equal to 100 microns, and the difference between the width of the first bottom surface 151 and the width of the first top surface 152 is less than or equal to 50 microns. In other words, the difference between the line width of the first line 15 near the base layer 11 and the line width away from the base layer 11 is less than or equal to 50 microns.

The second line 16 has a second bottom surface 161 and a second bottom surface 161 that are in contact with the base layer 11. The second top surface 162 and the second side surface 163 connected between the second bottom surface 161 and the second top surface 162 are opposite to each other. The width of the second bottom surface 161 is similar to the width of the second top surface 162. Basically, the height of the second bottom surface 161 and the second top surface 162 is greater than or equal to 100 micrometers, and the difference between the width of the second bottom surface 161 and the width of the second top surface 162 is less than or equal to 50 micrometers. In other words, the difference between the line width of the second line 16 near the base layer 11 and the line width away from the base layer 11 is less than or equal to 50 microns. The line width of the entire second line 16 is relatively uniform.

The line width of the entire first line 15 is relatively uniform, and the line width of the entire second line 16 is also relatively uniform, so that the line spacing between the first line 15 and the second line 16 is substantially uniform. Generally, the thickness of the first line 15 and the second line 16 is 100 μm or more, and the line widths of the first line 15 and the second line 16 are both 100 μm or more, and the line distance between the first line 15 and the second line 16 is Also above 100 microns.

In this embodiment, each of the first side surface 153 and each of the second side surfaces 163 has two spurs. Those skilled in the art will appreciate that during the multiple etching to form the first line 15 and the second line 16, a suitable copper etchant can be selected and the etching conditions and etching time can be controlled to avoid the formation of spurs on the sides of the line. Further, even as shown in the present embodiment, the first line 15 and the second line 16 having the spurs on the side are formed, but since the spurs are minute, the transmission performance of the first line 15 and the second line 16 is not caused. influences. If there is a requirement for the shape of the line, the spurs existing on the side of the line can be removed by subsequent grinding and micro-etching.

In the present embodiment, the first circuit 15 and the second line 16 having a thickness of 210 μm are formed by three etching processes as an example to describe a method of fabricating the circuit board. Those skilled in the art can understand that when the thickness of the copper foil layer 12 is other values, that is, the first line 15 and When the thickness of the second line 16 is other values, it can be produced by another number of etching processes. For example, when the thickness of the copper foil layer 12 is from 100 micrometers to 150 micrometers, the first line 15 and the second line 16 may be formed by two etching processes; when the thickness of the copper foil layer 12 is from 150 micrometers to 220 micrometers, The first line 15 and the second line 16 can be formed by three etching processes; when the thickness of the copper foil layer 12 is 220 micrometers to 290 micrometers, the first line 15 and the second line 16 can be formed by four etching processes. When making the circuit, it is only necessary to make the etching depth of the first etching to be 50 micrometers to 75 micrometers. When the thickness of the remaining copper foil layer 12 in the etching region after the first etching is less than or equal to 75 micrometers, the second etching is performed. The copper foil layer 12 of the etched region can be completely removed; when the remaining thickness of the copper foil layer 12 of the etched region after the first etching is greater than 75 micrometers, the second etching removes the copper foil layer 12 of the etched region of 50 micrometers to 75 micrometers. When the thickness of the remaining copper foil layer 12 in the etched area after the second etching is less than or equal to 75 micrometers, the third etching can completely remove the copper foil layer 12 of the etched region; when the second etching is performed, the copper of the etched region When the remaining thickness of the foil layer 12 is greater than 75 microns, a third, fourth or even more etching process is required to completely remove the copper foil layer 12 of the etched region. Of course, the etching depth of the copper foil layer 12 is 50 micrometers to 75 micrometers per etching.

It should be noted that, in this embodiment, only two lines, that is, the first line 15 and the second line 16 are taken as an example to describe a method for manufacturing a circuit board. In fact, when making a circuit board, the number of lines is not limited, and may be one or more, and in general, more than ten.

In the method for fabricating the circuit board 100 of the present technical solution, the circuit is formed by using two or more etching processes, and the isotropic etching and pool effect of the copper etching solution can be reduced compared with the method of fabricating the circuit by using one etching process. The influence of the shape of the line, The shape and size of the circuit can be ensured, so that the circuit of the circuit board 100 has a high yield. The circuit board manufacturing method of the present technical solution can obtain a line having a relatively uniform line width, or a line having a shape closer to a rectangle. Specifically, when the line thickness is 100 μm or more, a line having a line width difference of 50 μm or less across the line can be produced by two or more etching processes. Moreover, since the etching process is very mature and the cost is low, even if the circuit is fabricated by using two or more etching processes, the cost and efficiency of the board manufacturing are not affected.

In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

11‧‧‧ basal layer

12‧‧‧copper layer

22‧‧‧Second photoresist layer

133‧‧‧3rd bulge

134‧‧‧fourth bulge

144‧‧‧fourth opening

145‧‧‧ fifth opening

146‧‧‧ sixth opening

Claims (10)

A circuit board manufacturing method comprising the steps of: providing a circuit substrate, the circuit substrate comprising a copper foil layer, the copper foil layer having a thickness greater than or equal to 100 micrometers, the copper foil layer having a first line region and being close to the first line a second line region of the region and a first etch region between the first line region and the second line region; and removing the copper foil layer of the first etch region by two or more etching processes, thereby removing the first etch region After the copper foil layer, the first line region constitutes the first line, such that the second line region constitutes the second line, the circuit substrate further includes a base layer in contact with the copper foil layer, the first line having the base The first bottom surface of the layer contact, the first top surface opposite to the first bottom surface, the difference between the width of the first bottom surface and the width of the first top surface is less than or equal to 50 micrometers, wherein each etching step comprises the steps of: Forming a patterned photoresist layer on the surface of the copper foil layer to shield the copper foil layer of the first wiring region and the copper foil layer of the second wiring region, and exposing the copper foil layer of the first etching region; etching the first etching region Copper foil layer, etching Of between 50 microns to 75 microns; removing the patterned photoresist layer. The method for fabricating a circuit board according to claim 1, wherein the copper foil layer further has a second etching region and a third etching region, wherein the first wiring region is located in the second etching region and the first etching region. Between the third etched region and the first etched region, the second etched region and the second etched region are removed while removing the copper foil layer of the first etched region by two or more etching processes. A copper foil layer of the triple etched area. The method for fabricating a circuit board according to claim 1, wherein the circuit The substrate further includes a base layer in contact with the copper foil layer, and after removing the copper foil layer of the first etched region, exposing the base layer corresponding to the first etched region. The method for fabricating a circuit board according to claim 1, wherein a photoresist layer is formed on the surface of the copper foil layer by applying a liquid photoresist ink, and the photoresist layer is patterned by an exposure and development process to A patterned photoresist layer is formed on the surface of the copper foil layer. The method of fabricating a circuit board according to claim 4, wherein the patterned photoresist layer is removed by dissolution. The method of fabricating a circuit board according to claim 1, wherein the second line has a second bottom surface in contact with the base layer, a second top surface opposite to the second bottom surface, and a width of the second bottom surface The difference between the widths of the two top faces is less than or equal to 50 microns. The method for fabricating a circuit board according to the first aspect of the invention, wherein the etching of the copper foil layer of the first etching region is performed by using a copper chloride etching solution. The method for fabricating a circuit board according to the first aspect of the invention, wherein, when the thickness of the copper foil layer is from 100 micrometers to 150 micrometers, the copper foil layer of the first etching region is removed by two etching processes. The method for fabricating a circuit board according to claim 1, wherein the copper foil layer of the first etching region is removed by a third etching process when the thickness of the copper foil layer is from 150 micrometers to 220 micrometers. The method for fabricating a circuit board according to the first aspect of the invention, wherein, when the thickness of the copper foil layer is from 220 micrometers to 290 micrometers, the copper foil layer of the first etching region is removed by four etching processes.