JP2009117600A - Method of manufacturing wiring circuit board with bumps - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve the high density of a wiring circuit board through formation of microscopic patterns by preventing the width of circuit patterns from getting thin due to etching during formation of the wiring circuit board with bumps. <P>SOLUTION: One surface laminate sheet 10 having a seed layer 12 is prepared on one surface of an insulating base material 11. A plated resist layer 14 is arranged on the portion of the surface of the seed layer 12 excluding a circuit forming portion 13. A wiring circuit pattern 15 is formed on the surface of the exposed seed layer 12 by plating. An etch resist layer 17 is formed in the planned bump forming portion 16a on this wiring circuit pattern 15. The exposed portion of the wiring circuit pattern is made thinner by etching so that the height of the planned bump forming portion 16a may be a predetermined height. After removing the plated resist layer 14 and etch resist layer 17, the exposed seed layer 12 is removed by etching. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a circuit wiring board with bumps, and more particularly to a method of manufacturing a circuit wiring board in which bumps are provided on terminal portions of a circuit formed by a semi-additive method.

A tape carrier is known as a circuit wiring board in which bumps are provided on terminal portions. For example, a conductor layer is deposited on an insulating film in a thickness including a bump portion, and a resist layer is formed on the portion of the conductor layer where the bump is to be provided, and the remaining exposed conductor layer Is removed by etching until the bumps have a desired height, and then the resist layer is removed to form the desired bumps (see Patent Document 1).
Japanese Utility Model Publication No. 51-161073 (pages 5-6, FIG. 3)

  The tape carrier described in Patent Document 1 has an arbitrary pattern structure on an insulating film, and a conductor layer is deposited to a thickness including a bump portion, and the bump is formed by removing the thickness of the conductor layer by an etching process. A method is disclosed. In this case, as shown in FIG. 8, a conductor layer 51 previously formed in a pattern structure is provided on the insulating film 50 in a thickness including the bump portion, and the resist shown by hatching in the portion where the bump 52 is formed The layer 53 is covered, and the exposed conductor layer 51 is removed by etching until the bumps have a desired height.

  However, actually, as shown in FIG. 9, not only the thickness of the conductor layer 51 is removed by etching, but also the width direction of the conductor layer 51 becomes thin. Considering the amount of correction for narrowing due to etching at the design stage, it may be possible to increase the initial pattern width by the correction amount. However, in the case of a fine circuit pattern, it is already in contact with an adjacent circuit pattern at the design stage. There is a risk. Further, since the conductor layer 51 is thick together with the correction amount for the narrowing, it is difficult to form a fine circuit pattern, and it is difficult to cope with the higher density.

  Accordingly, an object of the present invention is to reduce the width of a circuit pattern by etching when forming a circuit wiring board with bumps, thereby enabling the formation of a fine circuit pattern and increasing the density.

  The present invention has been proposed to achieve the above object, and the invention according to claim 1 provides a single-area layer plate having a seed layer on one surface of an insulating base material, and the surface of the seed layer is provided. A plating resist layer is provided in a portion excluding the circuit forming portion, a circuit wiring pattern is formed on the exposed surface of the seed layer by plating, and an etching resist layer is provided in a portion where the bump is to be formed on the circuit wiring pattern. The exposed part of the circuit wiring pattern is thinned by etching so that the part to be formed has a predetermined height, and after removing the plating resist layer and the etching resist layer, the exposed seed layer is removed by etching. A method for manufacturing a circuit board with bumps is provided.

  According to this configuration, the plating resist layer is provided on a portion of the seed layer of the seed layer excluding the circuit forming portion, and the circuit wiring pattern is formed by plating. The plating thickness of this circuit wiring pattern is set to a thickness including the height of the bump to be formed. Thereafter, an etching resist layer is provided on the bump formation scheduled portion, and the other circuit wiring pattern portions are thinned by etching until a bump having a predetermined height is formed.

  At this time, the surface of the circuit wiring pattern portion is removed by etching, and the side surface (peripheral portion) of the circuit wiring pattern portion is surrounded by the plating resist layer, so that it is not removed by etching. Furthermore, if the exposed seed layer is removed by etching after removing the plating resist layer and the etching resist layer, the circuit wiring pattern is electrically independent and a bumped circuit wiring board is formed.

  According to a second aspect of the present invention, there is provided the method for manufacturing a circuit board with bumps according to the first aspect, wherein the etching resist layer is formed by ink jet means.

  According to this configuration, the liquid resist ink is ejected from the nozzle, and the etching resist layer is provided on the bump formation scheduled portion. Since the etching resist layer is formed by the ink jet means, a series of steps including application or lamination of the etching resist, exposure using a photomask, and development are not required.

  According to the first aspect of the present invention, when bumps are provided on a terminal portion of a circuit formed by a semi-additive method, only the surface of the circuit wiring pattern portion other than the bumps is etched and thinned, and the side surface of the circuit wiring pattern portion ( The peripheral edge is not removed by etching. Therefore, it is possible to prevent the circuit pattern from being narrowed by etching, and it is not necessary to increase the initial pattern width by the correction amount in consideration of the correction amount of the narrowing by etching, and it is possible to form a fine circuit pattern. High density can be achieved.

  According to the second aspect of the present invention, since the etching resist layer is formed by ink jet means, a series of processes including coating or laminating of the etching resist, exposure using a photomask, and development are not required, and the man-hour is reduced and the cost is reduced. Can contribute to down.

  Hereinafter, a method for manufacturing a circuit board with bumps according to the present invention will be described with reference to preferred embodiments. In forming a circuit wiring board with bumps, in order to achieve the object of achieving a high density by forming a fine circuit pattern by eliminating the narrowing of the circuit pattern by etching, the present invention provides an insulating base material. A single-area layer plate having a seed layer on one side of the substrate is prepared, a plating resist layer is provided on the surface of the seed layer except for a circuit forming portion, and a circuit wiring pattern is formed by plating on the exposed surface of the seed layer. Forming an etching resist layer on a portion where a bump is to be formed on the circuit wiring pattern, and thinning the exposed portion of the circuit wiring pattern by an etching process so that the portion where the bump is to be formed has a predetermined height. After removing the plating resist layer and the etching resist layer, the exposed seed layer is removed by an etching process. Represent it was.

  FIGS. 1-7 is explanatory drawing which shows the manufacturing process of the circuit wiring board with a bump | vamp concerning this invention, each figure (a) is a perspective view, (b) is XX sectional drawing of (a).

  FIG. 1 shows a single-area layer board 10 that is a material for a circuit wiring board. The single-area layer board 10 is a thin-film metal layer that is a power supply layer for forming a circuit wiring pattern on one surface of an insulating base material 11 so-called seed. It has a layer 12.

  The seed layer 12 is a base layer for suppressing adhesion and migration with the insulating base material 11, and a so-called anchor layer is formed by a thin film formation method such as a sputtering method or a vapor deposition method, and subsequently a copper layer that becomes a conductive layer. The layer is formed by the same thin film forming method or plating method. Alternatively, the copper layer of the widely used non-adhesive copper-clad laminate may be thinned by etching and used as a seed layer. Further, the seed layer is not limited to these methods and forms, and various seed layers that can be employed by the semi-additive method can be used.

  Next, as shown in FIG. 2, a plating resist layer 14 is provided on the surface of the seed layer 12 except for the circuit forming portion 13. The plating resist layer 14 is formed by a series of methods including application or lamination of a plating resist, exposure using a photomask, and development.

  Subsequently, as shown in FIG. 3, the surface of the seed layer 12 exposed as the circuit forming portion 13 is subjected to electrolytic copper plating using the seed layer 12 as a power feeding layer to form a circuit wiring pattern 15. The plating thickness of the circuit wiring pattern 15 is set to a thickness including the height of the bump to be formed.

  Next, as shown in FIG. 4, an etching resist layer 17 is provided on the bump formation scheduled portion 16 a on the circuit wiring pattern 15. In the present invention, the etching resist layer 17 is formed by ink jet means. That is, liquid resist ink is ejected from the nozzle, the resist ink is partially applied to the bump formation scheduled portion 16a, and curing (curing) is performed by ultraviolet rays or heat. Since the etching resist layer 17 is formed by the ink jet means, a series of steps including the application or lamination of the etching resist, exposure using a photomask, and development are not required, and man-hours can be reduced, contributing to cost reduction.

  Subsequently, as shown in FIG. 5, the exposed circuit wiring pattern 15 portion where the etching resist layer 17 is not formed is etched and thinned until a bump 16 having a predetermined height is formed. At this time, the surface of the circuit wiring pattern 15 is etched away by a thickness corresponding to the height of the predetermined bump 16, but the side surface (periphery) of the circuit wiring pattern 15 is surrounded by the plating resist layer 14. Therefore, it is not removed by etching. Therefore, it is possible to prevent the circuit pattern from being narrowed by etching.

  Next, as shown in FIG. 6, when the plating resist layer 14 and the etching resist layer 17 are removed, the seed layer 12 is exposed.

  Furthermore, as shown in FIG. 7, if the exposed portion of the seed layer 12 that has become unnecessary is removed by etching, the surface of the insulating base material 11 is exposed, and the circuit wiring pattern 15 and the bump 16 are electrically connected. Independently, the bumped circuit wiring board 20 is formed.

  As described above, when bumps are provided on the terminal portions of the circuit formed by the semi-additive method, only the surface of the circuit wiring pattern portion 15 other than the bumps 16 is etched and thinned, and the side surfaces (periphery edges) of the circuit wiring pattern portion 15 are thinned. Part) is not removed by etching, so that it is possible to prevent the circuit pattern from being thinned by etching, and it is not necessary to increase the initial pattern width by the correction amount in consideration of the thinning correction amount. It can be formed and the density can be increased.

  It should be noted that the present invention can be variously modified without departing from the spirit of the present invention, and the present invention naturally extends to the modified ones.

Explanatory drawing which shows the manufacturing process of the circuit wiring board with a bump which concerns on this invention. Explanatory drawing which shows the manufacturing process of the circuit wiring board with a bump which concerns on this invention. Explanatory drawing which shows the manufacturing process of the circuit wiring board with a bump which concerns on this invention. Explanatory drawing which shows the manufacturing process of the circuit wiring board with a bump which concerns on this invention. Explanatory drawing which shows the manufacturing process of the circuit wiring board with a bump which concerns on this invention. Explanatory drawing which shows the manufacturing process of the circuit wiring board with a bump which concerns on this invention. Explanatory drawing which shows the manufacturing process of the circuit wiring board with a bump which concerns on this invention. Explanatory drawing which shows the conventional manufacturing process. Explanatory drawing which shows the conventional manufacturing process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Single area layer board 11 Insulation base material 12 Seed layer 13 Circuit formation part 14 Plating resist layer 15 Circuit wiring pattern 16 Bump 16a Bump formation planned part 17 Etching resist layer 20 Circuit wiring board with bump

Claims (2)

  A single-area layer plate having a seed layer on one surface of the insulating base material is prepared, a plating resist layer is provided on the surface of the seed layer except for the circuit forming portion, and the exposed seed layer surface is subjected to a plating process. A wiring pattern is formed, an etching resist layer is provided on the bump formation planned portion on the circuit wiring pattern, and the exposed portion of the circuit wiring pattern is thinned by an etching process so that the bump formation planned portion has a predetermined height. Then, after removing the plating resist layer and the etching resist layer, the exposed seed layer is removed by an etching process.   2. The method for manufacturing a circuit board with bumps according to claim 1, wherein the etching resist layer is formed by ink jet means.

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