201218878 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及電路板領域，尤其涉及一種電路板文字漏印 之檢測方法。 【先前技冬舒】 [0002] 印刷電路板因具有裝配密度高等優點而得到了廣泛應用 。關於高密度互連電路板之應用請參見文獻Takahashi， A. Ooki, N. Nagai, A. Akahoshi, H. Mukoh, A. Wa j ima, M. Res. Lab, High density multi layer printed circuit board for HITAC M-880 ’ IEEE Trans, on Components, Packaging, and Manufacturing Technology， "1992， 15(4):. 418-425。 [0003] 於電路板外層導電線路製作完成後，需要於外層導電線 路之防焊層之一些位置印刷文字，以對電路板之中之線 路及電子元件進行識別。而於電路板製作過程中，由於 操作失誤等原因可能造成電路板表面之文字漏印。這樣 ，給後續電路板之使用造成不便。 【發明内容】 [0004] 有鑑於此，提供一種能夠檢測電路板表面漏印文字之電 路板文字漏印之檢測方法實屬必要。 [0005] 以下將以實施例說明一種電路板文字漏印之檢測方法。 [0006] 一種電路板文字漏印之檢測方法，包括步驟：提供待檢 測之電路板，所述電路板包括依次設置之導電層、防焊 層，所述導電層包括第一測試墊、第二測試墊及連通於 099136284 表單編號A0101 第4頁/共19頁 0992063441-0 201218878 第測試整和第二測試堅之間之連接線，所述防谭層内 具有與第-測試墊相對應之第—通孔和與第二測試勢相 對應之第二通孔’所述第-測試塾至少部分從所述第〜 通孔露出，所述第二測試塾至少部分從所述第二通孔露 出；提供《裝置，所料料置包括電職、第^ 試探針和第二測試探針，所述電測機用於制第一_ 探針檢測之區域和第二輯探針檢測之區域之間之電氣 導通情況；採用電測裝置對第1試墊對應之區域和$ 二測試塾對應之區域進行檢測，當電測裝置檢測第1 試墊對應之區域和第二測試塾對應之區域之間為斷路時 ’判定第—測試墊上形成有與文字同時形成之絕緣之第 一遮蔽圖祕述第二職塾上形成有與文字同時形成之 絕緣之第二遮蔽圖形’所述防焊層表面未漏印文字，當 電測裳置檢測第—測試墊對應之區域和第二測試墊對: ^區域之_短路時，判定第—測試塾上未形成有^ 字同時形成之第-遮蔽圖形，所述第二測試堅上未形成 有與文字同時形成H蔽圖形，所述防焊層表 印文字。 - 闺前技術，本⑽方錢供之電純文字漏印之 檢測方法，通過電測I置檢測電路板上預先設定之相互 連接之第-測試蟄和第二測試塾對應區域之電導通情況 從而判定第-測試塾和第二測試整上是否形成有遮蔽 圖形，從而判定電路板是否漏印文字。從而，本技術方 案提供之電路板文字漏印之檢測方法能夠快速並準確之 判定電路板是否漏印文字。 099136284 表單編號A0101 第5頁/共19頁 0992063441-0 201218878 [0008] [0009] [0010] 【實施方式】 下面、'° 5附圖及實施例對本技術方案提供之電路板文字 漏印之檢測方法作進一步說明。 本技術方案實施例提供之—種電路板文字漏印之檢測方 法’包括如下步驟： 第^ ^併參閱圖1及圖2，提供待檢測之電路板1 〇 〇 [0011] 電路板100可以為形成有外層線路之單層電路板，雙層電 路板或者多層電路板。本實施例中，以單層電路板為例 來進行說明。按照預定設計，電路板1〇()包括導電層u〇 、絕緣層120、防焊層130及文字層14〇。當電路板1〇〇為 多層電路板時’導電層11()可以為多層電路板之外層線路 田電路板100為雙層電路板時，導電層可以為雙層 電路板之任意一側導電線路。於進行實際電路板生成過 程中，容易造成由於操作誤差夢:造成文字層u〇漏印。因 此，待檢測之電路板1〇〇可〕能包括包括文字層 能不包括有文字層140。 140，也可201218878 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to the field of circuit boards, and in particular, to a method for detecting missed printing of circuit boards. [Formerly Dongshushu] [0002] Printed circuit boards have been widely used due to their high assembly density. For applications on high-density interconnect boards, see the literature Takahashi, A. Ooki, N. Nagai, A. Akahoshi, H. Mukoh, A. Wa j ima, M. Res. Lab, High density multi layer printed circuit board for HITAC M-880 'IEEE Trans, on Components, Packaging, and Manufacturing Technology, "1992, 15(4):. 418-425. [0003] After the conductive circuit on the outer layer of the circuit board is completed, it is necessary to print characters at some positions of the solder resist layer of the outer conductive line to identify the lines and electronic components in the circuit board. In the process of manufacturing the circuit board, the text on the surface of the circuit board may be missed due to operational errors and the like. This inconveniences the use of subsequent boards. SUMMARY OF THE INVENTION [0004] In view of the above, it is necessary to provide a method for detecting a printed circuit board miss print on a surface of a circuit board. [0005] Hereinafter, a method for detecting a board miss print will be described by way of an embodiment. [0006] A method for detecting leakage of a printed circuit board, comprising the steps of: providing a circuit board to be inspected, the circuit board comprising a conductive layer and a solder resist layer disposed in sequence, wherein the conductive layer comprises a first test pad and a second Test pad and connected to 099136284 Form No. A0101 Page 4 / 19 pages 0992063441-0 201218878 The connection between the test and the second test, the anti-tank layer has the corresponding to the first test pad a through hole and a second through hole corresponding to the second test potential, wherein the first test pad is at least partially exposed from the first through hole, and the second test port is at least partially exposed from the second through hole Providing a device, the material to be included includes an electric power, a test probe, and a second test probe, the electric test machine being used for the first _ probe detection area and the second series probe detection area The electrical conduction between the two places; the area corresponding to the first test pad and the area corresponding to the second test 进行 are detected by the electric measuring device, and the area corresponding to the first test pad and the area corresponding to the second test 当 are detected by the electric measuring device. 'determining the first test when the circuit is broken Forming a first masking pattern with insulation formed at the same time as the text. The second mask is formed with a second masking pattern formed at the same time as the text. The surface of the solder resist layer is not missing printed characters. The detection area corresponding to the first test pad and the second test pad pair: ^ When the area is short-circuited, it is determined that the first-masking pattern formed by the simultaneous formation of the word is not formed on the first test, and the second test is not An H-mask pattern is formed simultaneously with the text, and the solder resist layer is printed on the surface. - Pre-existing technology, this (10) square money supply for the detection of pure text miss printing, through the electrical test I to detect the pre-set interconnection of the first-test 蛰 and the second test 塾 corresponding area of electrical conduction Therefore, it is determined whether or not the mask pattern is formed on the first test cymbal and the second test, thereby determining whether the circuit board is missing printed characters. Therefore, the detection method of the board blank printing provided by the technical solution can quickly and accurately determine whether the board is missing text. 099136284 Form No. A0101 Page 5 / 19 pages 0992063441-0 201218878 [0008] [Embodiment] The following is a description of the printed circuit board text leakage provided by the present technical solution. The method is further explained. The method for detecting a printed circuit board miss print provided by the embodiment of the present technical solution includes the following steps: First, and referring to FIG. 1 and FIG. 2, providing a circuit board 1 to be detected [0011] The circuit board 100 may be A single-layer circuit board having an outer layer circuit, a two-layer circuit board or a multilayer circuit board. In the present embodiment, a single layer circuit board will be described as an example. According to a predetermined design, the circuit board 1A includes a conductive layer u, an insulating layer 120, a solder resist layer 130, and a text layer 14A. When the circuit board 1 is a multi-layer circuit board, the conductive layer 11 can be a multi-layer circuit board. When the circuit board 100 is a two-layer circuit board, the conductive layer can be a conductive circuit on either side of the double-layer circuit board. . During the actual board generation process, it is easy to cause a dream due to operational error: causing the text layer to leak. Therefore, the circuit board to be inspected can include a text layer that does not include the text layer 140. 140, also available
IJIJ
[0012] 099136284 β月參閱圖3，導電層110包括相互分離之線路圖形和測 試圖形112。本實施例中，測試圖形112包括第一測試墊 1121、第二測試墊1122及連接於第一測試墊和第二 測試塾1122之間之連接線1123。第一測試墊112ι和第二 測試墊1122均為圓形，第一測試墊U21和第二測試墊 1122之直徑均約為1毫米，即4〇密耳（raii，千分之一英 寸）。連接線112 3之寬度約為1 〇 m丨^。線路圖形} 1丨及測 試圖形11 2可以同時通過影像轉移工藝—蝕刻工藝。即將 0992063441-0 表單編號A0101 第6頁/共19頁 201218878 用於形成導電層之銅箔層除形成線路圖形丨丨丨及測試圖形 112其他區域之銅箔蝕刻去除。線路圖形lu包括多根導 電線路1111。測試圖形112與線路圖形U1相互分離，即 測试圖形112不與線路圖形111相互連接。 [0013] ❹ [0014] 第一測試墊1121和第二測試墊1122之形狀不限於本實施 例中提供之圓形，其也可以製作為橢圓形、多邊形或者 其他不規則形狀。第一測試墊1121和第二測試墊1122之 大小及連接線1123之寬度也不限於本實施中提供之尺寸 ’只要其大小能夠用於電檢測裝置測試即可。 防知層13 0形成於線路圖形1.11和測..試圖.形2上，防焊 層130内具有與第一測試墊1121對應第一通孔131、與第 一測試墊1122對應之第二通孔132以及與線路圖形111中 需要與外界相連通之區域相對應第三通孔（圖未示）。 ❹ 第一通孔131之中心與第一測試墊1121之中心相對應，第 一通孔131之孔徑大於第一測試墊112,1之直徑，第二通孔 132之中心與第二測試墊1122之中心相對應，第二通孔 132之孔徑大於第二測試塾1122之直徑。本實施例中，第 一通孔131和第二通孔132均為圓形孔，且孔徑均約為 45mil，從而使得第一測試墊1121和第二測試墊1122均 從防焊層130暴露出。 [0015] 第一通孔131和第二通孔132之形狀不限於本實施例中提 供之圓形孔。第一通孔131之形狀與第一測試塾1121之形 狀相對應即可，第二通孔132之形狀與第二測試墊1122之 形狀相對應。第一通孔131之開口大小也可以等於或者略 小於第一測試墊1121之大小，第二通孔132之開口大小也 099136284 表單編號A0101 第7頁/共19頁 0992063441-0 201218878 可以等於或者略小於第二測試墊丨1 2 2之大小。 [0016] [0017] [0018] 本實施例中，防焊層13〇可採用如下方式形成。首先，於 導電層11 0，即線路圖形Π丨、測試圖形丨丨2及線路圖形 111和測試圖形112—侧露出之絕緣層12〇之表面均形成 防焊油墨層。防焊油墨層可以通過喷塗或者印刷之方式 形成，防焊油墨層覆蓋線路圖形1 1丨之表面、測試圖形 11 2之表面及線路圖形11丨和測試圖形丨丨2 一側露出之絕 緣層120之表面。防焊油墨層採用顯影式油墨制程。其次 ，對喷塗或者印刷後之防焊油墨層進行曝光顯影，從而 使得與第一通孔131、笫二邊札13 2和第三通孔對應之區 域從防焊油墨去除，從而形成有第一通孔丨3丨、第二通孔 132及第三通孔之防焊層130。 文字層140通過印刷絕緣之油墨形成。設定之文字層14〇 包括开>成於防谭層130上之文字圖形141、形成於第一測 試墊1121上之第一遮蔽圖形142及形成於第二測試墊 1122上之第二遮蔽圖形143。 文子圖开>141用於標示線路圖形η 1,各不同區域，以方便 電路板之應用。第一遮蔽圖形142遮蔽從防焊層130露出 之第一測試塾11 21，第一遮蔽圖形14 2與第一測試塾 1121同軸設置》第二遮蔽圖形143遮蔽從防焊層13〇露出 之第二測試墊1122。第二遮蔽圖形143與第二測試墊 11 22同軸設置。本實施例中，第一遮蔽圖形142和第二遮 蔽圖形143均為圓形，且第一遮蔽圖形142和第二遮蔽圖 形143凸出於防焊層130表面部分之直徑均為4gmii。 099136284 表單編號A0101 第8頁/共19頁 0992063441-0 201218878 [0019] 第二步，請參見圖4，提供電測裝置20。 [0020] 電測裝置20包括電測機21、第一測試探針22和第二测試 探針23。第一測試探針22和第二測試探針23與電測機21 電連接。電測機21檢測第一測試探針22檢測之區域和第 二測試探針23檢測之區域之間之電氣導通情況。 [0021] 第三步，採用電測裝置20對第一測試墊1121對應之區域 和第二測試塾112 2對應之區域進行電學檢測，從而判定 電路板10 0是否漏印文字層140。 [0022] 請參閲圖4，由於文字圖形141與第一遮蔽圖形142和第二 遮蔽圖形143同時形成。因此，當形成有第一遮蔽圖形 142和第一遮蔽圖形143時，可以判定也同a^.於防焊層 13 0上形成文字圖形141。當第一測試墊η 2 i上形成有第 一遮蔽圖形142，第二測試墊1122上形成有第二遮蔽圖形 143時，由於第一遮蔽圖形142和第二遮蔽圖形143採用 絕緣材料製成，進行測試之電測裝亶20:乏:第一測試探針 22與第一遮蔽圖形142相接觸，第二測試探針23和第二遮 蔽圖形143接觸，則第一測試墊1121對應之區域和第二測 試墊1122對應之區域不相互導通，即第一測試墊1121對 應之區域與第二測試墊1122對應之區域之間為短路，此 時表明沒有漏印文字圖形141。即當電測裝置2 〇檢測第一 測試塾11 21對應之區域和第二測試墊丨丨22對應之區域之 結果為短路時，表明電路板1〇〇表面沒有漏印文字。 [0023] 請參閱圖5 ’當第一測試墊1121上沒有形成第一遮蔽圖形 142 ’第二測試墊1122上沒有形成第二遮蔽圖形143上， 099136284 表單編號A0101 第9頁/共19頁 0992063441-0 201218878 由於第一測試墊11 21和第二測試墊11 22均採用銅製成， 其第一測試墊1121和第二測試墊112 2之間通過連接線 1123相互導通。於進行測試時，電測裝置20之第一測試 探針22直接與第一測試墊1121，第二測試探針23直接與 第二測試墊11 22接觸，從而電測裝置20檢測之結果為第 一測試墊11 21對應之區域和第二測試墊11 22對應之區域 相互電氣連通，即第一測試墊1121對應區域和第二測試 墊11 22對應之區域之間為短路，此時表明防焊層130表面 漏印文字圖形141。 [0024] 本技術方案提供之電路板文字漏印之檢測方法，通過電 測裝置檢測電路板上預先設定之相互連接之第一測試墊 和第二測試墊對應區域之電導通情況，從而判定第一測 試墊和第二測試墊上是否形成有絕緣之遮蔽圖形，進而 判定電路板是否漏印文字。從而，本技術方案提供之電 路板文字漏印之檢測方法能夠快速並準確之判定電路板 是否漏印文字。 [0025] 惟，以上所述者僅為本發明之較佳實施方式，自不能以 此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士 援依本發明之精神所作之等效修飾或變化，皆應涵蓋於 以下申請專利範圍内。 【圖式簡單說明】 [0026] 圖1是本技術方案實施例提供之電路板之示意圖。 [0027] 圖2是圖1沿I I - II線之剖面示意圖。 [0028] 圖3是本技術方案實施例提供之導電層之示意圖。 099136284 表單編號A0101 第10頁/共19頁 0992063441-0 201218878 [0029] 圖4是本技術方案實施例提供之形成有文字層之電路板進 行檢測之示意圖。 [0030] 圖5是本技術方案實施例提供之未形成有文字層之電路板 進行檢測之示意圖。 【主要元件符號說明】 [0031] 電路板：100 [0032] 導電層：110 [0033] 線路圖形：111[0012] 099136284 β month Referring to FIG. 3, the conductive layer 110 includes line patterns and test patterns 112 that are separated from each other. In this embodiment, the test pattern 112 includes a first test pad 1121, a second test pad 1122, and a connecting line 1123 connected between the first test pad and the second test pad 1122. The first test pad 112i and the second test pad 1122 are both circular, and the first test pad U21 and the second test pad 1122 each have a diameter of about 1 mm, that is, 4 mils (a thousandth of an inch). The width of the connecting line 112 3 is about 1 〇 m丨^. Line pattern} 1 丨 and test The attempt 11 2 can pass the image transfer process-etching process at the same time. Coming soon 0992063441-0 Form No. A0101 Page 6 of 19 201218878 The copper foil layer used to form the conductive layer is formed by etching the copper foil in other areas except for the formation of the wiring pattern and the test pattern. The line pattern lu includes a plurality of conductive lines 1111. The test pattern 112 is separated from the line pattern U1, i.e., the test pattern 112 is not connected to the line pattern 111. [0013] The shape of the first test pad 1121 and the second test pad 1122 is not limited to the circular shape provided in the embodiment, and may be formed into an elliptical shape, a polygonal shape, or other irregular shape. The size of the first test pad 1121 and the second test pad 1122 and the width of the connecting line 1123 are also not limited to the size provided in the present embodiment as long as the size can be used for the electrical detecting device test. The anti-knowledge layer 130 is formed on the line pattern 1.11 and the test pattern 2, and the solder resist layer 130 has a first through hole 131 corresponding to the first test pad 1121 and a second pass corresponding to the first test pad 1122. The hole 132 and the area of the line pattern 111 that needs to communicate with the outside correspond to a third through hole (not shown). The center of the first through hole 131 corresponds to the center of the first test pad 1121. The diameter of the first through hole 131 is larger than the diameter of the first test pad 112, 1, the center of the second through hole 132, and the second test pad 1122. Corresponding to the center, the aperture of the second through hole 132 is larger than the diameter of the second test port 1122. In this embodiment, the first through hole 131 and the second through hole 132 are both circular holes, and the apertures are both about 45 mils, so that the first test pad 1121 and the second test pad 1122 are exposed from the solder resist layer 130. . The shape of the first through hole 131 and the second through hole 132 is not limited to the circular hole provided in the embodiment. The shape of the first through hole 131 corresponds to the shape of the first test piece 1121, and the shape of the second through hole 132 corresponds to the shape of the second test pad 1122. The opening size of the first through hole 131 may also be equal to or slightly smaller than the size of the first test pad 1121, and the opening size of the second through hole 132 is also 099136284. Form number A0101 Page 7 / 19 pages 0992063441-0 201218878 may be equal to or slightly It is smaller than the size of the second test pad 丨1 2 2 . [0018] In the present embodiment, the solder resist layer 13 can be formed in the following manner. First, a solder resist ink layer is formed on the surface of the conductive layer 110, i.e., the wiring pattern Π丨, the test pattern 丨丨2, and the wiring pattern 111 and the test pattern 112-side exposed insulating layer 12A. The solder resist ink layer may be formed by spraying or printing, and the solder resist ink layer covers the surface of the circuit pattern 1 1 , the surface of the test pattern 11 2 and the wiring pattern 11 丨 and the insulating layer exposed on the side of the test pattern 丨丨 2 The surface of 120. The solder resist ink layer is developed using a developing ink process. Next, the solder resist ink layer after the spraying or printing is exposed and developed, so that the area corresponding to the first through hole 131, the two sides of the second side 13 2 and the third through hole is removed from the solder resist ink, thereby forming the first A solder mask layer 130 of a via hole 3, a second via hole 132 and a third via hole. The text layer 140 is formed by printing an insulating ink. The set text layer 14 includes a text pattern 141 formed on the anti-tank layer 130, a first mask pattern 142 formed on the first test pad 1121, and a second mask pattern formed on the second test pad 1122. 143. The text picture opening > 141 is used to indicate the line pattern η 1, different areas to facilitate the application of the circuit board. The first masking pattern 142 shields the first test layer 11 21 exposed from the solder resist layer 130. The first mask pattern 14 2 is disposed coaxially with the first test layer 1121. The second mask pattern 143 shields the first exposed pattern 143 from the solder resist layer 13 Two test pads 1122. The second masking pattern 143 is disposed coaxially with the second test pad 11 22 . In this embodiment, the first shielding pattern 142 and the second masking pattern 143 are both circular, and the first shielding pattern 142 and the second shielding pattern 143 protrude from the surface portion of the solder resist layer 130 by a diameter of 4 gmii. 099136284 Form No. A0101 Page 8 of 19 0992063441-0 201218878 [0019] In the second step, referring to FIG. 4, an electrical measuring device 20 is provided. [0020] The electrical measuring device 20 includes an electrical tester 21, a first test probe 22, and a second test probe 23. The first test probe 22 and the second test probe 23 are electrically connected to the electrical test machine 21. The electric measuring machine 21 detects the electrical conduction between the area detected by the first test probe 22 and the area detected by the second test probe 23. [0021] In the third step, the area corresponding to the first test pad 1121 and the area corresponding to the second test set 112 2 are electrically detected by the electrical measuring device 20, thereby determining whether the circuit board 110 is missing the text layer 140. Referring to FIG. 4, the character pattern 141 is formed simultaneously with the first mask pattern 142 and the second mask pattern 143. Therefore, when the first mask pattern 142 and the first mask pattern 143 are formed, it can be determined that the character pattern 141 is also formed on the solder resist layer 130. When the first masking pattern 142 is formed on the first test pad η 2 i and the second masking pattern 143 is formed on the second test pad 1122, since the first masking pattern 142 and the second masking pattern 143 are made of an insulating material, The electrical test device 20 is tested: the first test probe 22 is in contact with the first shielding pattern 142, and the second test probe 23 is in contact with the second shielding pattern 143, and the first test pad 1121 corresponds to the area and The areas corresponding to the second test pads 1122 are not electrically connected to each other, that is, the area corresponding to the area corresponding to the first test pad 1121 and the area corresponding to the second test pad 1122 is short-circuited, indicating that there is no missing letter graphic 141. That is, when the electric detecting device 2 〇 detects that the region corresponding to the first test port 11 21 and the region corresponding to the second test pad 22 is short-circuited, it indicates that there is no missing text on the surface of the board 1 . [0023] Please refer to FIG. 5 'When the first masking pattern 142 is not formed on the first test pad 1121', the second masking pattern 143 is not formed on the second test pad 1122, 099136284 Form No. A0101 Page 9/19 pages 0992063441 -0 201218878 Since the first test pad 11 21 and the second test pad 11 22 are both made of copper, the first test pad 1121 and the second test pad 112 2 are electrically connected to each other through a connecting wire 1123. When the test is performed, the first test probe 22 of the electrical measuring device 20 directly contacts the first test pad 1121, and the second test probe 23 directly contacts the second test pad 11 22, so that the result of the electrical test device 20 is the first A region corresponding to the test pad 11 21 and a corresponding region of the second test pad 11 22 are in electrical communication with each other, that is, a short circuit between the corresponding region of the first test pad 1121 and the corresponding region of the second test pad 11 22, indicating that the solder resist is The character graphic 141 is missing on the surface of the layer 130. [0024] The method for detecting the printing of the printed circuit board of the present invention provides the method for detecting the electrical continuity of the corresponding first test pad and the corresponding area of the second test pad which are preset between the circuit board by the electrical measuring device, thereby determining the first Whether a shielding pattern of insulation is formed on a test pad and a second test pad, thereby determining whether the circuit board is missing printed characters. Therefore, the detection method of the circuit board text leakage provided by the technical solution can quickly and accurately determine whether the circuit board is missing printed characters. [0025] However, the above description is only a preferred embodiment of the present invention, and the scope of the patent application of the present invention cannot be limited thereby. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0026] FIG. 1 is a schematic diagram of a circuit board provided by an embodiment of the present technical solution. 2 is a cross-sectional view of FIG. 1 taken along line I I - II. 3 is a schematic diagram of a conductive layer provided by an embodiment of the present technical solution. 099136284 Form No. A0101 Page 10 of 19 0992063441-0 201218878 [0029] FIG. 4 is a schematic diagram of a circuit board formed with a text layer according to an embodiment of the present invention. 5 is a schematic diagram of detecting a circuit board without a text layer provided by an embodiment of the present technical solution. [Main component symbol description] [0031] Circuit board: 100 [0032] Conductive layer: 110 [0033] Line pattern: 111
[0034] 導電線路：1111 [0035] 測試圖形：112 [0036] 第一測試墊：11 21 [0037] 第二測試墊：1122 [0038] 連接線：1123 [0039] 絕緣層：120 [0040] 防焊層：130 [0041] 第一通孔：131 [0042] 第二通孔：132 [0043] 文字層：140 [0044] 文字圖形：141 [0045] 第一遮蔽圖形：142 099136284 表單編號A0101 第11頁/共19頁 0992063441-0 201218878 [0046] 第二遮蔽圖形：143 [0047] 電測裝置：2 0 [0048] 電測機：21 [0049] 第一測試探針：22 [0050] 第二測試探針：23 0992063441-0 099136284 表單編號A0101 第12頁/共19頁[0034] Conductive line: 1111 [0035] Test pattern: 112 [0036] First test pad: 11 21 [0037] Second test pad: 1122 [0038] Connecting wire: 1123 [0039] Insulation: 120 [0040] Solder mask: 130 [0041] First via: 131 [0042] Second via: 132 [0043] Text layer: 140 [0044] Text graphics: 141 [0045] First masking pattern: 142 099136284 Form number A0101 Page 11/19 pages 0992063441-0 201218878 [0046] Second masking pattern: 143 [0047] Electrical measuring device: 2 0 [0048] Electrical measuring machine: 21 [0049] First test probe: 22 [0050] Second test probe: 23 0992063441-0 099136284 Form number A0101 Page 12 of 19