201218377 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種金氧半場效電晶體（111以&1-〇?^(^-semiconductor field effect transistor ;簡稱 MOSFET)，特別 是指一種增強型（enhancement mode)氣化鎵系（GaN-based)金 氧半場效電晶體。 【先前技術】 基於GaN系MOSFET具有寬能隙（wide bandgap)、高 崩潰電壓、高飽和速度（saturation velocity)以及良好的熱傳 導性（thermal conductivity)等特性；因此，高功率（high-power)且 快速的 GaN 系 MOSFET已漸漸地受到關注。也因 為前述幾種特性，MOSFET中的汲極電壓引發通道位能障 降低效應（drain-induced barrier lowering)與帶對帶穿遂 (band-to-band tunneling)等問題是可以被降低的。 參閱圖 1 ，發明人於 IEEE ELECTRON DEVICE LETTERS，VOL. 31 NO. 6, JUNE 2010, PP 558〜560 中，揭示 出一種p-GaN系MOS電容器1及其製作方法。該p-GaN系 MOS電容器1，包含：一摻雜有Mg摻質之p-GaN基板 11、 一局部地形成於該p-GaN基板11上的閘極介電疊層 12、 一形成於該閘極介電疊層12上且是由Ni所構成的上 電極13, 一形成於該未形成有該閘極介電疊層12之p-GaN 基板11上並由Ni/Au所構成的歐姆電極14。 該閘極介電疊層12是由雙靶材射頻濺鍍系統（dualtarget r.f. sputtering system) 所製成 ，並具有一局部地 形成於 201218377 該p-GaN基板11上且厚度約1.8 nm的第一 MgO層121、 一形成於該第一 MgO層121上且厚度約6 4 nm的Ti〇2層 122，及一形成於該Ti02層122上且厚度約18 nm的第二 MgO 層 123。 參圖2所顯示之電流密度（J)對電壓（v)曲線圖可知，該 p-GaN系M0S電容器1於+ 1 V與-1 V下所取得的漏電流 (current leakage)密度分別約為 3·9χ1〇-8 A/cm2 與 3.7xl(T8 A/cm2。 另，參圖3所顯示之電容值（〇對電壓（v)曲線圖可知， 該p-GaN系MOS電容器1於1〇〇 mHz及-5 V的分析條 下’其電容值（capacitance)約為 1.58 pF/cm2。 該p-GaN系MOS電容器1 一方面是利用該閘極介電疊 層12之Τι〇2層122所賦予的高介電常數（dielectric constant，k值），來^昇其整體的驅動電流（drive current)及 電容值（capacitance，C)。然而，一般具有高让值之氧化物 的能隙大小卻不足以防止來自於該上電極13的熱離子放射 (thermionic emission)。因此，該 p-GaN 系 MOS 電容器 1 另 一方面則是利用該閘極介電疊層12之Mg〇層123具有高 能隙的特性來降低熱離子放射所造成的局部漏電流問題。 經上述說明可知，雖然該p_GaN系MOS電容器1之閘 極介電疊層12的膜層設計可改善漏電流等問題；然而，近 一步地降低漏電流並提昇電容值以獲得優異的元件性能， 則疋此技術領域者所需突破的課題。 【發明内容】 201218377 因此，本發明之目的’即在提供—種增強型氛化錄系 金氧半場效電晶體。 於是，本發明之增強型氮化鎵系金氧半場效電晶體， 包含：一六方晶系結構（hexagonal system巧如价⑽㈣ 之基板、-配置於該基板上且其内部含有第一導電型之播 質的第一 GaN層 '一對相間隔地自該第—㈣層内部延伸 至其表面的源極與汲極、一閘極介電膜層結構及一形成 於該閘極介電膜層結構上的閘極。該閘極介電膜層結構覆 蓋該未形成有該對源極與汲極之第一 GaN層的表面並具 有一 MgO層及一形成於該Mg〇層上之含有耵與Mg的氧 化層。 本發明之功效在於：改善漏電流的問題及提昇電晶體 之電容值’以獲得優異的元件性能。 【實施方式】 <發明詳細說明> 有關本發明t前述及其他技術内纟、特點與功效，在 以下配合參考圖式之-個較佳實施例與一個具體例的詳細 說明中，將可清楚的呈現。 參閱圖4’本發明之增強型氮化鎵系、金氧半場效電晶體 的一第一較佳實施例，包含：一六方晶系結構之基板2、一 配置於該基板2上且其内部含有第一導電型之掺質（如， 離子）的第一 GaN層3、一配置於該基板2與該第一 GaN層 3之間的第二GaN層4、一配置於該基板2與該第二GaN 層4之間之未經摻雜的第三GaNf 5、—對相間隔地自該 5 201218377 第一 GaN層3内部延伸至其表面的源極61與及極62、一 問極介電膜層結構7 ’及一形成於該閑極介電膜層結構7上 的閘極8。該第二GaN | 4内部含有相反於該第一導電型 之摻質的第二導電型之摻質（如，Si離子）。該閘極介電膜層 結構7覆蓋該未形成有該對源極61與汲極62之第一㈣ 層3的表面’並具有一吨〇層71及—形成於該叫〇層7i 上之含有Ti與Mg的氧化層72。 較佳地，該閘極介電膜層結構7之含有Ti與Mg的氧 化層72中的Ti原子比Mg原子，是介於〇 9 : i」至1」： 0.9之間。 較佳地，該閘極介電膜層結構7之含有Ti與Mg的氧 化層72的厚度是介於7 nm至1 〇 nm之間。 較佳地，該六方晶系結構之基板2是由藍寶石（sa卯hire) 所構成。 <具體例> 再參圖4,本發明之增強型氮化鎵系金氧半場效電晶體 的一具體例及其製作方法，是簡單地說明於下，此處需說 明的是’於以數下段落中涉及磊晶製程的設備、清洗流程 相關設備、黃光製程所衍生之圖案化閘極遮罩與閘極區 域、雙靶材射頻濺鍍系統相關設備、電漿輔助化學氣相沉 積法、圖案化Si〇2層及離子佈植區等相關說明，皆未顯示 於圖4中，以上合先敘明。 首先’將一藍寶石之基板2設置於一有機金屬化學氣 相沉積（metal-organic chemical-vapor-deposition ；簡稱 201218377 MOCVD)系統中以於其上依序磊製一厚度約2 μιη之無摻雜 的第二GaN層（u-GaN)5、一厚度約2 μιη之摻雜有Si摻質 的第二GaN層（n-GaN)4、一厚度約2 μηι之摻雜有Mg摻質 且》辰度約為8x1016 cm-3的第一 GaN層（p-GaN)5。將形成有 該等GaN層3、4、5的基板2依序放置於丙酮與異丙醇中 使用超音波震盪清洗3分鐘。之後’以去離子水過水後吹 乾。 接續地，將形成有該等GaN層3、4、5的基板2浸泡 % 於稀釋氫氟酸（diluted HF)中1分鐘後，立即對其吹乾以去 除原生氧化物（native oxide)。另，使用黃光製程 (photolithography process)以在該第一 GaN 層 3 上形成一圖 案化閘極遮罩（patterned gate mask，圖未示），進而在該第一 GaN層3上定義出一長度為1 的閘極區域；之後，對該 第一 GaN層3施予60°C持溫30分鐘的硫化處理[(nh4)xS treatment] ° 於一工作壓力為1〇 mT〇rr的雙靶材射頻濺鍍系統中放 • 置該形成有該圖案化閘極遮罩與該等GaN層3、4、5的基 板2。先對該雙靶材射頻濺鍍系統的一 MgO靶材提供3.7 W/cm2的輸出功率密度’以於該第一 GaN層3之閘極區域 上形成一厚度約.2 nm的MgO層71，並對該雙靶材射頻濺 鍍系統的MgO靶材與一 Ti〇2靶材分別提供3.0 W/cm2與 2.1 W/cm2的輸出功率密度，以於該MgO層71上形成一厚 度約8 nm之含有Ti與Mg的氧化層72，進而完成一閘極介 電膜層結構7。在本發明該具體例中，該含有Ti與Mg的氧 201218377 化層72中的Τι原子比Mg原子是1 : 1 ’即，Ti〇2_Mg〇。 於完成該閘極介電膜層結構7之後，先對該閘極介電 膜層結構7施予5001持溫15分鐘的氧氣退火處理 (annealing) ’以降低該閘極介電膜層結構7内的氧空缺 (oxygen vacancy)，並於該閘極介電膜層結構7上形成一厚 度約40 nm且是由Ni所構成的閘極8。於完成該閘極8之 後，移除該圖案化閘極遮罩。 以電漿輔助化學氣相沉積法（PECVD)於該閘極8與該第 一 GaN層3上覆蓋一厚度約2〇 nm的圖案化Si〇2層（圖未 示）’以於該第一 GaN層3上之位於該閘極8的兩側處定義 出兩離子佈植（ion implantation)區。對該第一 GaN層3之該 等離子佈植區施予濃賴1x1G2g咖.3的&料佈植，並施 予1050 °C持溫5分鐘的快速熱退火（rapid annealing，RTA) ’藉以活化（activati〇n)所佈植的Si離子， 並完成-對間隔地自該第—GaN | 3⑽延伸至其表面的 源極61與汲極62。之後，以反應式離子蝕刻法 ion etching，RIE)移除該圖案化Si〇2層。 於該對源極61與汲極62上分別依序沉積一厚度約5 謹的Ti層、一厚度約1〇11111的八1層、一厚度約5細的 Ti層與-厚度約50 nm的Au f ’藉以在該對源極61與沒 極62上分別形成一對接觸電極9。之後，對該對接觸電極 9施予氣氣退火處理，藉以完成歐姆接觸並製得本發明該具 體例之增強型氮化鎵系金氧半場效電晶體。 參圖5所顯示之i_V曲線可知，本發明該具體例之增強 201218377 ^氮化鎵系金氧半場效電晶體於+ι V與·！ v之分析條件 下，所取付的漏電流密度分別約為2 2χΐ〇.8狀出2幻5χΐ〇· 8 A/cm2 〇 ” 此處需說明的是，基於Ti02的能隙是 小於MgO，本發 月該閘極介電膜層結構7之該含有Ti與的氧化層（即，201218377 VI. Description of the Invention: [Technical Field] The present invention relates to a metal oxide half field effect transistor (111 is &1-〇?^(^-semiconductor field effect transistor; MOSFET), especially An enhancement mode GaN-based MOS field-effect transistor. [Prior Art] GaN-based MOSFETs have wide bandgap, high breakdown voltage, and high saturation velocity. And good thermal conductivity; therefore, high-power and fast GaN-based MOSFETs have gradually attracted attention. Because of the above characteristics, the gate voltage in the MOSFET induces channel bits. Problems such as drain-induced barrier lowering and band-to-band tunneling can be reduced. Referring to Figure 1, the inventor at IEEE ELECTRON DEVICE LETTERS, VOL. 31 NO. 6, JUNE 2010, PP 558~560, discloses a p-GaN MOS capacitor 1 and a method of fabricating the same, the p-GaN MOS capacitor 1 comprising: a doped Mg dopant a p-GaN substrate 11, a gate dielectric stack 12 partially formed on the p-GaN substrate 11, and an upper electrode 13 formed on the gate dielectric stack 12 and composed of Ni. An ohmic electrode 14 formed on the p-GaN substrate 11 on which the gate dielectric stack 12 is not formed and composed of Ni/Au. The gate dielectric stack 12 is RF sputtered by a double target. a system (dualtarget rf sputtering system) having a first MgO layer 121 partially formed on the p-GaN substrate 11 of 201218377 and having a thickness of about 1.8 nm, and a thickness formed on the first MgO layer 121 A Ti 2 layer 122 of about 64 nm, and a second MgO layer 123 formed on the Ti02 layer 122 and having a thickness of about 18 nm. The current density (J) vs. voltage (v) graph shown in FIG. It can be seen that the current leakage density of the p-GaN-based MOS capacitor 1 at + 1 V and -1 V is approximately 3·9 χ 1 〇 -8 A/cm 2 and 3.7 x 1 (T8 A/cm 2 , respectively). In addition, referring to the capacitance value shown in FIG. 3 (〇 vs. voltage (v) curve, the p-GaN-based MOS capacitor 1 has a capacitance value under the analysis bar of 1 〇〇mHz and -5 V. Is 1.58 pF / cm2. The p-GaN MOS capacitor 1 is based on a high dielectric constant (k value) imparted by the Τ 〇 2 layer 122 of the gate dielectric stack 12 to boost the overall driving current ( Drive current) and capacitance (capacitance, C). However, the size of the energy gap generally having a high value of oxide is insufficient to prevent thermionic emission from the upper electrode 13. Therefore, the p-GaN MOS capacitor 1 is further characterized in that the Mg 〇 layer 123 of the gate dielectric stack 12 has a high energy gap to reduce the local leakage current caused by thermionic radiation. As apparent from the above description, the film design of the gate dielectric stack 12 of the p-GaN-based MOS capacitor 1 can improve leakage current and the like; however, the leakage current is further reduced and the capacitance value is increased to obtain excellent device performance. Then, the subject of breakthroughs in this technical field is required. SUMMARY OF THE INVENTION 201218377 Accordingly, the object of the present invention is to provide an enhanced type of oxidized recording system metal oxide half field effect transistor. Therefore, the GaN-based MOS field-effect transistor of the present invention comprises: a hexagonal crystal structure (a substrate of a hexagonal system (10) (4), disposed on the substrate and having a first conductivity type therein) a first GaN layer of the broadcast quality 'a pair of source and drain electrodes, a gate dielectric film layer structure extending from the inside of the first (four) layer to the surface thereof, and a gate dielectric film formed thereon a gate electrode structure, the gate dielectric film layer structure covers a surface of the first GaN layer where the pair of source and drain electrodes are not formed, and has a MgO layer and a content formed on the Mg layer The present invention has the advantages of improving the leakage current and improving the capacitance value of the transistor to obtain excellent element performance. [Embodiment] <Detailed Description of the Invention> Other technical intrinsic features, features, and effects will be apparent from the following detailed description of a preferred embodiment and a specific example. Referring to Figure 4, the enhanced gallium nitride system of the present invention One of the gold-oxygen half-field effect transistors A preferred embodiment comprises: a substrate having a hexagonal crystal structure; a first GaN layer 3 disposed on the substrate 2 and containing a first conductivity type dopant (eg, ions) therein, and a configuration a second GaN layer 4 between the substrate 2 and the first GaN layer 3, an undoped third GaNf 5 disposed between the substrate 2 and the second GaN layer 4, and a phase interval a source 61 and a pole 62 extending from the inside of the first layer GaN layer 3 to the surface thereof, a gate dielectric layer structure 7', and a gate formed on the dummy dielectric layer structure 7 The second GaN | 4 internally contains a dopant of a second conductivity type opposite to the dopant of the first conductivity type (eg, Si ions). The gate dielectric film layer structure 7 covers the unformed The pair of source 61 and the surface 4 of the first (four) layer 3 of the drain 62 have a ton of germanium layer 71 and an oxide layer 72 containing Ti and Mg formed on the layer 7i. Preferably, The Ti atom in the oxide layer 72 containing Ti and Mg of the gate dielectric film layer structure 7 is between 〇9: i" and 1": 0.9. Preferably, the gate dielectric membrane The thickness of the oxide layer 72 containing Ti and Mg of the structure 7 is between 7 nm and 1 〇 nm. Preferably, the substrate 2 of the hexagonal crystal structure is composed of sapphire (sa卯hire). Specific Example> Referring again to FIG. 4, a specific example of the enhanced gallium nitride-based metal oxide half field effect transistor of the present invention and a method for fabricating the same are briefly described below. The following paragraphs refer to equipment for epitaxial process, cleaning process related equipment, patterned gate mask and gate region derived from yellow light process, dual target RF sputtering system related equipment, plasma assisted chemical vapor deposition The descriptions of the patterned Si〇2 layer and the ion implantation area are not shown in FIG. 4, and the above is described first. Firstly, a sapphire substrate 2 is placed in a metal-organic chemical-vapor-deposition (201218377 MOCVD) system to sequentially deposit a non-doped layer having a thickness of about 2 μm. a second GaN layer (u-GaN) 5, a second GaN layer (n-GaN) 4 doped with Si dopant having a thickness of about 2 μm, and a Mg dopant doped with a thickness of about 2 μm The first GaN layer (p-GaN) 5 having a thickness of about 8 x 1016 cm-3. The substrate 2 on which the GaN layers 3, 4, and 5 were formed was sequentially placed in acetone and isopropyl alcohol and washed by ultrasonic vibration for 3 minutes. After that, it was dried with deionized water and then dried. Successively, the substrate 2 on which the GaN layers 3, 4, 5 were formed was immersed in dilute HF for 1 minute, and immediately dried to remove the native oxide. In addition, a photolithography process is used to form a patterned gate mask (not shown) on the first GaN layer 3, thereby defining a length on the first GaN layer 3. a gate region of 1; thereafter, the first GaN layer 3 is subjected to a vulcanization treatment at 60 ° C for 30 minutes [(nh4)xS treatment] ° at a working pressure of 1 〇mT rr The substrate 2 in which the patterned gate mask and the GaN layers 3, 4, 5 are formed is placed in an RF sputtering system. First, an output power density of 3.7 W/cm 2 is provided for a MgO target of the dual target RF sputtering system to form a MgO layer 71 having a thickness of about .2 nm on the gate region of the first GaN layer 3, And an output power density of 3.0 W/cm 2 and 2.1 W/cm 2 is respectively provided for the MgO target and the Ti 2 target of the dual target RF sputtering system to form a thickness of about 8 nm on the MgO layer 71. The oxide layer 72 containing Ti and Mg completes a gate dielectric film layer structure 7. In this specific example of the present invention, the Τι atomic ratio Mg atom in the oxygen-containing 201218377 layer 72 containing Ti and Mg is 1:1, i.e., Ti〇2_Mg〇. After completing the gate dielectric film structure 7, the gate dielectric film structure 7 is first subjected to an oxygen annealing treatment of 5001 for 15 minutes to reduce the gate dielectric film structure. An oxygen vacancy is formed, and a gate 8 having a thickness of about 40 nm and composed of Ni is formed on the gate dielectric film structure 7. After the gate 8 is completed, the patterned gate mask is removed. The gate electrode 8 and the first GaN layer 3 are covered with a patterned Si 〇 2 layer (not shown) having a thickness of about 2 〇 nm by plasma-assisted chemical vapor deposition (PECVD). Two ion implantation regions are defined on the GaN layer 3 at both sides of the gate 8. The plasma implantation region of the first GaN layer 3 is subjected to a <1>G2g&> material implantation, and subjected to rapid annealing (RTA) at 1050 ° C for 5 minutes. The Si ions implanted are activated and the source 61 and the drain 62 extending from the first GaN | 3 (10) to the surface thereof are completed. Thereafter, the patterned Si 2 layer is removed by reactive ion etching (RIE). A Ti layer having a thickness of about 5 Å, an 18 layer having a thickness of about 1 〇 11111, a Ti layer having a thickness of about 5, and a thickness of about 50 nm are sequentially deposited on the pair of source 61 and the drain 62, respectively. Au f ' is formed by forming a pair of contact electrodes 9 on the pair of source 61 and the gate 62, respectively. Thereafter, the pair of contact electrodes 9 are subjected to an air-annealing treatment to complete ohmic contact and to obtain the specific GaN-based galvanic field-effect transistor of the present invention. Referring to the i_V curve shown in Fig. 5, the specific example of the present invention is enhanced. 201218377 ^ Gallium nitride-based metal oxide half field effect transistor in +ι V and ·! Under the analysis conditions of v, the leakage current density is about 2 2 χΐ〇.8, and 2 illusion 5 χΐ〇 8 A/cm 2 〇". It should be noted that the energy gap based on TiO 2 is smaller than MgO. The oxide layer of the gate dielectric structure 7 containing Ti and the oxide layer (ie,
Ti02Mg0)72的能隙理應小於該習知之閘極介電疊層12的 第一 MgO層123 ^因此，可預期地，本發明該具體例對於 來自該閘極8的熱離子放射的阻擋能力，理應低於該習知 之p-GaN系MOS電容器1 ;即，本發明該具體例之漏電流 密度理應大於該習知之p_GaN系M〇s電容器i。然而，本 發明該具體例於+ 1 V與-1 V下的漏電流密度（即，2.2χ1(Τ8 A/cm2與3·5χ1〇-8 A/cm2)卻不如預期地小於該習知的漏電流 密度（即’ 3.9><1〇-8 A/cm2與3H8 A/cm2)。因此，本發明 該具體例之增強型氮化鎵系金氧半場效電晶體的漏電流性 能較該習知佳。 此處需進一步說明的是，本發明該具體例之閘極介電 膜層結構7内只有一個界面（即，Mg〇/Ti〇2_Mg〇)，相對該 習知之閘極介電疊層12少一個介面（即，Mg〇/Ti〇2/Mg〇); 本發明該具體例之閘極介電膜層結構7内的界面缺陷密度 (interface trap density)較該習知少；因此，更可改善漏電流 的問題。 參圖6所顯示之C-V曲線可知，本發明該具體例之增 強型氮化録系金氧半場效電晶體於1 〇〇 MHz及-5 V的分析 條下，其電容值約為1.76 pF/cm2，相對該習知之p_GaN系 201218377 MOS電容器1的電容值高出約12%。 綜上所述，本發明之增強型氮化鎵系金氧半場效電晶 體，可進-步地改善該習知之漏電流的問題，並可提昇電 晶體之電容值以獲得優異的元件性能，故域實能達成本發 明之目的。 惟以上所述者，僅為本發明之較佳實施例與具體例而 已，當不能以此限定本發明實施之範圍，即大凡依本發明 申請專利範圍及發明說明内容所作之簡單的等效變化與修 飾，皆仍屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1是一正視示意圖，說明習知一種p_GaN系M〇s電 容器； 圖2是一 J-V曲線圖’說明該習知之漏電流特性； 圖3是一 C-V曲線圖，說明該習知之電容特性； 圖4是一正視示意圖，說明本發明之增強型氮化鎵系 金氧半場效電晶體的一較佳實施例； 圖5是一 J-V曲線圖’說明本發明增強型氮化鎵系金氧 半場效電晶體的一具體例之漏電流特性；及 圖6是一 C-V曲線圖’說明本發明該具體例之電容特 性0 10 201218377 【主要元件符號說明】 2 基板 7 閘極介電膜層結構 3 第一 GaN層 71 MgO層 4 第二GaN層 72 含有Ti與Mg的氧化層 5 第三GaN層 8 閘極 61 源極 9 接觸電極 62 汲極The energy gap of Ti02Mg0)72 should be less than the first MgO layer 123 of the conventional gate dielectric stack 12. Therefore, it is expected that the specific example of the present invention can block the thermionic emission from the gate 8. It should be lower than the conventional p-GaN-based MOS capacitor 1; that is, the leakage current density of this specific example of the present invention should be larger than that of the conventional p-GaN-based M〇s capacitor i. However, the leakage current density at this specific example of the present invention at + 1 V and -1 V (i.e., 2.2 χ 1 (Τ 8 A/cm 2 and 3·5 χ 1 〇 8 A/cm 2 ) is less than expected than the conventional one. Leakage current density (i.e., '3.9> <1〇-8 A/cm2 and 3H8 A/cm2). Therefore, the leakage current performance of the enhanced gallium nitride-based metal oxide half field effect transistor of this specific example of the present invention is higher. It should be further noted that there is only one interface (ie, Mg〇/Ti〇2_Mg〇) in the gate dielectric film layer structure 7 of the specific example of the present invention, which is compared with the conventional gate dielectric. The interface 12 has one less interface (ie, Mg〇/Ti〇2/Mg〇); the interface trap density in the gate dielectric film layer structure 7 of this embodiment of the present invention is less than the conventional one; Therefore, the problem of leakage current can be improved. Referring to the CV curve shown in FIG. 6, the analysis strip of the enhanced nitriding system of the present invention is in the range of 1 〇〇 MHz and -5 V. The capacitance value is about 1.76 pF/cm2, which is about 12% higher than the capacitance value of the conventional p_GaN system 201218377 MOS capacitor 1. In summary, the invention is increased. The type of gallium nitride-based metal oxide half field effect transistor can further improve the conventional leakage current problem, and can increase the capacitance value of the transistor to obtain excellent component performance, so that the domain can achieve the object of the present invention. The above is only the preferred embodiment and the specific examples of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent of the scope of the invention and the description of the invention. Variations and modifications are still within the scope of the present invention. [Simplified Schematic] FIG. 1 is a front elevational view showing a conventional p_GaN M〇s capacitor; FIG. 2 is a JV graph illustrating the FIG. 3 is a CV graph illustrating the conventional capacitive characteristics; FIG. 4 is a front elevational view showing a preferred embodiment of the enhanced gallium nitride-based MOS field effect transistor of the present invention; 5 is a JV graph ' illustrating leakage current characteristics of a specific example of the GaN-based MOS field-effect transistor of the present invention; and FIG. 6 is a CV graph ′ illustrating the specific example of the present invention. Capacitance characteristics 0 10 201218377 [Description of main component symbols] 2 Substrate 7 Gate dielectric film structure 3 First GaN layer 71 MgO layer 4 Second GaN layer 72 Oxide layer containing Ti and Mg 5 Third GaN layer 8 Gate 61 source 9 contact electrode 62 bungee