TWI409951B - Enhancement mode gan-based mosfet - Google Patents

Abstract

This invention provides an enhancement mode GaN-based MOSFET, which comprises a substrate of a hexagonal system crystal structure, a first GaN layer disposed on the substrate and containing first conductive dopants therein, a pair of source and drain extending apart from the inner first GaN layer toward the surface thereof, a gate dielectric layered structure covering the first GaN layer in which the pair of the source and the drain are not formed and having a MgO layer and an oxide layer, that contains Ti and Mg therein and is formed on the MgO layer, and a gate formed on the gate dielectric layered structure.

Description

Enhanced GaN-based metal oxide half field effect transistor

The invention relates to a metal-oxide-semiconductor field effect transistor (MOSFET), in particular to an enhancement mode GaN-based MOSFET. Crystal.

GaN-based MOSFETs have characteristics such as wide bandgap, high breakdown voltage, high saturation velocity, and good thermal conductivity; therefore, high-power and fast GaN systems MOSFETs have gradually received attention. Also, due to the foregoing characteristics, problems such as drain-induced barrier lowering and band-to-band tunneling in the MOSFET can be reduced.

Referring to Fig. 1, the inventors disclosed a p-GaN MOS capacitor 1 and a method of fabricating the same in IEEE ELECTRON DEVICE LETTERS, VOL. 31 NO. 6, JUNE 2010, PP 558~560. The p-GaN MOS capacitor 1 includes: a p-GaN substrate 11 doped with Mg dopants, and a gate dielectric stack 12 partially formed on the p-GaN substrate 11 An upper electrode 13 composed of Ni on the gate dielectric stack 12, and an ohm formed on the p-GaN substrate 11 on which the gate dielectric stack 12 is not formed and composed of Ni/Au Electrode 14.

The gate dielectric stack 12 is made of a dual-target rf sputtering system and has a portion partially formed on the p-GaN substrate 11 and having a thickness of about 1.8 nm. An MgO layer 121, a TiO ₂ layer 122 formed on the first MgO layer 121 and having a thickness of about 6.4 nm, and a second MgO layer 123 formed on the TiO ₂ layer 122 and having a thickness of about 1.8 nm.

Referring to the current density (J) versus voltage (V) graph shown in FIG. 2, the current leakage density of the p-GaN MOS capacitor 1 at +1 V and -1 V is approximately 3.9 × 10 ^-8 A / cm ² and 3.7 × 10 ^-8 A / cm ² .

In addition, referring to the capacitance value (C) versus voltage (V) graph shown in FIG. 3, the capacitance of the p-GaN MOS capacitor 1 is about 100 MHz and -5 V, and the capacitance is about 1.58 μF/cm ² .

On the one hand, the p-GaN MOS capacitor 1 uses a high dielectric constant (k value) imparted by the TiO ₂ layer 122 of the gate dielectric stack 12 to increase its overall driving current (drive current). And capacitance value (capacitance, C). However, the size of the energy gap of an oxide having a high k value is generally insufficient to prevent thermionic emission from the upper electrode 13. Therefore, the p-GaN-based MOS capacitor 1 on the other hand has a high energy gap characteristic by the MgO layer 123 of the gate dielectric stack 12 to reduce the local leakage current caused by thermionic radiation.

As apparent from the above description, the film design of the gate dielectric stack 12 of the p-GaN-based MOS capacitor 1 can improve leakage current and the like; however, the leakage current is further reduced and the capacitance value is increased to obtain an excellent device. Performance is the subject of breakthroughs in this technical field.

Accordingly, it is an object of the present invention to provide an enhanced gallium nitride based metal oxide half field effect transistor.

Therefore, the GaN-based MOS field-effect transistor of the present invention comprises: a substrate of a hexagonal system crystal structure, a substrate disposed on the substrate and having a first conductivity type therein a first GaN layer doped, a pair of source and drain electrodes extending from the inside of the first GaN layer to a surface thereof, a gate dielectric film layer structure, and a gate dielectric film formed thereon The gate on the layer structure. The gate dielectric film layer covers the surface of the first GaN layer where the pair of source and drain electrodes are not formed, and has an MgO layer and an oxide layer containing Ti and Mg formed on the MgO layer.

The effect of the present invention is to improve the leakage current problem and increase the capacitance value of the transistor to obtain excellent component performance.

<Detailed Description of the Invention>

The foregoing and other technical aspects, features and advantages of the present invention will be apparent from

Referring to FIG. 4, a first preferred embodiment of the GaN-based MOS field-effect transistor of the present invention comprises: a substrate 2 having a hexagonal crystal structure, and a substrate 2 disposed on the substrate 2 a first GaN layer 3 containing a first conductivity type dopant (eg, Mg ions), a second GaN layer 4 disposed between the substrate 2 and the first GaN layer 3, and a substrate 203 disposed on the substrate 2 An undoped third GaN layer 5 between the second GaN layers 4, a pair of source 61 and drain electrodes 62 extending from the inside of the first GaN layer 3 to the surface thereof, and a gate electrode The electro-membrane layer structure 7 and a gate 8 formed on the gate dielectric film layer structure 7. The second GaN layer 4 contains a dopant of a second conductivity type (e.g., Si ion) opposite to the dopant of the first conductivity type. The gate dielectric film layer structure 7 covers the surface of the first GaN layer 3 on which the pair of source 61 and the drain 62 are not formed, and has a MgO layer 71 and a Ti-containing layer formed on the MgO layer 71. Oxide layer 72 with Mg.

Preferably, the Ti atom in the oxide layer 72 containing Ti and Mg of the gate dielectric film layer structure 7 has a ratio of Ti atoms to Mg atoms of between 0.9:1.1 and 1.1:0.9.

Preferably, the thickness of the oxide layer 72 containing Ti and Mg of the gate dielectric film layer structure 7 is between 7 nm and 10 nm.

Preferably, the substrate 2 of the hexagonal crystal structure is composed of sapphire.

<Specific example>

Referring again to Fig. 4, a specific example of the enhanced gallium nitride-based metal oxide half field effect transistor of the present invention and a method for fabricating the same are briefly described below. It should be noted here that the equipment involved in the epitaxial process, the cleaning process related equipment, the patterned gate mask derived from the yellow light process and the gate region, and the double target RF sputtering system are related to the following paragraphs. The related descriptions of equipment, plasma-assisted chemical vapor deposition, patterned SiO ₂ layer and ion implantation area are not shown in Fig. 4, and the above is described first.

First, a sapphire substrate 2 is placed in a metal-organic chemical-vapor-deposition (MOCVD) system to sequentially deposit an undoped layer having a thickness of about 2 μm. a third GaN layer (u-GaN) 5, a second GaN layer (n-GaN) 4 doped with Si dopant having a thickness of about 2 μm, a Mg dopant having a thickness of about 2 μm, and a concentration of about It is a first GaN layer (p-GaN) 5 of 8 × 10 ¹⁶ cm ^-3 . The substrate 2 on which the GaN layers 3, 4, and 5 were formed was sequentially placed in acetone and isopropyl alcohol and washed by ultrasonic vibration for 3 minutes. After that, it was dried with deionized water and then dried.

Successively, the substrate 2 on which the GaN layers 3, 4, and 5 were formed was immersed in diluted hydrofluoric acid (diluted HF) for 1 minute, and then immediately dried to remove the native oxide. In addition, a photolithography process is used to form a patterned gate mask (not shown) on the first GaN layer 3, thereby defining a length on the first GaN layer 3. It is a gate region of 1 μm; thereafter, the first GaN layer 3 is subjected to a vulcanization treatment [(NH ₄ ) _x S treatment] at a temperature of 60 ° C for 30 minutes.

The substrate 2 on which the patterned gate mask and the GaN layers 3, 4, 5 are formed is placed in a dual target RF sputtering system with a working pressure of 10 mTorr. An output power density of 3.7 W/cm ² is first provided to a MgO target of the dual target RF sputtering system to form a MgO layer 71 having a thickness of about 2 nm on the gate region of the first GaN layer 3, And providing an output power density of 3.0 W/cm ² and 2.1 W/cm ² for the MgO target and the TiO ₂ target of the dual target RF sputtering system to form a thickness of about 8 on the MgO layer 71. The oxide layer 72 of Ti containing Mg and Mg completes a gate dielectric film structure 7. In this specific example of the present invention, the Ti atom in the oxide layer 72 containing Ti and Mg is 1:1, that is, TiO ₂ -MgO.

After the gate dielectric layer structure 7 is completed, the gate dielectric film layer structure 7 is subjected to an oxygen annealing treatment at 500 ° C for 15 minutes to reduce the structure of the gate dielectric film layer. Oxygen vacancy in 7 and a gate 8 having a thickness of about 40 nm and composed of Ni is formed on the gate dielectric film structure 7. After the gate 8 is completed, the patterned gate mask is removed.

The gate electrode 8 and the first GaN layer 3 are covered with a patterned SiO ₂ layer (not shown) having a thickness of about 20 nm by plasma assisted chemical vapor deposition (PECVD) to form the first GaN layer. A two ion implantation region is defined at the two sides of the gate 8 on the third. The plasma implantation region of the first GaN layer 3 is implanted with Si ion implantation at a concentration of about 1×10 ²⁰ cm ⁻³ , and subjected to rapid thermal annealing (RTA) at a temperature of 1050 ° C for 5 minutes. Thereby, the implanted Si ions are activated, and a pair of source 61 and drain 62 extending from the inside of the first GaN layer 3 to the surface thereof are completed. Thereafter, the patterned SiO ₂ layer is removed by reactive ion etching (RIE).

A Ti layer having a thickness of about 5 nm, an Al layer having a thickness of about 10 nm, a Ti layer having a thickness of about 5 nm, and an Au layer having a thickness of about 50 nm are sequentially deposited on the pair of source 61 and the drain 62, respectively. A pair of contact electrodes 9 are formed on the pair of source 61 and drain 62, respectively. Thereafter, the pair of contact electrodes 9 are subjected to a nitrogen annealing treatment to complete the ohmic contact and to obtain the enhanced gallium nitride-based metal oxide half field effect transistor of the specific example of the present invention.

Referring to the JV curve shown in FIG. 5, the leakage current density of the GaN-based MOS field-effect transistor of the specific example of the present invention is about +1 V and -1 V, respectively. 2.2 × 10 ^-8 A / cm ² and 3.5 × 10 ^-8 A / cm ² .

It should be noted that the energy gap based on TiO ₂ is smaller than MgO, and the energy gap of the oxide layer containing Ti and Mg (ie, TiO ₂ -MgO) 72 of the gate dielectric film layer structure 7 of the present invention should be Less than the second MgO layer 123 of the conventional gate dielectric stack 12. Therefore, it is expected that the specific example of the present invention has a lower blocking ability for thermionic radiation from the gate 8 than the conventional p-GaN-based MOS capacitor 1; that is, the leakage current density of the specific example of the present invention. It is supposed to be larger than the conventional p-GaN-based MOS capacitor 1. However, the specific example of the present invention has a leakage current density at +1 V and -1 V (i.e., 2.2 × 10 ^-8 A/cm ² and 3.5 × 10 ^-8 A/cm ² ) which is less than expected than the Known leakage current density (i.e., 3.9 x 10 ^-8 A/cm ² and 3.7 x 10 ^-8 A/cm ² ). Therefore, the leakage current performance of the enhanced gallium nitride based metal oxide half field effect transistor of this specific example of the present invention is better than the conventional one.

It should be further noted that there is only one interface (ie, MgO/TiO ₂ -MgO) in the gate dielectric film layer structure 7 of this embodiment of the present invention, one less than the conventional gate dielectric laminate 12 . The interface (ie, MgO/TiO ₂ /MgO); the interface trap density in the gate dielectric film layer structure 7 of this embodiment of the present invention is less than the conventional one; therefore, the leakage current is further improved. problem.

Referring to the CV curve shown in FIG. 6, the enhanced GaN-based MOS field-effect transistor of the specific example of the present invention has a capacitance value of about 1.76 μF/cm ² under the analysis strips of 100 MHz and -5 V. The capacitance value of the conventional p-GaN MOS capacitor 1 is about 12% higher.

In summary, the enhanced gallium nitride-based metal oxide half field effect transistor of the present invention can further improve the conventional leakage current problem, and can increase the capacitance value of the transistor to obtain excellent component performance, so The object of the invention can be achieved.

The above is only the preferred embodiment and the specific examples of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent change according to the scope of the invention and the description of the invention. And modifications are still within the scope of the invention patent.

2‧‧‧Substrate

3‧‧‧First GaN layer

4‧‧‧Second GaN layer

5‧‧‧ Third GaN layer

61‧‧‧ source

62‧‧‧汲polar

7‧‧‧ gate dielectric film structure

71‧‧‧MgO layer

72‧‧‧Oxide layer containing Ti and Mg

8‧‧‧ gate

9‧‧‧Contact electrode

1 is a front elevational view showing a conventional p-GaN based MOS capacitor;

Figure 2 is a J-V graph illustrating the conventional leakage current characteristics;

Figure 3 is a C-V graph illustrating the conventional capacitive characteristics;

Figure 4 is a front elevational view showing a preferred embodiment of the enhanced gallium nitride based metal oxide half field effect transistor of the present invention;

5 is a J-V graph illustrating leakage current characteristics of a specific example of the GaN-based MOS field effect transistor of the present invention; and

Fig. 6 is a C-V graph illustrating the capacitance characteristics of this specific example of the present invention.

2. . . Substrate

3. . . First GaN layer

4. . . Second GaN layer

5. . . Third GaN layer

61. . . Source

62. . . Bungee

7. . . Gate dielectric film structure

71. . . MgO layer

72. . . Oxide layer containing Ti and Mg

8. . . Gate

9. . . Contact electrode

Claims (6)

An enhanced GaN-based metal oxide half field effect transistor comprising: a substrate having a hexagonal crystal structure; a first GaN layer disposed on the substrate and having a first conductivity type dopant therein; a source and a drain extending from the inside of the first GaN layer to a surface thereof; and a gate dielectric film layer covering the surface of the first GaN layer where the pair of source and drain are not formed, And having a MgO layer and an oxide layer containing Ti and Mg formed on the MgO layer; and a gate formed on the gate dielectric film layer structure. The GaN-based MOS field-effect transistor according to the first aspect of the invention, wherein the gate dielectric film layer structure contains Ti atoms and Mg atoms in the oxide layer is larger than Mg atoms. Between 0.9:1.1 and 1.1:0.9. The GaN-based MOS field-effect transistor according to claim 2, wherein the thickness of the oxide layer containing Ti and Mg of the gate dielectric film layer is between 7 nm and 10 Between nm. The GaN-based MOS field-effect transistor according to claim 1, wherein the substrate of the hexagonal crystal structure is composed of sapphire. The GaN-based MOS field-effect transistor according to claim 1, further comprising a second GaN layer disposed between the substrate and the first GaN layer. And the dopant containing the second conductivity type opposite to the dopant of the first conductivity type is contained therein. The GaN-based MOS field-effect transistor according to claim 5, further comprising an undoped third GaN layer, wherein the undoped third GaN layer is disposed on the Between the substrate and the second GaN layer.