TWI230459B - GaN heterojunction field effect transistor device and manufacturing method thereof - Google Patents

GaN heterojunction field effect transistor device and manufacturing method thereof Download PDF

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TWI230459B
TWI230459B TW92112389A TW92112389A TWI230459B TW I230459 B TWI230459 B TW I230459B TW 92112389 A TW92112389 A TW 92112389A TW 92112389 A TW92112389 A TW 92112389A TW I230459 B TWI230459 B TW I230459B
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gallium nitride
nitride
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TW92112389A
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TW200425504A (en
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Lian-Bi Jang
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Jang Guo Ying
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Abstract

This invention relates to a microwave power heterojunction field effect transistor (FET) device and a manufacturing method thereof. GaN can be used to manufacture high voltage FET due to its high electron mobility and the densest packing structure for high voltage resistance, which is very suitable for high voltage output and high temperature operation environment. This invention is to grow a thin layer of InGaN contact epitaxy layer on the GaN high resistance epitaxy layer. Because the band gap width of the InGaN contact epitaxy layer is lower than that of the GaN high resistance epitaxy layer, better ohmic contact can result from lower band gap. Therefore, contact resistance of source/drain can be reduced. Further, when forming the ohmic contact, there is an AlGaN barrier layer on top of the InGaN contact epitaxy layer and there is a GaN high resistance epitaxy layer underneath the InGaN contact epitaxy layer. Since the band gap of the InGaN contact epitaxy layer is lower than that of GaN high resistance epitaxy layer and thus even lower than that of the AlGaN barrier layer, a double heterostructure is formed, which brings advantages of forming large electron energy state density and higher electron mobility and thus provides larger source current and increases output power.

Description

1230459 玖、發明說明 【發明所屬之技術領域】 本發明是杨 1-個微波轉的異質接㈣㈣晶體的裝置及其制 作方法。氮化鎵因它具有高的電子漂料,及具有最密堆積= 耐壓高’故可以製作出耐高壓的場效電晶體,非f適合用於高° 率的輸出及高溫的操作環境。 、回31 【先前技術】 化合物半導體通常較辨導體具有直接的·,及較高的電 子遷料,因歧魏合辨導做為财場效t晶義材料,已 是目前非常普遍_勢。其中,最常被使用㈣化鎵金半場效電 晶體’卻在高電場下有電子漂移率劣化的現象;雖糾化嫁場效 電晶體’較切元素半導體場效電晶體元件,已經有較高的操作 頻率,但相較於其他化合物半導體,在高功率之下仍有較低的崩 >貝電壓’ |父差的電子漂移轉處;無法達職輸出功率的要求, 因此’南功率輸出的微波場效電晶體,目前還有許多發展的空間。 同時’由於氮化鎵化合物半導體秘晶技術,錢元件製作技術 曰漸純熟,近年來更廣泛的應用在光電半導體元件之上,尤其是 在發光7L件及f射元件方面。近來,由魏化鎵有較高的崩潰電 壓幸乂f·夬的電子,示移專優點,而將它用到微波半導體場效電晶體 元件領域,也逐漸受到重視。 1230459 【内容】 有之财功率的氮鱗異_面場效電㈣的裝置,如圖1 曰乃疋在基材1〇之上生長未參雜之氮化録励―⑽高阻質蟲 曰曰層11 ’及另—層氮化銘鎵A1GaN阻擋層阻擔層12材料,讓這兩 7同的材料產生單異質接合面,在異質接合面中間會產生二維 子虱體14,這二維電子氣體可以提供一個電子移動的通道,用 來增加它導通㈣奴導輯度,因此可叫加操作時的功率輸 出’也可叫加它賴作鮮,以為高頻為波元件之用。 但是’在高功率大電流或⑽操作下,場效電晶體的源極歐 姆接觸15以及汲極歐姆接觸16,很容易造成劣化,阻值升高又再 度造成溫度_上升’如此這般之紐魏,至終將使元件失效; 因此,如何降低源極、汲極的接觸電阻,是本案之第i個目的。 其次雖然這種場效電可以在二維電子氣體通道中,增加 超作速率及增加若干電流以增大功率。但這在源極和祕之間的 薄薄-層二維電子氣體通道,是由單異#介面巾之導電能位不連 續所形成,通道寬度祕,不足輯職大的電子賴,因此如 何實質在結構上增加通道的厚度是本案之第2個目的。 至於在閘極方面,除現有之沉積一層鈍化層之外,如何利用 表面處理技術,來去除未鍵結之懸浮鍵並使之安定,以降低閘極 漏電,進而增加崩潰電壓,是本案之第3個目的。在氮化鋁鎵阻 1230459 播層的選雜_絲上,進行—個先氧化餘後,再_于姓刻 的兩段式方法來做選擇性糊,使1化銘鎵_述率增加,是本 案的第4個目的。 本發明解決之手段: 由本貫驗室先前的研究成果;如89年5月16日出版之中正 理工學院碩士論文「MOOT)生長GaN柏末特性研究」,及中華民國_ 專利公報TW5G2438中,可知道在氮化鎵高阻質蠢晶層上,生長一 層薄薄的氮化銦鎵磊晶層,因這一層氮化銦鎵能隙寬度較之氮化 鎵磊晶層能隙寬度低,較低的能隙可以造成較好^歐姆接觸,因 此可以降低源極、汲極的接觸電阻。如圖2所示,我們預計在氮 化鎵回阻質磊晶層21上面生長一層氮化銦鎵磊晶層2心可以做為 源極姆接觸層25、汲極間的歐姆接觸層26,來有效降低接觸電阻, 防止咼功率時的劣化。其次,在形成歐姆接觸的同時,它在氮化鲁 銘鎵阻擋層22和氮化鎵高阻質蠢晶層21巾間又扮演著一個雙異 貝釔構的角色24。在氮化銦鎵24的上方有一個氮化鋁鎵阻擋層 22,氮化銦鎵的下方有一個氮化鎵21高阻質磊晶層,氮化銦鎵較 之氣化鎵南阻質蟲晶層的能隙低,較氮化鋁鎵阻擋層則更低,因 此形成一個兩方有較高的能隙,中間是一個最低的能隙這樣的雙 兴質結構。也就是說在結構上,在氮化鎵高阻質磊晶層上面增加 1230459 一層氮化銦鎵的結構,可以同時解決接觸電阻,以及形成雙異質 結構通道,可改善氮化鎵功率場效電晶體的特性(本案的第丨、2 個解決手段)。 本案的第3個解決手段,乃是有關於利用硫化的方法來製作 微波場效電晶體表面閘極,用來降低它的漏電流。本實驗室在對 二五族化合物半導體做過一系列之實驗,例如1999年以 P2S5/(NH4)2Sx以及HF處理化合物半導體蕭基二極體表面,取得 較高之位障,、並發表於美國應用物理期刊JAp第86卷第Η期 馨 Ρ6261-6263 ;我們發現三五族化合物半導體經硫化處理以後有 效提高它的蕭基位障以降低漏電流,這結果也已揭示在美國專利 US6087714案及我國專利TW330344案中。另外也揭示一種在半導 體蕭基二極體表面表面上鍍-層賴哺土金屬,或其相關化合 物,或將其氧化形成閘極的絕緣層,行程MIS結構,可有效降低 漏電流,並發表於美國應用物理期刊Af>L第7〇卷四”卜•因 此。在本案中,將這兩種提高它的蕭基位障以降低漏電流技藝,_ 應用在Ιι化鎵場效電晶體上,用絲做低漏電流高輸出功率的場 效電晶體。 在氮化銘鎵阻擋層的選擇性姓刻去除上,直接進行姓刻去除 其實刻率相當慢;先進行-個絲化第製程步驟,將含有紹之氣 化銘鎵阻播層氧化後’再姓刻的兩段式方法來做選擇性姓刻,則 可增進其效率。首先將要保護的地方先用光阻,或氧切或氮化 1230459 ^等其他介咖軸;料_輪露咖後 、μ或水祕_境進行熱氧化,或氧佈植氧化等手續;氧化 ::ΓΓ:她式或電解方式崎除’以這種兩段式選:性 4,來達成精密的_效果(本案的第4個解決手段)。 【實施方式】 見有的衣作方法疋先以二氧化二銘或碳化石夕做為基材2〇,在上馨 面以瞻或VPE或職系統,視需要生長一層緩衝層(圖未表 )在緩衝層上面生長一層未換雜的氮化鎵做為高阻質蟲晶層 2卜在其上生長-層較低能隙的氮化銦鎵接_晶層24,復錄 在其上生長-層最高能_氮健鎵輯層層22 ;然、後作簡氮 化銘鎵阻擔層層的兩邊’讓中間凸起,兩邊凹下以形成源極區 及及極區’然後在其上蒸鍍金屬來形朗極肖基接觸,及源極、 沒極的歐姆接觸。在氮化鎵高阻雜晶層生長之時,若未參雜由籲 於缺陷濃度高達,,其電子遷移率會低至97或更低,若以随 流量0. 8 (Sccm/min)進行弱參雜至1〇π上,其電子遷移率會上升 至445。然後於其上生長一層薄薄的氮化銦鎵接觸蟲晶層,因這一 聽化銦鎵接觸蟲晶層能隙寬度較之肢鎵能隙寬度低,較低的 能隙可以造成較好的歐姆接觸,因此應該則可以降低源極、汲極 的接觸電阻。如圖3所示,我們麟在氮化鎵高阻轉晶層上面 1230459 生長-層含銦量為m之氮化銦鎵接觸磊晶層, 層,如圖所示含銦量為12%之1化銦鎵_,在於囉電壓 4以通過1. 5倍數的電流,有效降低接觸電阻。其次,在形成㉟ 姆接觸的同時,它在氮化_阻擒層接_晶層和 扮演著-個雙異質結構的角色24。在氮化銦録接觸蟲晶層Μ Z 方有-個氮化娜_層22,氮化銦鎵接義晶層的下方有—俩 氮化鎵21,氮化銦鎵接觸磊晶層較之氮化鎵的能隙低,較氮化2 鎵阻擔層則更低,S此形成-個兩方有較高的雜,巾間是一個 最低的能隙這樣的雙異質結構。如圖4可知,雙異質結構=造2 的能隙差異,較之異質結構可以形成電子遷移率較佳之優點,因 此能提供較佳的源極、汲極電流,可以提出較高的供電密度。其 次,傳統之氮化鎵雙異質結構,乃是以兩層氮化鋁鎵,中=夹二 層氮化鎵(未圖示);但是也如圖5可知,這種結構也將不如本案 (如圖2所示)所揭示之結構;也就是說在結構上,在氮化鎵高 阻質磊晶層上面增加一層氮化銦鎵的結構,可以同時解決接觸電 阻,以及形成雙異質結構通道,可改善氮化鎵功率場效電晶體的 輸出特性。 本案的另外一個實施例是,利用硫化的方法來製作表面閘極, 用來降低它的漏電流。本實驗室在對III—V族化合物半導體做過 硫化處理以後,能有效提高它的蕭基位障以降低漏電流,藉此來 降低它的漏電流。本案發現在製作過程中,如果能夠將其閑極高 1230459 阻值層IUb轉絲面L輕化氨的溶麟 氟硫化物可以使表面的斷鍵生成更為穩^,就能有效的降低它表 面的漏電流(在於偏塵一5伏特之時,為1〇1),平均可降低其表 面漏電流達1G倍(在於偏壓—5伏特之時,為1()-7A),較佳者可降 低達70倍左右(在於偏壓_5伏特之時,為16xl〇—%)。在更佳的 中為了去除氮化紹叙表面已經氧化這一層,可以先用稀釋 的氰氟酸加以清洗,清洗完之後再以硫化氨溶液加以浸泡,在浸 泡的過程巾射_料光加以騎,料線照射的結果可以使 表面生成一層氟硫化物,氟硫化物可以使表面的斷鍵生成更為穩 疋,可以防止漏電流的發生,因此可以使閘極的漏電流有效降低。 當然,也可以在閘極的處理過程中,在氟硫化物處理完畢之後, 先濺鍍一層稀土元素金屬,再繼續後續閘極電組之蒸鍍上或濺鍍 上,又加以氧化;或是直接鍍上稀土氧化物,使場效電晶體的結 構k成金屬絕緣半導體結構(MIS),可更有效降低漏電流達2〇〇 倍以上(在於偏壓—5伏特之時,為5χ1〇 9Α)。揭示一種在其表面 上鍍一層薄薄的稀土金屬或其相關化合物,並將其氧化形成閘極 的絕緣層,可有效降低漏電流,本案將這種技藝應用在氮化鎵場 效電晶體上,用來製做低漏電流高輸出功率的場效電晶體。 其次,在氮化鋁鎵阻擋層/氮化銦鎵之間的選擇性蝕刻去除氮化 鋁鎵阻擋層上,可進行一個先氧化後再蝕刻的方法來做選擇性蝕 刻’將要保護的地方先保護起來,將要蝕刻的地方露出來以後, 1230459 再以具有氧或财祕或水的財騎氧化,氧化以^ 再用濕式或電漿侧把它去除,用這種方絲進行兩段式選擇^ _,用兩段摘侧方法來達到比較乾淨的_效果。 本案的另-個目的,是在贿製作源極/汲極金屬接觸時,因 在回⑽程中必須姓錢化銘鎵材質,錢化紹錄材質在侧過 程中需要翻IGP-腿,它絲的侧速率不冑,修以紅流量 為 20sccm,以 BC13 流量 30sccmc,RF 功率 300W,ICP 功率 8〇⑽ 之狀況下,每分鐘之蚀刻率為100nm/min,戶斤以會造成製作時間長 久,並且選擇性不佳往往有過_之現象q因此如何有效的、快 速的做一個選擇性蝕刻,能夠持續進行製程,也是一個重要的課 題。本案採用先將高阻值層_部份,用光阻/或光阻配合沈積介 電層保護起來,再利用熱氧化的步驟將源極/汲極其上之高阻值声 進行氧化,氧化以後便可輕易用化學電解蝕刻法、電漿蝕刻、濕 式触刻或用ICP-腿侧將其去除,絲之後再來完成源極/沒極 的金屬蒸鍍過程。本案發現經過氧化以後,它的蝕刻速率可以提 高至原來的二到三倍,例如以Ar流量為20sccm,以BC13流量 3〇sccmc,RF功率300W,ICP功率800W之狀況下,每分鐘之蝕 刻率為可達200-320nm/min,對縮短製程時間有相當的幫助。] 以上所述僅為本發明之較佳實施例而已,並非用以限定本發 明之申請專利範圍;凡其它未脫離本發明所揭示之精神下所完成 之等效改變或修飾,均應包含在下述之申請專利範圍内。 1230459 【圖式簡單說明】 圖1現有之氮化蘇兴質接面場效電晶體裝置 圖2本案所揭示之氮化鎵異質接面場效電晶體裝置。 圖3雙異f結構與單異質結構之電子遷移率比較圖。 圖4氮化鎵雙異質結構與氮化銦鎵雙異質結構電子 電阻比較圖 圖5未參賴鱗與金狀接_㈣錄化銦鎵與金屬之接觸 【圖號簡單說明】 10基材。 11未参雜之氮化鎵UID-GaN高阻質磊晶層 U氮化鋁鎵mg-阻擋層阻擋層。 14單兴質接合面中間會產生二維電子氣體。 ^源極接觸金屬、16汲極接觸金屬、17 接觸 20基材。 21未芩#之氮化鎵UID-GaN高阻質磊晶層。 22氮化鋁鎵AlGaN阻擋層阻擋層。 24雙许質接合面中低能隙的氮化銦鎵接觸為晶層。 5源極接觸金屬、26汲極制金屬、27陳接觸金屬1230459 发明 Description of the invention [Technical field to which the invention belongs] The present invention is a 1-microwave-transformed hetero-junction crystal device and a method for making the same. Because of its high electronic bleaching and the densest packing = high withstand voltage, gallium nitride can produce high-efficiency field-effect transistors. Non-f is suitable for high-degree output and high-temperature operating environments. [Back to the prior art] Compound semiconductors usually have more direct and higher electron migration than discriminating conductors, and they are now very common because of Qi-Wei discrimination as a crystal field material. Among them, the most commonly used gallium-halide gold field-effect transistor 'has a phenomenon of degradation of the electron drift rate under a high electric field; High operating frequency, but compared with other compound semiconductors, there is still a lower burst under high power > Bayes voltage '| Paternity electron drift transfer; unable to meet the output power requirements, so' South Power There is still much room for development of the output microwave field effect transistor. At the same time, owing to the gallium nitride compound semiconductor secret crystal technology and the manufacturing technology of money devices, they are becoming more sophisticated. In recent years, they have been more widely used in optoelectronic semiconductor devices, especially in light-emitting 7L and f-emitting devices. Recently, gallium weird has a high breakdown voltage, and the electrons 乂 f · 夬 show its advantages, and its application in the field of microwave semiconductor field-effect transistor devices has also received increasing attention. 1230459 [Content] Nitrogen scale with a wealth of power _ surface field effect electric device, as shown in Figure 1 said that Naoya on the substrate 10 grows unmixed nitride recording excitation-⑽ high resistance mass insect The layer 11 'and another layer of gallium nitride gallium A1GaN barrier layer and barrier layer 12 materials, so that these two 7 identical materials produce a single heterojunction interface, and a two-dimensional lice body 14 will be generated in the middle of the heterojunction interface. Dimensional electronic gas can provide a channel for electron movement to increase its conductivity. Therefore, it can be called the power output during the addition operation. It can also be called as a fresh product for high frequency as a wave component. But 'under high power and high current or high voltage operation, the source ohmic contact 15 and the drain ohmic contact 16 of the field effect transistor can easily cause degradation, and the increase in resistance causes temperature_rise again. Wei will eventually make the component ineffective; therefore, how to reduce the contact resistance between the source and the drain is the i-th objective of this case. Secondly, although this field-effect electric power can increase the overshoot rate and increase the current in the two-dimensional electronic gas channel to increase the power. However, this thin-layer two-dimensional electronic gas channel between the source and the substrate is formed by the discontinuous conductive energy potential of the single-isolated #face towel. In essence, increasing the thickness of the channel in the structure is the second purpose of this case. As for the gate, in addition to the existing deposition of a passivation layer, how to use surface treatment technology to remove and stabilize unbonded floating bonds to reduce gate leakage and increase breakdown voltage is the first in this case. 3 goals. On the selective impurity wire of the aluminum gallium nitride resistance 1230459 seed layer, perform a two-stage method to make selective paste after oxidizing the remainder first, and then add a gallium oxide to increase the rate, This is the fourth purpose of this case. Means for solving the present invention: Previous research results of this laboratory; such as the research on the characteristics of growing GaN cypress in the Chung Cheng Polytechnic Institute published on May 16, 1989, and the Republic of China _ Patent Bulletin TW5G2438. It is known that a thin indium gallium nitride epitaxial layer is grown on the gallium nitride high-resistance stupid crystal layer, because the energy gap width of this layer of indium gallium nitride is lower than that of the gallium nitride epitaxial layer. A low energy gap can result in better ohmic contact, so the contact resistance of the source and drain can be reduced. As shown in FIG. 2, it is expected that a layer of indium gallium nitride epitaxial layer 2 grown on the gallium nitride resistive epitaxial layer 21 can be used as the source contact layer 25 and the ohmic contact layer 26 between the drain electrodes. It can effectively reduce the contact resistance and prevent the deterioration of the power. Secondly, while forming an ohmic contact, it also plays a role of a double-isopyrene structure between the Luminium gallium nitride barrier layer 22 and the gallium nitride high-resistance stupid crystal layer 2124. Above the indium gallium nitride 24 is an aluminum gallium nitride barrier layer 22, and below the indium gallium nitride is a gallium nitride 21 high-resistance epitaxial layer. The crystal layer has a low energy gap, which is lower than that of the aluminum gallium nitride barrier layer. Therefore, a dual structure with a higher energy gap on both sides and a lowest energy gap in the middle is formed. In other words, structurally, adding a 1230459 layer of indium gallium nitride on top of the gallium nitride high-resistance epitaxial layer can solve the contact resistance and form a double heterostructure channel at the same time, which can improve the power field effect of gallium nitride. Crystal characteristics (the first two solutions in this case). The third solution in this case is related to the use of sulfidation method to fabricate the surface gate of the microwave field effect transistor to reduce its leakage current. This laboratory has performed a series of experiments on Group II and Compound semiconductors. For example, in 1999, the surface of compound semiconductor Schottky diodes was treated with P2S5 / (NH4) 2Sx and HF to obtain higher barriers. American Journal of Applied Physics JAp Vol. 86 Issue No. Xin P6261-6263; we found that after curing the Group III compound semiconductor, it effectively increased its Schottky barrier to reduce leakage current. This result has also been disclosed in the US patent US6087714 And China's patent TW330344. In addition, a type of lanthanide metal, or its related compound, is plated on the surface of the semiconductor Schottky diode, or it is oxidized to form an insulating layer of the gate. The stroke MIS structure can effectively reduce the leakage current, and published In the American Journal of Applied Physics, Af &L; Volume 70, 4 "b. Therefore. In this case, these two techniques to improve its Schottky barrier to reduce leakage current are applied to the IlGa field-effect transistor. In the field effect transistor with low leakage current and high output power, the selective etching of the gallium nitride barrier layer is directly performed. In fact, the etching rate is quite slow; first, a silkization process is performed. Step, the two-stage method of engraving the gallium barrier layer containing Shaozhi ’s gasification ingot and then engraving it to make selective engraving can improve its efficiency. First, use the photoresist or oxygen to cut the place to be protected. Or nitriding 1230459 ^ and other other caffeine shafts; materials _ round Luka, μ or water secret _ environment for thermal oxidation, or oxygen plant oxidation and other procedures; oxidation: ΓΓ: her type or electrolytic method Qi This two-stage choice: sex 4, to achieve a precise _ effect (this The 4th solution to the case). [Embodiment] See some clothing methods: First use Dioxin or Carbide as the base material 20, on the surface of Xinxin, look at VPE or VPE or professional system. A buffer layer (not shown in the figure) needs to be grown on the buffer layer. An un-doped gallium nitride is grown on the buffer layer as a high-resistance parasite layer. 2 A layer is grown on it-a layer of indium gallium nitride with a lower energy gap. The crystal layer 24 is reproduced thereon-the layer with the highest energy _ nitrogen gallium layer layer 22; then, the two sides of the gallium nitride gallium barrier layer are made to be convex in the middle, and the two sides are recessed to form the source The polar region and the polar region 'are then vapor-deposited with metal to form a Lange Schottky contact, and an ohmic contact of the source and non-polar. During the growth of the gallium nitride high-resistance impurity crystal layer, Calling for a high defect concentration, its electron mobility will be as low as 97 or lower. If it is weakly doped to 10 π with a flow rate of 0.8 (Sccm / min), its electron mobility will rise to 445. Then a thin indium gallium nitride contact worm crystal layer is grown on it, because the indium gallium contact worm crystal layer has a lower energy gap width than the extremity gallium energy gap width. The energy gap can cause better ohmic contact, so the contact resistance of the source and the drain should be reduced. As shown in Figure 3, we grow 1230459 above the gallium nitride high-resistance crystal layer-the indium content of the layer is m of indium gallium nitride contacts the epitaxial layer. The layer, as shown in the figure, contains 12% indium gallium indium_, which lies in a voltage of 4 to pass a current of 1.5 times, effectively reducing the contact resistance. Second, At the same time as the contact formation, it plays a role of a double heterostructure in the nitriding_catch layer and the crystal layer. 24 In the nitride film contacting the worm crystal layer M Z, there is a nitride _Layer 22, below the indium gallium nitride junction layer—two gallium nitride 21, the contact gap between the indium gallium nitride epitaxial layer is lower than that of gallium nitride, and more than the 2 gallium nitride barrier layer Low, S is formed-there is a higher heterogeneity on both sides, and the double-heterostructure with the lowest energy gap between the towels. As can be seen in Figure 4, the difference in energy gap between the two heterostructures = 2 is better than that of the heterostructures, which can form a better electron mobility. Therefore, it can provide better source and sink currents, and can propose higher power supply densities. Secondly, the traditional GaN dual heterostructure is based on two layers of aluminum gallium nitride, with middle = two layers of gallium nitride (not shown); but as can be seen in Figure 5, this structure will also be inferior to this case ( (As shown in Figure 2); that is, the structure, adding a layer of indium gallium nitride on top of the gallium nitride high-resistance epitaxial layer, can solve the contact resistance at the same time, and form a double heterostructure channel , Can improve the output characteristics of GaN power field effect transistor. Another embodiment of the present case is to use a vulcanization method to fabricate a surface gate to reduce its leakage current. After the III-V compound semiconductor has been vulcanized in this laboratory, it can effectively increase its Schottky barrier to reduce leakage current, thereby reducing its leakage current. This case found that during the production process, if it can be extremely high 1230459 resistance layer IUb turn the surface L light ammonia ammonia soluble fluorosulfide can make the surface bond formation more stable ^, it can effectively reduce it The surface leakage current (10% when the dust is 5 volts) can reduce the surface leakage current by 1G times on average (1 () -7A when the bias voltage is -5 volts), preferably It can be reduced by about 70 times (16x10-% at the time of bias voltage_5 volts). In a better way, in order to remove the nitrided surface, this layer has been oxidized. It can be washed with diluted cyanofluoric acid. After cleaning, it can be soaked with ammonia sulfide solution. As a result of the irradiation of the material line, a layer of fluorosulfide can be formed on the surface, and the fluorosulfide can make the bond breaking on the surface more stable, prevent the leakage current from occurring, and therefore can effectively reduce the leakage current of the gate. Of course, during the processing of the gate electrode, after the fluorosulfide treatment is completed, a layer of a rare earth element metal is firstly sputtered, and then subsequent evaporation or sputtering of the gate electrode group is performed, and then oxidized; or Directly plated with a rare earth oxide, so that the structure of the field effect transistor becomes a metal-insulated semiconductor structure (MIS), which can more effectively reduce the leakage current by more than 200 times (at the bias voltage of -5 volts, it is 5x109). ). A thin layer of rare earth metal or its related compound is plated on its surface and oxidized to form an insulating layer of the gate electrode, which can effectively reduce leakage current. This case applies this technique to a GaN field effect transistor , Used to make field effect transistors with low leakage current and high output power. Secondly, the selective etching between the aluminum gallium nitride barrier layer / indium gallium nitride layer to remove the aluminum gallium nitride barrier layer can be performed by a method of oxidation first and then etching to perform selective etching. After protecting it, the area to be etched is exposed, and then 1230459 is oxidized with oxygen or treasure or water, and then oxidized to remove it with wet or plasma side, using this square wire for two-stage Select ^ _, and use two-section off-line method to achieve a clean _ effect. Another purpose of this case is that when bridging the source / drain metal contact, because the material must be Qian Huaming gallium in the process of rebirth, Qian Hualuo needs to turn the IGP-leg in the side process. The side velocity of the wire is not too high, and the red flow rate is 20sccm, the BC13 flow rate is 30sccmc, the RF power is 300W, and the ICP power is 80 ° C. The etching rate per minute is 100nm / min, which may cause long production time. In addition, the poor selectivity often has the phenomenon of q. Therefore, how to effectively and quickly do a selective etching and continue the process is also an important issue. In this case, the high-resistance layer _ part is first protected by a photoresist and / or a photoresist combined with a deposited dielectric layer, and then the high-resistance sound on the source / drain is oxidized by the thermal oxidation step. After the oxidation, It can be easily removed by chemical electrolytic etching, plasma etching, wet etching or ICP-leg side, and then the source / non-electrode metal evaporation process is completed after the wire. In this case, it was found that after oxidation, its etching rate can be increased to two to three times the original. For example, under the conditions of Ar flow rate of 20 sccm, BC13 flow rate of 30 sccmc, RF power of 300 W, and ICP power of 800 W, the etching rate per minute It can reach 200-320nm / min, which can help to shorten the process time. ] The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following Within the scope of the patent application. 1230459 [Brief description of the diagram] Fig. 1 A conventional field-effect transistor device of a nitrided Suxing interface Fig. 2 A field-effect transistor device of a gallium nitride heterojunction interface disclosed in this case. FIG. 3 is a comparison diagram of electron mobility between a double hetero f structure and a single hetero structure. Figure 4 Comparison of electronic resistance between gallium nitride double heterostructure and indium gallium nitride double heterostructure Figure 5 No reference to scales and gold-like contact between indium gallium and metal [Picture No.] 10 substrates. 11 Undoped gallium nitride UID-GaN high resistance epitaxial layer U aluminum gallium nitride mg-blocking layer blocking layer. 14 A two-dimensional electron gas will be generated in the middle of the single-junction interface. ^ Source contacts metal, 16 drain contacts metal, 17 contacts 20 substrates. 21 未 芩 # of gallium nitride UID-GaN high-resistance epitaxial layer. 22 aluminum gallium nitride AlGaN barrier layer barrier layer. The low-gap indium gallium nitride contact in the 24 double-mass joint interface is a crystal layer. 5 source contact metal, 26 drain metal, 27 Chen contact metal

Claims (1)

1230459 申請專利範圍 1. 一種氮化鎵場效電晶體裝置,包含:a)一基材;b)一氮化 鎵咼阻質磊晶層,安置於該基材上;c)一氮化銦鎵接觸磊 曰曰層’女置於5玄氬化鎵咼阻質蟲晶層上;d)一源極及汲極, 安置於該氮化銦鎵接觸磊晶層上,該源極及汲極定義一通 道區域’並鄰近頂表面之氮化鋁鎵阻擋層;及e)—介電層, 安置於該氮化鋁鎵阻擋層上。 2·如申請專利範圍第!項所述之裝置,其中該介電層係由氮 化矽,二氧化矽,氮氧化矽,氧化鎂及聚亞醯胺之群組中 選出之介電材料。 3·如申請專利範圍第1 J頁所述之裝置,#中該基材與氮化鎵 鬲阻質磊晶層間更包含有一緩衝層,安置於該基材上。 4. 如申請專利細第丨項職之裝置,其巾該基材係由包含 監寶石,碳化矽及氮化鎵之群組中選出之一材料所形成。 5. 如申請專利範圍第1項所述之裝置,其中裝置更包含一閘 極’安置於源極及; 及極間之阻障層上。 6·如申請專利範圍第1項所述之裝置,其中該場效電晶體係 為一金屬絕緣半導體場效電晶體,及該裝置更包含一稀土 金屬氧化物絕緣層安置於閘極下,氮化鋁鎵阻擋層之頂面 1230459 上。 7·如申凊專利範圍第1項所述之裝置,其中該氮化銘鎵阻擋 層為由摻雜η型雜質所形成。 8·如申鱗概圍第1項所述之裝置,其巾純她鎵阻擋 層為由摻雜Ρ型雜質所形成。 9·如申請專利範圍第1項所述之裝置,其中該氮化鎵高阻質 層為由摻雜弱η雜質或未參雜氮化鎵所形成。 1〇·如申請專利範圍第i項所述之裝置,其中該氮化銦録接 觸金屬矽選自鈦、金、鎳或其混合之組成者。 11· 一種氮化鎵異質接面場效電晶體裝置之製作方法,包 含:a)選用-基材;b)沉積生長一氮化録高阻質蟲晶層, 女置於忒基材上;c)復又沉積生長一氮化銦鎵接觸磊晶 層,安置於該氮化鎵高阻質磊晶層上;d)復又沉積生長一 氮化鋁鎵阻擋層,安置於該氮化銦鎵接觸屋晶層上;e)沉 積’丨電層,女置於該氮化銘鎵阻擋層上f)回飿I化銘 録阻擋層層的兩邊,讓中間凸起,兩邊凹下,以形成源極 區及汲極區;g)蒸鍍源極、汲極金屬形成歐姆接觸;h) 蒸鍍金屬形成閘極接觸。 12·如申請專利範圍第11項所述之製作方法,其中該介電 層係由氮化矽,二氧化矽,氮氧化矽,氧化鎂及聚亞醯胺 之群組中選出之介電材料。 13. 如申請專利範圍第11項所述之製作方法,其中該基材 與氮化鎵高阻質磊晶層間更包含有一緩衝層,安置於該基 材上。 14. 如申請專利範圍第11項所述之製作方法,其中該基材 係由包含藍寶石,碳化矽及氮化鎵之群組中選出之一材料 所形成。 15·如申請專利範圍第1項所述之製作方法,其中裝置更包 含一閘極,安置於源極及汲極間之阻障層上。 16·如申請專利範圍第11項所述之製作方法,其中該FET 係為一金屬絕緣半導體場效電晶體,及該裝置更包八稀 土金屬氧化物絕緣層安置於閘極下,氮化鋁鎵阻擔層之頂 面上。 17.如申請專利範圍第Π項所述之製作方法,其中該氮化 1呂鎵阻擋層為由摻雜η型雜質所形成。 18·如申請專利範圍第Η項所述之製作方法,其中該氮化 益呂I豕阻擋層為由摻雜Ρ型雜質所形成Q 19·如申請專利範圍第11項所述之製作方法,其中該氮化 叙馬阻質層為由推雜弱n雜質或未參雜質所形成。 20. 如申請專利範圍第11項所述之製作方法,其中該氮化 銦鎵接觸金屬矽選自鈦、金、鎳或其混合之組成者。 21. 如申請專利範圍第n項所述之製作方法,其中步驟h) 1230459 成間極接觸之前,更包含一硫化處 阻擋層之步驟。 22理^^專利朗第21撕狀#作找料硫化處 阻擋層之步驟’之前梗包括-氫氟酸之清洗步 驟,以去除氧化層並氟化表面。 23理觸21項所㈣物,其中硫化處 理亂化鱗阻擋層之步驟,更包括以短波長之光線照射, ί 以促進反應之發生。 録層材料之方法,包括:先魏化鱗 層材科進仃魏,再進行敍刻去除之方法。 25牛:申轉利範圍第24項所述之方法’其中舰刻去除 步驟選自濕式_或乾趣刻。 26·、登24項所述之方法,射該氧化步驟 廷自漁式氧化或乾式氧化。 27牛專利範’24項所述之方法,其愉刻去除 步驟廷自料酬魏式侧。 28步專利觸24項所述之方法,其中舰刻去除 ^ “化子蝕刎,而氮化鋁鎵層材料配置為電化學電 財的陽極’該電化學電池包括陽極、陰極及電解液;配 置该電池以造成氮化鋁層材料的蝕刻。1230459 Application Patent Scope 1. A gallium nitride field effect transistor device, comprising: a) a substrate; b) a gallium nitride gallium resist epitaxial layer disposed on the substrate; c) an indium nitride The gallium contact epitaxial layer is placed on the layer of 5 gallium argon gallium maggots; d) a source and a drain are disposed on the indium gallium nitride contact epitaxial layer, the source and the drain The pole defines a channel region 'and an aluminum gallium nitride barrier layer adjacent to the top surface; and e) a dielectric layer disposed on the aluminum gallium nitride barrier layer. 2 · If the scope of patent application is the first! The device according to the item, wherein the dielectric layer is a dielectric material selected from the group consisting of silicon nitride, silicon dioxide, silicon oxynitride, magnesium oxide, and polyimide. 3. According to the device described on page 1J of the scope of the patent application, a buffer layer is further included between the substrate and the gallium nitride gallium resist epitaxial layer in #, and the buffer layer is disposed on the substrate. 4. For a device applying for item No. 丨, the substrate of the device is made of one of the materials selected from the group consisting of gemstones, silicon carbide and gallium nitride. 5. The device according to item 1 of the scope of patent application, wherein the device further comprises a gate electrode 'disposed on the source electrode and the barrier layer between the electrodes. 6. The device according to item 1 of the scope of patent application, wherein the field effect transistor system is a metal-insulated semiconductor field effect transistor, and the device further comprises a rare earth metal oxide insulating layer disposed under the gate electrode, and nitrogen The top surface of the aluminum gallium barrier layer is 1230459. 7. The device as described in claim 1 of the patent application, wherein the gallium nitride barrier layer is formed by doping an n-type impurity. 8. The device as described in item 1 of Shen scales, wherein the pure gallium barrier layer is formed by doping P-type impurities. 9. The device according to item 1 of the scope of the patent application, wherein the gallium nitride high-resistance layer is formed by doping a weak η impurity or non-doped gallium nitride. 10. The device according to item i in the scope of the patent application, wherein the indium nitride contact metal silicon is selected from the group consisting of titanium, gold, nickel, or a mixture thereof. 11. A method for manufacturing a gallium nitride heterojunction field-effect transistor device, comprising: a) selection-substrate; b) deposition and growth of a nitride-resistant high-resistance parasite layer, and placing the female on a base material; c) depositing and growing an indium gallium nitride contact epitaxial layer on the gallium nitride high-resistance epitaxial layer; d) depositing and growing an aluminum gallium nitride barrier layer on the indium nitride Gallium contacts the crystal layer of the house; e) deposits an electric layer, and the female is placed on the gallium nitride barrier layer f) the two sides of the barrier layer are etched back, the middle is raised, and the two sides are recessed, The source and drain regions are formed; g) the source and drain metals are vapor-deposited to form an ohmic contact; h) the vapor-deposited metals form a gate contact. 12. The manufacturing method as described in item 11 of the scope of patent application, wherein the dielectric layer is a dielectric material selected from the group of silicon nitride, silicon dioxide, silicon oxynitride, magnesium oxide, and polyimide . 13. The manufacturing method according to item 11 of the scope of patent application, wherein the substrate and the gallium nitride high-resistance epitaxial layer further include a buffer layer disposed on the substrate. 14. The manufacturing method according to item 11 of the scope of patent application, wherein the substrate is formed of a material selected from the group consisting of sapphire, silicon carbide and gallium nitride. 15. The manufacturing method described in item 1 of the scope of patent application, wherein the device further includes a gate electrode disposed on the barrier layer between the source electrode and the drain electrode. 16. The manufacturing method as described in item 11 of the scope of patent application, wherein the FET is a metal-insulated semiconductor field-effect transistor, and the device further includes an eight rare earth metal oxide insulating layer disposed under the gate electrode, and aluminum nitride. The top surface of the gallium barrier layer. 17. The manufacturing method as described in item Π of the patent application scope, wherein the nitride nitride 1 gallium barrier layer is formed by doping an n-type impurity. 18. The manufacturing method described in item (1) of the scope of the patent application, wherein the nitride nitride I 吕 barrier layer is formed by doping a P-type impurity Q 19. The manufacturing method described in item (11) of the scope of patent application, Wherein, the nitrided silicon horse resistive layer is formed by doping with weak n impurities or non-reference impurities. 20. The manufacturing method according to item 11 of the scope of patent application, wherein the indium gallium nitride contact metal silicon is selected from the group consisting of titanium, gold, nickel, or a mixture thereof. 21. The manufacturing method as described in item n of the scope of patent application, wherein step h) 1230459 further comprises a step of curing a barrier layer before making interphase contact. 22 理 ^^ Patents 朗 第 21 泪 状 # as the material to find the vulcanization place. The step of the barrier layer 'includes a step of washing with hydrofluoric acid to remove the oxide layer and fluorinate the surface. The 23 steps touch the 21 items, in which the step of vulcanizing and dissolving the scale barrier layer further includes irradiating with short-wavelength light to promote the occurrence of the reaction. The method of recording layer materials includes: firstly weaning the scales and layering materials into the Wei Dynasty, and then performing the method of engraving and removing. 25 cattle: The method described in item 24 of the Shen Zhuanli range, wherein the step of removing the ship engraving is selected from wet _ or dry fun engraving. 26. The method as described in item 24 above, in which the oxidation step is performed by self-fishing oxidation or dry oxidation. The method described in item 27 of the 27th patent patent method, wherein the step of removing it is self-remunerated. The 28-step patent touches the method described in item 24, wherein the carrier is removed by chemical etching, and the aluminum gallium nitride layer material is configured as an anode of an electrochemical power source. The electrochemical cell includes an anode, a cathode, and an electrolyte; The cell is configured to cause etching of the aluminum nitride layer material.
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