201206280 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種印刷電路板及其製造方法 【先前技術】 因此對小型印 近來電子產品趨向迷你化、組裝化且小體積 刷電路板的需求隨之增加。 、201206280 VI. TECHNOLOGICAL FIELD OF THE INVENTION [Technical Field] The present invention relates to a printed circuit board and a method of manufacturing the same. [Prior Art] Therefore, there is a demand for miniaturized electronic products that are miniaturized, assembled, and small-sized brush boards. It will increase. ,
也因此增加了對内含晶片的嵌入式印刷電路板的需求。 嵌入式印刷電路板的製造過程包括―個將叙在印刷電路板 的晶片與印刷板之線路圖案（drcuitpattem)連接的步驟。 該晶片可包含裸晶和晶圓級封裝晶片，而晶圓級封裝 晶片可從在裸晶形成—重分配絲取得。就裸晶而言，連接至外 電路或令件的連接端子太小’而且連接端子間的間距(娜)很 窄^而«與線_轉接。鱗決關題而擁紅另外形 成重刀配層。但疋由於形成此重分配層需要額外製程，製造過 程複雜化且產量低，製造成柄而增加。 口此而要開《種製造印刷電路板的方法，使印刷電路板利 用裸晶即可將連接端子齡卜部電路或零件連接。 201206280 【發明内容】 【技術問題】 印刷電路板以及製造 本發明一實施例提供具有新穎結構的 該印刷電路板的方法。 本發明一實施例提供一印刷電路板 片與__雜。 單程序可以將晶 【解決方案】 Ο 恭Γ康本發明—實施例，—卩刷轨板㈣造方法包括準備 一载體具有-第-金屬層；在第—金屬層安裝—晶片·利用一導 線將晶片的連接端子與第-金屬層連接；在第—金屬層以及晶片 上形成-絕緣層及在第-絕緣層形成_第二金屬層；移除載體； 以及形成包括-連接線路圖案的—第―線路圖案及藉由選擇性移 除弟一和第二金屬層的一第二線路圖案。 根據本發明—實施例，—種印刷電路板包括具有-連接線路 圖案的—第一線路圖案;在第-線路圖案上的-晶片；將晶片的 連接端子與連接線路圖案連結的—導線；晶片上的—第一絕緣層 和第-線路圖案，第—絕緣層因此環繞該晶片；以及在第一絕緣 層上的一第二線路圖案。 【有利效應】 本發明-貫施例提供具有新穎結構的一印刷電路板以及製造 該印刷電路板的方法。 201206280 本發明-實_提供-印·路板經由—簡單程序可以將晶 片= 線路圖案連接，即使晶片的連接端子很小、線路圖案的間距 ㈣’以及—種製造該印刷電路板的方法。 【實施方式】 必須說明在實施例的說明中，當指明一層(或膜)、區域、圖案、 或是-架構是在另—個基板、_、區域、墊狀物、或佈線「之 或「之下」，則其可岐「直接」或「間接」在這另—個基板、 薄膜、區域、墊狀物、或佈線上，或者可能呈現—個以上的中間 層。再者’每一層是在「之上」或「之下」依據圖形而決定。 為求方便、，月0析’圖形所示每一層的厚度與大小，可能被誇 大、省略或是以示意_製。另外，圖中零件大小並不完全反映 實際的大小。 圖1至11為根據本發明實施例的印刷電路板以及該印刷電路 板製造方法的剖視圖。 圖11所不的印刷電路板是根據實施例的方法而製成。 爹閱圖11，印刷電路板包含具有一連接線路圖案85的一第 一線路圖案80、附著在第一線路圖案8〇的一晶片4〇 '將晶片如 的-連接端子41鱗接祕随85相連的—導線(wire)25曰 日白 片40和第-線路圖案80上形成的一第一絕緣層5〇、在第〜絕緣 層50上形成的一第二線路圖案81、通過第一絕緣層5〇以電性連 接第一線路圖案80至第二線路圖案81的一第一傳導孔口、在第 201206280 一線路圖案80、在第一和第二線路圖案80, 81和第一傳導孔Ή 上形成的一第二絕緣層90、在第二絕緣層90形成的一第三線路圖 案120以及用來將第一和第二線路圖案80, 81連接至一第三線路 圖案120的一第二傳導孔110。 導線25與連接線路圖案85接合。連接線路圖案85可包括與 第一線路圖案80完全一致的材質。 除此之外，可在第一線路圖案80形成—位置決定孔21。位 置決定孔21可作為偵測晶片40對齊位置以及導線25接合位置的 基準標 §己（fiducial mark )。 晶片40可對齊—黏著層3〇。該黏著層3〇與第一線路圖案别 和第二絕緣層90之至少一者接觸。黏著層3〇的面積可大於 40 ° 、 ' Q 至第一線路圖案80。 凸mr騎挪輸娜。叫，細向上 侧。導㈣㈣齊的黏著㈣ 第—部份位於晶片40之上、而延伸。導㈣具有一 第三部份則位於晶片40的外側=伤位於晶以0之下以及一 至少一部份的第二絕緣M 1巴緣層50職導線25。 第二絕緣層9G*帛傳.# 9⑽與轉層30接觸，且一部份的 /、弟—傳導孔71對齊。 7 201206280 以下將詳細描述根據實施例而定的印刷電路板及其製造方 法，並參閱圖1至11。 參閱圖1，準備形成有第一金屬層20的戟體1〇。例如，第一 金屬層20至少包括銅、錫、鋁、鎳、金、或銀的其中一種。 可在載體10的全部區域範圍形成第一金屬層2〇。 可經由濺鍍、電鍍或堆疊的過程，在載體1〇形成第一金屬層 20。 9This has also increased the need for embedded printed circuit boards containing wafers. The manufacturing process of the embedded printed circuit board includes a step of connecting a wafer of the printed circuit board to a circuit pattern of the printed board. The wafer can include bare die and wafer level packaged wafers, while wafer level packaged wafers can be obtained from die-forming redistribution wires. In the case of bare crystal, the connection terminals connected to the external circuit or the actuator are too small' and the spacing between the connection terminals (N) is narrow and the line is switched. The scales are related to the problem and the red is formed into a heavy knife. However, since the formation of this redistribution layer requires an additional process, the manufacturing process is complicated and the yield is low, and the manufacturing is increased. Therefore, it is necessary to open a method for manufacturing a printed circuit board, so that the printed circuit board can be connected to the circuit or the part of the connection terminal using the bare crystal. [062] [Technical Problem] Printed Circuit Board and Manufacturing An embodiment of the present invention provides a method of the printed circuit board having a novel structure. One embodiment of the present invention provides a printed circuit board and __. Single program can be used for crystal [solution] Γ Γ Γ 本 本 本 本 本 本 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本a wire connecting the connection terminal of the wafer to the first metal layer; forming an insulating layer on the first metal layer and the wafer; forming a second metal layer on the first insulating layer; removing the carrier; and forming a pattern including the connection line a first line pattern and a second line pattern by selectively removing the first and second metal layers. According to the present invention, a printed circuit board includes a first line pattern having a connection line pattern, a wafer on the first line pattern, a wire connecting the connection terminal of the wafer and the connection line pattern, and a wafer. And a first insulating layer and a first wiring pattern, the first insulating layer thus surrounding the wafer; and a second wiring pattern on the first insulating layer. [Advantageous Effects] The present invention provides a printed circuit board having a novel structure and a method of manufacturing the printed circuit board. 201206280 The present invention can provide a wafer = line pattern via a simple program, even if the connection terminals of the wafer are small, the pitch of the line pattern (4), and the method of manufacturing the printed circuit board. [Embodiment] It should be noted that in the description of the embodiment, when a layer (or film), a region, a pattern, or a structure is specified on another substrate, _, region, pad, or wiring "or" Underneath, it may be "directly" or "indirectly" on another substrate, film, area, mat, or wiring, or may present more than one intermediate layer. Furthermore, each layer is determined by "above" or "below" depending on the graphics. For the sake of convenience, the thickness and size of each layer shown in the figure may be exaggerated, omitted, or illustrated. In addition, the size of the parts in the figure does not fully reflect the actual size. 1 to 11 are cross-sectional views showing a printed circuit board and a method of manufacturing the printed circuit board according to an embodiment of the present invention. The printed circuit board shown in Fig. 11 is made according to the method of the embodiment. Referring to FIG. 11, the printed circuit board includes a first line pattern 80 having a connection line pattern 85, and a wafer 4' attached to the first line pattern 8'' to connect the wafer to the connection terminal 41. Connected wires 25 and a first insulating layer 5 formed on the first line pattern 80, a second line pattern 81 formed on the first insulating layer 50, through the first insulation The layer 5 〇 electrically connects the first line pattern 80 to a first conductive aperture of the second line pattern 81, at a 201206280 line pattern 80, at the first and second line patterns 80, 81 and the first conductive hole a second insulating layer 90 formed on Ή, a third line pattern 120 formed on the second insulating layer 90, and a first portion for connecting the first and second line patterns 80, 81 to a third line pattern 120 Two conductive holes 110. The wire 25 is joined to the connection wiring pattern 85. The connection line pattern 85 may include a material that is completely identical to the first line pattern 80. In addition to this, the position determining hole 21 can be formed in the first line pattern 80. The position determining hole 21 serves as a fiducial mark for detecting the alignment position of the wafer 40 and the bonding position of the wires 25. The wafer 40 can be aligned - the adhesive layer 3 〇. The adhesive layer 3 is in contact with at least one of the first line pattern and the second insulating layer 90. The area of the adhesive layer 3 可 may be greater than 40 °, 'Q to the first line pattern 80. The convex mr rides and moves to Na. Called, fine up side. Guide (4) (4) Adhesion (4) The first portion is located above the wafer 40 and extends. The fourth (4) portion has a third portion located on the outer side of the wafer 40. The second insulating M1 pad layer 50 is located below the wafer and the at least one portion of the second insulating M1 pad layer 50. The second insulating layer 9G*帛传.# 9(10) is in contact with the layer 30, and a part of the /, the conduction hole 71 is aligned. 7 201206280 A printed circuit board and a method of manufacturing the same according to the embodiment will be described in detail below, and reference is made to Figs. Referring to FIG. 1, a body 1〇 in which the first metal layer 20 is formed is prepared. For example, the first metal layer 20 includes at least one of copper, tin, aluminum, nickel, gold, or silver. The first metal layer 2 can be formed over the entire area of the carrier 10. The first metal layer 20 may be formed on the carrier 1 through a process of sputtering, plating or stacking. 9
載體10的材質可包括金屬或樹脂。可利用與第—金屬層2〇 不同的材質形成载體1〇。 參閱圖2，選擇性移除第-金屬層2〇以形成位置決定孔21 位置妓孔21提供了判定第—線路圖㈣位置、在印刷電路板 上形成連接線路圖案85、以及晶片4〇附著位置等的測量標準 (yardstick) °The material of the carrier 10 may include a metal or a resin. The carrier 1 can be formed using a material different from the first metal layer 2〇. Referring to FIG. 2, the selective removal of the first metal layer 2 to form the position determining hole 21 is provided. The position of the hole 21 provides the determination of the position of the first line (four), the formation of the connecting line pattern 85 on the printed circuit board, and the adhesion of the wafer 4 Measurement standard for position, etc. (yardstick) °
(未顯 20 „為形成位置歧孔21，在第—金屬層20上形成-光阻圖案 不）’利用此光阻圖案為光罩，而選擇性的餘刻第一金屬層 ，Γ如’可以在第一金屬層20的外部周邊形成位置決定孔21 ^ 二位蝴孔21可以在稍後形成第一線路圖㈣的地 21 f。取好是在第—線路_ 8G的外部周邊形成位置決定孔 17叫見應用狀況而改變位置決定孔21的位置。 參閱圖3，在第-金屬層2〇上形成黏著層3〇，晶片4〇則附 201206280 者在黏著層30。黏著層3〇的區域範圍可大於晶片4〇。 吳雖朗3顯示在第—蝴如局部獅著⑽，但是如 果必要醜可抑-金顧2Q的所魏卿雜著層加。 利用具有黏性特質的物質，例如環氧樹脂或祕樹月旨，形成 層30。 黏著層30 Ο Ο ^ 40可包括裸晶、從在裸晶上形成重分佈層而得的晶圓級 =日日片、或是可以透過引線搭接方法(咖⑽咖s 與外部裝置連接的各類晶片。 晶片40包括將其以電性連接至外部電路或是元件的連 子41。 可根據位置決定孔21而判定晶片4〇的附著位置。更詳細地 說，在晶片4G的附著位置形成黏著層3()，而晶片4q附著位置3 根據位置決定孔21而事先設計’之後晶片4〇附著在黏著層^ 參閱圖4 ’晶片4G的連接端子4卜經由導線25，而與第一 金屬層2G連接。根據位置決定孔21而判定導線25在第—金屬層 上的接合(bonding)位置。 曰 連接至導線25的第-金屬層20，被標稱為連接線路圖案阳， 稍後將詳細敘述。 根據相關技術，為了將晶片與線路圖案連接，在晶片與線路 圖案之間的一絕緣層形成一傳導孔。 然而，如上所述’晶片40可包括裸晶、從在裸晶上形成重分 201206280 ( 佈=而件的圓級聰晶片、较可以透過引線搭接方法而與外 部裝置連接的各類晶片。如果以裸晶做晶片4〇，則晶片4〇的連接 端子^之間的間距過窄（大約15〇微米或更小），而且連接端子 41的見度太小（大約⑽微求或更小），因此不易形成將晶片仙 與外部電路或元件連接的傳導孔。 、根據相隱術，為解紅簡題，在裸晶上_額外步驟形 〇成重分佈層，而使晶片與外部電路或元件連接，軸如 低其效率。 、但是根據實施例，晶片4〇的連接端子41經由導線25而電性 連接至第-金屬層20，因此即使晶片4〇是裸晶，還是可以做到電 十生連接。換句話說，形成再分配層以及傳導孔的額外程序可以省 . 略，製造過程因而簡化而且改善效率。 製造導線25的材料至少包括銅、錫、叙、錄、金、或銀的其 〇 中-種。 參閱圖5,在第一金屬層20和晶片仙上準備B-狀態(B—stage) 的絕緣層5G ;在第-絕緣層5G上準備第二金屬層。 第一絕緣層50圍繞第一金屬層2〇和晶片4〇頂部的表面，而 且包含-個高度符合晶片40高度的第一層51，以及蓋住晶片4〇 和第-層51頂部表面的第二層52。除此之外亦可提供複數個第一 層51和第二層52。 使用具有黏著性和絕緣特性的材料形成第一絕緣層5〇。例 10 201206280 如第絕緣層可包括如環氡樹脂或紛搭樹脂的樹脂材料。另外， 第一絕緣層50可包括預浸材料(prepreg)、聚醯亞胺(ployimide) 薄膜、或是氟化氫銨(ABF)薄膜。亦即，可第一絕緣層50可以根 據應用而包含多種材料。 使用至少含有銅、錫、鋁、鎳、金、或銀其中一種的材料形 成弟一金屬層60。 〇 參閱圖6 ’利用加熱和加壓，將B-狀態第一絕緣層50和在其 上的第二金屬層60與第一金屬層20和晶片40壓緊。之後，在第 —絕緣層5Q上加熱I·料線，使其HHWcured)。 一由於第—絕緣層50是以半固化狀態（B—狀態）形成，因此當 第—金屬層和第一絕緣層50緊壓第一金屬層20和晶片40時，導 線25可以形成在晶片4〇和第一金屬層2〇而不會受損。 因此，導線25因穿過第一絕緣層5〇❿延伸，將晶片4〇的連 Ο 接端子41連接至第一金屬層20。 參閱圖7，移除載體丨〇，且形成穿過第一金屬層20、第二金 _層6〇、以及第一絕緣層50的第-傳導孔71。 形成第-傳導孔71，使得在印刷電路板頂部及底部表面的線 路圖案得以通電。 _人為形成第—傳導孔7卜雷射穿孔穿過第-金屬層20、第 I屬層60、以第—絕緣層50形成一貫孔(Viah〇le)7〇，並將其 11 201206280 在電鍍的過程進行一非雷 、/ ，JCV%(electroless plating process)而形成一種子層， _ ^ a 便進行電鍍的步驟。 爹閱圖8，選擇性移除第— 丄咕. 金屬層20和第二金屬層60，以形 成第一線路圖案80和第二崎 、、裏路圖案81。第一線路圖案80包括該 連接線路圖案85。 為形成第一線路圖案8〇、證_ 、 年一線路圖案81、以及連接線路圖 案85，在第一金屬層、第二^ ^ 〇 _ 嚴屬層60上形成一光阻圖案（未 而在第一金屬層20和第二 顯示），之後利用此光阻圖案為光罩， 金屬層60進行蝕刻。 根據位置決定孔21而決定第1路_8〇、第二祕_ - 81、以及連接線路圖案85的位置。 在有導線25連接的區域形成連接線路圖案85，使其可以透 過導線25而與晶片40的連接端子41進行電性連接。 〇 由於第一線路圖案80、第二線路圖案8卜和連接線路圖案 85是藉由選擇性移除第一金屬層2〇而同時形成的，製造過程因而 簡化。 參閱圖9 ’在第-線路圖案8Q、第二線路圖㈣、以及第一 傳導孔71上形成第二絕緣層90 ;在第二絕緣層9〇上形成第三金 屬層100。 使用與第-絕緣層5Q相同的材料建立第二絕緣層⑽，為避 免多餘可因此省略細節描述。 12 201206280 為形成第二絕緣層90以及第z：本 ⑽立十 〜I屬層100,在第一線路圖案 80和弟二線路圖案81準備B〜狀態第_ 〜弟一絕緣層9〇,且在第二絕緣 層90上準備第三金屬層100。之後葬 積由加熱和加壓，將B-狀態第 二絕緣層90和第三金屬層1〇〇與第—φ 乐線路圖案80、第二線路圖案 81和傳導孔71塵緊。之後將第二絕緣層9〇固化。 第三金屬層100的材質可以和第—金屬層2〇和第二金屬層 60相同。(There is no 20 „to form the positional aperture 21, formed on the first metal layer 20-the photoresist pattern is not) 'Using this photoresist pattern as a mask, and selectively engraving the first metal layer, such as ' The position determining hole 21 may be formed on the outer periphery of the first metal layer 20. The second hole 21 may form the ground 21 f of the first wiring pattern (4) later. The position is formed at the outer periphery of the first line _ 8G. It is determined that the hole 17 is called the application state and the position of the position determining hole 21 is changed. Referring to Fig. 3, an adhesive layer 3 is formed on the first metal layer 2, and the wafer 4 is attached to the 201206280 adhesive layer 30. The adhesive layer 3 The area of the area can be larger than the wafer 4〇. Wu Danglang 3 is shown in the first butterfly as a local lion (10), but if necessary, the ugly can be suppressed - Jin Gu 2Q's Wei Qing mixed layer. Use the substance with sticky characteristics For example, epoxy resin or secret tree, forming layer 30. Adhesive layer 30 Ο Ο ^ 40 may include bare crystal, wafer level = day film formed by forming a redistribution layer on the bare crystal, or may Through the wire bonding method (coffee (10) coffee s connected to various types of wafers external devices. The wafer 40 includes The connection 41 electrically connected to the external circuit or the element can be determined according to the position determining hole 21, and in more detail, the adhesive layer 3 () is formed at the attachment position of the wafer 4G, and the wafer The 4q attachment position 3 is designed in advance according to the position determining hole 21, and the wafer 4 is attached to the adhesive layer. Referring to Fig. 4, the connection terminal 4 of the wafer 4G is connected to the first metal layer 2G via the wire 25. The hole is determined according to the position. The bonding position of the wire 25 on the first metal layer is determined. The first metal layer 20 connected to the wire 25 is referred to as a connecting line pattern yang, which will be described later in detail. The wafer is connected to the wiring pattern, and a conductive hole is formed in an insulating layer between the wafer and the wiring pattern. However, as described above, the wafer 40 may include a bare crystal, and a weight is formed on the bare crystal 201206280 (cloth = The round wafer wafer, the various types of wafers that can be connected to the external device through the wire bonding method. If the wafer is made of bare crystal, the pitch between the connection terminals ^ of the wafer 4 is too narrow (about 15 〇). micro- Meters or less), and the visibility of the connection terminal 41 is too small (about (10) or less), so it is difficult to form a conductive hole that connects the chip to an external circuit or component. On the bare die, an additional step is formed into a redistribution layer, and the wafer is connected to an external circuit or component, and the axis is as low as its efficiency. However, according to the embodiment, the connection terminal 41 of the wafer 4 is electrically connected via the wire 25. It is connected to the first metal layer 20, so that even if the wafer 4 is bare, it is possible to make an electrical connection. In other words, an additional procedure for forming the redistribution layer and the conduction holes can be omitted, and the manufacturing process is simplified. Improve efficiency. The material from which the wire 25 is made includes at least the copper, tin, Syrian, gold, or silver. Referring to FIG. 5, a B-stage insulating layer 5G is prepared on the first metal layer 20 and the wafer, and a second metal layer is prepared on the first insulating layer 5G. The first insulating layer 50 surrounds the surface of the first metal layer 2 and the top of the wafer 4, and includes a first layer 51 having a height corresponding to the height of the wafer 40, and a cover covering the top surface of the wafer 4 and the first layer 51. Second floor 52. In addition to this, a plurality of first layers 51 and second layers 52 may be provided. The first insulating layer 5 is formed using a material having adhesive properties and insulating properties. Example 10 201206280 The insulating layer may include a resin material such as a cyclic resin or a versatile resin. In addition, the first insulating layer 50 may include a prepreg, a floimimide film, or an ammonium hydrogen fluoride (ABF) film. That is, the first insulating layer 50 can comprise a plurality of materials depending on the application. A metal layer 60 is formed using a material containing at least one of copper, tin, aluminum, nickel, gold, or silver. ’ Referring to Fig. 6', the B-state first insulating layer 50 and the second metal layer 60 thereon are pressed against the first metal layer 20 and the wafer 40 by heat and pressure. Thereafter, the I·feed line is heated on the first insulating layer 5Q to be HHWcured). Since the first insulating layer 50 is formed in a semi-cured state (B-state), when the first metal layer and the first insulating layer 50 are pressed against the first metal layer 20 and the wafer 40, the wires 25 may be formed on the wafer 4. The crucible and the first metal layer 2 are not damaged. Therefore, the wire 25 is extended to the first insulating layer 5, and the connecting terminal 41 of the wafer 4 is connected to the first metal layer 20. Referring to Figure 7, the carrier crucible is removed and a first via hole 71 is formed through the first metal layer 20, the second metal layer 6, and the first insulating layer 50. The first conductive holes 71 are formed so that the line patterns on the top and bottom surfaces of the printed circuit board are energized. _ artificially forming the first conductive hole 7 by laser perforation through the first metal layer 20, the first genus layer 60, the first insulating layer 50 to form a uniform hole (Viah〇le) 7 〇, and its 11 201206280 in electroplating The process proceeds to a non-Ray, /, JCV% (electroless plating process) to form a sub-layer, _ ^ a to carry out the step of electroplating. Referring to Fig. 8, the first metal layer 20 and the second metal layer 60 are selectively removed to form a first line pattern 80 and a second pattern, a road pattern 81. The first line pattern 80 includes the connection line pattern 85. In order to form the first line pattern 8 〇, the _ _ , the year line pattern 81 , and the connection line pattern 85 , a photoresist pattern is formed on the first metal layer and the second 严 严 严 层 layer 60 (not in the The first metal layer 20 and the second display) are then etched using the photoresist pattern as a mask. The positions of the first path _8 〇, the second secret _ - 81 , and the connection line pattern 85 are determined based on the position determining hole 21 . The connection wiring pattern 85 is formed in a region where the wires 25 are connected so as to be electrically connected to the connection terminals 41 of the wafer 40 through the wires 25.制造 Since the first line pattern 80, the second line pattern 8 and the connection line pattern 85 are simultaneously formed by selectively removing the first metal layer 2, the manufacturing process is thus simplified. Referring to Fig. 9', a second insulating layer 90 is formed on the first wiring pattern 8Q, the second wiring pattern (4), and the first conductive via 71; and a third metal layer 100 is formed on the second insulating layer 9?. The second insulating layer (10) is formed using the same material as the first insulating layer 5Q, and the detailed description may be omitted to avoid redundancy. 12 201206280 In order to form the second insulating layer 90 and the z: the (10) tenth to the first genus layer 100, the first line pattern 80 and the second line pattern 81 are prepared in the B~ state _ _ _ an insulating layer 9 〇, and The third metal layer 100 is prepared on the second insulating layer 90. Thereafter, the B-state second insulating layer 90 and the third metal layer 1A are dusted by the heating and pressurization to the first φ line pattern 80, the second line pattern 81, and the conductive holes 71. The second insulating layer 9 is then cured. The material of the third metal layer 100 may be the same as that of the first metal layer 2 and the second metal layer 60.
參閱圖1〇,形成第二傳導孔⑽而將第-線路圖案80和第 二線路圖案81電性連接至第三金屬層1卯。 為形成第二傳導孔11Q’建立—貫孔(viahQie)(未顯示） 穿過第二絕緣層90，且對此貫孔進行電鍍。 參閱圖11 ’選擇性的將第三金屬層_多除以形成第三線路 圖案120。 〇 形成第三線路_12G的程序與形成第-線關細和第二 線路圖案81相似’為避免多餘因而省略其細節描述。 與此同時’視印刷電路板上的電路而決定重覆或省略在第一 至第三線路圖案80、81、120間形成第—和第二絕緣層5〇、9〇的 程序。此外，可在實施例的範圍内修改此程序。\ 之後在第三線路圖案12〇形成一防焊（solder mask)和焊球 (solder ball) ’使得_電路板可以與其它電路、元件或基板連 接。 13 201206280 以上雖然已描述了示範本發明的實施例，但必須了解這些示 範的實施例不應限制目前的發明，而且在以下本發明所中料利 勺精神契fe®内、可’由㈣鱗的驗進行各種各樣的變化 和改動。 【產業適用性】 本發明係可應用至—錄。， 種卩刷電路減製造該_電路板的方Referring to Fig. 1A, a second conductive via (10) is formed to electrically connect the first line pattern 80 and the second line pattern 81 to the third metal layer 1''. A via hole (not shown) is formed through the second insulating layer 90 for forming the second conductive via 11Q', and the via hole is plated. Referring to Fig. 11, 'the third metal layer_ is selectively divided to form a third line pattern 120.程序 The procedure for forming the third line _12G is similar to the formation of the first line line and the second line pattern 81'. To avoid redundancy, the detailed description thereof is omitted. At the same time, the procedure of forming the first and second insulating layers 5A, 9B between the first to third line patterns 80, 81, 120 is repeated or omitted depending on the circuit on the printed circuit board. Moreover, this procedure can be modified within the scope of the embodiments. Then, a solder mask and a solder ball are formed in the third line pattern 12, so that the board can be connected to other circuits, components or substrates. 13 201206280 Although the embodiments of the present invention have been described above, it is to be understood that these exemplary embodiments should not limit the present invention, and that in the following embodiments of the present invention, it is possible to use the "four" scales. The test carries a variety of changes and changes. [Industrial Applicability] The present invention is applicable to recording. , the type of brush circuit minus the side of the circuit board
【圖式簡單說明】 圖1至11為根據本發明實施 造方法的剖視圖。 、印刷電路板以及該印刷電路板製 【主要元件符號說明】BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1 to 11 are cross-sectional views showing a method of fabricating according to the present invention. , printed circuit board and the printed circuit board system [main component symbol description]
20 21 25 30 40 41 载體 第—金屬層 位置決定孔 導線 黏著層 晶片 連接端子 第一絕緣層 50 201206280 51 52 60 70 71 8020 21 25 30 40 41 Carrier First—metal layer Position determining hole Conductor layer Wafer Connection terminal First insulation layer 50 201206280 51 52 60 70 71 80
81 85 90 100 110 120 第一層 第二層 第二金屬層 貫孔 第一傳導孔 第一線路圖案 第二線路圖案 連接線路圖案 第二絕緣層 第三金屬層 第二傳導孔 第三線路圖案81 85 90 100 110 120 First layer Second layer Second metal layer Through hole First conduction hole First line pattern Second line pattern Connection line pattern Second insulation layer Third metal layer Second conduction hole Third line pattern
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