TWI431748B - Microelectronic assembly with impedance controlled wirebond and conductive reference element - Google Patents
Microelectronic assembly with impedance controlled wirebond and conductive reference element Download PDFInfo
- Publication number
- TWI431748B TWI431748B TW099107377A TW99107377A TWI431748B TW I431748 B TWI431748 B TW I431748B TW 099107377 A TW099107377 A TW 099107377A TW 99107377 A TW99107377 A TW 99107377A TW I431748 B TWI431748 B TW I431748B
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- conductive
- microelectronic
- microelectronic assembly
- contacts
- electrically conductive
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Description
微電子晶片通常係具有相對面向之大體平坦前表面及後表面之扁平體,其中在此等表面之間有邊緣延伸。晶片通常在前表面上具有電連接至晶片內之電路之觸點,有時亦稱作墊或接合墊。通常藉由用一適合之材料包圍晶片以形成具有電連接至晶片觸點之端子之微電子封裝來封裝該等晶片。然後,可將該封裝連接至測試設備以確定該經封裝之裝置是否符合一期望效能標準。一旦經測試,該封裝就可藉由通過一適合之連接方法(例如焊接)將該等封裝端子連接至一印刷電路板(PCB)上之匹配銲盤而連接至一較大電路(例如一電子產品(例如一電腦或一蜂巢式電話)中之一電路)。Microelectronic wafers typically have a flat body with generally flat front and back surfaces that face oppositely with an edge extending between the surfaces. Wafers typically have contacts on the front surface that are electrically connected to circuitry within the wafer, sometimes referred to as pads or bond pads. The wafers are typically packaged by surrounding the wafer with a suitable material to form a microelectronic package having terminals electrically connected to the wafer contacts. The package can then be connected to a test device to determine if the packaged device meets a desired performance criteria. Once tested, the package can be connected to a larger circuit (eg, an electronic device by connecting the package terminals to a mating pad on a printed circuit board (PCB) by a suitable bonding method (eg, soldering). A circuit in a product (such as a computer or a cellular phone).
可在晶圓層級處製備微電子封裝;亦即,在晶片或晶粒仍處於一晶圓形式時製備構成封裝之外殼、終端及其他特徵。在晶粒已形成之後,晶圓經受若干個額外製程步驟以在晶圓上形成封裝結構,且然後切分該晶圓以釋放個別經封裝之晶粒。晶圓層級處理可係一有效率之製備方法,此乃因可將每一晶粒封裝之佔用面積製成與該晶粒本身之大小相同或幾乎相同,從而導致對經封裝之晶粒所附接至的印刷電路板上之面積之極有效率之利用。The microelectronic package can be fabricated at the wafer level; that is, the outer casing, termination, and other features that make up the package are made while the wafer or die is still in the form of a wafer. After the dies have been formed, the wafer is subjected to a number of additional processing steps to form a package structure on the wafer, and then the wafer is diced to release the individual encapsulated dies. Wafer level processing can be an efficient method of fabrication because the footprint of each die package can be made the same or nearly the same as the die itself, resulting in the attachment of the packaged die. Extremely efficient use of the area on the printed circuit board.
用於形成一微電子晶片與一個或多個其他電子部件之間的導電連接之一常用技術係藉由引線接合。按傳統,一引線接合工具使用熱及/或超聲波能量將一引線之末端附接至一微電子晶片上之一墊且然後將該引線圈接至另一電子部件上之一觸點且使用熱及/或超聲波力形成至彼處的一第二接合。One common technique for forming an electrically conductive connection between a microelectronic wafer and one or more other electronic components is by wire bonding. Conventionally, a wire bonding tool attaches the end of one lead to one of the pads on a microelectronic wafer using heat and/or ultrasonic energy and then connects the lead coil to one of the contacts on the other electronic component and uses heat And/or an ultrasonic force is formed to a second junction there.
發明者已認識到,引線接合技術之問題中之一者係沿一引線之電磁傳輸可延伸至該引線周圍之空間中,從而在鄰近導體中感應出電流並導致不需要的輻射且使線路失諧。引線接合通常亦經受自身感應且經受外部雜訊(例如,來自鄰近電子部件)。最終,此產生電阻抗問題。隨著微電子晶片及其他電子部件上之觸點之間的間距變得更小,隨著晶片在更高頻率下運作且隨著對多個原始墊之使用變得更普遍,此等問題可變得更嚴重。The inventors have recognized that one of the problems with wire bonding techniques is that electromagnetic transmission along a lead can extend into the space around the lead, thereby inducing current in adjacent conductors and causing unwanted radiation and causing loss of the line. Harmony. Wire bonding is also typically subjected to self sensing and is subject to external noise (eg, from adjacent electronic components). Ultimately, this creates an electrical impedance problem. As the spacing between contacts on microelectronic wafers and other electronic components becomes smaller, as the wafers operate at higher frequencies and become more prevalent as the use of multiple original pads becomes available, such problems can Become more serious.
針對一微電子總成本文闡述其各種結構及製造技術。根據一項實施例,一微電子總成包括引線接合至一個或多個互連元件(例如,微電子子總成,例如一基板、晶片載體、帶等)之一微電子裝置。在一項實施例中,該微電子裝置與該一個或多個其他互連元件之間的引線接合係使用一絕緣引線而形成。該絕緣引線可係具有一絕緣護皮之一引線,例如可藉由用一絕緣材料塗佈該引線而提供。在引線接合以導電方式連接至該微電子裝置之一觸點及一互連元件之一對應觸點之後,可將一足夠量之絕緣材料施配至該引線接合之末端上以使該等觸點之任何曝露部分及該引線接合末端處之任何曝露導電部分絕緣。The various structures and manufacturing techniques are described for a total cost of microelectronics. In accordance with an embodiment, a microelectronic assembly includes a microelectronic device wire bonded to one or more interconnect elements (eg, a microelectronic subassembly, such as a substrate, wafer carrier, tape, etc.). In one embodiment, wire bonding between the microelectronic device and the one or more other interconnect elements is formed using an insulated lead. The insulated lead may have a lead of an insulating sheath, such as may be provided by coating the lead with an insulating material. After wire bonding is electrically connected to one of the contacts of the microelectronic device and one of the interconnecting contacts, a sufficient amount of insulating material can be applied to the end of the wire bond to enable the contact Any exposed portion of the point and any exposed conductive portions at the wire bond ends are insulated.
當該引線接合最初形成於該晶片上時,該引線接合之絕緣塗層可係相對薄。舉例而言,存在於該接合引線上之絕緣護皮可具有僅約一微米至數微米之一厚度。該護皮之厚度可係如此以便當一引線接合工具在將接合引線之一曝露尖端附接至一裝置或一互連元件之一觸點以形成該引線接合之一個末端之前將熱或一火焰施加至該尖端時該護皮可被容易地消耗。在將該引線接合附接至該裝置及該互連元件兩者之觸點之後,一製程可應用至該等引線接合以使該絕緣塗層生長至一期望厚度。舉例而言,某些絕緣材料可對一液體組合物中之分子具有一親和力,以便當曝露至此液體組合物時,分子可選擇性地聚集於該絕緣塗層上以致使該絕緣塗層之厚度增加。在一項實施例中,該絕緣塗層之厚度可係至少約30微米(micron)以達成絕緣引線接合與欲用作其一參考導體之一導電材料之間的一期望分離距離。該分離距離係與該引線接合之橫截面尺寸(例如,直徑)一起部分地確定該引線接合結構之阻抗之一因素。該絕緣塗層之厚度可相依於欲達成之阻抗而更大,例如50微米、75微米、100微米或另一值。When the wire bond is initially formed on the wafer, the wire bond insulating coating can be relatively thin. For example, the insulating sheath present on the bond wires can have a thickness of only about one micron to a few microns. The thickness of the sheath may be such that when a wire bonding tool attaches one of the bonding leads to one of the contacts of a device or an interconnecting member to form an end of the wire bond, a heat or a flame is applied. The sheath can be easily consumed when applied to the tip. After attaching the wire bond to the contacts of both the device and the interconnecting member, a process can be applied to the wire bonds to grow the insulating coating to a desired thickness. For example, certain insulating materials may have an affinity for molecules in a liquid composition such that upon exposure to the liquid composition, molecules may selectively aggregate on the insulating coating to cause thickness of the insulating coating. increase. In one embodiment, the thickness of the insulating coating can be at least about 30 microns to achieve a desired separation distance between the insulated wire bonds and the conductive material to be used as one of its reference conductors. The separation distance is a factor that determines, in part, the impedance of the wire bond structure along with the cross-sectional dimension (e.g., diameter) of the wire bond. The thickness of the insulating coating can be greater depending on the impedance to be achieved, such as 50 microns, 75 microns, 100 microns or another value.
然後,可在該引線接合上方施配導電囊封劑以填充經以絕緣方式塗佈之引線接合周圍之一容積。該導電囊封劑可電接觸該微電子裝置、一對應互連元件或兩者上之一曝露墊以連接至至少相對於用以操作該微電子裝置之所關注頻率係穩定之一參考電壓,例如接地、電源或其他電壓。該導電囊封劑給該微電子總成提供若干個優點。舉例而言,其可給該引線提供屏蔽及機械保護。在一些實施方案中,額外層(導電及不導電兩者)可施加於該導電囊封劑上方。A conductive encapsulant can then be applied over the wire bond to fill a volume around the wire bond that is coated in an insulating manner. The conductive encapsulant can electrically contact the microelectronic device, a corresponding interconnect element, or an exposure pad on both to connect to at least one of the reference voltages relative to the frequency of interest for operating the microelectronic device, For example, ground, power or other voltages. The conductive encapsulant provides several advantages to the microelectronic assembly. For example, it can provide shielding and mechanical protection for the lead. In some embodiments, additional layers (both conductive and non-conductive) can be applied over the conductive encapsulant.
在另一實施例中,一非絕緣引線用以形成該微電子裝置與該一個或多個互連元件之間的引線接合。在於兩末端處附接該引線接合之後,一介電材料可施配至該非絕緣引線接合上以覆蓋末端及該等末端之間的引線長度。該介電材料可給該非絕緣引線提供絕緣、屏蔽及機械保護。一旦已施配該介電材料,便於該介電材料上方施加一導電層。該導電層之特性(例如,尺寸及表面輪廓)可根據傳輸線之(例如)根據下伏電路之需要欲達成之特性阻抗而選擇。另外,該導電層可連接至該微電子裝置上及或該一個或多個互連元件上之一曝露墊以提供至一參考電壓源(例如接地、電源或其他電壓)的連接,該電壓至少相對於用以操作該微電子裝置之所關注頻率係穩定的。In another embodiment, a non-insulated wire is used to form a wire bond between the microelectronic device and the one or more interconnect elements. After the wire bonds are attached at both ends, a dielectric material can be applied to the non-insulated wire bonds to cover the ends and the length of the leads between the ends. The dielectric material provides insulation, shielding, and mechanical protection to the non-insulated lead. Once the dielectric material has been dispensed, a conductive layer is applied over the dielectric material. The characteristics of the conductive layer (e.g., size and surface profile) can be selected based on the characteristic impedance of the transmission line, for example, to be achieved according to the needs of the underlying circuit. Additionally, the conductive layer can be coupled to the microelectronic device and or one of the one or more interconnect elements to provide a connection to a reference voltage source (eg, ground, power, or other voltage), the voltage being at least It is stable relative to the frequency of interest for operating the microelectronic device.
在一項實施例中,在一微電子總成中,一非絕緣引線可直接接觸該導電層以提供該導電層之穩定(例如,接地或電源)參考與該微電子裝置之一對應接地或電源觸點之間的進一步導電互連。In one embodiment, in a microelectronic assembly, a non-insulated lead can directly contact the conductive layer to provide a stable (eg, ground or power) reference of the conductive layer to the ground or to one of the microelectronic devices Further conductive interconnection between the power contacts.
在一項實施例中,該導電層具有安置於該等導電元件或引線接合之段上面或下面中之至少一者之一至少大致均勻距離處之一導電表面。In one embodiment, the electrically conductive layer has one of the electrically conductive surfaces disposed at least substantially uniform distance from one of at least one of the upper or lower portions of the electrically conductive elements or wire bonds.
根據一實施例,提供可包括一微電子裝置之一微電子總成,該微電子裝置具有一表面及曝露於該表面處之裝置觸點。該表面可在一第一方向上具有一第一尺寸且在橫切該第一方向之一第二方向上具有一第二尺寸。該微電子總成亦包括具有毗鄰該微電子裝置之一面且具有複數個元件觸點之一互連元件。複數個導電元件可將該等裝置觸點與該等元件觸點連接,此等導電元件具有在該微電子裝置之表面上面成段地延伸之大部分。具有一導電表面之一導電材料可安置於該複數個段上面或下面中之至少一者之至少一大致均勻距離處。該導電材料之包括該第一方向上之一第一尺寸及該第二方向上之一第二尺寸之尺寸可小於該微電子裝置之第一尺寸及第二尺寸。此導電材料可連接至一參考電位源以便針對該等導電元件達成一期望阻抗。According to an embodiment, a microelectronic assembly is provided that can include a microelectronic device having a surface and device contacts exposed to the surface. The surface may have a first dimension in a first direction and a second dimension in a second direction transverse to the first direction. The microelectronic assembly also includes an interconnecting member having one of a plurality of component contacts adjacent one side of the microelectronic device. A plurality of conductive elements can connect the device contacts to the component contacts, the conductive elements having a majority extending over the surface of the microelectronic device. A conductive material having a conductive surface can be disposed at at least a substantially uniform distance above or below at least one of the plurality of segments. The conductive material includes a first dimension in the first direction and a second dimension in the second direction may be smaller than the first dimension and the second dimension of the microelectronic device. The electrically conductive material can be coupled to a reference potential source to achieve a desired impedance for the electrically conductive elements.
根據一實施例,提供包括一微電子裝置之一微電子總成,該微電子裝置具有一表面及曝露於該表面處之裝置觸點。該總成可進一步包括具有毗鄰該微電子裝置之一面及複數個元件觸點之一互連元件。複數個導電元件可將該等裝置觸點與該等元件觸點連接,該等導電元件具有在該微電子裝置之表面上面延伸之段。具有一導電表面之一導電材料可安置於在該等導電元件上面或該等導電元件下面之一方向中之至少一者上離該等導電元件之長度之至少大部分至少一大致均勻距離處。該導電材料可連接至一參考電位源,以便針對該等導電元件達成一期望阻抗。該導電表面可進一步界定至少大致平行於該等導電元件佈設於其中之一平面之一平面。In accordance with an embodiment, a microelectronic assembly including a microelectronic device having a surface and device contacts exposed to the surface is provided. The assembly can further include an interconnecting member having one of a plurality of component contacts adjacent to the microelectronic device. A plurality of electrically conductive elements can connect the device contacts to the component contacts, the electrically conductive elements having segments extending over the surface of the microelectronic device. A conductive material having a conductive surface can be disposed on at least one of at least a majority of the length of the conductive elements or at least one of the lengths of the conductive elements at least a substantially uniform distance. The electrically conductive material can be coupled to a reference potential source to achieve a desired impedance for the electrically conductive elements. The electrically conductive surface can be further defined to be at least substantially parallel to a plane in which one of the conductive elements is disposed in one of the planes.
根據一項實施例,該導電表面可上覆於該等導電元件之複數個段。在一特定實施例中,該導電表面可為至少大體平坦。在一項實施例中,該導電表面可以相對於該微電子裝置之表面之一角度傾斜。According to an embodiment, the electrically conductive surface may overlie a plurality of segments of the electrically conductive elements. In a particular embodiment, the electrically conductive surface can be at least substantially flat. In one embodiment, the electrically conductive surface can be angled relative to an angle of the surface of the microelectronic device.
該等導電元件可經配置以使得該複數個段包括至少接合引線部分。在一特定實施例中,該等導電元件可係接合引線。The electrically conductive elements can be configured such that the plurality of segments include at least a bonding lead portion. In a particular embodiment, the electrically conductive elements can be bonded to the leads.
在一項實施例中,該等接合引線可作為複數個連接臺階延伸,且該導電表面可至少大致平行於該等接合引線之該複數個臺階逐臺階延伸。In one embodiment, the bond wires can extend as a plurality of connection steps, and the conductive surface can extend at least substantially parallel to the plurality of steps of the bond wires.
該互連元件可包括一介電元件。在一項實施例中,該互連元件可包括可連接至參考電位源之一參考觸點,且該導電材料可與該參考觸點以導電方式連接以形成一導電連接。The interconnect element can include a dielectric element. In one embodiment, the interconnect element can include a reference contact connectable to a reference potential source, and the conductive material can be electrically connected to the reference contact to form a conductive connection.
在一特定實施例中,該介電元件可包括具有小於200微米之一厚度(如在遠離該微電子元件之表面之一方向上確定)之一聚合物元件。在一項實施例中,該聚合物元件可係一薄片狀元件,且可係撓性或非撓性。在一項實施例中,該等導電元件可以冶金方式接合至晶片觸點。In a particular embodiment, the dielectric component can comprise a polymeric component having a thickness of less than 200 microns (as determined in a direction away from one of the surfaces of the microelectronic component). In one embodiment, the polymeric element can be a sheet-like element and can be flexible or non-flexible. In one embodiment, the electrically conductive elements can be metallurgically bonded to the wafer contacts.
在一項實施例中,該導電表面可藉由絕緣材料與該等接合引線之複數個段分離。該絕緣材料可係如此以便至少大致填充一容積,其中該等接合引線之複數個段延伸穿過該容積。In one embodiment, the electrically conductive surface may be separated from the plurality of segments of the bond wires by an insulating material. The insulating material can be such that at least substantially fills a volume, wherein a plurality of segments of the bond wires extend through the volume.
該導電材料可連結至曝露於該互連元件之一表面處之一參考觸點,且在一項實施例中可符合該互連元件之表面。該互連元件可包括將該參考觸點電連接至一參考電位源之一導體。The electrically conductive material can be bonded to a reference contact exposed at one of the surfaces of the interconnecting member and, in one embodiment, can conform to the surface of the interconnecting member. The interconnect element can include electrically connecting the reference contact to a conductor of a reference potential source.
該微電子總成之一參考導電元件可具有在沿該微電子裝置之表面之一方向上延伸之一段。在一項實施例中,該導電材料可連結至該參考導電元件之段。One of the reference conductive elements of the microelectronic assembly can have a segment extending in a direction along one of the surfaces of the microelectronic device. In one embodiment, the electrically conductive material can be joined to the segment of the reference electrically conductive element.
在一項實施例中,該導電材料可具有一至少大體平坦之導電表面且介電(亦即絕緣)材料可使此表面與導電元件隔開一至少大致均勻距離。該導電材料可包括安置於該至少大體平坦之導電表面下面之一連接部分。在一項實施例中,該連接部分可具有至該參考導電元件的一機械連接及導電連接。In one embodiment, the electrically conductive material can have an at least substantially planar electrically conductive surface and a dielectric (ie, insulating) material can separate the surface from the electrically conductive element by at least a substantially uniform distance. The electrically conductive material can include a connecting portion disposed below the at least substantially planar electrically conductive surface. In an embodiment, the connecting portion can have a mechanical connection and an electrically conductive connection to the reference conductive element.
在一特定實施例中,該參考導電元件之段可至少大致位於與該等導電元件之複數個段相同之平面中。In a particular embodiment, the segments of the reference conductive element can be at least substantially in the same plane as the plurality of segments of the conductive elements.
在一項實施例中,該絕緣材料可具有一外部表面及沿其外部表面之複數個向內延伸槽,且該導電材料可安置於該等槽內。此等槽可包括毗鄰連接至裝置觸點之接合引線之上升部分安置之槽。In one embodiment, the insulating material can have an outer surface and a plurality of inwardly extending grooves along its outer surface, and the electrically conductive material can be disposed within the grooves. The slots may include slots disposed adjacent the raised portions of the bond wires that are connected to the device contacts.
在一特定實施例中,該等接合引線可包括在沿該微電子裝置之一主表面之第一方向上延伸之部分。在此情形中之槽可包括在該第一方向上在橫向延伸之接合引線部分之間延伸之槽。In a particular embodiment, the bond wires can include portions that extend in a first direction along one of the major surfaces of the microelectronic device. The slot in this case can include a slot extending between the laterally extending bond lead portions in the first direction.
在一項實施例中,導電材料之邊緣可毗鄰互連元件之邊緣而安置。In an embodiment, the edges of the electrically conductive material may be disposed adjacent the edges of the interconnecting elements.
在一特定實施例中,裝置觸點可曝露於該微電子裝置之一前表面處且該微電子裝置可具有離該前表面遙遠之一後表面及在該前表面與後表面之間延伸之邊緣。該後表面可安裝至該互連元件,且該等導電元件可延伸超過該微電子裝置之邊緣。In a particular embodiment, the device contact can be exposed at a front surface of the microelectronic device and the microelectronic device can have a rear surface remote from the front surface and extend between the front surface and the back surface edge. The back surface can be mounted to the interconnecting element and the conductive elements can extend beyond the edge of the microelectronic device.
根據本發明之一項實施例,提供一微電子總成,其包括具有一前表面、離其遙遠之一後表面及沿該前表面延伸之一個或多個表面導電元件之一微電子裝置,該微電子裝置具有曝露於該前表面處之裝置觸點。該總成之一互連元件可包括下伏於該微電子裝置之後表面之一介電元件,此互連元件在其上具有複數個元件觸點。複數個凸起導電元件可將該等裝置觸點與該等元件觸點連接。該等凸起導電元件可具有與該等表面導電元件隔開一第一高度且至少大體平行於該一個或多個表面導電元件成段地延伸之大部分。在此實施例中,一個或多個表面導電元件可連接至一參考電位源,以便針對該等凸起導電元件達成一期望阻抗。In accordance with an embodiment of the present invention, a microelectronic assembly is provided that includes a microelectronic device having a front surface, a rear surface that is remote from it, and one or more surface conductive elements extending along the front surface, The microelectronic device has device contacts that are exposed at the front surface. One of the interconnecting elements of the assembly can include a dielectric element underlying the surface of the microelectronic device having a plurality of component contacts thereon. A plurality of raised conductive elements can connect the device contacts to the component contacts. The raised conductive elements can have a first height that is spaced apart from the surface conductive elements and that extends at least substantially in parallel with the one or more surface conductive elements. In this embodiment, one or more surface conductive elements can be coupled to a reference potential source to achieve a desired impedance for the raised conductive elements.
根據此實施例,一個或多個表面導電元件可包括接合至該微電子裝置之前表面之一金屬層。一黏合劑可將該一個或多個表面導電元件接合至該微電子裝置之前表面。在一項實施例中,該金屬層可包括開口,其中該等表面導電元件透過該金屬層中之開口連接至裝置觸點。In accordance with this embodiment, the one or more surface conductive elements can include a metal layer bonded to a front surface of the microelectronic device. An adhesive can bond the one or more surface conductive elements to the front surface of the microelectronic device. In an embodiment, the metal layer can include an opening, wherein the surface conductive elements are coupled to the device contacts through openings in the metal layer.
根據一項實施例,提供包括一微電子裝置之一微電子總成,該微電子裝置具有一表面及曝露於此表面處之裝置觸點。該總成之一互連元件可具有毗鄰該微電子裝置之一面且具有複數個元件觸點。複數個接合引線可將該等裝置觸點與該等元件觸點連接。絕緣材料可包覆該等接合引線中之個別接合引線,此絕緣材料通常具有大於約30微米之一厚度,此厚度沿該等導電元件之相當長的長度至少大致均勻。該總成可進一步包括一導電材料,該導電材料符合該絕緣材料之外部表面且填充經以絕緣方式包覆之接合引線之間的一容積。此導電材料可連接至一參考電位源,以便針對該等導電元件達成一期望阻抗。According to one embodiment, a microelectronic assembly including a microelectronic device having a surface and device contacts exposed to the surface is provided. One of the interconnection elements of the assembly can have a face adjacent to the microelectronic device and have a plurality of component contacts. A plurality of bond wires can connect the device contacts to the component contacts. The insulating material can coat individual bond wires of the bond wires, the insulating material typically having a thickness greater than about 30 microns, the thickness being at least substantially uniform along a relatively long length of the conductive elements. The assembly can further include a conductive material conforming to an outer surface of the insulating material and filling a volume between the insulated lead-coated bond wires. The electrically conductive material can be connected to a reference potential source to achieve a desired impedance for the electrically conductive elements.
在一特定實施例中,可提供絕緣塊,其至少將該等裝置觸點與該導電材料分離。該總成可進一步包括至少將該等元件觸點與該導電材料分離之額外絕緣塊。In a particular embodiment, an insulating block can be provided that separates at least the device contacts from the conductive material. The assembly can further include an additional insulating block that separates at least the component contacts from the electrically conductive material.
圖1A展示根據一項實施例之一實例性微電子總成100之一剖視圖。圖1B係自上面看去之一對應平面視圖,其中圖1A中之視圖係穿過圖1B之剖面線1A-1A。在此實例中,微電子總成100包括藉由一引線接合165以導電方式連接至互連元件130之一微電子裝置110。微電子總成100不同於習用配置之處在於其包括被一絕緣(介電)塗層168以絕緣方式包覆之一導體166。除了介電塗層168之外,一導電囊封劑160覆蓋並至少大致圍繞引線接合165。因此,導電囊封劑160安置於離內部導體166一至少相對均勻之距離(其可係一均勻距離)處,以便該導電囊封劑可用作包括中心導體166及導電囊封劑160之一傳輸線中之一參考導體。FIG. 1A shows a cross-sectional view of an exemplary microelectronic assembly 100 in accordance with an embodiment. Figure 1B is a plan view corresponding to one of the above, wherein the view in Figure 1A passes through the section line 1A-1A of Figure 1B. In this example, microelectronic assembly 100 includes a microelectronic device 110 that is electrically coupled to interconnect element 130 by a wire bond 165. Microelectronic assembly 100 differs from conventional configurations in that it includes an insulator 166 that is insulatively covered by an insulating (dielectric) coating 168. In addition to the dielectric coating 168, a conductive encapsulant 160 covers and at least substantially surrounds the wire bonds 165. Accordingly, the conductive encapsulant 160 is disposed at least a relatively uniform distance from the inner conductor 166 (which may be a uniform distance) such that the conductive encapsulant can be used as one of the center conductor 166 and the conductive encapsulant 160. One of the reference conductors in the transmission line.
微電子裝置110可係一單個「裸露」(亦即,未經封裝)晶粒,例如其上具有微電子電路之一半導體晶片。在替代性實施例中,微電子裝置110可包括一經封裝之半導體晶粒。最初,複數個觸點112曝露於該微電子裝置之一表面128處。舉例而言,複數個觸點112可曝露於一半導體晶粒之一具有觸點之表面處且可配置成曝露於此表面處之一個或多個列。Microelectronic device 110 can be a single "naked" (i.e., unpackaged) die, such as a semiconductor wafer having one of the microelectronic circuits thereon. In an alternative embodiment, microelectronic device 110 can include a packaged semiconductor die. Initially, a plurality of contacts 112 are exposed at one surface 128 of the microelectronic device. For example, a plurality of contacts 112 can be exposed to one or more columns at one of the semiconductor dies that have contacts and can be configured to be exposed at the surface.
為便於參照,在此揭示內容中參照一半導體晶片110之一「頂部」(亦即,具有觸點之表面128)陳述方向。通常,稱作「朝上」或「自...上升」之方向應指代正交及遠離於晶片頂部表面128之方向。稱作「朝下」之方向應指代正交於晶片頂部表面128且與該朝上方向相反之方向。一「垂直」方向應指代正交於該晶片頂部表面之一方向。術語「在」一參照點「上面」應指代自該參照點朝上之一點,且術語「在」一參照點「下面」應指代自該參照點朝下之一點。任一個別元件之「頂部」應指代彼元件之在朝上方向上延伸最遠之一個點或若干點,且術語任一元件之「底部」應指代彼元件之在朝下方向上延伸最遠之一個點或若干點。For ease of reference, reference is made herein to a "top" (i.e., surface 128 having contacts) of a semiconductor wafer 110 to indicate direction. Generally, the direction referred to as "upward" or "rising from" should refer to the direction orthogonal and away from the top surface 128 of the wafer. The direction referred to as "downward" should refer to a direction orthogonal to the top surface 128 of the wafer and opposite the upward direction. A "vertical" direction shall mean a direction orthogonal to one of the top surfaces of the wafer. The term "at" a reference point "above" shall mean a point from the reference point upwards, and the term "at" a reference point "below" shall mean a point from the reference point downward. The "top" of any individual component shall mean the point or points that extend the farthest direction of the component in the upward direction, and the "bottom" of any element shall mean that the component extends upwards downwards most. A point or points away.
如圖1A中所展示之互連元件130能夠藉由導電互連與微電子裝置連接。舉例而言,該互連元件可係一封裝之一元件,該封裝具有複數個導電導線或跡線135、通常配置於第一位置處以用於與該微電子裝置互連之連接至該等導線或跡線之複數個第一觸點175、180及通常配置於第二位置處(例如)以用於互連至另一元件(例如用於外部互連至一印刷電路板)之複數個第二觸點175'、180'。另一選擇為,該互連元件可係另一微電子裝置或包括一個或多個此等裝置以及其他裝置之一單元。互連元件130可包括可至少部分地覆蓋跡線135同時曝露用於形成該等導電互連之觸點之一焊料遮罩或其他介電膜150。The interconnect element 130 as shown in FIG. 1A can be coupled to the microelectronic device by a conductive interconnect. For example, the interconnect element can be a packaged component having a plurality of conductive traces or traces 135, typically disposed at a first location for interconnecting with the microelectronic device to the wires Or a plurality of first contacts 175, 180 of the trace and a plurality of firstly disposed at a second location, for example, for interconnection to another component (eg, for external interconnection to a printed circuit board) Two contacts 175', 180'. Alternatively, the interconnect element can be another microelectronic device or include one or more of such devices and one of the other devices. Interconnect element 130 can include a solder mask or other dielectric film 150 that can at least partially cover trace 135 while exposing one of the contacts used to form the conductive interconnects.
在圖1A中所圖解說明之實例中,觸點175、175'可攜載隨時間變化且通常傳達資訊之信號(亦即,電壓或電流)。舉例而言,在無限制條件之情形下,隨時間變化且表示狀態、改變、一量測、一時脈或時序輸入或一控制或回饋輸入之電壓或電流係信號之實例。另一方面,觸點180、180'可提供至接地或一電源供應電壓的連接。至接地或一電源供應電壓的一連接通常在一電路中提供對至少相對於用以操作該電路之所關注頻率係隨時間相當穩定之一電壓之一參考。在形成該微電子裝置與該互連元件之間的導電互連之前,觸點175、175'、180、180'曝露於互連元件130之一朝外指向之面190處。如在此揭示內容中所使用,一導電結構「曝露於」一介電結構之一表面「處」之一陳述指示該導電結構可用於與在垂直於該介電結構之該表面之一方向上自該介電結構外面朝向該介電結構之該表面移動之一理論點接觸。因此,曝露於一介電結構之一表面處之一端子或其他導電結構可自此表面突出;可與此表面齊平;或可相對於此表面凹進且透過電介質中之一孔或凹坑曝露。In the example illustrated in FIG. 1A, the contacts 175, 175' can carry signals that vary over time and typically convey information (ie, voltage or current). For example, in the case of an unrestricted condition, an instance of a voltage or current system signal that changes over time and represents a state, a change, a measurement, a clock or a timing input, or a control or feedback input. On the other hand, the contacts 180, 180' can provide a connection to ground or a power supply voltage. A connection to ground or a supply voltage typically provides a reference in a circuit to at least one of the voltages that are relatively stable over time relative to the frequency of interest for operating the circuit. The contacts 175, 175', 180, 180' are exposed at an outwardly directed face 190 of the interconnecting member 130 prior to forming a conductive interconnection between the microelectronic device and the interconnecting member. As used in this disclosure, a conductive structure "exposed" to one of the surfaces "on" a surface indicates that the conductive structure is available for use in a direction perpendicular to the surface of the dielectric structure. The outer surface of the dielectric structure is in contact with a theoretical point of movement of the surface of the dielectric structure. Thus, one of the terminals or other conductive structures exposed to one surface of a dielectric structure may protrude from the surface; may be flush with the surface; or may be recessed relative to the surface and penetrate a hole or pit in the dielectric exposure.
在一項特定實施例中,該互連元件可包括一「基板」,例如具有複數個跡線及觸點之一介電元件。在無限制條件之情形下,一基板之一項特定實例可係一薄片狀撓性介電元件,其通常由一聚合物(例如,聚醯亞胺以及其他聚合物)製成,其上圖案化有金屬跡線及觸點,該等觸點係曝露於該介電元件之至少一個面處。在一項實施例中,該介電元件可在遠離該微電子裝置之表面128延伸之一方向上具有200微米或更小之一厚度。In a particular embodiment, the interconnect component can include a "substrate", such as a dielectric component having a plurality of traces and contacts. In the case of no limitation, a specific example of a substrate may be a sheet-like flexible dielectric member, which is typically made of a polymer (e.g., polyimine and other polymers) having a pattern thereon. Metal traces and contacts are exposed, the contacts being exposed to at least one face of the dielectric component. In one embodiment, the dielectric element can have a thickness of one of 200 microns or less in one direction away from the surface 128 of the microelectronic device.
參照圖1A至圖1B,具有一介電元件120之一互連元件130藉由引線接合165具有與一微電子裝置110之導電互連。該等引線接合可係使用絕緣引線而形成。使用一絕緣引線之一引線接合可具有優於其他類型之引線接合之優點。舉例而言,該絕緣引線可防止引線交叉時的短路且其可給引線提供以其他方式不可獲得之機械保護或加固。根據一項實施例,現在將參照圖1A至圖1B闡述將一絕緣引線自一微電子裝置附接至一互連元件之一製程。Referring to FIGS. 1A-1B, an interconnecting component 130 having a dielectric component 120 has a conductive interconnection with a microelectronic device 110 by wire bonding 165. These wire bonds can be formed using insulated leads. Wire bonding using one of the insulated leads can have advantages over other types of wire bonding. For example, the insulated leads can prevent short circuits when the leads are crossed and they can provide mechanical protection or reinforcement to the leads that is otherwise not available. According to one embodiment, a process for attaching an insulated lead from a microelectronic device to an interconnect component will now be described with reference to FIGS. 1A-1B.
引線接合165之絕緣塗層168可具有根據引線166之一尺寸(例如,一直徑)選定之一厚度。該絕緣塗層之厚度可被確定為該塗層之在遠離該引線之一中心導電金屬芯之一外部表面之一正交方向上之尺寸。在一特定實施例中,該引線之中心金屬芯之直徑可係約1密耳(0.001英吋)或更小,等於約30微米或更小之一量測(在下文中,將對微米之提及替代性地陳述為「micrometers」、「microns」或「μm」)。在一項實施例中,該絕緣塗層之厚度可經選擇以具有在約30微米與約75微米之間(亦即,在約1密耳與3密耳之間)的一厚度。將引線166以導電方式且機械地連接至互連元件130之一觸點175且至微電子裝置110上之一觸點125(例如,一接合墊)。絕緣引線165所連接至的裝置觸點可係該微電子裝置之一信號墊或一接地墊。一引線接合可係藉由將一金屬引線(通常係金或銅,該引線具有一絕緣塗層)連結至微電子裝置110上之一觸點112,然後牽拉該引線且將其附接至互連元件130之一對應觸點或觸點175而形成。另一選擇為,該引線可首先連結至子總成130之墊且其後連結至微電子裝置110之觸點。The insulating coating 168 of the wire bonds 165 can have a thickness selected according to one of the dimensions (eg, a diameter) of the leads 166. The thickness of the insulating coating can be determined as the dimension of the coating in a direction orthogonal to one of the outer surfaces of one of the central conductive metal cores of the lead. In a particular embodiment, the diameter of the central metal core of the lead can be about 1 mil (0.001 inch) or less, equal to one of about 30 microns or less (hereinafter, the micron will be raised) And alternatively stated as "micrometers", "microns" or "μm"). In one embodiment, the thickness of the insulative coating can be selected to have a thickness between about 30 microns and about 75 microns (ie, between about 1 mil and 3 mils). Lead 166 is electrically and mechanically coupled to one of contacts 175 of interconnect element 130 and to one of contacts 125 (eg, a bond pad) on microelectronic device 110. The device contact to which the insulated lead 165 is connected may be a signal pad or a ground pad of the microelectronic device. A wire bond can be joined to one of the contacts 112 on the microelectronic device 110 by attaching a metal lead (usually gold or copper with an insulating coating), then pulling the lead and attaching it to One of the interconnecting elements 130 is formed corresponding to a contact or contact 175. Alternatively, the leads may be first bonded to the pads of the sub-assembly 130 and thereafter joined to the contacts of the microelectronic device 110.
在一項實施例中,一引線接合165可係使用其上預形成有一絕緣層之一引線而形成,在一饋送捲盤上提供此引線至一自動引線接合器。提供於饋送至該引線接合器之引線上之絕緣塗層可具有一相當小之厚度(例如,一至數微米之一厚度)。在此情形中,當連結該絕緣引線時,引線接合器設備可在即將形成與每一觸點之連結之前將該引線之尖端處之絕緣塗層燒掉。當該引線接合最初形成於該晶片上時,引線接合165之絕緣塗層可係相對薄。舉例而言,存在於該接合引線上之一絕緣塗層可具有僅約一微米至數微米之一厚度。護皮之厚度可係如此以便當一引線接合工具在將該接合引線之一曝露尖端附接至一裝置或子總成之一觸點以形成引線接合之一個末端之前將熱或一火焰施加至該尖端時該護皮可被容易地消耗。In one embodiment, a wire bond 165 can be formed using a lead on which a layer of insulating layer is pre-formed, which is provided on a feed reel to an automated wire bonder. The insulating coating provided on the leads fed to the wire bonder may have a relatively small thickness (e.g., one to several microns of thickness). In this case, when the insulated lead is joined, the wire bonder device can burn off the insulating coating at the tip of the lead just prior to forming a bond with each contact. When the wire bond is initially formed on the wafer, the insulating coating of wire bond 165 can be relatively thin. For example, one of the insulating coatings present on the bond wires can have a thickness of only about one micron to a few microns. The thickness of the sheath may be such that a wire bonding tool applies heat or a flame to the end of one of the bonding leads before attaching it to one of the contacts of a device or subassembly to form one end of the wire bond. The sheath can be easily consumed when the tip is used.
在將該引線接合附接至該裝置及該子總成兩者之觸點之後,可將一製程應用於該等引線接合以將一另外絕緣層添加至該絕緣塗層以使得該塗層生長至一期望厚度。舉例而言,某些絕緣材料可對一液體組合物中之分子具有一親和力,以便當曝露至此液體組合物時,分子可選擇性地聚集於該絕緣塗層上以致使該絕緣塗層之厚度增加。在一項實施例中,該絕緣塗層之厚度可係至少約30微米以達成絕緣引線接合與欲用作其一參考導體之一導電材料之間的一期望分離距離。該分離距離係與該引線接合之橫截面尺寸(例如,直徑)一起部分地確定該引線接合結構之阻抗之一因素。該絕緣塗層之厚度可相依於引線166之直徑、該絕緣塗層之滲透性及欲達成之阻抗值而更大,例如50微米、75微米、100微米或另一值。After attaching the wire bond to the contacts of both the device and the subassembly, a process can be applied to the wire bonds to add an additional insulating layer to the insulating coating to cause the coating to grow To a desired thickness. For example, certain insulating materials may have an affinity for molecules in a liquid composition such that upon exposure to the liquid composition, molecules may selectively aggregate on the insulating coating to cause thickness of the insulating coating. increase. In one embodiment, the thickness of the insulating coating can be at least about 30 microns to achieve a desired separation distance between the insulated wire bonds and the conductive material to be used as one of its reference conductors. The separation distance is a factor that determines, in part, the impedance of the wire bond structure along with the cross-sectional dimension (e.g., diameter) of the wire bond. The thickness of the insulating coating can be greater depending on the diameter of the lead 166, the permeability of the insulating coating, and the impedance value to be achieved, such as 50 microns, 75 microns, 100 microns or another.
一旦已形成至微電子裝置觸點的引線接合165,可沈積介電材料之團塊169、179以覆蓋微電子裝置觸點112及互連元件之觸點175之可仍曝露之任何部分。介電材料之量可僅限於對確保觸點112及觸點175對於隨後處理為完全絕緣係必要的量。因此,該介電材料可係相對薄,亦即,在厚度上無需多於數微米。此絕緣介電材料層可係(例如)藉由一旋塗或噴塗製程或藉由填充至某一高度而沈積。在一項實施例(圖2)中,絕緣介電材料169'、179'可沈積至觸點112及元件觸點175之曝露部分上至足夠使該等觸點與隨後沈積之導電材料絕緣之一深度。Once the wire bonds 165 have been formed to the contacts of the microelectronic device, agglomerates 169, 179 of dielectric material may be deposited to cover any portions of the contacts 175 of the microelectronic device contacts 112 and interconnecting components that may still be exposed. The amount of dielectric material can be limited to the amount necessary to ensure that contacts 112 and contacts 175 are fully insulated for subsequent processing. Thus, the dielectric material can be relatively thin, i.e., need not be more than a few microns in thickness. The layer of insulating dielectric material can be deposited, for example, by a spin coating or spray coating process or by filling to a certain height. In one embodiment (Fig. 2), insulating dielectric material 169', 179' may be deposited onto contact portion 112 and the exposed portion of component contact 175 sufficient to insulate the contacts from subsequently deposited conductive material. A depth.
此處理之後,可形成一導電層160。在一個實例中,可在絕緣引線165上方施配一導電囊封劑以形成導電層160。在一項實施例中,導電層160可整體囊封絕緣引線165。在一項實施例中,導電材料可係一導電膏(例如,一銀膏、焊料膏或類似物)。在替代性實施例中,其可係一不同材料。After this treatment, a conductive layer 160 can be formed. In one example, a conductive encapsulant can be applied over the insulated leads 165 to form the conductive layer 160. In one embodiment, the conductive layer 160 may encapsulate the insulated leads 165 as a whole. In one embodiment, the electrically conductive material can be a conductive paste (eg, a silver paste, solder paste, or the like). In an alternative embodiment, it can be a different material.
在一項實施例中,當形成導電層160時導電層160形成與互連元件之觸點180之一導電互連。舉例而言,互連元件上之觸點180在導電囊封劑提供於該結構上時可係曝露以便該囊封劑然後與該等觸點進行導電接觸。當觸點180係一接地觸點時,導電囊封劑160為傳輸線提供一接地參考,該等傳輸線係藉由絕緣引線接合165與接地參考通過導電層160之並列而形成。In one embodiment, the conductive layer 160 forms a conductive interconnect with one of the contacts 180 of the interconnect element when the conductive layer 160 is formed. For example, the contacts 180 on the interconnect elements can be exposed when the conductive encapsulant is provided on the structure such that the encapsulant is then in conductive contact with the contacts. When the contact 180 is a ground contact, the conductive encapsulant 160 provides a ground reference for the transmission line formed by the juxtaposition of the insulated wire bond 165 and the ground reference through the conductive layer 160.
根據上文所闡述之結構,一傳輸線結構係針對與互連元件130上之信號觸點連接之絕緣引線接合165而實現。而且,該結構之參數可經選擇以便達成一期望特性阻抗。舉例而言,在某些電子系統中,(例如)當一外部介面上之信號在具有50歐姆特性阻抗之傳輸線上傳輸時,可選擇50歐姆之一特性阻抗以滿足信號介面需要。為達成選定阻抗,可選擇參數,例如金屬之導電性質,以及引線之形狀及厚度,介電絕緣材料之厚度,其介電常數(亦即滲透性)以及導電層160(例如,導電囊封劑)之性質。In accordance with the structure set forth above, a transmission line structure is implemented for insulated wire bonds 165 that are coupled to signal contacts on interconnect element 130. Moreover, the parameters of the structure can be selected to achieve a desired characteristic impedance. For example, in some electronic systems, for example, when a signal on an external interface is transmitted over a transmission line having a 50 ohm characteristic impedance, one of 50 ohms of characteristic impedance can be selected to meet the signal interface requirements. To achieve the selected impedance, parameters such as the conductive properties of the metal, the shape and thickness of the lead, the thickness of the dielectric insulating material, its dielectric constant (ie, permeability), and the conductive layer 160 (eg, conductive encapsulant) may be selected. The nature of ).
可以所闡述之次序或另一選擇為以一不同次序執行上文所闡述之結構。在某些實施方案中,所闡述之步驟中之兩者或更多者可組合成一單個步驟。在其他實施方案中,一所闡述之步驟可自製程中完全排除。在又其他變體中,可需要額外處理步驟。在替代性實施方案(圖中未展示)中,可安置至少一個第二微電子裝置來替代互連元件130且可藉助絕緣引線以導電方式將其連接至微電子裝置110,從而以與上文所闡述之微電子總成100中相同之方式達成傳輸線結構。在又另一替代性實施方案中,兩個互連元件130之觸點可藉助絕緣接合引線以導電方式連接,從而以如上文所闡述之一方式達成傳輸線結構。舉例而言,兩個或多個電路板或兩個或多個其他互連部件之觸點可以此方式互連。The order set forth above or another alternative may be to perform the structures set forth above in a different order. In certain embodiments, two or more of the steps set forth may be combined into a single step. In other embodiments, one of the steps set forth may be completely excluded from the process. In still other variations, additional processing steps may be required. In an alternative embodiment (not shown), at least one second microelectronic device can be disposed in place of the interconnect element 130 and can be electrically connected to the microelectronic device 110 by means of insulated leads, thereby The transmission line structure is achieved in the same manner as in the illustrated microelectronic assembly 100. In yet another alternative embodiment, the contacts of the two interconnecting elements 130 can be electrically connected by means of insulated bond wires to achieve a transmission line structure in one of the ways set forth above. For example, two or more circuit boards or contacts of two or more other interconnecting components may be interconnected in this manner.
圖3A展示包括複數個阻抗控制引線接合之一實例性微電子總成300之一剖視圖。圖3C展示自上面看去之一對應平面視圖,其中圖3A係穿過圖3C之線3A-3A之一視圖。圖3B係穿過圖3C在橫切圖3A中所圖解說明之剖面之一方向上之線3B-3B之一剖視圖。微電子總成300包括微電子裝置310及互連元件330。在一項實施例中,微電子裝置310類似於結合圖1A至1B所闡述之微電子裝置110。在一項實施例中,互連元件330類似於結合圖1A至1B所闡述之互連元件130。3A shows a cross-sectional view of an exemplary microelectronic assembly 300 including a plurality of impedance controlled wire bonds. Figure 3C shows a corresponding plan view from above, wherein Figure 3A is a view through line 3A-3A of Figure 3C. Figure 3B is a cross-sectional view through line 3B-3B in a direction transverse to the section illustrated in Figure 3A through Figure 3C. Microelectronic assembly 300 includes microelectronic device 310 and interconnecting component 330. In one embodiment, microelectronic device 310 is similar to microelectronic device 110 set forth in connection with Figures 1A-1B. In one embodiment, interconnect element 330 is similar to interconnect element 130 set forth in connection with Figures 1A-1B.
如所圖解說明,使用一引線365將一微電子裝置310(例如,一半導體晶粒)之一表面328處之一觸點312引線接合至互連元件330。引線365通常係非絕緣。如在圖3B中所見,通常複數個此等引線365使用習用引線接合技術接合至微電子裝置310且至互連元件330。在一項實施例中,引線365可不同於上文所論述之絕緣引線165。在一項實施例中,引線365可係用於一習用引線接合製程中之典型引線類型。舉例而言,引線365可基本上由銅、金、一金-銀合金或某些其他金屬或一金屬與一個或多個其他金屬或材料之合金或一金屬與一個或多個其他金屬及一個或多個其他材料之一合金構成。As illustrated, one lead 365 is used to wire bond one of the contacts 312 at one surface 328 of a microelectronic device 310 (eg, a semiconductor die) to interconnect element 330. Lead 365 is typically uninsulated. As seen in FIG. 3B, typically a plurality of such leads 365 are bonded to the microelectronic device 310 and to the interconnecting member 330 using conventional wire bonding techniques. In one embodiment, the leads 365 can be different than the insulated leads 165 discussed above. In one embodiment, lead 365 can be used in a typical lead type in a conventional wire bonding process. For example, lead 365 can be substantially comprised of copper, gold, a gold-silver alloy or some other metal or alloy of one metal with one or more other metals or materials or a metal with one or more other metals and one Or one of a plurality of other materials alloyed.
引線接合可在相對精確設置之情形下且在期望容限內形成以便可達成平行於該晶粒之表面328佈設之平行緊密隔開之段。如本文所使用,「平行」指示在製造容限內平行於另一結構之一結構。舉例而言,自Kulicke及Soffa(在下文中,為「K&S」)購得之引線接合設備可用以達成精確引線接合。因此,可形成具有在晶片表面上面在橫向方向上完全筆直或接近筆直之段之引線接合365。雖然此精確性可在形成該等引線接合中達成,但除了在隨附申請專利範圍中具體陳述以外不意欲需要精確形成之平行筆直之引線接合。Wire bonding can be formed with relatively precise placement and within desired tolerances so that parallel closely spaced segments disposed parallel to the surface 328 of the die can be achieved. As used herein, "parallel" indicates a structure that is parallel to one of the other structures within the manufacturing tolerance. For example, wire bonding equipment available from Kulicke and Soffa (hereinafter, "K&S") can be used to achieve precise wire bonding. Thus, a wire bond 365 having a segment that is completely straight or nearly straight in the lateral direction above the surface of the wafer can be formed. While this accuracy may be achieved in forming such wire bonds, it is not intended to require precisely formed parallel straight wire bonds other than as specifically set forth in the accompanying claims.
如在圖3A至3C中所見,在一項實施例中,一旦引線365已引線接合至微電子裝置310及互連元件330,便形成一介電層350以覆蓋該等接合引線並使其絕緣。此情形中,電介質350可係若干種不同材料中之一者,例如一聚合物,例如一環氧樹脂或另一介電材料等。在一項實施例中,介電材料350填充互連元件330與微電子裝置310之間的整個空隙。As seen in Figures 3A through 3C, in one embodiment, once the leads 365 have been wire bonded to the microelectronic device 310 and the interconnect member 330, a dielectric layer 350 is formed to cover and insulate the bond wires. . In this case, the dielectric 350 can be one of several different materials, such as a polymer, such as an epoxy or another dielectric material. In one embodiment, the dielectric material 350 fills the entire gap between the interconnect element 330 and the microelectronic device 310.
如在圖3B中所見,引線接合365具有在進出其上印刷圖3B之紙張之方向上延伸之段。因此,該等引線接合之段界定在圖3A至圖3B中所展示之方向上延伸之一平面377。在一項實施例中,該介電材料可藉由模製形成於互連元件330及微電子裝置310上以便產生具有離微電子裝置表面328遙遠之一表面之一經模製之介電區域,且形成至少大致平坦之一表面。該介電層之此遙遠表面可在一垂直方向380上與引線接合365佈設於其中之平面377隔開至少一大致均勻之距離「D」。因此,該經模製之介電區域可以其離微電子裝置表面328遙遠之表面平行於引線接合365之跨越該引線接合之長度之至少約50%之段之方式而形成。As seen in Figure 3B, wire bond 365 has a section that extends in the direction in which the paper of Figure 3B is printed in and out. Thus, the segments of the wire bonds define a plane 377 that extends in the direction shown in Figures 3A-3B. In one embodiment, the dielectric material can be formed over interconnect element 330 and microelectronic device 310 by molding to create a dielectric region that is molded to one of the surfaces remote from surface 328 of microelectronic device. And forming at least substantially flat one surface. The remote surface of the dielectric layer can be spaced apart from the plane 377 in which the wire bonds 365 are disposed in a vertical direction 380 by at least a substantially uniform distance "D". Thus, the molded dielectric region can be formed such that its surface remote from the surface 328 of the microelectronic device is parallel to the portion of the wire bond 365 that spans at least about 50% of the length of the wire bond.
其後,一導電層360形成於介電層350上方。可藉助各種方式中之任一者來提供導電層360。導電層360可沿介電層350之表面延伸且鄰接該表面(如圖3A至圖3B中所展示),以便具有與該介電層之上文所闡述之表面接觸之一導電表面375。在一個實例中,可藉由電鍍、濺射或以其他方式將一金屬層沈積至該介電層之一表面上而形成該導電層。在另一實施例中,導電層360可由一填充有導電粒子的熱固性樹脂形成,該導電層360係在一形成腔內按照一選定形狀及距離真空形成於引線接合365上面。Thereafter, a conductive layer 360 is formed over the dielectric layer 350. Conductive layer 360 can be provided by any of a variety of means. Conductive layer 360 can extend along the surface of dielectric layer 350 and abut the surface (as shown in Figures 3A-3B) to have a conductive surface 375 in contact with the surface of the dielectric layer described above. In one example, the conductive layer can be formed by plating, sputtering, or otherwise depositing a metal layer onto one surface of the dielectric layer. In another embodiment, the conductive layer 360 can be formed of a thermosetting resin filled with conductive particles formed in a forming cavity over a wire bond 365 in a selected shape and distance.
在一特定實施例中,導電層係(例如)藉由一施配、模製、絲網印刷或模板印刷製程將一導電膏(例如,一銀膏、焊料膏或其他導電填充膏)施加至介電層之曝露表面而形成。導電膏之其他實例可包括一導電聚合物或與主體樹脂合金之一聚合物。在一特定實例中,導電膏可包含一導電粉末、一有機黏結劑(例如,一聚羥基苯乙烯衍生物)及一熱固性樹脂。使用一導電膏之一可能益處可係獲得可在重量上較輕之一成品。若其可導致消除二級製程則製備亦可更簡單且不那麼昂貴。在一項實施例中,導電層360接觸互連元件330上之一墊370。該墊可係一接地或電源供應墊。藉由接觸觸點180且與觸點180形成一接合,導電層變成電連接至互連元件。In a particular embodiment, the conductive layer is applied, for example, to a conductive paste (eg, a silver paste, solder paste, or other conductive paste) by a dispensing, molding, screen printing, or stencil printing process. Formed by the exposed surface of the dielectric layer. Other examples of the conductive paste may include a conductive polymer or a polymer with one of the host resin alloys. In a specific example, the conductive paste may comprise a conductive powder, an organic binder (for example, a polyhydroxystyrene derivative), and a thermosetting resin. One benefit of using one of the conductive pastes may be to obtain one of the finished products that is lighter in weight. If it can result in the elimination of the secondary process, the preparation can be simpler and less expensive. In one embodiment, conductive layer 360 contacts one of pads 370 on interconnect element 330. The pad can be a ground or power supply pad. By contacting the contacts 180 and forming a bond with the contacts 180, the conductive layer becomes electrically connected to the interconnect elements.
在一項實施例中,導電層360在相對於微電子裝置310之表面328水平定向之方向上之尺寸可比微電子裝置表面328之對應尺寸小。如圖3A至圖3B中所見,該微電子裝置之表面328具有在一第一方向上延伸之一第一尺寸324且具有在橫切該第一方向之一第二方向上延伸之一第二尺寸334。該第一方向及第二方向相對於微電子裝置表面328水平延伸,亦即,在沿此表面之方向上。在此實施例中,導電層360可在該第一方向上具有比微電子裝置表面328之對應第一尺寸324小之一尺寸326。類似地,導電層360可在該第二方向上具有比微電子裝置表面328之對應第二尺寸334小之一尺寸336。In one embodiment, the conductive layer 360 may be smaller in size in a direction that is horizontally oriented relative to the surface 328 of the microelectronic device 310 than the corresponding size of the microelectronic device surface 328. As seen in Figures 3A-3B, the surface 328 of the microelectronic device has a first dimension 324 extending in a first direction and having a second dimension extending in a second direction transverse to the first direction. Size 334. The first direction and the second direction extend horizontally relative to the surface 328 of the microelectronic device, that is, in a direction along the surface. In this embodiment, the conductive layer 360 can have a dimension 326 that is less than the corresponding first dimension 324 of the microelectronic device surface 328 in the first direction. Similarly, conductive layer 360 can have a dimension 336 that is smaller than the corresponding second dimension 334 of microelectronic device surface 328 in the second direction.
在一項實施例中,導電層360可具有安置於該等引線接合之長度之至少大部分上面至少一大致均勻距離處之一表面375,以使得每一引線接合及連至一參考電壓源之毗鄰導電層形成具有一期望特性阻抗之一傳輸線結構。在一項實施例中,導電表面可安置於離該等引線接合之跨越該等引線接合之長度之50%或更多延伸之段此大致均勻距離處。為達成一期望特性阻抗,可選擇參數,例如用於引線中之金屬之導電性質,以及該引線之形狀及厚度、該引線與導電層360之間的絕緣材料350之厚度、該絕緣材料之介電常數(亦即,滲透性)以及導電層360之厚度及性質。In one embodiment, the conductive layer 360 can have one surface 375 disposed over at least a substantially uniform distance over at least a majority of the length of the wire bonds such that each wire is bonded and connected to a reference voltage source. Adjacent to the conductive layer forms a transmission line structure having a desired characteristic impedance. In one embodiment, the electrically conductive surface can be disposed at a substantially uniform distance from the portion of the wire that extends across 50% or more of the length of the wire bonds. In order to achieve a desired characteristic impedance, parameters such as the conductive properties of the metal used in the lead, and the shape and thickness of the lead, the thickness of the insulating material 350 between the lead and the conductive layer 360, and the dielectric material may be selected. The electrical constant (i.e., permeability) and the thickness and nature of the conductive layer 360.
圖3D圖表表示特性阻抗Z0 (以歐姆為單位)對一信號導體或導電元件(例如,圓柱形橫截面之一引線)與一參考導體或導電元件(例如,「接地平面」)之間的分離距離(以英吋為單位)。假定該參考導體係相比於信號導體之直徑大之一平坦結構。圖3D針對兩個不同直徑引線繪示特性阻抗。圖3D中之曲線圖可自支配具有當前幾何形狀之一配置中之特性阻抗之一方程式導出。在此方程式中,特性阻抗Z0 由以下公式給出FIG 3D is a graph showing the characteristic impedance between Z 0 (in ohms) of a signal conductor or conductive element (e.g., a cylindrical cross-section of one lead) and a reference conductor or conductive element (e.g., "ground plane") Separation distance (in miles). It is assumed that the reference conduction system is flat compared to the diameter of the signal conductor. Figure 3D shows the characteristic impedance for two different diameter leads. The graph in Figure 3D can be derived from an equation governing one of the characteristic impedances in one of the configurations of the current geometry. In this equation, the characteristic impedance Z 0 is given by the following formula
歐姆, ohm,
其中H係該引線與導電平面之間的分離距離,d係該引線之直徑且εR 係將該引線與該導電平面分離之介電材料之滲透性。滲透性εR 可相依於所使用之介電材料之類型而變化。分離距離H係可至少部分地由用以製備微電子總成之製程確定之一因素。該引線直徑可至少部分地由用以製備微電子總成之製程確定。Where H is the separation distance between the lead and the conductive plane, d is the diameter of the lead and ε R is the permeability of the dielectric material separating the lead from the conductive plane. The permeability ε R can vary depending on the type of dielectric material used. The separation distance H can be determined, at least in part, by one of the processes used to prepare the microelectronic assembly. The lead diameter can be determined, at least in part, by a process used to prepare the microelectronic assembly.
在圖3D中,下部曲線320繪示當用以形成一引線接合之引線具有1密耳(亦即,0.001英吋)之一厚度時之特性阻抗。上部曲線322繪示當用以形成該引線接合之引線具有0.7密耳(亦即,0.0007英吋)之一厚度時之特性阻抗。如圖3D中所見,當該引線與該導電平面之間的一分離距離H小於或等於約0.002英吋(2密耳)(亦即,約50微米)時提供低於約70歐姆之特性阻抗。圖3B展示微電子總成300之一橫截面。此圖展示多個接合引線可自互連元件330接合至微電子裝置310且總成300中之如此形成之引線接合中之每一者由介電材料350圍繞。如所圖解說明,導電囊封劑可覆蓋整個子總成。在一替代性實施例中,該導電囊封劑可僅覆蓋介電材料350之一部分,例如介電材料350之一頂部表面。In FIG. 3D, lower curve 320 depicts the characteristic impedance when the lead used to form a wire bond has a thickness of one mil (ie, 0.001 inch). The upper curve 322 depicts the characteristic impedance when the lead used to form the wire bond has a thickness of 0.7 mils (i.e., 0.0007 inch). As seen in Figure 3D, a characteristic impedance of less than about 70 ohms is provided when a separation distance H between the lead and the conductive plane is less than or equal to about 0.002 inches (i.e., about 50 microns). . FIG. 3B shows a cross section of one of the microelectronic assemblies 300. This figure shows that a plurality of bond wires can be bonded from interconnect element 330 to microelectronic device 310 and each of the wire bonds thus formed in assembly 300 is surrounded by dielectric material 350. As illustrated, a conductive encapsulant can cover the entire subassembly. In an alternative embodiment, the conductive encapsulant may cover only a portion of the dielectric material 350, such as a top surface of one of the dielectric materials 350.
圖4A至圖4B展示表示自圖3中所展示之總成300之一變化形式之一替代性總成400。圖4A係一正視圖且圖4B係在橫切圖4A中所圖解說明之視圖之一方向上之一對應剖視圖。如所展示,兩個引線465及466引線接合於互連元件430及微電子裝置410之各別觸點對之間。在一項實施例中,引線465係一信號引線(例如用以在互連元件430與微電子裝置410之間傳送信號)且另一引線466係一接地或電源引線,亦即,接合至互連元件430之一接地或電源觸點之一引線。4A-4B show an alternative assembly 400 representing one variation from one of the assemblies 300 shown in FIG. 4A is a front view and FIG. 4B is a cross-sectional view corresponding to one of the directions across the view illustrated in FIG. 4A. As shown, two leads 465 and 466 are wire bonded between the respective pairs of contacts of interconnect element 430 and microelectronic device 410. In one embodiment, lead 465 is a signal lead (eg, for transmitting signals between interconnect element 430 and microelectronic device 410) and the other lead 466 is a ground or power lead, ie, bonded to each other One of the components 430 is grounded or one of the power contacts leads.
在一項實施例中,一參考引線接合466經形成以使得其比引線465延伸至微電子裝置410之具有觸點之表面428上面較高之一位置。因此,當在引線465及466上方提供介電材料450時,介電材料450不完全覆蓋引線466。因此,當形成導電層460時引線466仍至少部分地曝露。然後,當形成導電層460時,層460接觸引線466且形成與該引線之一導電連接。引線466可連接至微電子裝置及互連元件上之各別參考觸點(例如,接地觸點或電壓供應觸點)。如在圖4A中進一步所見,該導電層連接至互連元件之一參考觸點480(例如,一接地或電源接觸墊)。以此方式,該導電層可充當用於一傳輸線之一參考導體,該傳輸線包括信號引線465及參考引線466且亦可包括導電層460作為該傳輸線之一部分。因為參考引線466亦連接至微電子裝置410上之一觸點,因此由信號及參考引線465、466形成之傳輸線延伸至該微電子裝置上之觸點。In one embodiment, a reference wire bond 466 is formed such that it extends beyond the lead 465 to a higher position above the surface 428 of the microelectronic device 410 having contacts. Thus, when dielectric material 450 is provided over leads 465 and 466, dielectric material 450 does not completely cover leads 466. Thus, lead 466 is still at least partially exposed when conductive layer 460 is formed. Then, when conductive layer 460 is formed, layer 460 contacts lead 466 and forms an electrically conductive connection with one of the leads. Leads 466 can be connected to respective reference contacts (eg, ground contacts or voltage supply contacts) on the microelectronic device and interconnect components. As further seen in FIG. 4A, the conductive layer is connected to one of the interconnect elements, reference contact 480 (eg, a ground or power contact pad). In this manner, the conductive layer can serve as a reference conductor for a transmission line that includes signal leads 465 and reference leads 466 and can also include a conductive layer 460 as part of the transmission line. Because reference lead 466 is also coupled to one of the contacts on microelectronic device 410, the transmission line formed by signal and reference leads 465, 466 extends to the contacts on the microelectronic device.
圖4C係圖解說明圖4A至圖4B中所展示之實施例之一變化形式之一剖視圖。如圖4C中所見,如在上文所論述之圖4A至圖4B中,參考引線476比一信號引線475延伸至微電子裝置之表面428上面較高之一位置。如亦在圖4C中所見,類似於圖4A至圖4B之導電層460,導電層462呈現與絕緣介電層450接觸之一至少大體平坦之表面464。導電層462額外具有朝向微電子裝置410遠離表面464朝下延伸之一接觸部分478。此接觸部分478具有與參考引線466之一導電連接,但與信號引線475絕緣。Figure 4C is a cross-sectional view illustrating one variation of the embodiment shown in Figures 4A-4B. As seen in FIG. 4C, as in FIGS. 4A-4B discussed above, the reference lead 476 extends to a higher position above the surface 428 of the microelectronic device than a signal lead 475. As also seen in FIG. 4C, similar to the conductive layer 460 of FIGS. 4A-4B, the conductive layer 462 exhibits a surface 464 that is at least substantially planar in contact with the insulating dielectric layer 450. Conductive layer 462 additionally has a contact portion 478 that extends downwardly toward microelectronic device 410 away from surface 464. This contact portion 478 has an electrically conductive connection to one of the reference leads 466 but is insulated from the signal leads 475.
如圖4C中所展示具有接觸部分478之導電層462可係如下形成。形成信號引線及參考引線且可於其上形成一介電囊封劑層450,該介電囊封劑層具有至少足夠之硬度以在隨後處理中抵抗流動。然後,形成自該介電囊封劑材料之一外表面朝下延伸之一溝槽,其使參考引線476曝露。舉例而言,可使用一機械或雷射製程來自該囊封劑層移除材料。隨後,當形成導電層462時,該導電材料朝下延伸至該溝槽中且形成導電層462與參考引線466之間的一導電連接。Conductive layer 462 having contact portion 478 as shown in Figure 4C can be formed as follows. A signal lead and a reference lead are formed and a dielectric encapsulant layer 450 can be formed thereon, the dielectric encapsulant layer having at least sufficient hardness to resist flow during subsequent processing. A trench is then formed extending from the outer surface of one of the dielectric encapsulant materials, which exposes the reference lead 476. For example, the material can be removed from the encapsulant layer using a mechanical or laser process. Subsequently, when conductive layer 462 is formed, the conductive material extends downward into the trench and forms an electrically conductive connection between conductive layer 462 and reference lead 466.
圖4D圖解說明相對於圖4C所闡述之實施例之一變化形式。圖4D係在對應於圖4C之方向線4D-4D之一方向上截取以使得信號引線485及參考引線486好似在進出於其上印刷圖4D之紙張之平面之方向上佈設之一橫向剖視圖。在圖4D中所展示之變化形式中,參考引線486之段大致位於與信號引線485之段相同之平面中。接觸部分488安置於自該導電層之至少大體平坦之表面464朝向微電子裝置410朝下延伸之溝槽中,以使得參考引線經安置與該等接觸部分之導電材料接觸,同時信號引線485經安置與介電囊封材料450接觸。Figure 4D illustrates a variation of the embodiment illustrated with respect to Figure 4C. 4D is a transverse cross-sectional view taken in a direction corresponding to one of the direction lines 4D-4D of FIG. 4C such that the signal lead 485 and the reference lead 486 are arranged in the direction in which the plane of the sheet of FIG. 4D is printed. In the variation shown in Figure 4D, the segment of reference lead 486 is located substantially in the same plane as the segment of signal lead 485. Contact portion 488 is disposed in a trench extending downwardly from at least substantially planar surface 464 of the conductive layer toward microelectronic device 410 such that the reference leads are placed in contact with the conductive material of the contact portions while signal lead 485 is passed The placement is in contact with the dielectric encapsulating material 450.
圖4E圖解說明該實施例(圖4D)之一變化形式,其中參考引線496及信號引線495具有至少大致安置於微電子裝置410之表面428上面之相同平面內,但其中一參考引線496在與該信號引線延伸之一方向495相反之一方向上延伸。參考引線496與導電層460之間的接觸可用以沿參考引線496之長度且在導電層之表面464上建立一穩定參考電壓。因此,參考引線496針對信號引線495之自微電子裝置410在一朝上方向上延伸之部分491充當該信號引線之一參考導體。另一方面,且導電層460充當該信號引線之另一部分之參考導體,該另一部分在沿微電子裝置之表面428之一方向上延伸且至少大體延伸至導電層460之表面464。4E illustrates a variation of this embodiment (FIG. 4D) in which reference lead 496 and signal lead 495 have at least substantially disposed in the same plane above surface 428 of microelectronic device 410, but with a reference lead 496 in The signal lead extends in one of the directions 495 opposite one direction. Contact between reference lead 496 and conductive layer 460 can be used to establish a stable reference voltage along the length of reference lead 496 and on surface 464 of the conductive layer. Thus, reference lead 496 acts as a reference conductor for the signal lead 491 for portion 491 of signal lead 495 extending from the microelectronic device 410 in an upward direction. On the other hand, and conductive layer 460 acts as a reference conductor for another portion of the signal lead that extends in one direction along surface 428 of the microelectronic device and extends at least generally to surface 464 of conductive layer 460.
在圖4F中所展示之變化形式中,參考引線496'可包括一朝上延伸之部分497或「絞結」部分,而不是僅在大體平行於微電子裝置410之表面428之一方向上延伸。此形狀可幫助確保在參考引線496'與導電層之連接部分498之間建立一良好導電連接。In the variation shown in FIG. 4F, the reference lead 496' can include an upwardly extending portion 497 or "twisted" portion rather than extending only in a direction generally parallel to the surface 428 of the microelectronic device 410. This shape can help ensure that a good conductive connection is established between the reference lead 496' and the connecting portion 498 of the conductive layer.
在圖4G中所展示之變化形式中,參考引線508在每一末端處具有至基板或互連元件的導電連接。此變化形式之其他特徵係如上文參照圖4A至圖4F中之一者或多者所闡述。In the variation shown in Figure 4G, the reference lead 508 has an electrically conductive connection to the substrate or interconnect element at each end. Other features of this variation are as described above with reference to one or more of Figures 4A-4F.
圖5圖解說明一微電子總成300之一替代性實施例。此處,微電子總成500包括微電子裝置510及互連元件530。在此實施例中,介電材料550包括一槽570。此槽可在形成介電層550時模製至該總成中。另一選擇為,可在該電介質已固化之後切割形成槽570。可經由鑽、鋸或一些其他技術切割形成槽570。在此實施例中,當形成導電層560時,該導電層延伸至槽570中。然後該導電層可包括該槽內之導電材料,該槽安置於毗鄰引線接合之上升部分處,亦即,毗鄰複數個引線接合之在一垂直方向上遠離微電子裝置表面上升之部分處,如圖5中所展示。FIG. 5 illustrates an alternate embodiment of a microelectronic assembly 300. Here, microelectronic assembly 500 includes microelectronic device 510 and interconnect element 530. In this embodiment, dielectric material 550 includes a slot 570. This trench can be molded into the assembly as it is formed. Alternatively, the trench 570 can be formed after the dielectric has cured. The slot 570 can be formed by drilling, sawing, or some other technique. In this embodiment, the conductive layer extends into the trench 570 when the conductive layer 560 is formed. The conductive layer may then comprise a conductive material within the trench disposed adjacent the rising portion of the wire bond, i.e., adjacent a portion of the wire bond that is raised in a vertical direction away from the surface of the microelectronic device, such as Shown in Figure 5.
圖6圖解說明互連元件300之另一替代性實施例。此處,導電層660經延伸以上覆於互連元件630上之由介電層670(例如,一經圖案化之介電層,例如焊料遮罩)與其絕緣之跡線635。這樣做延伸對該等跡線之阻抗控制及屏蔽。FIG. 6 illustrates another alternative embodiment of interconnect element 300. Here, the conductive layer 660 is overlying the trace 635 overlying the interconnect element 630 from the dielectric layer 670 (eg, a patterned dielectric layer, such as a solder mask). This extends the impedance control and shielding of the traces.
圖7圖解說明根據又另一替代性實施例之一微電子總成700。此處,介電層750包括自其一頂部表面朝下延伸之溝或槽770。該等槽可在平行於引線接合765之段之一方向上(亦即在進出於其上印刷圖7之頁所界定之平面之方向上)延伸。該等槽可(例如)在形成該介電層時(例如,舉例而言,當施配介電材料時)形成。另一選擇為,該等槽可在已施配或固化該介電材料之後形成。當形成導電層760時,其可延伸至槽770中且可在引線之間提供屏蔽。FIG. 7 illustrates a microelectronic assembly 700 in accordance with yet another alternative embodiment. Here, dielectric layer 750 includes trenches or trenches 770 that extend downwardly from a top surface thereof. The slots may extend in a direction parallel to one of the segments of wire bond 765 (i.e., in a direction into which the plane defined by the page of Figure 7 is printed). The trenches can be formed, for example, when forming the dielectric layer (e.g., when dispensing a dielectric material, for example). Alternatively, the grooves can be formed after the dielectric material has been dispensed or cured. When conductive layer 760 is formed, it can extend into trench 770 and can provide shielding between the leads.
圖8圖解說明根據另一替代性實施例之一微電子總成800。此處,微電子裝置810以一面朝上定向與互連元件830引線接合。此處,該微電子裝置之一後面附接至該互連元件,且引線接合自該微電子裝置上之觸點815延伸至該互連元件之對應觸點875,子總成觸點875超出該微電子裝置之邊緣812安置。FIG. 8 illustrates a microelectronic assembly 800 in accordance with another alternative embodiment. Here, the microelectronic device 810 is wire bonded to the interconnect member 830 with the side facing up. Here, one of the microelectronic devices is attached to the interconnect element, and the wire bonds extend from the contact 815 on the microelectronic device to the corresponding contact 875 of the interconnect element, the subassembly contact 875 is beyond The edge 812 of the microelectronic device is placed.
在一項實施例中,微電子裝置810之一堆疊可係一者在另一者之頂部上堆疊而成。引線接合可形成於一微電子裝置810與一對應互連元件830之間。然後,可形成一介電層850,且然後可形成一導電層860。此等層可形成以使堆疊互連端子(例如,堆疊觸點(圖中未展示))曝露於互連元件830上。然後,一第二完成之微電子總成800可堆疊於該第二介電層之頂部上,(例如)以使得每一總成800中之微電子裝置處於一面朝上定向。該第二微電子總成可藉助在該等堆疊互連端子之間延伸之導電元件與該第一微電子總成以導電方式互連。In one embodiment, one of the stacks of microelectronic devices 810 can be stacked on top of the other. Wire bonding can be formed between a microelectronic device 810 and a corresponding interconnecting component 830. A dielectric layer 850 can then be formed and a conductive layer 860 can then be formed. Such layers may be formed to expose stacked interconnect terminals (eg, stacked contacts (not shown)) to interconnect element 830. A second completed microelectronic assembly 800 can then be stacked on top of the second dielectric layer, for example, such that the microelectronic devices in each assembly 800 are oriented face up. The second microelectronic assembly can be electrically interconnected with the first microelectronic assembly by conductive elements extending between the stacked interconnect terminals.
圖9圖解說明上文實施例(圖3A至圖3B)之一變化形式,其中信號引線1065沿微電子裝置1010之表面1028成段地延伸,其中段1067不與表面1028之平面平行。而是,引線接合之段1067以相對於表面1028之一角度傾斜。在此情形下,導電層1060可以一間隔1061平行於段1067而延伸,該間隔沿引線接合之長度之50%或更多係均勻或至少大致均勻。以此方式,達成具有一有益特性阻抗之一傳輸線結構。製備方法可與上文相對於圖3A至3B所闡述相同,除了在形成該導電層之前可使用具有一山形形狀之一模具來模製介電囊封劑層1050。9 illustrates one variation of the above embodiment (FIGS. 3A-3B) in which signal leads 1065 extend in sections along surface 1028 of microelectronic device 1010, wherein segment 1067 is not parallel to the plane of surface 1028. Rather, the wire bonded segments 1067 are inclined at an angle relative to the surface 1028. In this case, the conductive layer 1060 can extend parallel to the segment 1067 with a spacing 1061 that is uniform or at least substantially uniform along 50% or more of the length of the wire bond. In this way, a transmission line structure having a beneficial characteristic impedance is achieved. The method of preparation can be the same as set forth above with respect to Figures 3A through 3B, except that a dielectric encapsulant layer 1050 can be molded using a mold having a mountain shape prior to forming the conductive layer.
圖10圖解說明又另一變化形式,其中引線接合1085不以均勻線性段延伸。而是,該等引線接合具有一階梯形狀,該階梯形狀包括主要朝下延伸之相對短的凸凹部1082及在跨越微電子裝置1010之表面1028之方向上延伸之稍微較長之凸凹部或臺階1084。在此情形下,該導電層亦可經配置以具有毗鄰引線接合1084之一階梯形狀之內表面,此內表面係由遵循該等引線接合之輪廓之一系列類似臺階界定。結果,導電層1080之內表面可以一間隔1081平行於該等引線接合之凸凹部1084而延伸,該間隔沿該等引線接合之長度之50%或更多係均勻或至少大致均勻。再者,與上文所闡述(圖3A至圖3B)相同之方法可用以製備該結構,除了可使用具有一不同形狀之一模具來形成階梯形狀之導電層。Figure 10 illustrates yet another variation in which wire bonds 1085 do not extend in a uniform linear segment. Rather, the wire bonds have a stepped shape that includes relatively short convex and concave portions 1082 that extend primarily downward and slightly longer convex or concave portions or steps that extend across the surface 1028 of the microelectronic device 1010. 1084. In this case, the conductive layer can also be configured to have an inner surface adjacent one of the stepped features of the wire bond 1084, the inner surface being defined by a series of similar steps following the contour of the wire bonds. As a result, the inner surface of the conductive layer 1080 can extend parallel to the wire-bonded convex and concave portions 1084 at a spacing 1081 that is uniform or at least substantially uniform along 50% or more of the length of the wire bonds. Further, the same method as described above (Figs. 3A to 3B) can be used to prepare the structure except that a one having a different shape can be used to form a stepped conductive layer.
在圖11A至圖11B中所圖解說明之實施例中,一導電平面960沿一微電子裝置910之一表面928延伸且連接至該微電子裝置之觸點912之引線接合965以離導電平面960一隔開距離平行於表面928而延伸。圖11A係圖解說明一微電子總成900之一剖視圖,該微電子總成包括微電子裝置910及與其連接之互連元件。圖11B係自表面928上面且朝向朝向觸點912之表面觀察之一平面視圖。如在圖11A至圖11B中所見,該導電平面可包括曝露觸點912中之個別觸點之開口964。另一選擇為,該導電平面可包括曝露該微電子裝置之一些或所有觸點之一個或多個較大開口。In the embodiment illustrated in FIGS. 11A-11B, a conductive plane 960 extends along a surface 928 of a microelectronic device 910 and is connected to the wire bond 965 of the contact 912 of the microelectronic device to exit the conductive plane 960. A spaced apart distance extends parallel to surface 928. 11A is a cross-sectional view of a microelectronic assembly 900 including a microelectronic device 910 and interconnecting components coupled thereto. FIG. 11B is a plan view from above surface 928 and toward the surface facing contact 912. As seen in FIGS. 11A-11B, the electrically conductive plane can include an opening 964 that exposes individual contacts in contact 912. Alternatively, the electrically conductive plane can include one or more larger openings that expose some or all of the contacts of the microelectronic device.
在一項實施例中,該導電平面可係在一微電子裝置成含有複數個連接裝置之一晶圓或板之形式時或在該裝置已自其他此等裝置單個化之後藉由施加至該裝置之表面928之處理(例如施加至該裝置之一金屬沈積或電鍍製程)而形成。另一選擇為,可藉由預處理一金屬薄片(例如一銅箔)以在該金屬薄片中形成開口964來提供該導電平面。然後,可(例如)藉由使用一黏合劑將該金屬薄片接合至該微電子裝置之表面928。In one embodiment, the conductive plane can be applied to the microelectronic device in the form of a wafer or plate containing one of the plurality of connecting devices or after the device has been singulated from other such devices. The treatment of the surface 928 of the device (e.g., application to a metal deposition or electroplating process of the device) is formed. Alternatively, the conductive plane can be provided by pretreating a metal foil (e.g., a copper foil) to form openings 964 in the foil. The foil can then be bonded to the surface 928 of the microelectronic device, for example, by using a bonding agent.
然後形成引線接合965,其連接該微電子裝置之觸點912與微電子裝置910上之觸點975。如在圖11A中所見,引線接合965具有凸起高於該微電子裝置之表面928之段。在形成該等引線接合之後,(例如)出於機械支撐該等引線接合之目的可形成一介電層950。引線接合965之段可在平行於或至少大體平行於微電子裝置表面928之一水平方向上延伸,如圖11A中所展示。在此情形下,該等段可在其製造容限內平行。此等水平段通常係該等引線接合之大部分,亦即,該等引線接合之長度之50%或更大。該等段可在該導電平面上以一大致均勻高度(例如,通常自表面928之約50微米至自表面928之約100微米之一高度)隔開。以此方式,可針對該等引線接合達成一期望阻抗。以此方式,來往於該微電子裝置之信號可在較少雜訊進入攜載該等信號之連接(例如,引線接合)之情形下傳輸。A wire bond 965 is then formed that connects the contact 912 of the microelectronic device to the contact 975 on the microelectronic device 910. As seen in Figure 11A, wire bond 965 has a segment that is raised above surface 928 of the microelectronic device. After forming the wire bonds, a dielectric layer 950 can be formed, for example, for mechanical support of the wire bonds. The segments of wire bonds 965 can extend in a horizontal direction parallel or at least substantially parallel to one of the surfaces 928 of the microelectronic device, as shown in Figure 11A. In this case, the segments can be parallel within their manufacturing tolerances. These horizontal segments are typically the majority of the wire bonds, i.e., 50% or more of the length of the wire bonds. The segments may be spaced apart on the conductive plane by a substantially uniform height (e.g., typically from about 50 microns from surface 928 to a height from about 100 microns from surface 928). In this way, a desired impedance can be achieved for the wire bonds. In this manner, signals to and from the microelectronic device can be transmitted with less noise entering the connection (e.g., wire bonding) that carries the signals.
圖12中所展示之變化形式表明導電層沒必要係一完整金屬薄片。而是,如在圖12中所見,該導電層可以複數個導電條帶980之形式提供,該等導電條帶沿微電子裝置910之表面在平行於信號引線接合965在裝置觸點912與互連元件930之觸點975之間之段之方向上延伸。該等導電條帶可由支撐部分982機械支撐或固持在一起。在一項實施例中,藉由以相減方式圖案化一銅箔或薄片且(例如)藉助一黏合劑材料962將剩餘金屬結構接合至該微電子裝置之表面928將該等導電條帶及支撐部分形成為一金屬結構。The variation shown in Figure 12 indicates that the conductive layer does not necessarily have to be a complete foil. Rather, as seen in FIG. 12, the conductive layer can be provided in the form of a plurality of conductive strips 980 along the surface of the microelectronic device 910 in parallel with the signal wire bonds 965 at the device contacts 912 and Extending in the direction of the segment between the contacts 975 of the component 930. The conductive strips can be mechanically supported or held together by the support portion 982. In one embodiment, the conductive strips are patterned by subtracting a copper foil or sheet in a subtractive manner and bonding the remaining metal structures to the surface 928 of the microelectronic device, for example, via an adhesive material 962. The support portion is formed as a metal structure.
已相對於個別微電子裝置(例如,半導體晶片)之互連闡述了前述實施例。然而,預期本文所闡述之方法可在同時施加至在晶片之邊緣處連接在一起之複數個晶片(例如,以一單元、板、晶圓或一晶圓之部分之形式在邊緣處連接在一起之複數個晶片)之一晶圓層級製造製程中運用。The foregoing embodiments have been described in relation to interconnections of individual microelectronic devices (e.g., semiconductor wafers). However, it is contemplated that the methods described herein can be applied simultaneously to a plurality of wafers joined together at the edges of the wafer (eg, joined together at the edges in the form of a unit, plate, wafer, or portion of a wafer). One of a plurality of wafers) is used in a wafer level manufacturing process.
在上文所闡述之實施例之一特定變化形式中,該導電材料無需符合圍繞該等引線接合之介電區域之輪廓。舉例而言,替代在一經模製之介電區域上形成該導電層,可藉由附接一金屬罐以上覆於該等接合引線及介電區域350以便將該金屬罐之內部表面設置於離該微電子總成之引線接合365之一期望間隔處來實現該導電層。In a particular variation of one of the embodiments set forth above, the electrically conductive material need not conform to the contour of the dielectric region surrounding the wire bonds. For example, instead of forming the conductive layer on a molded dielectric region, the inner surface of the metal can can be disposed by attaching a metal can over the bonding wires and the dielectric region 350. The conductive layer is implemented at a desired spacing of one of the wire bonds 365 of the microelectronic assembly.
儘管上文之闡述參照用於特定應用之說明性實施例,但應理解所請求之發明並不侷限於該等實施例。彼等熟習此項技術者通過閱讀本文中所提供之教示將認識到隨附申請專利範圍之範疇內之額外修改、應用及實施例。Although the above description refers to illustrative embodiments for a particular application, it should be understood that the claimed invention is not limited to such embodiments. Additional modifications, applications, and embodiments within the scope of the appended claims will be apparent to those skilled in the art.
100...微電子總成100. . . Microelectronic assembly
110...微電子裝置110. . . Microelectronic device
112...觸點112. . . Contact
120...介電元件120. . . Dielectric element
128...表面128. . . surface
130...互連元件130. . . Interconnect component
135...導電導線或跡線135. . . Conductive wire or trace
150...介電膜150. . . Dielectric film
160...導電囊封劑160. . . Conductive encapsulant
165...引線接合165. . . Wire bonding
166...導體166. . . conductor
168...絕緣(介電)塗層168. . . Insulating (dielectric) coating
169...團塊169. . . Bump
169'...絕緣介電材料169'. . . Insulating dielectric material
175...第一觸點175. . . First contact
175'...第二觸點175'. . . Second contact
179...團塊179. . . Bump
179'...絕緣介電材料179'. . . Insulating dielectric material
180...第一觸點180. . . First contact
180'...第二觸點180'. . . Second contact
190...朝外指向之面190. . . Pointing outward
300...微電子總成300. . . Microelectronic assembly
310...微電子裝置310. . . Microelectronic device
312...觸點312. . . Contact
324...第一尺寸324. . . First size
326...尺寸326. . . size
328...微電子裝置表面328. . . Microelectronic device surface
330...互連元件330. . . Interconnect component
334...第二尺寸334. . . Second size
336...尺寸336. . . size
350...絕緣(介電)材料(層)350. . . Insulating (dielectric) material (layer)
360...導電層360. . . Conductive layer
365...引線接合365. . . Wire bonding
370...墊370. . . pad
375...導電表面375. . . Conductive surface
377...平面377. . . flat
380...垂直方向380. . . Vertical direction
400...替代性總成400. . . Alternative assembly
410...微電子裝置410. . . Microelectronic device
428...表面428. . . surface
430...互連元件430. . . Interconnect component
450...介電(絕緣)材料450. . . Dielectric (insulating) material
460...導電層460. . . Conductive layer
462...導電層462. . . Conductive layer
464...表面464. . . surface
465...引線465. . . lead
466...引線466. . . lead
475...信號引線475. . . Signal lead
476...參考引線476. . . Reference lead
478...接觸部分478. . . Contact part
480...參考觸點480. . . Reference contact
485...信號引線485. . . Signal lead
486...參考引線486. . . Reference lead
488...接觸部分488. . . Contact part
491...部分491. . . section
495...信號引線495. . . Signal lead
496...參考引線496. . . Reference lead
496'...參考引線496'. . . Reference lead
497...部分497. . . section
498...連接部分498. . . Connection part
500...微電子總成500. . . Microelectronic assembly
508...參考引線508. . . Reference lead
530...互連元件530. . . Interconnect component
550...介電材料550. . . Dielectric material
560...導電層560. . . Conductive layer
570...槽570. . . groove
635...跡線635. . . Trace
660...導電層660. . . Conductive layer
670...介電層670. . . Dielectric layer
700...微電子總成700. . . Microelectronic assembly
760...導電層760. . . Conductive layer
765...引線接合765. . . Wire bonding
770...槽770. . . groove
800...微電子總成800. . . Microelectronic assembly
810...微電子裝置810. . . Microelectronic device
812...邊緣812. . . edge
815...觸點815. . . Contact
830...互連元件830. . . Interconnect component
850...介電層850. . . Dielectric layer
860...導電層860. . . Conductive layer
875...觸點875. . . Contact
910...微電子裝置910. . . Microelectronic device
912...觸點912. . . Contact
928...表面928. . . surface
930...互連元件930. . . Interconnect component
950...介電層950. . . Dielectric layer
960...導電平面960. . . Conductive plane
962...黏合劑材料962. . . Adhesive material
964...開口964. . . Opening
965...引線接合965. . . Wire bonding
975...觸點975. . . Contact
980...導電條帶980. . . Conductive strip
982...支撐部分982. . . Support part
1010...微電子裝置1010. . . Microelectronic device
1028...表面1028. . . surface
1060...導電層1060. . . Conductive layer
1061...間隔1061. . . interval
1065...信號引線1065. . . Signal lead
1067...段1067. . . segment
1080...導電層1080. . . Conductive layer
1081...間隔1081. . . interval
1082...凸凹部1082. . . Convex and concave
1084...凸凹部或臺階/引線接合1084. . . Concave or concave or step/wire bonding
1085...引線接合1085. . . Wire bonding
圖1A係根據一實施例之一微電子總成之一剖視圖。1A is a cross-sectional view of a microelectronic assembly in accordance with an embodiment.
圖1B係對應於圖1A之剖視圖之一平面視圖。Figure 1B is a plan view corresponding to the cross-sectional view of Figure 1A.
圖2係根據圖1A中所展示之實施例之一變化形式之一微電子總成之一剖視圖。2 is a cross-sectional view of one of the microelectronic assemblies in accordance with one variation of the embodiment shown in FIG. 1A.
圖3A係根據一實施例之一微電子總成之一剖視圖。3A is a cross-sectional view of a microelectronic assembly in accordance with an embodiment.
圖3B係圖3A中所展示之實施例中沿橫切圖3A之剖視圖之一剖面線之一剖視圖。Figure 3B is a cross-sectional view of a section taken along the cross-sectional view of Figure 3A in the embodiment shown in Figure 3A.
圖3C係圖3A至圖3B中所展示之實施例之一平面視圖。Figure 3C is a plan view of one of the embodiments shown in Figures 3A-3B.
圖3D係根據一實施例針對接合引線之不同直徑圖表表示特性阻抗Z0 對分離高度H之一圖形。FIG. 3D line characteristic impedance Z 0 represents one of the isolated pattern height H according to a different embodiment of the bonding wire diameter graph.
圖4A係圖解說明根據圖1A至圖1B中所圖解說明之實施例之一變化形式之一微電子總成之一剖視圖。4A is a cross-sectional view of one of the microelectronic assemblies in accordance with one variation of the embodiment illustrated in FIGS. 1A-1B.
圖4B係圖4A中所展示之實施例中沿橫切圖4A之剖視圖之一剖面線之一剖視圖。4B is a cross-sectional view of a section taken along the cross-sectional view of FIG. 4A in the embodiment shown in FIG. 4A.
圖4C係圖解說明根據圖4A至圖4B中所圖解說明之實施例之一變化形式之一微電子總成之一剖視圖。4C is a cross-sectional view of one of the microelectronic assemblies in accordance with one variation of the embodiment illustrated in FIGS. 4A-4B.
圖4D係橫切圖4C之剖視圖之一剖視圖,其圖解說明根據一特定實施例之一微電子總成。4D is a cross-sectional view, taken through section of FIG. 4C, illustrating a microelectronic assembly in accordance with a particular embodiment.
圖4E係圖解說明根據圖4C中所圖解說明之實施例之一變化形式之一微電子總成之一剖視圖。4E is a cross-sectional view of one of the microelectronic assemblies in accordance with one variation of the embodiment illustrated in FIG. 4C.
圖4F係圖解說明圖4E中所圖解說明之實施例之一變化形式之一局部剖視圖。Figure 4F is a partial cross-sectional view illustrating one variation of one of the embodiments illustrated in Figure 4E.
圖4G係圖解說明根據圖4C中所圖解說明之實施例之一變化形式之一微電子總成之一剖視圖。Figure 4G is a cross-sectional view of one of the microelectronic assemblies in accordance with one variation of the embodiment illustrated in Figure 4C.
圖5係圖解說明圖3A至圖3C中所圖解說明之實施例之一變化形式之一剖視圖。Figure 5 is a cross-sectional view illustrating one variation of the embodiment illustrated in Figures 3A-3C.
圖6係圖解說明圖3A至圖3C中所圖解說明之實施例之一變化形式之一剖視圖。Figure 6 is a cross-sectional view illustrating one variation of the embodiment illustrated in Figures 3A-3C.
圖7係橫切圖6中所圖解說明之剖面之一剖視圖,其圖解說明圖3A至圖3C中所圖解說明之實施例之一變化形式。Figure 7 is a cross-sectional view, taken through section of the section illustrated in Figure 6, illustrating a variation of the embodiment illustrated in Figures 3A-3C.
圖8係圖解說明根據圖3A至圖3C中所圖解說明之實施例之一變化形式之一微電子總成之一剖視圖。Figure 8 is a cross-sectional view of one of the microelectronic assemblies in accordance with one variation of the embodiment illustrated in Figures 3A-3C.
圖9係圖解說明根據圖3A至圖3C中所圖解說明之實施例之一變化形式之一微電子總成之一剖視圖。Figure 9 is a cross-sectional view of one of the microelectronic assemblies in accordance with one variation of the embodiment illustrated in Figures 3A-3C.
圖10係圖解說明根據圖3A至圖3C中所圖解說明之實施例之一變化形式之一微電子總成之一剖視圖。Figure 10 is a cross-sectional view of one of the microelectronic assemblies in accordance with one variation of the embodiment illustrated in Figures 3A-3C.
圖11A係根據另一實施例之一微電子總成之一剖視圖。Figure 11A is a cross-sectional view of a microelectronic assembly in accordance with another embodiment.
圖11B係根據一項實施例對應於圖11A之剖視圖之一平面視圖。Figure 11B is a plan view of a cross-sectional view corresponding to Figure 11A, in accordance with an embodiment.
圖12係圖解說明根據圖11A至圖11B中所圖解說明之實施例之一變化形式之一微電子總成之一平面視圖。Figure 12 is a plan view illustrating one of the microelectronic assemblies in accordance with one variation of the embodiment illustrated in Figures 11A-11B.
100...微電子總成100. . . Microelectronic assembly
110...微電子裝置110. . . Microelectronic device
112...觸點112. . . Contact
120...介電元件120. . . Dielectric element
128...表面128. . . surface
130...互連元件130. . . Interconnect component
135...導電導線或跡線135. . . Conductive wire or trace
150...介電膜150. . . Dielectric film
160...導電囊封劑160. . . Conductive encapsulant
165...引線接合165. . . Wire bonding
166...導體166. . . conductor
168...絕緣(介電)塗層168. . . Insulating (dielectric) coating
169...團塊169. . . Bump
175...第一觸點175. . . First contact
175'...第二觸點175'. . . Second contact
179...團塊179. . . Bump
180...第一觸點180. . . First contact
180'...第二觸點180'. . . Second contact
190...朝外指向之面190. . . Pointing outward
Claims (52)
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US21006309P | 2009-03-13 | 2009-03-13 | |
KR1020090089470A KR100950511B1 (en) | 2009-09-22 | 2009-09-22 | Microelectronic assembly with impedance controlled wirebond and conductive reference element |
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KR (1) | KR100950511B1 (en) |
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WO2010105157A3 (en) | 2012-02-23 |
JP2012520573A (en) | 2012-09-06 |
WO2010105157A2 (en) | 2010-09-16 |
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US8994195B2 (en) | 2015-03-31 |
US7923851B2 (en) | 2011-04-12 |
US20140103500A1 (en) | 2014-04-17 |
US8575766B2 (en) | 2013-11-05 |
CN102449760A (en) | 2012-05-09 |
US20110101535A1 (en) | 2011-05-05 |
US20110095408A1 (en) | 2011-04-28 |
US20100230828A1 (en) | 2010-09-16 |
JP5651608B2 (en) | 2015-01-14 |
KR100950511B1 (en) | 2010-03-30 |
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US8269357B2 (en) | 2012-09-18 |
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