TW201205760A - Multi-chip package with pillar connection - Google Patents

Multi-chip package with pillar connection Download PDF

Info

Publication number
TW201205760A
TW201205760A TW100113345A TW100113345A TW201205760A TW 201205760 A TW201205760 A TW 201205760A TW 100113345 A TW100113345 A TW 100113345A TW 100113345 A TW100113345 A TW 100113345A TW 201205760 A TW201205760 A TW 201205760A
Authority
TW
Taiwan
Prior art keywords
bonding
substrate
die
pads
bond
Prior art date
Application number
TW100113345A
Other languages
English (en)
Inventor
Roland Schuetz
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Publication of TW201205760A publication Critical patent/TW201205760A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/16105—Disposition relative to the bonding area, e.g. bond pad the bump connector connecting bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81194—Lateral distribution of the bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92127—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06551—Conductive connections on the side of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)

Description

201205760 六、發明說明： 【相關申請案參照】 本申請案主張美國臨時申請案第61/352,624號的優先權， 該申請案之全文以引用之方式併入本文中。 【發明所屬之技術領域】 本發明一般有關半導體記憶體裝置，及更明確地說，有關 多晶片封裝。 【先前技術】 使用諸如可攜式記憶卡的半導體積體電路晶片進行資料 存相當普遍。這些裝置的使用者希望資料儲存容量不斷増加=， ，而製造商想盡辦法以符合成本交文益的方式提供較大的儲存容 量〇 已知藉由堆疊多個半導體晶片或晶粒於單一封裝 晶片封f(MCP))中，可增加單_封|中的記㈣密度。晶粒二 增加使付相對於單-晶粒的儲存容量對應地增加。參考圖1 MCP卿由四個N娜快閃記憶體晶粒1〇2組成。應明’ 方法同樣適用於其他記憶體裝置且刺於任何數 粒。每個晶粒丨〇2具有經由接合引線電連接至共同基=曰曰 的接合^ 104。雖然顯示晶粒1〇2的接合墊刚在兩個相對側 二=明白，每個晶粒1〇2可替代地具有不同配置的接 H)4，例如在單一側上、或在兩個 基板丨08在基板|〇8的相蚪、他配置。 no的另外⑥/丨上^供從接合引線106至焊料球 ' $連接，形成連接至外部裝置（未顯示）的球柵陣列 4 201205760 (=A)。在每對連續的晶㈣2之間提供插入物ιΐ2，以在盆間 的間隙，從而允許接合引線1〇6附著至接合整ι〇4。此 =置^有以下缺點：插入物m的厚度限制了晶粒搬可在固 數目’因而限制了 Mcp励的總儲存容 〒二另外’由於每個晶粒脱突出在下方晶粒⑽的接合塾1〇4 入在堆疊下一個晶粒102之前附著每個晶粒102的接 a引線106，導致製造步驟的數目增加及組裝既費時又費力。 另-方法如圖2所示。MCP 200由接合塾2()4沿著一侧 ===閃記憶體晶粒撕組成。應明白此方法同 置且剌練喊目神疊晶粒。此配置可 ^ 具有接合墊2〇4沿著兩個相鄰側的晶粒和吏用， 的接2 2^"V晶粒I彼此側向偏移以暴露每個晶粒202 置中’所有晶粒202可以單一步驟堆疊， 線2〇U番引I接合機(未顯示)以單一步驟附著所有接合引 4 L &置不需要制插人物以接近接合墊2G4,導致更緊 =酉己置。此配置具有以下缺點：所有晶粒2q 1因為在晶粒2G2之相對側上的接合部位 及引起規舰―所錢峨高喊線密度可導致擁塞 美括208 一卜:丁 尤其是在其中每個晶粒202需要在 ΐϊ Γ獨立内連線跡線的裳置(諸如hln繼，中。 或者’可使用減少數目的接合引線 :=rr藉由在基板208上心=: 在某场決這些馳，岐卻又增加了料成本。 5 201205760 ★在圖3及4中顯不另一種配置。參考圖3，MCp 3⑽具 m向中的—組⑽3q2a及在第二⑽中的另-組晶粒 μ明白，此方法同樣適用於其他記憶體裝置且適用於任 :數目的堆疊晶粒。每個晶粒302具有沿著一侧的接合塾取。 晶粒3—02的兩個定向可讓接合引線3〇6的擁塞減少5〇%。在圖 4中’每個晶粒402另外在相對於圖3晶粒302的第二方向中偏 移，因而允許第二組接合引線406在每個晶粒4〇2的第二側上 連接至第二組接合墊404，附帶地增加了内連線密度。第二侧與 第一侧相鄰。然而’在兩個MCP 300及400中，可能無法使用 晶粒302、402與接合墊304、404相對的那一側314、414作為 額外的接合塾。即使晶粒3.02、402及任何插入物的尺寸導致^ 堆疊幾何使得晶粒302、402之側314、414不會受到堆疊中其 他晶粒302、402的阻礙，但仍無法使用該等側314、414作為 額外的接合塾，例如因為晶粒302、402之突出於上方的側314、 414缺少結構剛性以承受引線接合操作。 因此，需要一種減少内連線擁塞的多晶片封裝。 還需要一種每個晶粒具有增加數目之内連線的多晶片封 裝。 0Θ 也需要一種具有緊密配置的多晶片封裝。 並且需要一種組裝具有這些特性之多晶片封裝的方法。 【發明内容】 201205760 本發明實施例之一目的在於解決先前技術的一或多個缺 點。 本發明實施例之另一目的在於提供一種多晶片封裝，其中 多個晶片沿著至少一個邊緣堆疊於基板上且與基板電連接，且 有接合柱實質上垂直地從基板延伸至晶片。 本發明實施例之另一目的在於提供在基板及晶片的一或多 個邊緣(習用接合引線通常無法接近)之間的電連接。 、本發明實施例之另一目的在於提供一種組裝多晶片封裝的 方法，其係藉由以下方式：形成從基板實質上垂直地延伸的複 數個接合柱；及定位至少—個晶片於該基板上，使得沿著該至 少二個晶2之至少—個邊緣的接合墊與職數健合柱接觸； 及形成沿著該至少—個晶片的至少-個其他邊緣將接合墊連接 至該基板的接合引線。 板换種半導體裝置包含—基板。第—複數個基 係布置在該基板上。該複數個晶㈣每個晶粒具有 的第一複數個晶粒接合墊。複數個接合柱從 5亥專基板接&塾貫質上垂直地延伸。每個接合柱將該第一複數 應者 ，，板接合墊之-者電連接至該第—複數個晶粒接合墊之一對 在另外H該基板具㈣二複數個基_合墊布置於 7 201205760 ‘之一對 應者 ，上。該複數個晶粒的每個晶粒具有第二複數個晶粒接合墊〉八 著其至少一個第二邊緣配置。複數個接合引線將該第二σ /〇 基板接合墊之每一者電連接至該第二複數個晶粒接合墊 在另外一方面，該至少一個第一邊緣及該至少一個第二 緣係該日日粒的相對邊緣(〇pp〇site e(jges)。 在另外一方面，該第一複數個晶粒接合墊之每一 在該晶粒的至少一個側面(lateral surface)上。 、 在另外一方面，該第二複數個晶粒接合墊之每一者係布署 在該晶粒的至少一個頂部表面上。 至該ΐΐί:::該等接合柱經由球形接合_ b。，連接 在另外方面，該至少一個第一邊緣係一單一第一邊緣。 在另外一方面，該至少一個第二邊緣係一單一第二邊緣。 在另外一方面，該至少一個第一邊緣係兩個相鄰的第— 緣0 在另外一方面，該至少一個第二邊緣係兩個相鄰的第二邊 〇 201205760 在另外一方面，該複數個晶粒之至少一個晶粒的至少一個 第一邊緣突出(overhang)於該等基板接合墊及連接至該複數個 晶粒之至少一個其他晶粒的該等接合柱上方。 ^在另外一方面，該複數個晶粒之至少一個晶粒與連接至該 複數個晶粒之至少-自其他晶粒的該等接合柱之一頂部部 開。 在另外一方面，在該複數個晶粒的連續晶粒之間提供插入 物（interposer)。 在一附加方面，一種組裝一半導體装置的方法包含形成與 第一複數個基板接合墊電連接之複數個實質上垂直接合柱於一 基板之一接合表面上。複數個半導體晶粒堆疊在該基板的接合 表面上。該複數個晶粒之每一者具有沿著其至少一個第一邊緣 配置的第-複數個晶粒接合墊，使得該第_複數個晶粒接合塾 之，一者鄰近職數健合柱之—對應者。在職數個接合柱 之母一者及該第一複數個晶粒接合墊之一對應者之間形成電連 接。 垃人外—方面，該基板之該接合表面具有第二複數個基板 曰。置於其上。該複數個晶粒的每個晶粒具有第二複數個 ίϊίί塾沿著其至少—個第二邊緣配置。在該第二複數個基 =接5塾之每—者及該第二複數個晶粒接合墊之—對 附者接合引線。 201205760 在另外方面，在該複數個接合柱之每一者及該第一彳n =物之—對應者之間形成一電二=數： σ母者焊接至該第-複數個晶粒接合整之一對應者。 在另外一方面，在該複數個接合柱之每一者及該第一複 =了粒接。塾之—對應者之間形成—電連接包含使用一導電淨 2脂將該複數個接合柱之每—者連接至該第—複數個接 合墊之一對應者。 恢 入在另外一方面，形成該複數個實質上垂直接合柱之每—者 包含：使用一引線接合機形成一球形接合於該第一複數個基板 接合墊之一對應者上；形成一附著至該球形接合且一般從該基 板之表面延伸的引線；及在距該基板之接合表面之一所要距ς 處剪下該引線，藉此形成一所要高度的一接合柱。 在另外一方面，形成該複數個實質上垂直接合柱之每一者 另外包含形成一球於該引線之一上端處。 在另外一方面’堆疊複數個晶粒包含定位該複數個晶粒的 至少一個晶粒，使得該至少一個晶粒的第一邊緣突出於連接至 先前堆疊晶粒的接合柱上方。 從以下說明、附圖、及隨附申請專利範圍，將明白本發明 具體實施例的附加及/或替代特徵、方面、及優點。 10 201205760 【實施方式】 參考圖14，根據第一具體實施例的多晶片封裝(Multi-Chip
Package ’ 簡稱 MCP) 500 具有三個晶粒 502A、502B、502C。每 個晶粒可以是記憶體晶片’諸如NAND快閃晶片。或者，晶粒 的部分或全部可以是不同類型的晶片，諸如控制器晶片。每個
晶粒502A、502B、502C具有沿著一個邊緣的接合墊5〇4A、 504B、504C (如圖8所示）。接合墊504A、504B、504C經由相 應的接合引線506A、506B、506C連接至基板508的接合表面。 每個晶粒502A、502B、502C另外具有沿著第二邊緣配置的接 合墊505A、505B、505C (在圖8中看得最清楚），在此具體實施 例中’接合塾 505A、505B、505C 與接合墊 504A、504B、504C 相對。接合墊504、505可構造成從側面至頂部表面，繞著晶粒 的一個角落包覆，使得這些接合墊能夠在側向方向中或在頂部 表面上形成電接觸，如美國專利第5，126,286號中所示。接合墊 505A 505B、505C經由相應的接合柱5〇7A、507B、507C連 接至基板508的表面，其詳細論述如下。接合柱、5〇7B、 507C提供與接合引線遐、涵、鼠相_連通功能性。 在基板之相料面上的減鱗料球(未顯示)形成連接至 外部裝置的球柵陣列(簡稱BGA)。BGA中焊料球的數目及位置 知且衫本發明的難内。設想可替代使 ^連接^至外縣置的其他已知方法。應明白，此配置同樣 裝置且適用於任何數目的堆疊晶粒。基於以
5〇0組裝方权敛述，熟此技藝者應可明白MCP 500的其他特徵。 ί考圖 將。兒明MCP 500的姐裝，其始於步驟|6〇〇， 201205760 的適當 其中基板508具有電接觸或接合墊516在其接合表面上 配置。 在步驟1605，參考圖5A、5B及5C，使用可以是 接合機的引線形成設備518形成接合柱507 〇參考圖5八， 用的方式在接合墊516上形成球形接合跡如熟此技蔽者= 的，可使用形成接合墊训之接合的替代方法。參考圖^ ^ 線形成設備518 -般在遠離基板508之表面的方向中收回，以 形成一般從基板508之表面延伸的引線522。參考圖5c， 要長度處剪下引線522，以形成所要高度的接合柱5()7 段，接合柱5〇7僅由球形接合52〇接合至基板SOS的接 516，且並未在上端處接合。 σ 參考圖6A-6C ’顯示形成接合柱術的替代方法。 6Α ’以習用的方式在接合墊516上形成球形接合㈣。如鮮 j術者明白的，可使用形成接合墊516之接合的替代方^ ^圖紐’引線形成設備518 一般在遠離基板之表面的方 ^所_之表面_ 5丨線622，然後 =度處努下引線622 ’以形成所要高度的接合柱術。參 fw- ff/以習用的方式，諸如利用電子燒球器（electronic 6〇7的接合柱607的頂部形成球624。球624在接合柱 氣面、’t、附加金屬，其可用來建立與接合墊5G5的較大接 減少電;且接it明Ϊ下。在形成至接合墊5G5的高電流接觸-或 人;^m妾觸時’需要較大的接觸面。應明白，本文以下對接 。柱507的敘述可應用於接合柱6〇7。 201205760 圖7顯示接合柱507A、507B、507C的陣列，接合柱507A、 507B、507C之每一者根據圖5A-5C的程序形成於基板508上。 接合柱507A、507B、507C的每一列具有與晶粒5〇2A、502B、 502C之一相應者接合的適當高度，其詳細敘述如下。應明白， 取決於MCP 500中需要多少晶粒5〇2A、502B、502C，可使用 更多或更少列的接合柱507A、507B、507C。接合柱507A、507B、 507C的實際高度將取決於各種因數，諸如每個晶粒的厚度及在 晶粒之間任何插入物的厚度。在連續列的接合柱5〇7a、5〇7b、 507C之間的間距對應於在連續晶粒5〇2A、5〇2β、5〇2匸之間的 側向偏移，此側向偏移至少足以暴露接合墊5〇4A、5〇4B、5〇4C 以進行稍後的引線接合，其詳細論述如下。 顯示圖5A-5C及6A-6C中的接合柱507、607垂直於基板 508的表面延伸，然而應明白，接合柱5〇7、6〇7不必確切^垂 直於基板508的表面’只要接合至特定基板5〇8的所有接人柱 5〇7 ' 607彼此充分隔開即可，以防止意外短路或其他不想要的 電連接，及接合柱507、6〇7從表面延伸足夠遠以接觸適當晶粒 502的接合墊505，其詳細論述如下。應明白，所謂「實質上垂 直」涵蓋这些可允許定向的全部。接合柱5〇7、6〇7可由 以提供勁度(stiffness),但，取決於特定應用所要的物理及^ 性，也可以使祕何其他合適金屬，諸如# 驟 1610繼續。 々汴仕步·驟 .在步驟1610，第—晶粒篇堆疊於基板508上，視需要 堆登於間隔物或插入物5I2A的頂部上，如圖8所示。可以= 的方式完成堆疊’只要晶粒502A定位成接合墊5G5A與對^的 201205760 接合柱507A接觸或與其充分鄰近，使得可在其間形成電連接， 其詳細論述如下。晶粒502A視情況可定位成接合墊5〇5A鄰接 對應的接合柱507A且對其施加側向力，以在其間形成較佳電連 接’其詳細論述如下。程序在步驟1615繼續。 在步驟1615，在每個接合柱507A的頂部部分及對應的接 合墊505A之間形成電連接。此連接可利用任何合適方法形成。 參考圖9，根據一具體實施例，晶粒502A在基板5〇8上定位成 每個接合墊505A對其對應的接合柱507A施加水平壓力，或替 代地定位成接合墊505A及對應的接合柱507A密切鄰近。藉由 使用雷射焊接設備526或其他合適裝置，將每個接合柱5〇7A接 合至對應的接合墊5〇5A，以形成連接。參考圖i〇A及1〇B，根 據一替代的具體實施例，晶粒5〇2A在基板508上定位成每個接 &墊505A對其對應接合柱607A的球624施加水平壓力，或替 代地定位成接合墊505A及對應的接合柱607A密切鄰近。藉由 使用雷射焊接設備526或其他合適裝置，將每個接合柱6〇7八接 合至對應的接合墊505A，以形成連接》參考圖ha及iiB，根 據一替代的具體實施例，接合墊5〇5A各具有在其上形成的凸塊 528。可以任何已知方式，諸如美國專利第6,410,406號中說明 的方式，形成凸塊528 ;該專利之全文以引用之方式併入本文 中。晶粒502A在基板508上定位成每個凸塊528對其對應的接 合柱507A施加水平壓力，或替代地定位成接合墊5〇5A及對應 的-接-合教507A—密切鄰近。藉由使用雷射焊接設備526或其他合 適的接合裝置’將每個接合柱507A接合至對應的接合墊505A， 以形成連接。設想可使用在接合柱5〇7A及接合墊5〇5A之間形 成連接的其他方法，諸如導電環氧樹脂。程序在步驟162〇繼續。 201205760 在步驟1620，如果最後一個晶粒502已堆疊且接合至基板 508 ’則程序在步驟1625繼續。如果還有更多晶粒5〇2要堆疊 及接合至基板508，則程序返回步驟1610，以堆疊其他晶粒 502。每個晶粒502與下方的晶粒502側向偏移，以確保對接合 柱507的正確接合’及使在下方晶粒5〇2之上表面上的接合墊 504暴露。參考圖12，可使用間隔物512，以在第一晶粒5〇2a 及基板508之間提供足夠的間隙，使在晶粒5〇2a及接合柱5〇7A 之間的接觸不會受到球形接合52〇的阻礙。可另外使用間隔物 512 ’以在連續晶粒502a、5〇2b之間提供足夠的間隙，以在對 應於下方晶粒502A及上方晶粒502B的接合柱507A之間形成 突出於接合柱507A上方的空隙530。應明白，空隙530可以很 小，且尤其空隙530可以比所要求的還小，以允許接合習用的 接合引線取代接合柱507，藉此需要較薄的間隔物512。以此方 式，接合柱507A及其基板接合墊516的整體可布置在基板5〇8 及突出於上方的晶粒502B之間’以形成緊密的配置。 在步驟1625，參考圖13，以已知的方式，將接合引線5〇6 連接至基板508的接合塾517及至晶粒5〇2的接合墊5〇4{>根據 一具體實施例，每個接合引線506利用球形接合532連接至其 對應的接合塾517’及利用楔形接合534連接至並對應的接人勢 504。設想可替代地使用任何合適類型的引線接^。$以單二製 造步㈣接所有晶-粒5Q2❾搔合引線5的，固為晶粒5()2的側向 偏移允許引線接合機(未顯示)接近所有的接合墊〇 續。 201205760 在步驟1630’程序結束及MCP 500已準備就緒可進行其他 處理，包括以保護性塑膠膜製化合物包封晶粒、接合柱、及接 合引線，或以某一其他合適方法密封封裝。 參考圖15’根據一替代的具體實施例，晶粒丨5〇2八及15〇2C 以第一定向堆疊，及晶粒1502B及1502D以垂直於第一定向的 第二定向堆疊。在此配置中，每個晶粒15〇2具有沿著單一邊緣 的接合引線1506及沿著與接合引線1506相對之單一邊緣的接 合柱1507。晶粒1502的交替定向導致接合引線15〇6及接合柱 1507各沿著MCP 1500的兩個相鄰侧分布。在此配置中，進一 步減少擁塞。另外，減輕或消除插入物的需要，因為每個晶粒 1502用作其他定向之兩個相鄰晶粒15〇2之間的間隔物。例如， 晶粒1502B的厚度形成相鄰晶粒15〇2入及15〇2c之間的間隙， 其可利用自身或比圖12具體實施例薄的插入物，在接合柱 1507A及晶粒1502C的底部之間提供足夠的空隙。因此，可減 少MCP 1500的高度，或可在適配於標準尺寸封裝的Mcp丨5〇〇 中堆疊更多晶粒1502。應明白，組裝MCP 15〇〇的方法實質上 類似於組裝MCP 500的方法，因此將不詳細論述。 參考圖17，根據一替代的具體實施例，每個晶粒17〇2具 有沿著兩個婦侧的接合引線丨7G6及沿著剩餘兩個相鄰側的接 合柱170—7。設想每個晶粒17Q2可替代地沒有附著的接合引線 Π06，在此例中，沿著兩側僅提供接合柱17〇7。在此配】中' 可進一步減少内連線擁塞，或每個晶粒丨7〇2之接合引線Η% .及接合柱1707的數目可以加倍且同時維持相同擁塞程度。應明 201205760 白’組裝MCP 1700的方法實質上類似於組裝MCp5〇〇的方法， 只是加入第二組接合墊、接合柱及接合引線，因此將不詳細論 述。 熟悉本技術者應明白對本發明上述具體實施例的修改及改 =。預期以上說明係為示範性而非限制性。因此預期本發明範 舜僅受到隨附申請專利範圍之範疇的限制。 【圖式簡單說明】 一圖疋根據第一先則技術具體實施例之多晶片封裝(MCP) 的示意橫截面圖； V》 的示 ^ 的示^封裝(mcp) 的示⑼先前麟频實細之多^縣(MCP) 的示=立及5C是顯示形成根據第—具體實施例之接合柱 的示及6c是顯示形成根據第二具體實施例之接合柱 圖；圖7疋根據本發明一具體實施例之接合柱陣列的示意透視 Ξ 例具體實施例之晶粒堆疊的示意分解圖； 觸的示意難ΐ圖㈣實關在接合墊及接合柱之間形成接 201205760 圖10A及10B疋根據第一具體實施例在接合整及接合柱之 間形成接觸的示意圖； 圖11A及11B疋根據第二具體實施例在接合塾及接合柱之 間形成接觸的示意圖； ^ 圖12是接合柱及晶粒堆疊之周圍部分的示意橫截面圖； 圖13是具接合柱及接合引線之晶粒堆疊的示意透視圖； 圖Μ是根據一具體實施例具接合柱及接合引線之晶粒堆 疊的示意立面圖； 圖是根據一替代具體實施例具接合柱及接合引線之晶 粒堆疊的示意俯視平面圖； 圖16是根據一具體實施例組裝晶粒堆疊之方法的邏輯 圖；及 β圖17是根據一具體實施例具接合柱及接合引線之晶粒堆 疊的示意俯視平面圖。 【主要元件符號說明】 100 102 104 106 108 110 112 200 202 204 多晶片封裝(MCP) 四個NAND快閃記憶體晶粒 接合墊 接合引線 基板 焊球 _入物 多晶片封裝(MCP) 四個NAND快閃記憶體晶粒 接合塾. 201205760 206 接合引線 208 基板 300 多晶片封裝(MCP) 302 晶粒 302A 晶粒 302B 晶粒 304 接合墊 306 接合引線 400 多晶片封裝(MCP) 402 晶粒 404 接合墊 406 接合引線 500 多晶片封裝(MCP) 502 晶粒 502A 晶粒 502B 晶粒 502C 晶粒 504 接合墊 504A 接合墊 504B 接合墊 504C 接合墊 505 接合墊 505A 接舍蟄 505B 接合墊 505C 接合墊 506 接合引線 201205760 506A 接合引線 506B 接合引線 506C 接合引線 507 接合柱 507A 接合柱 507B 接合柱 507C 接合柱 508 基板 512 間隔物 512A 間隔物或插入物 516 接合墊 517 接合墊 518 引線形成設備 520 球形接合 522 引線 526 雷射焊接設備 528 凸塊 530 空隙 532 球形接合 534 楔形接合 607 接合柱 607A 接合柱 620 球形接合 622 引線 624 球 1500 多晶片封裝(MCP) 20 201205760 1502 晶粒 1502A 晶粒 1502B 晶粒 1502C 晶粒 1502D 晶粒 1506 接合引線 1507 接合柱 1702 晶粒 1706 接合引線 1707 接合柱

Claims (1)

  1. 201205760 七、申請專利範圍： 1. 一種半導體裝置，包含： 合塾^基板’其具有布置在其一接合表面上的第一複數個基板接 個曰=，料置在職板上，該複數個晶粒的每 塾S;曰有者其至少—個第—邊緣配置的第—複數個晶粒接合 複數健合柱從該等基板接合墊實f上垂直地延伸，每 晶 第一複數個基板接合墊之一者電連接至該第-複數個 叔接合墊之一對應者。 如申咕專利範圍第1項所述的半導體裝置，其中： 該基板具有布置在其上的第二複數個基板接合墊； 該複數個晶㈣每個晶粒具有第二複數個晶粒接合墊沿著盆 至少一個第二邊緣配置；及 另外包含複油接合引線將該第二複數個基板接合塾之每— 電連接至該第二複數個晶粒接合墊之一對應者。 如申响專利範圍第2項所述的半導體裝置，其中： 邊緣该至少""個第—邊緣及該至少—個第二邊緣係該晶粒的相對 4.如申請專科範1第3項所述的半導體裝置，其中： 該第-複數個晶粒接合塾之每—者係^置在該晶粒的 個側面上。 22 201205760 5. 如申請專利範圍第4項所述的半導體裝置，其中· 個頂數娜轉合墊之每-者料置找晶粒的至 少 6. 如申請專利範圍第3項所述的半導體裝置’其中： 該等接合柱經由球形接合連接至該等基板接合墊。 7. 如申凊專利範圍第3項所述的半導體裝置，其中： 該至少一個第一邊緣係一單一第一邊緣。 8_如申請專利範圍第7項所述的半導體裝置，盆令： 該至少一個第二邊緣係一單—第二邊緣。一 9’如申請專利範圍第3項所述的半導體裝置，其中： 3亥至少一個第一邊緣係兩個相鄰第一邊緣。 10. 如申请專利範圍第9項所述的半導體裝置，其中： 該至少一個第二邊緣係兩個相鄰第二邊緣。 11. 如申请專利範圍第1項所述的半導體裝置，其中： *該複數個晶粒之至少-個晶粒的至少―個第—邊緣突出於該 等基板接合墊及連接至該複數個晶粒之至少一個其他晶粒的該^ 接合柱上方。 23 201205760 12. 如申請專利範圍第u項所述的半導體裝置，其申該複叙個晶 粒之至少一個晶粒與連接至該複數個晶粒之至少一個I 社哲人t 日日祖的 涊寺接合柱之一頂部部分隔開。 13. 如申請專利範圍第丨項所述的半導體裝置，另外包含在該複 數個晶粒的連續晶粒之間的插入物。 14. 一種組裝一半導體裝置之方法，包含： 形成與第一複數個基板接合墊電連接之複數個實質上垂直接 合柱於一基板之一接合表面上； 堆疊複數個半導體晶粒於該基板的該接合表面上，該複數個 晶粒之每一者具有第一複數個晶粒接合墊沿著其至少一個第一邊 緣配置，使得該第-複數個晶粒接合墊之每一者與該複數個接合 柱之一對應者鄰近；及 σ 在該複數個接合柱之每一者及該第一複數個晶粒接合墊之一 對應者之間形成一電連接。 15. 如申請專利範圍第14項所述的方法，其中： 該基板之該接合表面具有第二複數個基板接合墊布置於其 上；及 ^ 該複數個晶粒的每個晶粒具有第二複數個晶粒接合墊沿著其 至少一個第二邊緣配置； ^ 該方法另外包含： 在泫第一複數個基板接合墊之每一者及該第二複數個晶粒接 合墊之一對應者之間附著接合引線。 24 201205760 16. 如申請專利範圍第15項所述的方法，其中： 在該複數個接合柱之每—者及該第—複數個晶_合塾〜— 對應者之間形成-電連接包含職複數個接合枉之每 ^ 該第一複數個晶粒接合墊之一對應者。 17. 如申請專利範圍第15項所述的方法，其中： 之一 在該複數個接合柱之每一者及該第—複數個晶粒接合塾 =者巧形成-電連接包含制—導電環氧細旨將該複數個接 &柱之母—者連接至該第—複數個晶粒接合塾之—對應者。 18_如申請專利範圍第14項所述的方法，其中： 形成該複數個實質上垂直接合柱之每一者包含： 接合墊之接合機形成—球形接合於該第—複數個基板 引線；及形成—附著至該球形接合且—般從該基板之表面延伸的 在距该基板之該接合表面之一所要 藉此形成-所要高度的—接合柱。Η離妨下該引線， 19.如申請專利範圍第18項所述的方法，其中. 形成該複數财質上垂直接妹之每—者料包含： 形成一球於該引線之一上端。 2〇.如:請專利範圍第丨4項所述的方法，其中： 複數個晶粒包含定位該複數個晶_至少―個晶粒 晶粒的第一邊緣突出於連接至-先前堆疊晶粒的該 25
TW100113345A 2010-06-08 2011-04-18 Multi-chip package with pillar connection TW201205760A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US35262410P 2010-06-08 2010-06-08

Publications (1)

Publication Number Publication Date
TW201205760A true TW201205760A (en) 2012-02-01

Family

ID=45063842

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100113345A TW201205760A (en) 2010-06-08 2011-04-18 Multi-chip package with pillar connection

Country Status (5)

Country Link
US (2) US8637984B2 (zh)
JP (1) JP2013528324A (zh)
KR (1) KR20130129165A (zh)
TW (1) TW201205760A (zh)
WO (1) WO2011153609A1 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014082245A (ja) * 2012-10-15 2014-05-08 J Devices:Kk 半導体記憶装置及びその製造方法
US8987009B1 (en) 2013-01-15 2015-03-24 Xilinx, Inc. Method and apparatus for tracking interposer dies in a silicon stacked interconnect technology (SSIT) product
KR102110984B1 (ko) 2013-03-04 2020-05-14 삼성전자주식회사 적층형 반도체 패키지
KR102299673B1 (ko) 2014-08-11 2021-09-10 삼성전자주식회사 반도체 패키지
WO2016049940A1 (en) * 2014-10-03 2016-04-07 Intel Corporation Overlapping stacked die package with vertical columns
TWI566356B (zh) 2015-10-15 2017-01-11 力成科技股份有限公司 封裝結構及其製造方法
WO2018125159A1 (en) * 2016-12-29 2018-07-05 Intel Corporation Semiconductor package having singular wire bond on bonding pads
WO2019066986A1 (en) * 2017-09-30 2019-04-04 Intel Corporation STACK OF NON-TSV CHIPS USING PLATED PILLARS / CROSSING MOLD INTERCONNECTION
DE112017008335T5 (de) 2017-12-28 2020-09-03 Intel Corporation Multi-Die, Vertikal-Draht-Package-in-Package-Vorrichtung und Verfahren zum Herstellen desselben
US10593383B1 (en) 2018-09-04 2020-03-17 Micron Technology, Inc. System-level timing budget improvements
US10642512B2 (en) 2018-09-04 2020-05-05 Micron Technology, Inc. Low-speed memory operation
US20200075548A1 (en) * 2018-09-04 2020-03-05 Micron Technology, Inc. Interconnects for a multi-die package

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5422435A (en) * 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5721452A (en) * 1995-08-16 1998-02-24 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
JP3879351B2 (ja) * 2000-01-27 2007-02-14 セイコーエプソン株式会社 半導体チップの製造方法
US6818545B2 (en) 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US7618848B2 (en) 2006-08-09 2009-11-17 Stats Chippac Ltd. Integrated circuit package system with supported stacked die
US7737563B2 (en) 2008-06-04 2010-06-15 Globalfoundries Inc. Semiconductor chip with reinforcement structure
US20100044861A1 (en) * 2008-08-20 2010-02-25 Chin-Tien Chiu Semiconductor die support in an offset die stack
US20100270668A1 (en) 2009-04-28 2010-10-28 Wafer-Level Packaging Portfolio Llc Dual Interconnection in Stacked Memory and Controller Module
US20110227216A1 (en) * 2010-03-16 2011-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Under-Bump Metallization Structure for Semiconductor Devices

Also Published As

Publication number Publication date
KR20130129165A (ko) 2013-11-27
US20140141566A1 (en) 2014-05-22
US8637984B2 (en) 2014-01-28
JP2013528324A (ja) 2013-07-08
WO2011153609A1 (en) 2011-12-15
US20110298128A1 (en) 2011-12-08

Similar Documents

Publication Publication Date Title
TW201205760A (en) Multi-chip package with pillar connection
US10510659B2 (en) Substrate-less stackable package with wire-bond interconnect
TWI686918B (zh) 晶圓級堆疊晶片封裝及製造其之方法
US7355274B2 (en) Semiconductor package, manufacturing method thereof and IC chip
TWI408795B (zh) Semiconductor device and manufacturing method thereof
US7547630B2 (en) Method for stacking semiconductor chips
TWI303096B (zh)
TWI355061B (en) Stacked-type chip package structure and fabricatio
TWI330872B (en) Semiconductor device
TW201222721A (en) Method of manufacturing semiconductor device
US20070216008A1 (en) Low profile semiconductor package-on-package
KR102438456B1 (ko) 반도체 패키지 및 반도체 패키지의 제조 방법
TW200913210A (en) Packaged semiconductor assemblies and methods for manufactruing such assemblies
TW200919691A (en) Stacked package and method of manufacturing the same
TW200818435A (en) Metal core foldover package structures, systems including same and methods of fabrication
JP2009506571A (ja) インターポーザー基板に接続するための中間コンタクトを有するマイクロ電子デバイスおよびそれに関連する中間コンタクトを備えたマイクロ電子デバイスをパッケージする方法
TWI622107B (zh) 具有嵌入在延伸基板和底部基板之間的半導體晶粒的半導體裝置
TW201140712A (en) Method of stacking flip-chip on wire-bonded chip
TW201250942A (en) Integrated circuit packaging system with routed circuit lead array and method of manufacture thereof
JP2007027526A (ja) 両面電極パッケージ及びその製造方法
TW200805620A (en) Method of packaging a plurality of integrated circuit devices and semiconductor package so formed
JP3972182B2 (ja) 半導体装置の製造方法
KR100800149B1 (ko) 스택 패키지
JP2007214238A (ja) 半導体装置およびその製造方法
TWI651827B (zh) 無基板封裝結構