201142963 發明說明： 【發明所屬之技術領域】 本發明係有關於1半導義裝技術， 腳（quad flat nolead)封裝方法。 〜裡迓狗十熟按 【先前技術】 ，半賴難製財，由於電子產雜驗 斷增多，使得封裝密度隨之不斷摞离，亦刀月匕个 r •wrMn 斷挺亦％縮小封裝尺寸與改良封 裝技術。如何開發㊉讀與細間闕職製雖 為此技術領域之重要課題。 -衣故取不直馬 【發明内容】 ^解決上述問題，本發明目的之—係提供_種四邊扁平益接腳 封裝方法，可祕純度與細間距_裝製程且提高製程良率。 上述目的，本發明—實施例之-種四邊扁平無接腳封穿 方法’係包括下列步驟：提供—封賴板，其中雕载板至少二= δ又置離金屬層；形成―®案化金屬層於封裝載板上，並暴露出 .可剝離金屬層，其巾_化金屬層係包含 個導獅、複編; 及移除封裝載板並暴露出對外接墊。 ” 以下藉由賤實_配合__式詳加綱 發明之目的、技術内容、特點及其所達成之功效。^易瞭解本 【實施方式】 以限定本發 其詳細說明如下’所述較佳實施例僅做—說明非用 201142963 ^圖1A、圖1D、圖1E、圖IF、圖1G與圖1H為本發明一 =例之四邊扁平無接腳封裝方法的流程示意圖。於本實施例中，四 邊扁平無接腳封裝方法包括下列步驟。 之$ If ’如圖1八所示’提供—封裝載板ig。其中，此封裝載板10 ^表面叹置-可剝離金屬層2G。接著，請繼續參顏，形 伤勺I案化金屬層40於可剝離金屬層20上。其中’圖案化金屬層40 係匕3至少一晶片承座42與複數個導電接塾44。 著置一晶片5〇於晶片承座42上，如圖1E所示。晶片5〇 複數剌^耆材料（圖上未標）固定於晶片承座42上。之後，利用 複數條引線60電性連接晶片50與導電接墊44。 電接in參照圖if，利用一封裝材料7〇覆蓋晶片5〇、引線6〇、導 電接塾44與可剥離金屬層20。 2〇之ΪΪ面如圖—示’移除封裝載板1〇並暴露出可剝離金屬層 士口圖1Η所示’對可剝離金屬層2〇 (如圖戰 =序用以形成複數個外部接點22。其中，外 g 墊44電性連接。 货…守电接 請2續參聞1H，於本實施财，每—外部接點U之 於母一導電触44，可提供魏魏㈣ 然，本發祕於此，外部_ 22之Η* 大的接觸面積。 者與設計者的需求。於-實施例中，如狀取決於使用 如導電柱—d⑽ive pillar)，其尺寸係; =之輸㈣叫物稱做 於本發明中，《封裝_外部接點是儀移 麵金屬層進行圖案化製程所得。因此，如圖M所示:== 201142963 ^|^可°又汁成具有重新佈線(re-lay〇Ut)導電接塾44的對外接點，如 此可因應客戶需求增加封裝體的可變化性。 卜接..沾 金屬’同實_中’封裝»10的表面可設置一 表面4金面屬可剝離金屬層20之剝離。此金屬易剝離 衣囟了為金屬㈣或其他統㈣所構成表面。 «===_彻峨，如影像轉移製 可利用影像轉移製程^製m圖^與圖=，圖案化金屬層40 進可糖金屬層2g之上表面，如_所示。 圖rd成圖案化金屬層4〇於暴露於外的可剝離金屬層2〇上，如 實施像轉移層3°完成圖案化金屬層-之製作。於另-貝爛甲（圖上未不），形成圖案化 力 層於封裝載板之表面上，之後^ ^亦可先形成一金屬 屬層。 ㈣订麟麵刻程序以形成此圓案化金 請同時參照圖1Α、圖1D，1e 實施例中’四邊扁平無接腳封裝miF、圖1g與圖兀，於本 封裝載板H)，其中此封裝載板10之至;。首先，提供― 20，如圖1A所示。接著， ^面汉置一可剝離金屬層 20上，其中此圖案化金屬層40係包^：、驾曰層40於可獅金屬層 電接墊44，如圖m所示。 V阳片承座42與複數個導 之後，參照圖1E ,設置—曰κ ςΛ ^ 引線60電性連接晶片5〇與導電接執；:片承座42並利用複數條 示’利用-封裝材料70覆蓋晶片5〇绩、後，如圖iF與圖1〇所 離金屬層2〇 ;以及利用一敍刻 引線60、導電接墊44與可剥 收序猶可_金屬層20。 201142963 於本實施例中，本發明所使用之封裝載板具有可剝離金屬層2〇， 因此可選擇性對此可剝離金屬層20進行圖案化製 移除此可剝離金屬層20，如圖1G與圖2C所示。於一實施例中，移 除此可娜金屬層％之同時更可進—步移除部份厚度之圖案化金屬 層40，如圖，如圖ig '圖2D所示。 請參照圖3A、圖3B、圖3C與圖3D，本發明之導電接塾與外部 接點之結構係、具有多種變化外’更可選擇性的形成—金屬表面處理層 80於外部接點22或導電接墊私上。其中’導電接墊私之上下表: 都可選擇性的設置金屬表面處理層80於其上。201142963 DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to a semi-conducting technology, a quad flat nolead encapsulation method. ~ 迓 迓 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十 十With improved packaging technology. How to develop the ten-reading and fine-duty system is an important issue in this technical field. - The present invention solves the above problems. The object of the present invention is to provide a method for encapsulating a four-sided flat benefit pin, which can be used for secret purity and fine pitch_loading process and improve process yield. The above object, the method of the present invention - the four-sided flat-free pin-free sealing method comprises the following steps: providing a sealing plate, wherein the carving plate is at least two = δ and is further separated from the metal layer; forming a "--" The metal layer is on the package carrier and exposes the strippable metal layer, the towel-metal layer includes a lion, a composite; and the package carrier is removed and the external pad is exposed. The following is a summary of the purpose, technical content, features and effects achieved by the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The embodiment is only used to illustrate the non-use 201142963. FIG. 1A, FIG. 1D, FIG. 1E, FIG. 1F, FIG. 1G and FIG. 1H are schematic flowcharts of a four-sided flat pinless package method according to an embodiment of the present invention. The four-sided flat pinless package method includes the following steps: $If ' is provided as shown in Fig. 18. The package carrier ig is provided. The package carrier 10 ^ surface is slid - the peelable metal layer 2G. Then, Please continue to refer to the shape of the metal layer 40 on the peelable metal layer 20. The 'patterned metal layer 40 is 3 至少 3 at least one wafer holder 42 and a plurality of conductive interfaces 44. 5 is mounted on the wafer holder 42, as shown in FIG. 1E. The wafer 5 is affixed to the wafer holder 42 by a plurality of materials (not shown). Thereafter, the plurality of leads 60 are used to electrically connect the wafer 50 with Conductive pad 44. Electrical connection in reference to Figure if, using a packaging material 7 〇 cover the wafer 5 〇, lead 6〇, conductive interface 44 and strippable metal layer 20. 2〇 ΪΪ 如图 — — 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除Stripping the metal layer 2〇 (as shown in the battle = sequence to form a plurality of external contacts 22. Among them, the outer g pad 44 is electrically connected. The goods... the power is connected to the 2nd to continue to participate in the 1H, in this implementation, each - The external contact U is connected to the mother-conductive contact 44, which can provide Wei Wei (four). However, the external contact is outside, and the external contact area is large. The contact area of the designer and the designer. In the embodiment, The shape depends on the use of a conductive column - d (10) ive pillar, its size is; = the input (four) called the object is said to be in the present invention, "package _ external contact is the transfer surface of the metal layer for the patterning process. Therefore, such as As shown in Fig. M: == 201142963 ^|^ can be etched into an external contact with re-laying (Ut) conductive interface 44, so that the variability of the package can be increased according to customer needs. .. The surface of the metal-on-consolidation package can be peeled off. The metal is easily peeled off. The clothes are made of metal (4) or other systems (4). «===_Clean, such as image transfer system can use image transfer process ^ m picture ^ and figure =, patterned metal layer 40 into the sugar metal layer 2g upper surface, as shown in _. Figure rd is patterned metal layer 4 on the outer strippable metal layer 2, such as the implementation of the transfer layer 3 ° to complete the patterned metal layer - the other -Bei rotten nail (not shown on the picture), forming a patterned force layer on the surface of the package carrier, and then forming a metal layer first. (4) Ordering the face engraving program to form the round gold Referring to FIG. 1A, FIG. 1D, and the 1e embodiment, a four-sided flat pinless package miF, FIG. 1g and FIG. 2, in the package carrier board H), wherein the package carrier board 10; First, provide -20, as shown in Figure 1A. Then, a patterned metal layer 40 is disposed on the metal layer 40, and the driving layer 40 is mounted on the metal layer 44 of the lion metal layer, as shown in FIG. After the V-positive holder 42 and the plurality of leads, referring to FIG. 1E, the 曰κ ςΛ ^ lead 60 is electrically connected to the wafer 5 〇 and the conductive connection; the sheet holder 42 is represented by a plurality of 'utilization-encapsulation materials 70 covers the wafer 5 performance, after, as shown in Figure iF and Figure 1 〇 away from the metal layer 2 〇; and utilizes a scribe conductor 60, a conductive pad 44 and a peelable sequence _ metal layer 20. 201142963 In the present embodiment, the package carrier used in the present invention has a peelable metal layer 2, so that the strippable metal layer 20 can be selectively patterned to remove the peelable metal layer 20, as shown in FIG. 1G. As shown in Figure 2C. In one embodiment, the portion of the thickness of the metal layer can be removed while removing the patterned metal layer 40 of a portion of the thickness, as shown in FIG. 2D. Referring to FIG. 3A, FIG. 3B, FIG. 3C and FIG. 3D, the structure of the conductive interface and the external contact of the present invention has a plurality of variations and is more selectively formed - the metal surface treatment layer 80 is on the external contact 22 Or the conductive pads are private. Wherein the conductive pads are privately placed on the table: the metal surface treatment layer 80 can be selectively disposed thereon.
於本發明中，作為晶片承座與導電接墊之圖案化金屬層可選擇電 ，的方式製作，因此只要纏曝紐術可配合做_間距此方法可 製作出品質優良之小尺寸與細間距的導電接墊。相較於蝕刻方式，由 於觉限於藥水置換速度影響侧率以及厚度的關，其對於細間距的 控制難度提高1此，使用紐方式可具雜高的可紐與達成率， 故可製作#又複雜的導電接墊結構，如圖5所示，側面為階梯狀的導電 接塾44’的結構。此方法亦可製作導電接塾可具有一正梯形或倒梯形 結構，如圖4A與圖4B所示。 接續上述說明，製成此結構的方法如後所述，參照圖1C，於影 像轉移層3G間與可剝離金屬層％上電難作—第—圖案化金屬: 後’例如圖案化金屬層*，可設置一次影像轉移I 3〇,於圖案化金屬 f 4〇上並暴露出部分圖案化金屬層40之上表面，如圖6A所示。接 者，電鍍形成一第二圖案化金屬層43於暴露於外的圖案化金屬層 上，如圖6B所示。然後，參照圖6C，移除影像轉移層3〇與次影像 轉移層3〇’即可獲得導電接& 44’之側邊具有一階梯狀結構，如圖π 所V ^本發明之四邊扁平無接腳封裝結構並不限於此，卿上述方 法製作如圖4D所示側邊具有一階梯狀結構之導電接塾44。 本發明方法可藉由控制影像轉移層（30，圖1B)形狀，如梯形 201142963 吻謹正賴軸結構，如 於-實施例中’請參照圖？A與圖π，圖案化金屬層 夕一晶片承座42與複數個導電接墊44外，更包括-線路仏 電性連接兩兩導電接塾44。其中，兩兩導電接墊料之：= 5〇利用引線60電性連接，而莫雷垃埶心^ 7 用从與日曰片 (如圖黯另—側物卜部接點22 之電性連接。其中，如前所述，更 置金屬表面處理層80於用於打線的導電接墊料上。更I擇性的设 製造平無接㈣財法，用以 板，其中雜餘S I ^胸：提供—封裝載 屬層置一可剝離金屬層;形成-圖案化金 係包含至少-Μ ^ 可剝離金屬層’其中圖案化金屬層 墊;進行一曰：封ϋ、複數個導雜墊、複數線路與複數個對外接 中Η 都驟，以及移除封輯板並暴露㈣外接墊。豆 ==她一實施— 層^牛:層於圖案化金屬層與暴露出的可剝離金屬 f至圖9G為本發明一實施例之四邊爲平無接 步驟巧 μ τ思圖，繪不设置一下接合層於圖案化金屬層下之 化圖^繪示同時分別形成上接合層與下接合層於圖案 金屬層上與下。其貫施瓣細說明如下。 少-參ΐΓΑ，提供一封裝载板10，其中封裝載板1〇的至 夕表面汉置一可制離金屬層20。接著 化金屬層40於可剝離金屬声2 α Β所不I成一圖案 ，其中圖案化金屬層4〇係曰包含至上曰並^出部分可剝離金屬層 執44 、卜^h b ^ 日日片承座42、複數個導電接 的與複數個對外接塾48。如圖8C所示，可選擇性 圖案:化於用於打線的導電接塾44上。於此實施例中，形成 上.電卿^安的步驟包括：設置一影像轉移層於可剝離金屬層20 ，電錢喊_化金麟⑽於可_金顧Μ上；錢移除 [] 201142963 轉移層。 法形I - 所示’糊包含顧、蒸鑛或電鑛的方 20上。以及，JJ8D所。4°與暴露於外的可剝離金屬層 更者，，參老 不’移除部份上接合層90以露出打線藝82。 晶片承座42。以適當方式移除部份上接合層90以暴露出部分 片承ΪΓ上進晶片封農步驟。如圖8F所示，設置一晶片5〇於晶 44 ’、且彻触條.⑼電性連接^ Μ與導電接墊 :或者如有設置打線塾82則電性連接晶片 8 =塾 旋^塗佈= 其中封裝材料7G包含但不限於利用注膠、網印、 t ""44 ° - 使翌*44且兩兩導電接墊44之一與晶〇 =兩:電接：之另一與對外接墊48電性連接。最後，如圖ί 接人心Λ τ移除_敏1G以暴露出®案化金屬層4G及部分上 j 90。射移除触1G後，更包括以包含侧的方式移除 式移以形成如圖8G的結構。請參考圖8H，更包括以適當方 工矛、暴路出的部分上接合層9〇，如圖中箭頭所示，以電性分離 ^ 42與導電接塾44 ^再來，請參相81，可選擇性的設置金: ^處^層8〇於外露的對外 48上。於一實施射，請繼續參考圖 絕緣^暴Si的勺圖人案Γ金屬層仙上設置一絕緣層％ ’其中形成此 H 、式0 3但不限於棕氧化（Brown Oxide)及黑化㈤喊 〇她）處理。在金朗與職㈣之_成—接合層可增 料與金屬層之間的接合功能。 裝材 接續上述，圖9A至圖9H為本發明又一實施例之四邊扁平 腳封襄方法的流程示賴，於本實施例中，四邊扁平無接腳封襄^； 包括下列步驟。與上述實施例差異在於，形成-下接合層於圖案化金 屬層之下。 、 201142963 首先如® 9A所不，提供一封裝載板10，其中封裝載板10的 至少一表面設置一可剝離金屬層20。接著，如圖9B所示，形成一下 接合層92於可刻離金屬層2〇上，其中下接合層％為一圖案化接合 層使心可$彳離錢層2〇暴露於外，且下接合層％包含但不限於以 至/接口層堆疊形成。再來，如圖9C所示，形成一圖案化金屬層 4〇’於可娜金屬層2〇収科下接合層92上。如同上述實施例中 所描述，圖案化金屬層40,包括至少一晶片 42,、複數個導電接整 44’、複數線路46,與對外接墊48，，其中部分圖案化金屬層奶，完全設 置^下接合層92上’如晶片承座42’ ；_部分圖案化金屬層4。，部分In the present invention, the patterned metal layer as the wafer holder and the conductive pad can be electrically selected, so that the small size and the fine pitch can be produced by the method. Conductive pads. Compared with the etching method, it is limited to the influence of the speed of the medicinal water replacement on the side rate and the thickness, and the control of the fine pitch is more difficult. The use of the nucleus method can have a high and a high rate of achievement, and thus can be made. The complex conductive pad structure, as shown in FIG. 5, has a structure of a stepped conductive interface 44' on the side. The method can also produce a conductive interface which can have a positive trapezoidal or inverted trapezoidal structure, as shown in Figures 4A and 4B. Following the above description, the method of fabricating the structure will be described as follows. Referring to FIG. 1C, it is difficult to electrically charge the peelable metal layer between the image transfer layer 3G. - Patterned metal: After 'eg patterned metal layer* An image transfer I 3 可 can be set on the patterned metal f 4 并 and expose the upper surface of the partially patterned metal layer 40 as shown in FIG. 6A. The substrate is electroplated to form a second patterned metal layer 43 on the exposed patterned metal layer, as shown in Figure 6B. Then, referring to FIG. 6C, the image transfer layer 3〇 and the sub-image transfer layer 3〇' are removed to obtain a stepped structure on the side of the conductive connection & 44', as shown in FIG. The pinless package structure is not limited thereto, and the above method produces a conductive interface 44 having a stepped structure on the side as shown in FIG. 4D. The method of the present invention can control the shape of the image transfer layer (30, Fig. 1B), such as the trapezoidal 201142963. The kiss structure depends on the axis structure, as in the embodiment, please refer to the figure. A and the figure π, the patterned metal layer, the wafer carrier 42 and the plurality of conductive pads 44, further includes a circuit 仏 electrically connecting the two conductive pads 44. Wherein, two or two conductive pad materials: = 5 〇 electrically connected by the lead wire 60, and the Morey 埶 heart ^ 7 is electrically connected with the 曰 曰 ( 黯 ( ( ( ( 侧 侧 侧 侧In the above, as described above, the metal surface treatment layer 80 is further disposed on the conductive pad material for wire bonding. The more selective design is to manufacture the flat connection (four) financial method for the board, wherein the residual SI ^ chest Providing a package-loading layer with a strippable metal layer; forming-patterning a gold system comprising at least - Μ ^ strippable metal layer 'where the metal layer pad is patterned; performing a 曰: sealing, a plurality of conductive pads, Multiple lines and a plurality of external contacts are removed, and the seal plate is removed and exposed (4) the outer pad. Bean == her implementation - layer ^ cow: layer on the patterned metal layer and the exposed strippable metal f to FIG. 9G is a schematic diagram of a four-side flat connection method according to an embodiment of the present invention, in which the bonding layer is not disposed under the patterned metal layer, and the upper bonding layer and the lower bonding layer are respectively formed. The pattern metal layer is upper and lower. The detailed application of the valve is as follows: Less-Shenzhen, providing a loading plate 10, The surface of the package carrier is placed on the surface of the metal layer 20. The metal layer 40 is then formed into a pattern of the strippable metal 2α ,, wherein the patterned metal layer 4曰 ^ 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分 部分In the wire bonding conductive interface 44. In this embodiment, the step of forming the upper electrode includes: setting an image transfer layer on the peelable metal layer 20, and the electric money shouting _ ing Jinlin (10) in the _ gold Gu Yushang; money removal [] 201142963 transfer layer. Form I - shown in the 'paste containing Gu, steam or ore on the side 20. And, JJ8D. 4 ° and the exposed stripped metal layer Moreover, the old part does not remove part of the upper bonding layer 90 to expose the bonding pattern 82. The wafer holder 42. The partial upper bonding layer 90 is removed in an appropriate manner to expose a portion of the upper substrate to the wafer. Step 8. As shown in FIG. 8F, a wafer 5 is disposed on the crystal 44', and the strip is electrically connected. (9) electrically connected to the conductive pad: or If the wire 塾 82 is set, the chip 8 is electrically connected. The coating material 7G includes, but is not limited to, using glue injection, screen printing, t "<44 ° - making 翌*44 and two-conducting One of the pads 44 and the wafer = two: electrical connection: the other is electrically connected to the external pad 48. Finally, as shown in Figure ί, the _1G is removed to expose the metal layer 4G and Part of the j 90. After removing the touch 1G, it further includes removing the movement in a manner including the side to form the structure as shown in Fig. 8G. Please refer to Fig. 8H, and further including the part with the appropriate square spear and the violent path. The bonding layer 9〇, as shown by the arrow in the figure, is electrically separated by 42 and the conductive interface 44 ^, please refer to phase 81, and the gold can be selectively set: ^ where the layer 8 is exposed to the external 48 on. In the first shot, please continue to refer to the figure insulation ^ storm Si's spoon figure, the metal layer is set on an insulating layer % ' which forms this H, formula 0 3 but not limited to brown oxidation (Brown Oxide) and blackening (five) Shouting her) deal with it. In the Jinlang and the (4) _ into the joint layer can increase the bonding function between the metal layer. Continuing the above, FIG. 9A to FIG. 9H are schematic diagrams showing a flow of a four-sided flat foot sealing method according to still another embodiment of the present invention. In the present embodiment, the four-sided flat no-pin sealing device includes the following steps. The difference from the above embodiment is that the formation-lower bonding layer is under the patterned metal layer. , 201142963 First, as shown in ® 9A, a loading plate 10 is provided in which at least one surface of the package carrier 10 is provided with a peelable metal layer 20. Next, as shown in FIG. 9B, a lower bonding layer 92 is formed on the etchable metal layer 2, wherein the lower bonding layer % is a patterned bonding layer, so that the core can be exposed to the outside, and the lower The bonding layer % includes, but is not limited to, a stack of / interface layers. Further, as shown in Fig. 9C, a patterned metal layer 4?' is formed on the bonding layer 92 of the Kona metal layer. As described in the above embodiments, the patterned metal layer 40 includes at least one wafer 42, a plurality of conductive arrays 44', a plurality of lines 46, and an external pad 48, wherein a portion of the patterned metal layer milk is completely disposed. ^ Under the bonding layer 92 'such as the wafer holder 42'; _ partially patterned metal layer 4. ,section
覆盖下接合層92部分覆蓋可娜金屬層π，如導電触从、線路 ”對外接塾48。接著，如圖9D所示，移除晶片承座42,周圍下方 =下接。層92如圖中箭頭所示，使晶片承座42,與設置於其周圍的 導電接墊44’電性分離。 接著，’進仃-晶片封裝步驟。如圖9E所示，設置一晶片％,於晶 承座42，且利用複數條引線6〇，電性連接晶片％，與導電接墊叫，； 以及利用-缝材料7G，包封引線⑽、晶片5〇,、下接合層92、可剝 電接墊44’ °並且選擇性在導電接墊44,上形成打線 最後，如圖9E_F穌，移除封裝載板 H)以及侧掉可剝離金屬層2〇後，暴露出對外接塾仙，及下接合層 其中Γ處下接合層92具有防悍層之作用。於-實施例中，如圖 』不可選擇性的設置金屬表面處理層8〇,於外露的對外接塾糾， 9〇,於如同上述實施例中所示，更包括形成一上接合層 7t 70""5 -5 金屬邊騎無接崎財法藉錢料有可剝離 、反’並可_此可齡金屬層進行_化作為其後封 μ的Γ提供整體職製程與職結構❹樣性；而在上下接 曰、处理上射糊其材料特性以增加㈣化金屬層與封裝材料 201142963 間的結構強度，加強其拉力值，並避免在SMT _程中造成因線路 橋接而短路，同時保護金顧㈣免祕。另外 传 2技術與設備，並未增加成本與_。更者，由=== ^層之製鶴彡轉雜術或黃級馳術，因財有效達成 構°本發明除可使用現有技術外，亦可應用於雙 用了口收或重複仙材f，具有較低的成本與較佳的優勢。 at所述之實施例僅係為說明本發明之技術思想及特點，宜目的 =:=rr本發明之内容並據•，當： 等變化或修飾，減涵蓋&在本揭示之精神所作之均The underlying bonding layer 92 partially covers the Kona metal layer π, such as the conductive contact, the line "external contact" 48. Next, as shown in Fig. 9D, the wafer holder 42 is removed, and the lower side = bottom is connected. As shown by the middle arrow, the wafer holder 42 is electrically separated from the conductive pads 44' disposed around it. Next, 'into the wafer-packaging step. As shown in FIG. 9E, a wafer % is set. The socket 42 is electrically connected to the wafer by a plurality of leads 6 ,, electrically connected to the wafer, and the conductive material is used to cover the lead (10), the wafer 5 〇, the lower bonding layer 92, and the strippable electrical connection. The pad 44'° and selectively forms a wire on the conductive pad 44, finally, as shown in FIG. 9E_F, removes the package carrier H) and side away from the peelable metal layer 2, and exposes the external connection, and the lower In the bonding layer, the lower bonding layer 92 has the function of the anti-mite layer. In the embodiment, the metal surface treatment layer 8〇 is not selectively disposed as shown in the figure, and the external external contact is corrected, 9〇, as in the case The above embodiment further includes forming an upper bonding layer 7t 70""5 -5 metal side riding without connection The financial method borrows money and has the material that can be stripped, reversed, and can be used as the post-sealing metal layer to provide the overall job and job structure. Its material properties increase the structural strength between the (four) metal layer and the encapsulation material 201142963, strengthen its tensile value, and avoid short circuit caused by line bridging in the SMT process, while protecting the Jin Gu (4) exemption. Equipment, does not increase the cost and _. Moreover, by the === ^ layer of the crane 彡 彡 or yellow grading, due to the effective realization of the structure of the invention, in addition to the use of the existing technology, can also be applied The utility model has the advantages of lower cost and better advantage. The embodiment described above is only for explaining the technical idea and characteristics of the present invention, and the purpose of the invention is:==rr And according to •, when: change or modify, reduce coverage &
[S] 201142963 【圖式簡單說明】 圖1A、圖1B、圖1C、圖1D、圖1E、圖1F、圖1G與圖 1H為本發明一實施例之流程示意圖。 圖2A、圖2B、圖2C與圖2D為本發明不同實施例之示意 圖。 圖3A、圖3B、圖3C與圖3D為本發明不同實施例之局部 放大示意圖。[S] 201142963 [Simplified Schematic Description] FIG. 1A, FIG. 1B, FIG. 1C, FIG. 1D, FIG. 1E, FIG. 1F, FIG. 1G and FIG. 1H are schematic diagrams showing the flow of an embodiment of the present invention. 2A, 2B, 2C and 2D are schematic views of different embodiments of the present invention. 3A, 3B, 3C and 3D are partially enlarged schematic views of different embodiments of the present invention.
圖4A、圖4B、圖4C與圖4D為本發明不同實施例之局部 放大不意圖。 圖5為本發明一實施例之示意圖。 圖6A、圖6B與圖6C為本發明一實施例之部分流程示意圖。 圖7A與圖7B為本發明一實施例之示意圖。 圖8A、圖8B、圖8C、圖8D、圖8E、圖8F、圖8G、圖8H 與圖81為本發明不同實施例之示意圖。 圖9A、圖9B、圖9C、圖9D、圖9E、圖9F、圖9G與圖 9H為本發明不同實施例之示意圖。 【主要元件符號說明】 10 封裝載板 12 金屬易剝離表面 20 可剝離金屬層 22 外部接點 30、32 影像轉移層 2011429634A, 4B, 4C and 4D are partial enlarged views of different embodiments of the present invention. Figure 5 is a schematic illustration of an embodiment of the invention. 6A, 6B and 6C are partial flow diagrams of an embodiment of the present invention. 7A and 7B are schematic views of an embodiment of the present invention. 8A, 8B, 8C, 8D, 8E, 8F, 8G, 8H and 81 are schematic views of different embodiments of the present invention. 9A, 9B, 9C, 9D, 9E, 9F, 9G and 9H are schematic views of different embodiments of the present invention. [Main component symbol description] 10 Package carrier board 12 Metal easily peelable surface 20 Peelable metal layer 22 External contacts 30, 32 Image transfer layer 201142963
30， 次影像轉移層 40 圖案化金屬層 42、42， 晶片承座 43 第二圖案化金屬層 44、44， 導電接墊 46、46， 線路 48、48， 對外接墊 50、50， 晶片 60、60， 引線 70、70， 封裝材料 80、80， 金屬表面處理層 82 、 82， 打線墊 90、90， 上接合層 91 絕緣層 92 下接合層 m 1230, secondary image transfer layer 40 patterned metal layers 42, 42, wafer carrier 43 second patterned metal layer 44, 44, conductive pads 46, 46, lines 48, 48, external pads 50, 50, wafer 60 60, leads 70, 70, encapsulating materials 80, 80, metal surface treatment layers 82, 82, wire pads 90, 90, upper bonding layer 91 insulating layer 92 lower bonding layer m 12