201140671 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及一種管芯貼片的製造方法，特別涉及一種用 於超薄晶圓工藝的管芯貼片方法。 【先前技術】 [0002] 為了適應積體電路晶片封裝輕小化發展趨勢，人們往往 希望晶圓的厚度能夠做到非常的薄。然而，在晶片的封 裝製造過程中，矽片需要有足夠的厚度’否則其機械強 度不夠，會在封裝製造過程中產生破裂，特別是在晶圓 者面減薄工藝（Wafer Backside Grinding)以及晶圓 顆粒裝片粘合（Die Attach)工藝過程中，將晶圓減薄 至100仁m或者以下，極易造咸良品率啲極大降低。 [〇〇〇3]在晶圓顆粒的裝片粘合（Die Attach)過程中，晶圓顆 粒是靠導電銀漿（Ep〇xy)將晶圓顆粒貼合於引線框架或 是佈線基板上，由於導電銀漿钓分散劑是環氧類的樹脂 ，與矽的接觸角很小，同時存在“銀遷移”現象，所以 ，傳統封裝方式中，導電銀漿易於吸附晶圓顆粒的矽基 底並攀爬至晶圓顆粒配置有積體電路的一面，從而腐蝕 積體電路單元或導致積體電路的短路，損壞晶圓顆粒的 電性能。 [0004]另一方面’導電銀衆過高，或是枯接晶圓顆粒的工藝過 程，晶圓顆粒可能有小的橫向移位，搓動導電銀漿導致 晶圓顆粒表面覆蓋有少許銀漿，從而導致後續的引線鍵 合（Wire Bonding)將難以進行，容易造成鍵合在引線 鍵合區（Pad)的引線不粘（N〇n_Stick)或是虛焊（ 099114638 表單編號A0101 第4頁/共23頁 0993263731-0 201140671 [0005] ❹ [0006] Ο [0007] [0008] [0009]201140671 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a method of manufacturing a die chip, and more particularly to a die attach method for an ultra-thin wafer process. [Prior Art] [0002] In order to adapt to the trend of slimming of integrated circuit chip packages, it is often desired that the thickness of the wafer can be made very thin. However, in the package manufacturing process of the wafer, the ruthenium sheet needs to have sufficient thickness 'otherwise its mechanical strength is insufficient, which will cause cracks in the package manufacturing process, especially in the Wafer Backside Grinding and Crystal During the Die Attach process, the wafer is thinned to 100 m or less, and the yield of the salt is greatly reduced. [〇〇〇3] In the die attach process of wafer particles, the wafer particles are bonded to the lead frame or the wiring substrate by conductive silver paste (Ep〇xy). Since the conductive silver paste dispersant is an epoxy resin, the contact angle with the crucible is small, and there is a phenomenon of “silver migration”. Therefore, in the conventional packaging method, the conductive silver paste is easy to adsorb the crucible base of the wafer particles and climb. Climb to the side of the wafer particles where the integrated circuit is disposed, thereby corroding the integrated circuit unit or causing a short circuit in the integrated circuit, damaging the electrical properties of the wafer particles. [0004] On the other hand, 'the conductive silver is too high, or the process of burying the wafer particles, the wafer particles may have a small lateral shift, and the conductive silver paste is tilted to cause the surface of the wafer particles to be covered with a little silver paste. Therefore, subsequent wire bonding (Wire Bonding) will be difficult to perform, and it is easy to cause the bonding of the bonding wires in the wire bonding region (Pad) to be non-sticky (N〇n_Stick) or solder joint (099114638 Form No. A0101 Page 4 / 23 pages 0993263731-0 201140671 [0005] ❹ [0006] Ο [0007] [0008] [0009]
Incomplete Bond)，而在之後的塑封（Molding)過 程t ’虛焊（Incompiete Bond )將導致弓丨線從引線 鍵合區（Pad)脫離（Baii Lift)，以致晶片功能性失 效。 如美國專利公開號為US2006/0035443A1，由hsu等人發 明的專利中，提出了局部晶圓的粘接及切割方法，是對 —支撐晶圓進行至少局部氧化構成多個氧化區，且對氧 化區進行平整化，支撐晶圓及其氧化區表面無任何材料 遮蓋，以氧化區作為粘接點將支撐晶圓與積體電路晶圓 粘接，通過這種绪構完成後續的工序。在對支撐晶圓和 積體電路晶圓的切割過程中，支撐晶圓會從積體電路晶 圓上分離開。這有利於增強晶圓的機械強度，然而其工 藝複雜，製作成本高^ 鑒於上述問題，本發明公開一種用於超薄晶圓工藝的管 芯貼片方法。其具有如下文所述之技術特康，以解決現 有的問題。 【發明内容】 為了解決上述技術問題，本發明提供了—種用於超薄晶 圓工藝的管芯貼片方法’該方法成本低廉、生產製作簡 單、工藝穩定，並且能有效提高產品良品率，提高晶圓 上電路的性能。 本發明的-種用於超薄晶圓卫藝的管芯貼片方法，包括 如下步驟： 提供-晶圓’所述晶圓包含晶圓正面和晶圓背面，在所 099114638 表單編號A0101 第5頁/共23頁 0993263731-0 201140671 [0010] [0011] [0012] [0013] [0014] [0015] [0016] [0017] [0018] [0019] 述晶圓正面形成積體電路； 提供一枯合層； 提供一支撐襯底，利用所述粘合層將支撐襯底粘合至晶 圓正面； 在晶圓背面進行晶圓背面減薄； 將帶有支撐襯底的晶圓粘合至切割膜上並對晶圓及支撐 襯底進行切割以形成數個帶有支撐襯底顆粒的晶圓顆粒 ， 將所述的數個晶圓顆粒粘合至與之相應的引線框架上； 從晶圓顆粒上剝離支撐襯底顆粒以完成管芯貼片。 上述的用於超薄晶圓工藝的管芯貼片方法，其中，晶圓 減薄後還包括對晶圓的背面進行背面工藝以形成器件電 極，所述背面工藝包括背面刻蝕、背面蒸發、背面注入 以及背面鐳射退火。 上述的用於超薄晶圓工藝的管芯貼片方法，其中，所述 支撑襯底為玻璃或石英。 上述的用於超薄晶圓工藝的管芯貼片方法，其中，所述 粘合層為雙面熱剝離膠帶。 上述的用於超薄晶圓工藝的管芯貼片方法，其中，所述 雙面熱剝離膠帶一面為壓敏膠粘合層，其另一面為熱剝 離膠粘合層，所述壓敏膠粘合層粘合在支撐襯底上，所 述熱剝離膠粘合層粘合在晶圓正面。 099114638 表單編號A0101 第6頁/共23頁 0993263731-0 201140671 [0020] [0021] [0022] Ο [0023] [0024]Ο [0025] [0026] 上述的用於超薄晶圓工藝的管芯貼片方法，其中，通過 對所述的粘合層進行加熱以從晶圓顆粒上分離粘合層的 ，從而實現從晶圓顆粒上剝離支撐襯底顆粒。 上述的用於超薄晶圓工藝的管芯貼片方法，其中，所述 粘合層為雙面紫外光照射自剝離膠帶。 上述的用於超薄晶圓工藝的管芯貼片方法，其中，所述 雙面紫外光照射自剝離膠帶一面為紫外光照射剝離輔助 粘合層，其另一面為紫外光照射自剝離粘合層，所述紫 外光照射剝離輔助粘合層粘合在支撐襯底上，所述紫外 光照射自剝離粘合層粘合在晶圓上。 上述的用於超薄晶圓工藝的管芯貼片方法，其中，通過 對所述雙面紫外光照射自剝離膠帶進行紫外線照射以從 晶圓顆粒上分離粘合層的，從而實現從晶圓顆粒上剝離 支撐襯底顆粒。 上述的用於超薄晶圓工藝的管芯貼片方法，其特徵在於 ，所述晶圓背面減薄是將晶圓減薄至小於等於100 。 本發明一種用於超薄晶圓工藝的管芯貼片方法由於採用 上述技術方案，使之與現有技術相比，具有以下優點和 積極效果： 1、本發明由於採用粘合層將支撐襯底粘貼在設有積體電 路的晶圓的正面，然後將晶圓進行背面減薄，在此過程 中，由於粘接一個支撐襯底於晶圓正面，使得晶圓的機 械強度大為增強，提高晶圓在背面減薄過程中的良品率 ，並可將晶圓減薄至100 A m或者以下。 099114638 表單編號A0101 第7頁/共23頁 0993263731-0 201140671 [0027] 2、本發明支撐襯底及粘合層隨著晶圓同步被切割，由於 晶圓顆粒上粘附有支撐襯底顆粒，增加了晶圓顆粒的機 械強度，使晶圓顆粒能以高良率粘貼在引線框架上或是 佈線基板上。 [0028] 3、本發明在晶圓顆粒粘合工藝過程中，粘合層及支撐槻 底顆粒覆蓋晶圓顆粒設有積體電路的那一面，避免由於 導電銀漿過高攀爬至積體電路，而影響晶圓上的積體電 路的性能。 【實施方式】 [0029] 根據本發明的申請專利範圍和發明内容所公開的内容， 本發明的技術方案具體如下所述： [0030] 如第1圖所示，一種單面膠包含離形紙層100、熱剝離膠 粘合層110、聚酯纖維層120，離形紙層100用於保護熱 剝離膠粘合層110，使用時撕去離形紙層100，熱剝離膠 粘合層110起粘合作用。 [0031] 如第2圖所示，相對於上述單面膠，雙面熱剝離膠帶包含 離形紙層200、另一離形紙層240、熱剝離膠粘合層210 、聚酯纖維層220、壓敏膠粘合層230。離形紙層200及 另一離形紙層240分別用於保護熱剝離膠粘合層210、壓 敏膠粘合層230，其中，熱剝離膠粘合層210、壓敏膠粘 合層230起粘合作用，可通過溫度調節熱剝離膠粘合層 210的粘合力。 [0032] 如第3圖所示，雙面紫外光照射自剝離膠帶包含離形紙層 300、另一離形紙層360、紫外光照射自剝離粘合層310 099114638 表單編號A0101 第8頁/共23頁 0993263731-0 201140671 、基帶薄膜340、紫外光照射剝離輔助粘合層350。其中 ，紫外光照射自剝離粘合層310、紫外光照射剝離輔助粘 合層350起粘合作用。當紫外光照射劑量在—定範圍内， 紫外光照射自剝離粘合層310完全釋放氣體並脫離粘合面 〇 [0033] Ο 如第4圖所示’晶圓400包含晶圓正面和晶圓背面，在所 述晶圓正面形成積體電路，利用枯合層410將支樓襯底 420枯附在晶圓400正面。在一個優選的實施例中，枯合 層410為雙面熱剝離膠帶，粘合層410的壓敏膠粘合層粘 合在支撐襯底420上’並且，粘合層41€襄熱剝離膠粘合 層粘合在晶圓400正面。在丹一個實施例中，粘合層410 為雙面紫外光照射自剝離膠帶，粘合層410的紫外光照射 剝離輔助粘合層粘合在支撐襯底420上，雄且，粘合層 410的紫外光照射自剝離粘合層粘合在晶圓400正面。Incomplete Bond), and the subsequent Molding process t'Incompiete Bond will cause the bow line to escape from the wire bond pad (Baid Lift), causing the wafer functionality to fail. For example, in U.S. Patent Publication No. US2006/0035443A1, a method of bonding and cutting a partial wafer is proposed in the patent of Hsu et al., which is to at least partially oxidize a supporting wafer to form a plurality of oxidized regions, and to oxidize The area is flattened, the surface of the supporting wafer and its oxidized area is covered by any material, and the supporting wafer is bonded to the integrated circuit wafer by using the oxidized area as a bonding point, and the subsequent process is completed by this structure. During the cutting process of the supporting wafer and the integrated circuit wafer, the supporting wafer is separated from the integrated circuit crystal. This is advantageous for enhancing the mechanical strength of the wafer, however, the process is complicated and the fabrication cost is high. In view of the above problems, the present invention discloses a die attach method for an ultra-thin wafer process. It has the technical well-being described below to solve existing problems. SUMMARY OF THE INVENTION In order to solve the above technical problems, the present invention provides a die attach method for an ultra-thin wafer process, which is low in cost, simple in production, stable in process, and can effectively improve product yield. Improve the performance of circuits on the wafer. The die attach method for ultra-thin wafer art of the present invention comprises the following steps: providing - wafer 'the wafer comprising a wafer front side and a wafer back side, at 099114638 Form No. A0101 No. 5 [0012] [0019] [0019] [0019] [0019] [0019] The front side of the wafer is formed into an integrated circuit; a dry layer; a support substrate is provided, the support substrate is bonded to the front side of the wafer by the adhesive layer; the back surface of the wafer is thinned on the back side of the wafer; and the wafer with the support substrate is bonded to Cutting the film and cutting the wafer and the supporting substrate to form a plurality of wafer particles with supporting substrate particles, and bonding the plurality of wafer particles to the corresponding lead frame; The support substrate particles are peeled off on the round particles to complete the die patch. The above-described die attach method for an ultra-thin wafer process, wherein after the wafer is thinned, a back surface process is performed on the back surface of the wafer to form a device electrode, and the back surface process includes back etching, back evaporation, Backside implant and backside laser annealing. The above-described die attach method for an ultra-thin wafer process, wherein the support substrate is glass or quartz. The above-described die attach method for an ultra-thin wafer process, wherein the adhesive layer is a double-sided thermal release tape. The above-described die attaching method for an ultra-thin wafer process, wherein the double-sided thermal release tape has a pressure-sensitive adhesive layer on one side and a thermal release adhesive layer on the other side, the pressure-sensitive adhesive The adhesive layer is bonded to the support substrate, and the thermal release adhesive layer is bonded to the front side of the wafer. 099114638 Form No. A0101 Page 6 of 23 0993263731-0 201140671 [0022] [0022] [0024] [0024] [0026] The above-described die for ultra-thin wafer process A pasting method in which the adhesive layer is heated to separate the adhesive layer from the wafer particles, thereby effecting peeling of the support substrate particles from the wafer particles. The above-described die attach method for an ultra-thin wafer process, wherein the adhesive layer is a double-sided ultraviolet light-irradiated self-peeling tape. The above-described die attaching method for an ultra-thin wafer process, wherein the double-sided ultraviolet light is irradiated from the peeling tape on one side of the peeling auxiliary adhesion layer by ultraviolet light, and the other side is ultraviolet light irradiation self-peeling bonding The layer, the ultraviolet light-emitting peeling auxiliary adhesive layer is adhered to the support substrate, and the ultraviolet light is adhered to the wafer from the peeling adhesive layer. The above-described die attach method for an ultra-thin wafer process, wherein the double-sided ultraviolet light is irradiated with ultraviolet rays from a release tape to separate the adhesive layer from the wafer particles, thereby realizing the slave wafer The support substrate particles are peeled off from the particles. The above-described die attach method for an ultra-thin wafer process is characterized in that the wafer back thinning is to thin the wafer to 100 or less. The die attaching method for the ultra-thin wafer process of the present invention has the following advantages and positive effects compared with the prior art by adopting the above technical solution: 1. The present invention supports the substrate by using an adhesive layer. Pasted on the front side of the wafer with the integrated circuit, and then the back side of the wafer is thinned. In this process, the mechanical strength of the wafer is greatly enhanced by bonding a supporting substrate to the front side of the wafer. The yield of the wafer during the backside thinning process, and the wafer can be thinned to 100 A or less. 099114638 Form No. A0101 Page 7 / Total 23 Page 0993263731-0 201140671 [0027] 2. The support substrate and the adhesive layer of the present invention are cut synchronously with the wafer, since the support substrate particles are adhered to the wafer particles, The mechanical strength of the wafer particles is increased, so that the wafer particles can be attached to the lead frame or the wiring substrate with high yield. [0028] 3. In the wafer particle bonding process of the present invention, the adhesive layer and the supporting bottom particles cover the side of the wafer particle on which the integrated circuit is provided, thereby avoiding the climbing of the conductive silver paste to the integrated body. The circuit affects the performance of the integrated circuit on the wafer. [Embodiment] According to the disclosure of the patent application and the disclosure of the present invention, the technical solution of the present invention is specifically as follows: [0030] As shown in FIG. 1, a single-sided adhesive comprises a release paper. The layer 100, the thermal release adhesive layer 110, the polyester fiber layer 120, the release paper layer 100 is used to protect the thermal release adhesive layer 110, and the release paper layer 100 is peeled off during use, and the thermal release adhesive layer 110 is removed. Adhesion. [0031] As shown in FIG. 2, the double-sided thermal release tape comprises a release paper layer 200, another release paper layer 240, a thermal release adhesive layer 210, and a polyester fiber layer 220 with respect to the single-sided adhesive. , pressure sensitive adhesive layer 230. The release paper layer 200 and the other release paper layer 240 are respectively used to protect the thermal release adhesive layer 210 and the pressure sensitive adhesive layer 230, wherein the thermal release adhesive layer 210 and the pressure sensitive adhesive layer 230 The adhesion of the adhesive layer 210 can be adjusted by thermal adjustment of the adhesion of the adhesive layer 210. [0032] As shown in FIG. 3, the double-sided ultraviolet light irradiation self-peeling tape comprises a release paper layer 300, another release paper layer 360, and ultraviolet light irradiation from the release adhesive layer 310 099114638 Form No. A0101 Page 8 / A total of 23 pages 0993263731-0 201140671, base tape film 340, ultraviolet light irradiation peeling auxiliary adhesion layer 350. Among them, the ultraviolet light is irradiated from the peeling adhesive layer 310 and the ultraviolet light is irradiated to the peeling auxiliary adhesive layer 350. When the ultraviolet light irradiation dose is within a certain range, the ultraviolet light is completely released from the peeling adhesive layer 310 and is released from the adhesive surface. [0033] As shown in FIG. 4, the wafer 400 includes the wafer front side and the wafer. On the back side, an integrated circuit is formed on the front surface of the wafer, and the branch substrate 420 is adhered to the front surface of the wafer 400 by the dry layer 410. In a preferred embodiment, the dead layer 410 is a double-sided thermal release tape, the pressure-sensitive adhesive layer of the adhesive layer 410 is bonded to the support substrate 420', and the adhesive layer 41 The adhesive layer is bonded to the front side of the wafer 400. In one embodiment of the invention, the adhesive layer 410 is double-sided ultraviolet light irradiated from the release tape, and the ultraviolet light-emitting peeling auxiliary adhesive layer of the adhesive layer 410 is adhered to the support substrate 420, and the adhesive layer 410 is bonded. The ultraviolet light is adhered to the front side of the wafer 400 from the peeling adhesive layer.
[0034] G 如第5圖所示，對第4圖中晶圓400在晶圓f面進行背面減 薄，可採用切割或研磨的方式，由於支撐襯底420對晶圓 400的支撐，增強晶圓400的機械強度，晶圓400可被減 薄至100/zm或者以下，對於功率半導體器件，當晶圓400 滅薄後，對晶圓400背面進行刻蝕（etch)、蒸發（ evaporation)、離子注入（implant)以及錯射退火 (laser anneal )等背面工藝，以形成晶圓的背面電極 〇 如第6圖所示，將經過背面減薄及背面工藝處理所得到的 帶有支撐襯底420的晶圓400的背面粘合在切割膜430上 099114638 表單編號A0101 第9頁/共23頁 0993263731-0 [0035] 201140671 [0036] 如第7圖所示，對放置在切割膜430上的帶有支撑襯底420 的晶圓400進行切割，支撐襯底420、粘合層410、晶圓 400按照單個晶片的尺寸（Di e S i ze )被切割成多個組 合有支撐襯底顆粒420a、粘合層顆粒41 0a、晶圓顆粒 400a的晶片組440 ’粘合層顆粒410a保持其粘合特性用 於將支撐襯底顆粒420a粘合在晶圓顆粒400a上。同時， 切割膜430在縱向上部分被切割但保持整體連接性。由於 切割設備需要透過支撐襯底420並在光學上識別單個晶片 的尺寸（Die Size) ’即是支撐襯底420須保障光學設 備對晶圓400a的單個晶片的’尺寸(.·_Μ ei z e )具可辨認 性，所以，支推襯底420優選對光學設備有較好透明性的 玻璃或石英》 [0037] 如第8圖所示，在切割膜430上，整個晶圓被切割成多個 晶片組4 4 0。 [0038] 如第9圖所示’在引線框架碑60却小島區（pda)上進行“ 點膠”構成多個導電銀漿區450，並通過導電銀漿區450 的導電銀漿的粘合作用分Μ #多個晶片組440粘合在該多 個導電銀漿區450上。此過程為晶圓顆粒4〇〇a的裝片粘合 (Die Attach)，當然也可將單個晶片組粘合至引線框 架460上，這取決於實際需要。 [0039] 099114638 相對於不帶有支撐襯底而單獨的將晶圓顆粒4〇〇a粘合在 引線框架上’晶圓顆粒400a的厚度在uin或者以下時 ，在切割及裝片粘合過程中，晶圓顆粒4〇〇a具有易碎性 ’因此’支撐襯底顆粒420a增強了晶圓顆粒4〇〇a的機械 強度，以避免晶圓顆粒40 0a破碎（Die Crack)，並且使 表單編號A0101 第10頁/共23頁 nqc 201140671 付晶圓顆粒400a的裝片枯合（Die Attach)過程順利進 行。 [0040] Ο [0041] 其中，任何一顆晶片組440包含支撐襯底顆粒42〇a、枯合 層顆粒410a、晶圓顆粒40 0a，晶圓顆粒4〇〇a的背面通過 導電銀漿區450固定在引線框架460上。支撐襯底顆粒 420a、枯合層顆粒410a覆蓋晶圓顆粒4〇〇a正面的積體電 路部位’以避免導電銀漿區450中由於導電銀漿過多或者 晶圓顆粒400a的移位帶來所引起的導電銀漿觸及晶圓顆 粒400a積體電路區域從而對積體電路帶來腐蝕或者引起 積體電路的短路。 Ο 在第9圖中，導電銀漿區450固化後即可移去晶片組44〇的 支撐襯底顆粒420a、粘合層顆粒41〇a，以完成管芯貼片 ，得到如第10圖所示的設置在引線框架460上的晶圓顆粒 400a。在一個優選的實施例中，粘合層顆粒410a為雙面 熱剝離膠帶’通過對雙面熱剝離朦帶加熱，粘附在晶圓 頂部的熱剝離膠粘合層在高溫下失去粘附性，從而使粘 合層顆粒410a及與其:枯附在一起的:支撑襯底顆粒420a從 晶圓顆粒400a上剝離，剝離溫度可以選擇為90 °C 、 120 °C或150 °C 。在另一個優選地實施例中，枯合層 顆粒410a為雙面紫外光照射自剝離膠帶，對雙面紫外光 照射自剝離膠帶進行紫外光照射，粘附在晶圓頂部的紫 外光照射自剝離粘合層在紫外光的照射下失去粘附性， 從而使粘合層顆粒410a及與其粘附在一起的支撐襯底顆 粒420a從晶圓顆粒400a上剝離。 如第11圖所示，本發明的一種用於超薄晶圓工藝的管芯 099114638 表單編號A0101 第11頁/共23頁 0993263731-0 [0042] 201140671 貼片方法的流程步驟如下： [0043] 提供 一晶0 ’晶0包含晶0正面和晶0背面’在晶圓正 面形成積體電路；提供一粘合層；提供一支撐襯底，利 用粘合層將該支撐襯底粘合至晶圓正面；在晶圓背面進 行晶圓背面減薄；基於減薄後的晶圓，在其晶圓背面進 行背面工藝以形成器件電極；將帶有支撐襯底的晶圓的 底部粘合至切割膜上並對晶圓及支撐襯底進行切割以形 成多個帶有支撐襯底顆粒的晶圓顆粒；將多個晶圓顆粒 粘合至與之相應的引線框架上；從晶圓顆粒上剝離支撐 襯底顆粒以完成管芯貼片。 [0044] 得到如第10圖所示的完成管芯貼片的產品後，對包含導 電銀漿區450、晶圓顆粒400a的引線框架460進行烘烤（ Cur e )，然後進行清洗、引線鍵合以及塑封，從而得到 塑封完畢的具有超薄晶圓的晶片。 [0045] 本發明一種用於超薄晶圓工藝的管芯貼片方法，該方法 枯附支樓概底於晶圓的正面*對帶有支撑概底的晶圓進 行背面研磨，並且在切割膜上同時切割支撐襯底及晶圓 ，將切割後的帶有支撐襯底顆粒的晶圓顆粒粘合在與其 對應的引線框架上以完成管芯貼片，該方法一方面保證 晶圓具有足夠的機械強度，另一方面使晶圓在管芯貼片 時避免導電銀漿影響電路性能。 [0046] 當然，必須認識到，上述介紹是有關本發明優選實施例 的說明，只要不偏離隨後所附權利要求所顯示的精神和 範圍，本發明還存在著許多修改。 099114638 表單編號A0101 第12頁/共23頁 0993263731-0 201140671 [0047] 本發明決不是僅局限於上述說明或附圖所顯示的細節和 方法。本發明能夠擁有其他的實施例，並可採用多種方 式予以實施。另外，大家還必須認識到，這裏所使用的 措辭和術語以及文摘只是為了實現介紹的目的，決不是 僅僅局限於此。 [0048] 正因為如此，本領域的技術人員將會理解，本發明所基 於的觀點可隨時用來作為實施本發明的幾種目標而設計 其他結構、方法和系統。所以，至關重要的是，所附的 0 權利要求將被視為包括了所有這些等價的建構，只要它 們不偏離本發明的精神和範圍。 【圖式簡單說明】 [0049] 參考所附附圖，以更加充分的描述本發明的實施例。然 而，所附附圖僅用於說明和闡述，並不構成對本發明範 圍的限制。 [0050] 第1圖是一種單面膠帶的結構示意圖。 0 [0051] 第2圖是雙面熱剝離膠帶的結構示意圖。 [0052] 第3圖是雙面紫外光照射自剝離膠帶的結構示意圖。 [0053] 第4圖是利用粘合層將支撐襯底粘合在晶圓正面的截面示 意圖。 [0054] 第5圖是帶有支撐襯底的晶圓背面經減薄後的截面示意圖 〇 [0055] 第6圖是將帶有支撐襯底的晶圓粘合在切割膜上的截面示 意圖。 099114638 表單編號A0101 第13頁/共23頁 0993263731-0 201140671 [0056] 第7圖是將帶有支撐襯底的晶圓切割為帶有支撐襯底顆粒 的晶圓顆粒的截面不意圖。 [0057] 第8圖是帶有支撐襯底的晶圓被劃分為晶圓顆粒的平面結 構示意圖。 [0058] 第9圖是將帶有支撐襯底顆粒的晶圓顆粒粘合在引線框架 上的截面示意圖。 [0059] 第1 0圖是將粘合至引線框架上的晶圓顆粒剝離支撐襯底 顆粒後的截面示意圖。 [0060] 第11圖是本發明用於超薄晶圓工藝的管芯貼片方法的流 程圖。 【主要元件符號說明】 [0061] 450導電銀漿區 [0062] 40 0a晶圓顆粒 [0063] 410a粘合層顆粒 [0064] 420a支撐襯底顆粒 [0065] 440晶片組 [0066] 460引線框架 [0067] 100、200、300 離形紙層 [0068] 110、210熱剝離膠粘合層 [0069] 120 ' 220聚酯纖維層 [0070 ] 230壓敏膠粘合層 099114638 表單編號A0101 第14頁/共23頁 0993263731-0 201140671 [0071] [0072] [0073] [0074] [0075] [0076] [οοπ] θ [0078] 240、360另一離形紙層 310自剝離粘合層 340基帶薄膜 350剝離輔助粘合層 400晶圓 410粘合層 420支撐襯底 430切割膜 Ο 099114638 表單編號Α0101 第15頁/共23頁 0993263731-0[0034] G As shown in FIG. 5, the wafer 400 of FIG. 4 is back-thinned on the f-plane of the wafer, and may be cut or polished by the support substrate 420 to support the wafer 400. For the mechanical strength of the wafer 400, the wafer 400 can be thinned to 100/zm or less. For the power semiconductor device, after the wafer 400 is thinned, the back surface of the wafer 400 is etched and evaporated. Backside processes such as ion implantation and laser anneal to form the backside electrode of the wafer, as shown in Fig. 6, with a support substrate obtained by backside thinning and backside processing The back surface of the wafer 400 of 420 is bonded to the dicing film 430. 099114638 Form No. A0101 Page 9/Total 23 page 0993263731-0 [0035] 201140671 [0036] As shown in FIG. 7, the pair is placed on the dicing film 430. The wafer 400 with the support substrate 420 is cut, and the support substrate 420, the adhesive layer 410, and the wafer 400 are cut into a plurality of combined support substrate particles 420a according to the size of a single wafer (Di e S i ze ). , the adhesive layer particles 41 0a, the wafer set 440 of the wafer particles 400a are sticky Particle layer 410a maintains its adhesive properties for bonding the support substrate particles 420a on the wafer particles 400a. At the same time, the dicing film 430 is partially cut in the longitudinal direction but maintains overall connectivity. Since the cutting device needs to pass through the support substrate 420 and optically recognize the size of the individual wafers, that is, the support substrate 420 must ensure the 'size of the individual wafers of the optical device to the wafer 400a (.·_Μ ei ze ) It is identifiable, so that the support substrate 420 is preferably glass or quartz having good transparency to the optical device. As shown in FIG. 8, on the dicing film 430, the entire wafer is cut into a plurality of pieces. Wafer set 4 4 0. [0038] As shown in FIG. 9, 'spotting on the lead frame monument 60 but on the island area (pda) constitutes a plurality of conductive silver paste regions 450, and is bonded through the conductive silver paste of the conductive silver paste region 450. Action Tiller #Multiple wafer sets 440 are bonded to the plurality of conductive silver paste regions 450. This process is a Die Attachment of the wafer particles 4A, although it is of course also possible to bond a single wafer set to the lead frame 460, depending on actual needs. [0039] 099114638 separately bonding the wafer particles 4〇〇a to the lead frame without the support substrate. 'When the thickness of the wafer particles 400a is uin or less, in the cutting and loading process The wafer particles 4〇〇a have friability. Therefore, the supporting substrate particles 420a enhance the mechanical strength of the wafer particles 4〇〇a to prevent the wafer particles 40a from breaking (Die Crack) and making the form No. A0101 Page 10 of 23 nqc 201140671 The die attach process of wafer wafer 400a goes smoothly. [0040] wherein any one of the wafer sets 440 includes support substrate particles 42A, dry layer particles 410a, wafer particles 40a, and the back side of the wafer particles 4a passes through the conductive silver paste region. 450 is attached to lead frame 460. The support substrate particles 420a and the dry layer particles 410a cover the integrated circuit portion of the front surface of the wafer particles 4〇〇a to avoid excessive conductive silver paste or displacement of the wafer particles 400a in the conductive silver paste region 450. The resulting conductive silver paste touches the integrated circuit region of the wafer particles 400a to cause corrosion of the integrated circuit or cause a short circuit of the integrated circuit.第 In FIG. 9, after the conductive silver paste region 450 is cured, the support substrate particles 420a and the adhesive layer particles 41〇a of the wafer group 44〇 can be removed to complete the die patch, and the image is obtained as shown in FIG. Wafer particles 400a disposed on lead frame 460 are shown. In a preferred embodiment, the adhesive layer particles 410a are double-sided thermal release tapes. By heating the double-sided thermal release tape, the thermal release adhesive layer adhered to the top of the wafer loses adhesion at high temperatures. Thereby, the adhesive layer particles 410a and the support substrate particles 420a which are attached thereto are peeled off from the wafer particles 400a, and the peeling temperature can be selected to be 90 ° C, 120 ° C or 150 ° C. In another preferred embodiment, the dry layer particles 410a are double-sided ultraviolet light irradiated from the peeling tape, and the double-sided ultraviolet light is irradiated with ultraviolet light from the peeling tape, and the ultraviolet light adhered to the top of the wafer is irradiated and peeled off. The adhesive layer loses adhesion under irradiation of ultraviolet light, so that the adhesive layer particles 410a and the supporting substrate particles 420a adhered thereto are peeled off from the wafer particles 400a. As shown in FIG. 11, a die for an ultra-thin wafer process of the present invention 099114638 Form No. A0101 Page 11 of 23 0993263731-0 [0042] The process steps of the 201140671 patch method are as follows: [0043] Providing a crystal 0' crystal 0 comprising a crystal 0 front side and a crystal 0 back side forming an integrated circuit on the front side of the wafer; providing an adhesive layer; providing a supporting substrate, bonding the supporting substrate to the crystal by an adhesive layer a round front; wafer backside thinning on the back side of the wafer; a backside process on the back side of the wafer to form the device electrode based on the thinned wafer; bonding the bottom of the wafer with the supporting substrate to the cut Film and supporting the substrate to form a plurality of wafer particles with supporting substrate particles; bonding a plurality of wafer particles to the corresponding lead frame; stripping from the wafer particles The substrate particles are supported to complete the die patch. [0044] After obtaining the product of the completed die patch as shown in FIG. 10, the lead frame 460 including the conductive silver paste region 450 and the wafer particles 400a is baked (Cur e), and then cleaned and wire-bonded. And plastic packaging to obtain a molded wafer with ultra-thin wafers. [0045] A die attach method for an ultra-thin wafer process, the method of attaching a branch to the front side of the wafer*, back grinding the wafer with the support base, and cutting The support substrate and the wafer are simultaneously cut on the film, and the diced wafer particles with the support substrate particles are bonded to the corresponding lead frame to complete the die patch, and the method ensures that the wafer has sufficient The mechanical strength, on the other hand, prevents the conductive silver paste from affecting circuit performance when the wafer is mounted on the die. [0046] It is to be understood that the foregoing description of the preferred embodiments of the invention is in the 099114638 Form No. A0101 Page 12 of 23 0993263731-0 201140671 [0047] The present invention is by no means limited to the details and methods shown in the above description or the drawings. The invention is capable of other embodiments and of various embodiments. In addition, you must also understand that the words and terms used herein and the abstracts are for the purpose of illustration only and are by no means limited. [0048] As such, those skilled in the art will appreciate that the present invention is capable of other structures, methods and systems. Therefore, it is essential that the appended claims be construed as including all such equivalent constructions as the invention BRIEF DESCRIPTION OF THE DRAWINGS [0049] Embodiments of the present invention will be described more fully with reference to the appended drawings. The accompanying drawings are for the purpose of illustration and illustration only, [0050] FIG. 1 is a schematic structural view of a single-sided tape. 0 [0051] FIG. 2 is a schematic view showing the structure of a double-sided thermal release tape. [0052] FIG. 3 is a schematic view showing the structure of a double-sided ultraviolet light irradiation self-peeling tape. [0053] Fig. 4 is a cross-sectional view showing the bonding substrate bonded to the front side of the wafer by an adhesive layer. 5 is a schematic cross-sectional view of the back side of the wafer with the support substrate after being thinned. [0055] FIG. 6 is a cross-sectional view showing the bonding of the wafer with the support substrate to the dicing film. 099114638 Form No. A0101 Page 13 of 23 0993263731-0 201140671 [0056] Figure 7 is a cross-sectional view of a wafer having a support substrate cut into wafer particles with supporting substrate particles. [0057] Fig. 8 is a schematic view showing a planar structure in which a wafer with a supporting substrate is divided into wafer particles. Figure 9 is a schematic cross-sectional view showing the bonding of wafer particles with supporting substrate particles to a lead frame. 10 is a schematic cross-sectional view showing the wafer particles adhered to the lead frame peeled off the support substrate particles. 11 is a flow chart of a die attach method for an ultra-thin wafer process of the present invention. [Main Component Symbol Description] [0061] 450 conductive silver paste region [0062] 40 0a wafer particles [0063] 410a adhesive layer particles [0064] 420a supporting substrate particles [0065] 440 wafer set [0066] 460 lead frame 100, 200, 300 release paper layer [0068] 110, 210 thermal release adhesive layer [0069] 120 '220 polyester fiber layer [0070] 230 pressure sensitive adhesive layer 099114638 Form No. A0101 No. 14 Page 23 of 2393263731-0 201140671 [0071] [0075] [0076] [0076] [0078] 240, 360 another release paper layer 310 from the release adhesive layer 340 Baseband film 350 peeling auxiliary adhesive layer 400 wafer 410 adhesive layer 420 supporting substrate 430 cutting film Ο 099114638 Form No. 1010101 Page 15 of 23 0993263731-0