TW201126498A - Gate driver - Google Patents

Gate driver Download PDF

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Publication number
TW201126498A
TW201126498A TW99101569A TW99101569A TW201126498A TW 201126498 A TW201126498 A TW 201126498A TW 99101569 A TW99101569 A TW 99101569A TW 99101569 A TW99101569 A TW 99101569A TW 201126498 A TW201126498 A TW 201126498A
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TW
Taiwan
Prior art keywords
amplifier
gate voltage
gate
level
vgn
Prior art date
Application number
TW99101569A
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Chinese (zh)
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TWI419134B (en
Inventor
Han-Shui Hsueh
Fa-Ming Chen
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Himax Tech Ltd
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Priority to TW99101569A priority Critical patent/TWI419134B/en
Publication of TW201126498A publication Critical patent/TW201126498A/en
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Publication of TWI419134B publication Critical patent/TWI419134B/en

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Abstract

The present invention is directed to a gate driver, which includes a shift register, a level shifter and a buffer. A portion of the buffer is powered by a middle-level gate voltage (VGN), which is lower than a high-level gate voltage (VGH) used in other portions of the buffer. Accordingly, the waveform of a generated scan line has a gradual falling edge.

Description

201126498 VI. Description of the Invention: [Technical Field to Which the Invention Is Applicable] In particular, the present invention relates to a gate driver for driving a scan signal of a display panel. [0002] 〇

099101569 The liquid crystal display (L(8) panel is usually composed of pixel units (or simply pixels) arranged in a matrix of rows and columns. Each of the main pixels includes a thin film transistor (TFT) and a pixel electrode, which are raised together and recognized. Formed on a substrate. The gates of the thin film transistors in the same column are connected by a scan line, and then controlled by a gate driver. The source of the thin film transistor is located at the same time. The poles are connected by a data line, and the π field body is controlled by the pole drive 1 §. The common electrode (common electro^ ν , ae ' VC0m ) is formed on another substrate. The liquid crystal (L〇_ in pixels) Between the electrode substrate and the common electrode substrate, display of each pixel is performed by controlling the electric power difference between the two substrates. The first figure shows a structural diagram of one pixel, wherein the thin film transistor (m) _ pole G Connected to the scan line, and its drain is connected to the data line. When the thin film transistor (m) is turned on by the scan signal on the scan line (for example, the rising level scan signal), the data signal passes through the data line through the data line. Transistor The channel stores the charge in the storage capacitor U. After the storage is completed, the scanning signal is reduced to return to the original level, thereby closing the thin film transistor. However, the thin film transistor has a closed-pole G_ immersed D and a gate G - The source S usually has a stray capacitance Cp. When the scan signal is about to lower the level to turn off the thin film transistor, the stray capacitance Cp tends to lower the drain D and source S voltage levels of the thin film transistor. Therefore, it affects the amount of charge in the storage capacitor Cs. This phenomenon is generally called the feed through effect, which causes the display color to be uneven ( mura ). ° In order to improve the feedthrough effect, a chamfering circuit is proposed for chamfering the falling sharp angle of the waveform of the scanning signal Vg, as shown in the second figure, wherein the original scanning signal Vg (at time t2) has a vertical The falling edge. At time t1 before t2, the chamfer circuit is used to lower the high-level gate voltage VGH of the gate driver by a quasi-drop, and then return to the original high-level gate voltage VGH at time t2. Thereby, the chamfering scanning signal Vg can be generated. The chamfering technique of the scanning signal can be used to reduce the feedthrough effect. However, the chamfering technique needs to control complicated timing, and the required chamfering circuit increases the circuit area and Power consumption. Therefore, it is not suitable for a driver of a high-resolution liquid crystal display panel. [0003] In view of the above, one of the objects of the embodiments of the present invention is to provide a gate driver with a slow-down scan signal to reduce Or avoiding the feed through effect, thereby reducing or avoiding the phenomenon of color mura. According to an embodiment of the invention, the gate driver comprises a shift register, an electric displacement rotator and a buffer. The shift register is responsive to a predetermined sequence to generate control signals for the plurality of scan lines. The electric displacement transducer converts the control signal from a low level to a high level required for the switching elements of the display panel. Buffer generation sweep 099101569 Form number A0101 Page 4 of 15 0992003051-0 201126498 信号 Signal to drive the scan line of the display panel. Wherein, part of the circuit power supply of the buffer uses a level gate voltage (VGN) lower than the high level gate voltage (VGH), thereby causing the waveform of the scan signal to have a falling edge. According to an embodiment, the buffer includes a first amplifier, a second amplifier, and a driver circuit. The power of the first amplifier is a low level gate voltage (VGL) and a medium level gate voltage (VGN); the power source of the second amplifier is a low level gate voltage (VGL) and a high level gate voltage (VGH), wherein The value of the median threshold voltage (VGN) is between the high level gate voltage (VGH) and the low level gate voltage (VGL). The input end of the first amplifier and the input end of the second amplifier are electrically coupled to the output end of the electric displacement converter, and the driving circuit is controlled by the first amplifier and the second amplifier for generating a scan signal to drive the display. The scan line of the panel. [Embodiment] The third figure shows a gate driver of an embodiment of the present invention for driving a display panel 10 such as a liquid crystal display (LCD) panel. The gate driver of this embodiment mainly includes a shift register 12, a level shifter 14 and a buffer 16. The shift register 12 is responsive to a predetermined sequence to generate an open control signal for each scan line. The electric displacement transducer 14 converts the control signal from a low level (eg, 3/0 volts or 5/0 volts) to a high level (eg, 20/-5 volts) required for a panel switching element, such as a thin film transistor (TFT). . The buffer 16 provides a drive capability to the control signal to drive the scan lines of the panel 10. The buffer 16 of this embodiment mainly includes a first amplifier 160N, a second amplifier 160P, and a drive circuit 162. In the present embodiment, the first amplifier form number A0101 page 5/15 page 0992003051-0 201126498 160N is an inverting amplifier' and the second amplifier i6〇p is also an inverting amplifier. The driving circuit 162 includes a P-type transistor (for example, a p-type metal oxide semiconductor (PMOS) transistor) P1 and an N-type transistor (for example, an N-type metal oxide semiconductor (NMOS) transistor) N1, which are connected in series to a high-level gate voltage. Between VGH and low level gate voltage VGL. In detail, the source S of the PIOS transistor P1 is connected to the high level gate voltage VGH, the drain D of the P0O transistor P1 is connected to the drain D of the NM0S transistor N1, and the source S of the NM0S transistor N1 is connected. To the low level of the gate voltage VGL. The input end of the first amplifier 160N is electrically coupled to the input end of the second amplifier 160P; the output end of the first amplifier 160N is connected to the gate of the NM0S transistor, to control the opening or closing of the NM0S transistor N1; The output of the second amplifier WOP is connected to the gate of the PMOS transistor P1 to control the PMOS transistor? 1 is turned on or off. Although the number of the first amplifier 16 〇Ν and the second amplifier 1600 P of the present embodiment is one, respectively, a plurality of amplifiers may be connected in series. Usually, an odd number of amplifiers are connected in series, and the number of series connection of the first amplifier 160N and the second amplifier 16p is the same. . . . :-· if'-...... According to one of the features of the embodiment, the voltage source supplied to the first amplifier 16〇N is a low-level gate voltage VGL and a medium-level gate. Voltage VGN. In other words, the output level of the first amplifier 160N is approximately between VGN and VGL. If the plurality of first amplifiers 16 are connected in series, the median gate voltage VGN is supplied to the first amplifier 16 of the last stage, and the remaining first amplifier 160N can (but not necessarily) replace the high level gate voltage. VGH. As for the second amplifier 160P', a low level gate voltage VGL and a high level gate voltage VGH are provided. In other words, the output level of the second amplifier 16 〇p is approximately between VGH and VGL. 099101569 Form No. A0101 Page 6 of 15 0992003051-0 201126498 The fourth figure shows the voltage level of the median quasi-gate voltage VGN, which is between the high level gate voltage VGH and the low level gate voltage vgl. . The value of the median gate voltage VGN is set in advance, however, it can also be set by the user. Further, the median quasi-gate voltage VGN may be generated internally by the gate driver or externally. Since the present embodiment provides the median gate voltage VGN to the first amplifier 16〇N', the voltage (about VGN) of the first amplifier 160N at the high level output is smaller than the conventional high level output voltage (approximately & VGH) thus reducing the driving force to the NM0S transistor N1. Thereby, the scanning signal Vg generated by the buffer 6 has a side edge which is slow off, as shown in the fourth figure. The ramp-down scanning signal Vg can reduce or avoid the feed through effect caused by the gate-drain and gate-source parasitic capacitance of the thin film transistor (TFT), thereby reducing or avoiding

' I does not have the phenomenon of color unevenness (mura). As mentioned above, the level of the median quasi-gate voltage VGN can be adjusted. Figure 5A shows the on-current Ids and the drain-source voltage drop Vds curve of the NM0S transistor N1. As shown in the figure, 'increasing the level of the medium-level gate voltage VGN will increase the on-current Ids', that is, increasing the driving force of the NM0S transistor N1; lowering the level of the center-level gate voltage VGN will lower the on-current ids. That is, the driving force of the NM0S transistor N1 is lowered. The fifth B diagram illustrates that the waveform of the second ramp-down scan signal Vg corresponds to a larger center-level gate voltage VGN, and the other corresponds to a smaller center-level gate voltage VGN. As shown in the figure, the smaller the medium-level gate voltage VGN can be obtained more slowly. 099101569 Form No. A0101 Page 7 of 15 0992003051-0 201126498 The scanning signal Vg is lowered. In the autumn, a*, , and, too, the scanning signal Vg that is too slow may cause an overlap between the front and rear scanning signals Vg. The J error can be reduced by (10) (10) the transistor by providing the scan signal Vg with the median quasi-gate voltage VGN at the edge to reduce the edge, thereby reducing or avoiding the feedthrough plus the "one (5)) painful power conventional technology (for example, the second figure) In contrast, the second embodiment is combined with a complicated chamfering circuit for chamfering the scanning signal (10). This is greedy: the feedthrough effect is improved by using a simple mechanism to generate a slow-down scanning signal (4). The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; any other equivalent changes or modifications which are not disclosed in the invention, and which are It should be included in the scope of the following patents. ^ [0005] [Simple diagram of the diagram] The first diagram shows the diagram of the junction of one pixel. The second diagram shows the waveform diagram of the traditional chamfering technique. The third diagram shows the implementation of the present invention. The gate driver of the example. The fourth figure shows the voltage level and the slow drop number of the center-level gate voltage VGN. The fifth Figure A shows the on-current of the transistor and the drain-source voltage drop. Illustrate the waveform of the second descending scan signal [0006] The main reference numerals DESCRIPTION 1〇 display panel A0101 099 101 569 Table · Single Page number 8/15 Total 201 126 498

12 Shift register 14 Electro-displacer 16 Buffer 160N First amplifier 160P Second amplifier 162 Drive circuit G Gate S Source D D-Cs Storage capacitor Cp Stray capacitance Vg Scan signal VGH High-level gate voltage VGL low-level gate voltage VGN medium-level gate voltage N1 NM0S transistor ^ PI PM0S transistor f,

099101569 Form No. A0101 Page 9 of 15 0992003051-0

Claims (1)

  1. 201126498 VII. Patent application scope: 1. A gate driver comprising: a shift register for generating control signals of a plurality of scan lines in a predetermined order; an electric displacement converter for using the control signal a low level is converted to a high level required for a switching element of the display panel; and a buffer for generating a scan signal for driving the scan line of the display panel, wherein part of the circuit power supply of the buffer uses a lower level The gate voltage (VGN) among the gate voltages (VGH) causes the waveform of the scan signal to have a falling edge. 2. The gate driver of claim 1, wherein the buffer comprises: a first amplifier, the power source of which is a low level gate voltage (VGL) and a medium level gate voltage (VGN); A second amplifier whose power supply is a low level gate voltage (VGL) and a high level gate voltage (VGH), wherein the value of the center gate voltage (VGN) is between a high level gate voltage (VGH) and Between the low-level gate voltage (VGL), and the input end of the first amplifier and the input end of the second amplifier are electrically coupled to the output end of the electric displacement converter; and a driving circuit controlled by the The first amplifier and the second amplifier are configured to generate the scan signal to drive a scan line of the display panel. 3. The gate driver of claim 2, wherein the first amplifier and the second amplifier respectively comprise an inverting amplifier. 4. The gate driver of claim 2, wherein the driving circuit comprises a P-type transistor and an N-type transistor, and is connected in series to the high-level gate 099101569. Form No. A0101 Page 10 of 15 Page 0992003051-0 201126498 between a pole voltage (VGH) and a low level gate voltage (VGL), wherein the opening and closing of the N-type transistor and the P-type transistor are controlled by the first amplifier and the second Amplifier. 5. The gate driver of claim 4, wherein a source of the P-type transistor is connected to a high level gate voltage (VGH), and a drain of the P-type transistor is connected to the N-type a drain of the crystal, the source of the N-type transistor being connected to a low-level gate voltage (VGL), the gate of the N-type transistor being connected to the output of the first amplifier, the gate of the P-type transistor Connected to the output of the second amplifier. 6. The gate driver of claim 2, wherein the number of the first amplifiers is more than one and an odd number, and the plurality of first amplifiers are connected in series, and the number of the second amplifiers is the same And the number of the first amplifiers, and the plurality of second amplifiers are connected in series with each other. 7. The gate driver of claim 6, wherein the power source of the last stage first amplifier is a low level gate voltage (VGL) and a center gate voltage (VGN). Ο » 山a士由-fl tsi Air 1 , 丄, Λ * ηβ Xtr xttx tW -I-* » , 丄, 山Ο · π T萌斧孑_J祀固禾 ia mr甲143E which cup, six丫 The 准 gate threshold voltage (VGN) is generated internally by the gate driver. 9. The gate driver of claim 1, wherein said intermediate gate voltage (VGN) is provided externally by said gate driver. 0992003051-0 099101569 Form No. A0101 Page II / Total 15 Pages
TW99101569A 2010-01-21 2010-01-21 Gate driver TWI419134B (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8779684B2 (en) 2011-12-30 2014-07-15 Au Optronics Corporation High gate voltage generator and display module including the same
TWI453719B (en) * 2012-03-30 2014-09-21 Himax Tech Ltd Gate driver
TWI514356B (en) * 2013-02-06 2015-12-21 Au Optronics Corp Display panel and gate driver thereof
US9275569B2 (en) 2012-09-27 2016-03-01 E Ink Holdings Inc. Flat panel display, threshold voltage sensing circuit, and method for sensing threshold voltage
CN107293267A (en) * 2017-07-19 2017-10-24 深圳市华星光电半导体显示技术有限公司 A kind of control method of display panel and display panel signal

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7002542B2 (en) * 1998-09-19 2006-02-21 Lg.Philips Lcd Co., Ltd. Active matrix liquid crystal display
TWI389071B (en) * 2008-01-25 2013-03-11 Au Optronics Corp Panel display apparatus and controlling circuit and method for controlling same
CN101447177B (en) * 2009-01-05 2011-06-08 友达光电股份有限公司 Display capable of actively regulating drive voltage, voltage compensation circuit and driving method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8779684B2 (en) 2011-12-30 2014-07-15 Au Optronics Corporation High gate voltage generator and display module including the same
TWI453719B (en) * 2012-03-30 2014-09-21 Himax Tech Ltd Gate driver
US9275569B2 (en) 2012-09-27 2016-03-01 E Ink Holdings Inc. Flat panel display, threshold voltage sensing circuit, and method for sensing threshold voltage
TWI514356B (en) * 2013-02-06 2015-12-21 Au Optronics Corp Display panel and gate driver thereof
CN107293267A (en) * 2017-07-19 2017-10-24 深圳市华星光电半导体显示技术有限公司 A kind of control method of display panel and display panel signal

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