201126498 六、發明說明： 【發明所屬之技術領域】 特別是關於一種具緩降 師1] 本發明係有關顯示面板之驅動 掃描信號之閘極驅動器。 [0002] 〇201126498 VI. Description of the Invention: [Technical Field to Which the Invention Is Applicable] In particular, the present invention relates to a gate driver for driving a scan signal of a display panel. [0002] 〇
099101569 液晶顯示（L⑻面板通常由排列成行列矩陣形式的像素 單元（或簡稱像素）所組成。每—德主a入 像素包含一薄膜電晶 體（TFT)及一像素電極，其共同升,说认 成於一基板上。位於 同-列之薄膜電晶體的閘極藉由—掃描線連接在—起，、 再由閘極驅動器來控淛°位於同一，_ t J仃之薄膜電晶體的源 極則藉由一資料線連接在一起， π田身'極驅動1§來控制 。共電極（common electro^ ν 、 ae’ VC0m)則是形成於另 一基板上。液晶（L〇 _於像素電極基板與共電極基 板之間，藉由控制兩基板之間的電愿差而得以進行每： 像素的顯示。 第-圖顯示一個像素的結構示意圖。其中，薄膜電晶體 (m) _極G連接至掃描線，而其汲極則連接至資料 線。當薄膜電晶體（m)受到掃描線上之掃描信號（例 如升高位準的掃描信號）的開啟後，資料信號即藉由資 料線通過薄膜電晶體的通道而將電荷儲存於儲存電容U 内。儲存完成後，掃描信號即降低回復為原來位準，因 而關閉薄膜電晶體。然而’薄膜電晶體的閉極G_沒極D間 以及閘極G-源極S間通常具有雜散電容Cp。當掃描信號即 將降低位準以關閉薄膜電晶體的時候，雜散電容Cp往往 會拉低薄膜電晶體的汲極D和源極S電壓位準，因而影響 0992003051-0 表單編號A0101 第3頁/共15頁 201126498 到儲存電容Cs内的電荷量。此種現象一般稱為饋通（ feed through)效應，其會造成顯示顏色的不均勻（ mura) ° 為了改善饋通效應，有人提出一種削角電路，用以將掃 描信號Vg波形的下降尖角予以削角，如第二圖所示。其 中，原始的掃描信號Vg (於時間t2)具有垂直的下降邊 緣。於t2之前的時間tl，使用削角電路將閘極驅動器的 高位準閘極電壓VGH下降一位準落差，再於時間t2將其回 復為原來的高位準閘極電壓VGH。藉此，可產生削角之掃 描信號Vg〇 上述掃描信號之削角技術雖然可用以降低饋通效應，然 而，削角技術需控制複雜的時序，且所需之削角電路會 增加電路面積及功率消耗。因而，並不適於高解析度液 晶顯示面板之驅動器。 【發明内容】 [0003] 鑑於上述，本發明實施例的目的之一在於提出一種具緩 降掃描信號之閘極驅動器，以減少或避免饋通（feed through)效應，因而得以減少或避免顏色不均（mura )的現象。 根據本發明實施例，閘極驅動器包含移位暫存器、電位 移轉器及緩衝器。移位暫存器依照預定順序以產生多條 掃描線的控制信號。電位移轉器將控制信號由低位準轉 換為顯示面板之開關元件所需的高位準。緩衝器產生掃 099101569 表單編號 A0101 第 4 頁/共 15 頁 0992003051-0 201126498 Ο 描信號，以便驅動顯示面板的掃描線。其中，緩衝器的 部分電路電源使用一低於高位準閘極電壓（VGH)之中位 準閘極電壓（VGN)，因而使得掃描信號之波形具有緩降 邊緣。根據一實施例，緩衝器包含第一放大器、第二放 大器及驅動電路。第一放大器之電源為低位準閘極電壓 (VGL)及中位準閘極電壓（VGN);第二放大器之電源 為低位準閘極電壓（VGL)及高位準閘極電壓（VGH)， 其中，中位準閘極電壓（VGN)之值介於高位準閘極電壓 (VGH)和低位準閘極電壓（VGL)之間。上述第一放大 器的輸入端和第二放大器的輸入端電性耦接至電位移轉 器的輸出端，而驅動電路則受控於第一放大器及第二放 大器，用以產生掃描信號以驅動顯示面板的掃描線。 [0004] 【實施方式】 第三圖顯示本發明實施例的閘極驅動器，用以驅動顯示 面板10，例如液晶顯示（LCD)面板。本實施例之閘極驅 動器主要包含移位暫存器（shi ft register ) 12、電 ❹ 位移轉器（level shifter) 14及緩衝器（buffer) 16 。其中，移位暫存器12依照預定順序以產生各掃描線的 開啟控制信號。電位移轉器14將控制信號由低位準（例 如3/0伏特或5/0伏特）轉換為面板開關元件（例如薄膜 電晶體（TFT))所需的高位準（例如20/-5伏特）。緩 衝器16則是提供驅動能力給控制信號，以便驅動面板10 的掃描線。 099101569 本實施例的緩衝器16主要包含第一放大器160N、第二放 大器160P及驅動電路162。在本實施例中，第一放大器 表單編號A0101 第5頁/共15頁 0992003051-0 201126498 160N為反相放大器’且第二放大器i6〇p也為反相放大器 。驅動電路162包含P型電晶體（例如p型金屬氧化半導體 (PM0S)電晶體）P1和N型電晶體（例如N型金屬氧化半 導體（NM0S)電晶體）N1，串接於高位準閘極電壓VGH 和低位準閘極電壓VGL之間。詳而言之，PM0S電晶體P1 的源極S連接至高位準閘極電壓VGH，PM0S電晶體P1的汲 極D連接至NM0S電晶體N1的汲極D，NM0S電晶體N1的源極 S連接至低位準閘極電壓VGL。第一放大器160N的輸入端 和第二放大器160P的輸入端電性耦接；第一放大器160N 的輸出端連接至NM0S電晶體说1的閘極，以控制NM0S電晶 體N1的開啟或關閉；而第二放大器WOP的輸出端則連接 至PM0S電晶體P1的閘極，以控制PM0S電晶體？1的開啟或 關閉。雖然本實施例的第一放大器16〇Ν、第二放大器 16 0 P的數目分別為一個，然而，也可以分別串接多個放 大器。通常為分別串接奇數個放大器，且第一放大器 160N和第二放大器l6〇p的串接數目相同。 . .. ：-· if'-. .... ·. ： 根據本實施例的特徵之一，提供給第一放大器16〇N的電 壓源為低位準閘極電壓VGL及中位準閘極電壓VGN。換句 話說’第一放大器160N的輸出位準大約介於VGN和VGL之 間。如果是串接多個第一放大器16帅，則提供中位準閘 極電壓VGN給最後一級的第一放大器16帅，其餘之第一放 大器160N可（但非必須）代以高位準閘極電壓VGH。至於 第二放大器160P ’則是提供低位準閘極電壓VGL及高位準 閘極電壓VGH。換句話說，第二放大器16〇p的輸出位準大 約介於VGH和VGL之間。 099101569 表單編號A0101 第6頁/共15頁 0992003051-0 201126498 第四圖顯示中位準閘極電壓VGN的電壓位準，其大小介於 高位準閘極電壓VGH和低位準閘極電壓vgl之間。中位準 閘極電壓VGN之值係為預先設定，然而，也可以由使用者 來設定。此外’中位準閘極電壓VGN可以由閘極驅動器内 部產生，也可以由外部提供。 由於本實施例提供中位準閘極電壓VGN予第一放大器16〇N ’將使得第一放大器160N於高位準輸出時之電壓（大約 為VGN)小於傳統一般的高位準輸出電壓（大約&VGH) ，因而降低對NM0S電晶體N1的驅動力。藉此，緩衝6 所產生的掃描信號Vg會具有緩降（slow off)的邊·緣， 如第四圖所示。緩降之掃描信號Vg可減少或避免因薄膜 電晶體（TFT)之閘極-汲極間和閘極-源極間寄生電容所 產生的饋通（feed through)效應’因而得以減少或避099101569 The liquid crystal display (L(8) panel is usually composed of pixel units (or simply pixels) arranged in a matrix of rows and columns. Each of the main pixels includes a thin film transistor (TFT) and a pixel electrode, which are raised together and recognized. Formed on a substrate. The gates of the thin film transistors in the same column are connected by a scan line, and then controlled by a gate driver. The source of the thin film transistor is located at the same time. The poles are connected by a data line, and the π field body is controlled by the pole drive 1 §. The common electrode (common electro^ ν , ae ' VC0m ) is formed on another substrate. The liquid crystal (L〇_ in pixels) Between the electrode substrate and the common electrode substrate, display of each pixel is performed by controlling the electric power difference between the two substrates. The first figure shows a structural diagram of one pixel, wherein the thin film transistor (m) _ pole G Connected to the scan line, and its drain is connected to the data line. When the thin film transistor (m) is turned on by the scan signal on the scan line (for example, the rising level scan signal), the data signal passes through the data line through the data line. Transistor The channel stores the charge in the storage capacitor U. After the storage is completed, the scanning signal is reduced to return to the original level, thereby closing the thin film transistor. However, the thin film transistor has a closed-pole G_ immersed D and a gate G - The source S usually has a stray capacitance Cp. When the scan signal is about to lower the level to turn off the thin film transistor, the stray capacitance Cp tends to lower the drain D and source S voltage levels of the thin film transistor. Therefore, it affects the amount of charge in the storage capacitor Cs. This phenomenon is generally called the feed through effect, which causes the display color to be uneven ( mura ). ° In order to improve the feedthrough effect, a chamfering circuit is proposed for chamfering the falling sharp angle of the waveform of the scanning signal Vg, as shown in the second figure, wherein the original scanning signal Vg (at time t2) has a vertical The falling edge. At time t1 before t2, the chamfer circuit is used to lower the high-level gate voltage VGH of the gate driver by a quasi-drop, and then return to the original high-level gate voltage VGH at time t2. Thereby, the chamfering scanning signal Vg can be generated. The chamfering technique of the scanning signal can be used to reduce the feedthrough effect. However, the chamfering technique needs to control complicated timing, and the required chamfering circuit increases the circuit area and Power consumption. Therefore, it is not suitable for a driver of a high-resolution liquid crystal display panel. [0003] In view of the above, one of the objects of the embodiments of the present invention is to provide a gate driver with a slow-down scan signal to reduce Or avoiding the feed through effect, thereby reducing or avoiding the phenomenon of color mura. According to an embodiment of the invention, the gate driver comprises a shift register, an electric displacement rotator and a buffer. The shift register is responsive to a predetermined sequence to generate control signals for the plurality of scan lines. The electric displacement transducer converts the control signal from a low level to a high level required for the switching elements of the display panel. Buffer generation sweep 099101569 Form number A0101 Page 4 of 15 0992003051-0 201126498 信号 Signal to drive the scan line of the display panel. Wherein, part of the circuit power supply of the buffer uses a level gate voltage (VGN) lower than the high level gate voltage (VGH), thereby causing the waveform of the scan signal to have a falling edge. According to an embodiment, the buffer includes a first amplifier, a second amplifier, and a driver circuit. The power of the first amplifier is a low level gate voltage (VGL) and a medium level gate voltage (VGN); the power source of the second amplifier is a low level gate voltage (VGL) and a high level gate voltage (VGH), wherein The value of the median threshold voltage (VGN) is between the high level gate voltage (VGH) and the low level gate voltage (VGL). The input end of the first amplifier and the input end of the second amplifier are electrically coupled to the output end of the electric displacement converter, and the driving circuit is controlled by the first amplifier and the second amplifier for generating a scan signal to drive the display. The scan line of the panel. [Embodiment] The third figure shows a gate driver of an embodiment of the present invention for driving a display panel 10 such as a liquid crystal display (LCD) panel. The gate driver of this embodiment mainly includes a shift register 12, a level shifter 14 and a buffer 16. The shift register 12 is responsive to a predetermined sequence to generate an open control signal for each scan line. The electric displacement transducer 14 converts the control signal from a low level (eg, 3/0 volts or 5/0 volts) to a high level (eg, 20/-5 volts) required for a panel switching element, such as a thin film transistor (TFT). . The buffer 16 provides a drive capability to the control signal to drive the scan lines of the panel 10. The buffer 16 of this embodiment mainly includes a first amplifier 160N, a second amplifier 160P, and a drive circuit 162. In the present embodiment, the first amplifier form number A0101 page 5/15 page 0992003051-0 201126498 160N is an inverting amplifier' and the second amplifier i6〇p is also an inverting amplifier. The driving circuit 162 includes a P-type transistor (for example, a p-type metal oxide semiconductor (PMOS) transistor) P1 and an N-type transistor (for example, an N-type metal oxide semiconductor (NMOS) transistor) N1, which are connected in series to a high-level gate voltage. Between VGH and low level gate voltage VGL. In detail, the source S of the PIOS transistor P1 is connected to the high level gate voltage VGH, the drain D of the P0O transistor P1 is connected to the drain D of the NM0S transistor N1, and the source S of the NM0S transistor N1 is connected. To the low level of the gate voltage VGL. The input end of the first amplifier 160N is electrically coupled to the input end of the second amplifier 160P; the output end of the first amplifier 160N is connected to the gate of the NM0S transistor, to control the opening or closing of the NM0S transistor N1; The output of the second amplifier WOP is connected to the gate of the PMOS transistor P1 to control the PMOS transistor? 1 is turned on or off. Although the number of the first amplifier 16 〇Ν and the second amplifier 1600 P of the present embodiment is one, respectively, a plurality of amplifiers may be connected in series. Usually, an odd number of amplifiers are connected in series, and the number of series connection of the first amplifier 160N and the second amplifier 16p is the same. . . . :-· if'-...... According to one of the features of the embodiment, the voltage source supplied to the first amplifier 16〇N is a low-level gate voltage VGL and a medium-level gate. Voltage VGN. In other words, the output level of the first amplifier 160N is approximately between VGN and VGL. If the plurality of first amplifiers 16 are connected in series, the median gate voltage VGN is supplied to the first amplifier 16 of the last stage, and the remaining first amplifier 160N can (but not necessarily) replace the high level gate voltage. VGH. As for the second amplifier 160P', a low level gate voltage VGL and a high level gate voltage VGH are provided. In other words, the output level of the second amplifier 16 〇p is approximately between VGH and VGL. 099101569 Form No. A0101 Page 6 of 15 0992003051-0 201126498 The fourth figure shows the voltage level of the median quasi-gate voltage VGN, which is between the high level gate voltage VGH and the low level gate voltage vgl. . The value of the median gate voltage VGN is set in advance, however, it can also be set by the user. Further, the median quasi-gate voltage VGN may be generated internally by the gate driver or externally. Since the present embodiment provides the median gate voltage VGN to the first amplifier 16〇N', the voltage (about VGN) of the first amplifier 160N at the high level output is smaller than the conventional high level output voltage (approximately & VGH) thus reducing the driving force to the NM0S transistor N1. Thereby, the scanning signal Vg generated by the buffer 6 has a side edge which is slow off, as shown in the fourth figure. The ramp-down scanning signal Vg can reduce or avoid the feed through effect caused by the gate-drain and gate-source parasitic capacitance of the thin film transistor (TFT), thereby reducing or avoiding
' I 免顏色不均（mura)的現象。 如前所述，中位準閘極電壓VGN的位準大小可以作調整。 第五A圖顯示NM0S電晶體N1之導通電流Ids和汲極-源極 壓降Vds曲線。如圖所示’調高中位準閘極電壓VGN的位 準會增加導通電流Ids ’亦即增加NM0S電晶體N1之驅動 力；調低中位準閘極電壓VGN的位準會降低導通電流ids ，亦即降低NM0S電晶體N1之驅動力。第五B圖例示二緩降 之掃描信號Vg的波形’其中一個對應至較大的中位準閘 極電壓VGN，而另一個則對應至較小的中位準閘極電壓 VGN。如圖所示，愈小之中位準閘極電壓VGN可得到更緩 099101569 表單編號A0101 第7頁/共15頁 0992003051-0 201126498 降之掃描信號Vg。秋而、a *、、、而，過於緩降之掃描信號Vg則可能 造成前、後掃描信號Vg之間的重疊。 J错由提供中位準閘極電壓VGN以 邊緣緩降之掃描信號Vg，可降低⑽⑽電晶體以 ，因而得以減少或避免饋通加“一㈤敦痛動力 傳統技術（例如第二圖）相較之下，本實施例二。與 複雜的削角電路用以對掃描信號⑽行削角，本貪:用 僅需使用簡單機制以產生緩降之掃描信㈣ 改善饋通效應。 得从 . .. ' . 以上所述僅為本發明之較佳實施例而已，並非 本發明之申請專利範圍；凡其它未脫離發明所揭 、 、文格 神下所元成之等效改變或修飾，均應包含在下述欠申 專利範圍内。 ^ [0005] 【圖式簡單說明】 第一圖顯示一個像素的結‘示意圖。 第二圖顯示傳統削角技術的波形圖。 第三圖顯示本發明實施例的閘極驅動器。 第四圖顯示中位準閘極電壓VGN的電壓位準及緩降 號。 信 第五A圖顯示電晶體之導通電流和汲極-源極壓降故 第五B圖例示二緩降之掃描信號的波形。 [0006] 【主要元件符號說明】 1〇 顯示面板 099101569 表·單編號A0101 第8頁/共15頁 201126498' I does not have the phenomenon of color unevenness (mura). As mentioned above, the level of the median quasi-gate voltage VGN can be adjusted. Figure 5A shows the on-current Ids and the drain-source voltage drop Vds curve of the NM0S transistor N1. As shown in the figure, 'increasing the level of the medium-level gate voltage VGN will increase the on-current Ids', that is, increasing the driving force of the NM0S transistor N1; lowering the level of the center-level gate voltage VGN will lower the on-current ids. That is, the driving force of the NM0S transistor N1 is lowered. The fifth B diagram illustrates that the waveform of the second ramp-down scan signal Vg corresponds to a larger center-level gate voltage VGN, and the other corresponds to a smaller center-level gate voltage VGN. As shown in the figure, the smaller the medium-level gate voltage VGN can be obtained more slowly. 099101569 Form No. A0101 Page 7 of 15 0992003051-0 201126498 The scanning signal Vg is lowered. In the autumn, a*, , and, too, the scanning signal Vg that is too slow may cause an overlap between the front and rear scanning signals Vg. The J error can be reduced by (10) (10) the transistor by providing the scan signal Vg with the median quasi-gate voltage VGN at the edge to reduce the edge, thereby reducing or avoiding the feedthrough plus the "one (5)) painful power conventional technology (for example, the second figure) In contrast, the second embodiment is combined with a complicated chamfering circuit for chamfering the scanning signal (10). This is greedy: the feedthrough effect is improved by using a simple mechanism to generate a slow-down scanning signal (4). The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; any other equivalent changes or modifications which are not disclosed in the invention, and which are It should be included in the scope of the following patents. ^ [0005] [Simple diagram of the diagram] The first diagram shows the diagram of the junction of one pixel. The second diagram shows the waveform diagram of the traditional chamfering technique. The third diagram shows the implementation of the present invention. The gate driver of the example. The fourth figure shows the voltage level and the slow drop number of the center-level gate voltage VGN. The fifth Figure A shows the on-current of the transistor and the drain-source voltage drop. Illustrate the waveform of the second descending scan signal [0006] The main reference numerals DESCRIPTION 1〇 display panel A0101 099 101 569 Table · Single Page number 8/15 Total 201 126 498
12 移位暫存器 14 電位移轉器 16 緩衝器 160N 第一放大器 160P 第二放大器 162 驅動電路 G 閘極 S 源極 D 汲極 Cs 儲存電容 Cp 雜散電容 Vg 掃描信號 VGH 高位準閘極電壓 VGL 低位準閘極電壓 VGN 中位準閘極電壓 N1 NM0S電晶體^ PI PM0S電晶體f、12 Shift register 14 Electro-displacer 16 Buffer 160N First amplifier 160P Second amplifier 162 Drive circuit G Gate S Source D D-Cs Storage capacitor Cp Stray capacitance Vg Scan signal VGH High-level gate voltage VGL low-level gate voltage VGN medium-level gate voltage N1 NM0S transistor ^ PI PM0S transistor f,
099101569 表單編號A0101 第9頁/共15頁 0992003051-0099101569 Form No. A0101 Page 9 of 15 0992003051-0