TWI419134B - Gate driver - Google Patents

Gate driver Download PDF

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Publication number
TWI419134B
TWI419134B TW99101569A TW99101569A TWI419134B TW I419134 B TWI419134 B TW I419134B TW 99101569 A TW99101569 A TW 99101569A TW 99101569 A TW99101569 A TW 99101569A TW I419134 B TWI419134 B TW I419134B
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TW
Taiwan
Prior art keywords
amplifier
gate voltage
level
type transistor
vgn
Prior art date
Application number
TW99101569A
Other languages
Chinese (zh)
Other versions
TW201126498A (en
Inventor
Han Shui Hsueh
Fa Ming Chen
Original Assignee
Himax Tech Ltd
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Filing date
Publication date
Application filed by Himax Tech Ltd filed Critical Himax Tech Ltd
Priority to TW99101569A priority Critical patent/TWI419134B/en
Publication of TW201126498A publication Critical patent/TW201126498A/en
Application granted granted Critical
Publication of TWI419134B publication Critical patent/TWI419134B/en

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Description

Gate driver

The invention relates to the driving of a display panel, and more particularly to a gate driver having a slow-down scanning signal.

Liquid crystal display (LCD) panels typically consist of pixel cells (or simply pixels) arranged in a matrix of rows and columns. Each of the pixels includes a thin film transistor (TFT) and a pixel electrode which are collectively formed on a substrate. The gates of the thin film transistors in the same column are connected together by a scan line and then controlled by a gate driver. The sources of the thin film transistors in the same row are connected by a data line and then controlled by the source driver. A common electrode (Vcom) is formed on another substrate. A liquid crystal (LC) is sealed between the pixel electrode substrate and the common electrode substrate, and display of each pixel is performed by controlling a voltage difference between the two substrates.

The first figure shows a schematic diagram of the structure of one pixel. Wherein, the gate G of the thin film transistor (TFT) is connected to the scan line, and the drain of the thin film transistor is connected to the data line. When the thin film transistor (TFT) is turned on by the scan signal on the scan line (for example, the rising level scan signal), the data signal is stored in the storage capacitor Cs by the data line passing through the channel of the thin film transistor. After the storage is completed, the scan signal is reduced to the original level, thus closing Closed film transistor. However, the gate transistor G-drain D of the thin film transistor and the gate G-source S usually have a stray capacitance Cp. When the scan signal is about to lower the level to turn off the thin film transistor, the stray capacitance Cp tends to lower the drain D and source S voltage levels of the thin film transistor, thus affecting the amount of charge in the storage capacitor Cs. This phenomenon is generally referred to as a feed through effect, which causes a display color unevenness (mura).

In order to improve the feedthrough effect, a chamfering circuit is proposed for chamfering the falling sharp angle of the waveform of the scanning signal Vg, as shown in the second figure. Among them, the original scanning signal Vg (at time t2) has a vertical falling edge. At time t1 before t2, the chamfering circuit is used to lower the high-level gate voltage VGH of the gate driver by a predetermined drop, and then return to the original high-level gate voltage VGH at time t2. Thereby, the chamfered scanning signal Vg can be generated.

Although the chamfering technique of the above scanning signal can be used to reduce the feedthrough effect, the chamfering technique needs to control complicated timing, and the required chamfering circuit increases the circuit area and power consumption. Therefore, it is not suitable for a driver of a high-resolution liquid crystal display panel.

In view of the above, one of the objects of embodiments of the present invention is to provide a gate driver having a ramp-down scan signal to reduce or avoid the feed through effect, thereby reducing or avoiding mura.

According to an embodiment of the invention, the gate driver includes a shift register, an electrical shifter, and a buffer. The shift register is responsive to a predetermined sequence to generate control signals for the plurality of scan lines. The electric displacement transducer converts the control signal from a low level to a high level required for the switching elements of the display panel. The buffer generates a scan signal to drive the scan line of the display panel. Among them, slow Part of the circuit power supply of the punch uses a level gate voltage (VGN) lower than the high level gate voltage (VGH), thus causing the waveform of the scan signal to have a falling edge. According to an embodiment, the buffer includes a first amplifier, a second amplifier, and a drive circuit. The power of the first amplifier is a low level gate voltage (VGL) and a medium level gate voltage (VGN); the power source of the second amplifier is a low level gate voltage (VGL) and a high level gate voltage (VGH), wherein The value of the median threshold voltage (VGN) is between the high level gate voltage (VGH) and the low level gate voltage (VGL). The input end of the first amplifier and the input end of the second amplifier are electrically coupled to the output end of the electric displacement converter, and the driving circuit is controlled by the first amplifier and the second amplifier for generating a scan signal to drive the display. The scan line of the panel.

10‧‧‧ display panel

12‧‧‧Shift register

14‧‧‧Electric displacement transducer

16‧‧‧buffer

160N‧‧‧First Amplifier

160P‧‧‧second amplifier

162‧‧‧ drive circuit

G‧‧‧ gate

S‧‧‧ source

D‧‧‧汲

Cs‧‧‧ storage capacitor

Cp‧‧‧ stray capacitance

Vg‧‧‧ scan signal

VGH‧‧‧ high level threshold voltage

VGL‧‧‧low level gate voltage

VGN‧‧‧median threshold voltage

N1‧‧‧ NMOS transistor

P1‧‧‧ PMOS transistor

The first figure shows a schematic diagram of the structure of one pixel.

The second figure shows the waveform of a conventional chamfering technique.

The third figure shows a gate driver of an embodiment of the present invention.

The fourth graph shows the voltage level and the ramp-down scan signal of the center-level gate voltage VGN.

Figure 5A shows the on-current and drain-source voltage drop curves of the transistor.

Figure 5B illustrates the waveform of the second ramped scan signal.

The third figure shows a gate driver of an embodiment of the invention for driving a display surface A board 10, such as a liquid crystal display (LCD) panel. The gate driver of this embodiment mainly includes a shift register 12, a level shifter 14 and a buffer 16. The shift register 12 is configured to generate an open control signal for each scan line in a predetermined order. The electric displacement transducer 14 converts the control signal from a low level (eg, 3/0 volts or 5/0 volts) to a high level (eg, 20/-5 volts) required for a panel switching element, such as a thin film transistor (TFT). . The buffer 16 is a drive line that provides drive capability to the control signal to drive the panel 10.

The buffer 16 of this embodiment mainly includes a first amplifier 160N, a second amplifier 160P, and a driving circuit 162. In the present embodiment, the first amplifier 160N is an inverting amplifier, and the second amplifier 160P is also an inverting amplifier. The driving circuit 162 includes a P-type transistor (for example, a P-type metal oxide semiconductor (PMOS) transistor) P1 and an N-type transistor (for example, an N-type metal oxide semiconductor (NMOS) transistor) N1, which are connected in series to a high-level gate voltage. VGH and low level gate voltage VGL. In detail, the source S of the PMOS transistor P1 is connected to the high level gate voltage VGH, the drain D of the PMOS transistor P1 is connected to the drain D of the NMOS transistor N1, and the source S of the NMOS transistor N1 is connected. To the low level of the gate voltage VGL. The input end of the first amplifier 160N and the input end of the second amplifier 160P are electrically coupled; the output end of the first amplifier 160N is connected to the gate of the NMOS transistor N1 to control the opening or closing of the NMOS transistor N1; The output of the second amplifier 160P is then connected to the gate of the PMOS transistor P1 to control the turning on or off of the PMOS transistor P1. Although the number of the first amplifier 160N and the second amplifier 160P of the present embodiment is one, respectively, a plurality of amplifiers may be connected in series. Usually, an odd number of amplifiers are serially connected in series, and the number of series connection of the first amplifier 160N and the second amplifier 160P is the same.

According to one of the features of the embodiment, the voltage supplied to the first amplifier 160N The source is the low level gate voltage VGL and the middle level gate voltage VGN. In other words, the output level of the first amplifier 160N is approximately between VGN and VGL. If a plurality of first amplifiers 160N are connected in series, a mid-level gate voltage VGN is supplied to the first amplifier 160N of the last stage, and the remaining first amplifier 160N may (but not necessarily) be substituted with a high level gate voltage VGH. As for the second amplifier 160P, a low level gate voltage VGL and a high level gate voltage VGH are provided. In other words, the output level of the second amplifier 160P is approximately between VGH and VGL.

The fourth graph shows the voltage level of the center-level gate voltage VGN, which is between the high-level gate voltage VGH and the low-level gate voltage VGL. The value of the median threshold voltage VGN is set in advance, however, it can also be set by the user. Further, the median quasi-gate voltage VGN may be generated internally by the gate driver or externally.

Since the present embodiment provides the center-level gate voltage VGN to the first amplifier 160N, the voltage (about VGN) when the first amplifier 160N is output at a high level is smaller than the conventional high-level output voltage (about VGH). Thus, the driving force to the NMOS transistor N1 is lowered. Thereby, the scan signal Vg generated by the buffer 16 will have a edge that is slow off, as shown in the fourth figure. The ramp-down scan signal Vg reduces or avoids the feed through effect caused by the gate-drain and gate-source parasitic capacitances of the thin film transistor (TFT), thereby reducing or avoiding color The phenomenon of unevenness (mura).

As mentioned above, the level of the median quasi-gate voltage VGN can be adjusted. The fifth graph A shows the on-current Ids and the drain-source voltage drop Vds curve of the NMOS transistor N1. As shown in the figure, increasing the level of the center-level gate voltage VGN increases the on-current Ids. That is, the driving force of the NMOS transistor N1 is increased; lowering the level of the center-level gate voltage VGN reduces the on-current Ids, that is, reduces the driving force of the NMOS transistor N1. Figure 5B illustrates the waveform of the two ramp-down scan signals Vg, one corresponding to a larger mid-level gate voltage VGN and the other corresponding to a smaller mid-level gate voltage VGN. As shown, the smaller the intermediate gate voltage VGN, the more slowly the scan signal Vg is obtained. However, the scan signal Vg which is too slow may cause an overlap between the front and rear scan signals Vg.

According to the above, in the present embodiment, by providing the middle-level gate voltage VGN to generate the edge-down scanning signal Vg, the driving force of the NMOS transistor N1 can be reduced, thereby reducing or avoiding the feed through effect. Compared with the conventional technology (for example, the second figure), this embodiment does not need to use a complicated chamfering circuit for chamfering the scanning signal Vg. This embodiment only needs to use a simple mechanism to generate a slow-down scanning signal. Vg, thus improving the feedthrough effect.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

10‧‧‧ display panel

12‧‧‧Shift register

14‧‧‧Electric displacement transducer

16‧‧‧buffer

160N‧‧‧First Amplifier

160P‧‧‧second amplifier

162‧‧‧ drive circuit

G‧‧‧ gate

S‧‧‧ source

D‧‧‧汲

Vg‧‧‧ scan signal

VGH‧‧‧ high level threshold voltage

VGL‧‧‧low level gate voltage

VGN‧‧‧median threshold voltage

N1‧‧‧ NMOS transistor

P1‧‧‧ PMOS transistor

Claims (8)

  1. A gate driver includes: a shift register for generating control signals of a plurality of scan lines in a predetermined order; and an electric shifter for converting the control signal from a low level to a switch of a display panel a high level required for the component; and a buffer for generating a scan signal for driving the scan line of the display panel, wherein a portion of the circuit power supply of the buffer uses a bit lower than a high level gate voltage (VGH) a quasi-gate voltage (VGN), thereby causing the waveform of the scan signal to have a falling edge; wherein the buffer includes: a first amplifier whose power supply is a low-level gate voltage (VGL) and a center-level gate voltage (VGN); a second amplifier whose power supply is a low level gate voltage (VGL) and a high level gate voltage (VGH), wherein the value of the center gate voltage (VGN) is between the high level gate voltage (VGH) and a low-level gate voltage (VGL), and the input end of the first amplifier and the input end of the second amplifier are electrically coupled to the output end of the electric displacement converter; and a driving circuit, Controlled by the first amplifier and the second amplifier For generating the scan signals to drive scan lines of the display panel.
  2. The gate driver of claim 1, wherein the first amplifier and the second amplifier respectively comprise an inverting amplifier.
  3. Such as the gate driver described in claim 1, wherein the above drive The dynamic circuit comprises a P-type transistor and an N-type transistor connected in series between a high level gate voltage (VGH) and a low level gate voltage (VGL), wherein the N type transistor and the P type transistor The turning on or off is controlled by the first amplifier and the second amplifier, respectively.
  4. The gate driver of claim 3, wherein a source of the P-type transistor is connected to a high level gate voltage (VGH), and a drain of the P-type transistor is connected to the N-type transistor a drain, a source of the N-type transistor is coupled to a low-level gate voltage (VGL), a gate of the N-type transistor is coupled to an output of the first amplifier, and a gate of the P-type transistor is coupled to The output of the second amplifier.
  5. The gate driver of claim 1, wherein the number of the first amplifiers is more than one and an odd number, and the plurality of first amplifiers are connected in series with each other, and the number of the second amplifiers is the same as the number The number of first amplifiers, and the plurality of second amplifiers are connected in series with each other.
  6. The gate driver of claim 5, wherein the power source of the last stage first amplifier is a low level gate voltage (VGL) and a medium level gate voltage (VGN).
  7. The gate driver of claim 1, wherein the middle level gate voltage (VGN) is generated internally by the gate driver.
  8. The gate driver of claim 1, wherein the middle level gate voltage (VGN) is provided externally by the gate driver.
TW99101569A 2010-01-21 2010-01-21 Gate driver TWI419134B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW99101569A TWI419134B (en) 2010-01-21 2010-01-21 Gate driver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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TWI419134B true TWI419134B (en) 2013-12-11

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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI444965B (en) 2011-12-30 2014-07-11 Au Optronics Corp High gate voltage generator and display module of same
TWI453719B (en) * 2012-03-30 2014-09-21 Himax Tech Ltd Gate driver
TWI463459B (en) 2012-09-27 2014-12-01 E Ink Holdings Inc Flat panel display and threshold voltage sensing circuit thereof
TWI514356B (en) * 2013-02-06 2015-12-21 Au Optronics Corp Display panel and gate driver thereof
CN107293267B (en) * 2017-07-19 2020-05-05 深圳市华星光电半导体显示技术有限公司 Display panel and control method of display panel grid signals

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010033266A1 (en) * 1998-09-19 2001-10-25 Hyun Chang Lee Active matrix liquid crystal display
CN101447177A (en) * 2009-01-05 2009-06-03 友达光电股份有限公司 Display capable of actively regulating drive voltage, voltage compensation circuit and driving method
TW200933568A (en) * 2008-01-25 2009-08-01 Au Optronics Corp Panel display apparatus and controlling circuit and method for controlling same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010033266A1 (en) * 1998-09-19 2001-10-25 Hyun Chang Lee Active matrix liquid crystal display
US20060001640A1 (en) * 1998-09-19 2006-01-05 Hyun Chang Lee Active matrix liquid crystal display
TW200933568A (en) * 2008-01-25 2009-08-01 Au Optronics Corp Panel display apparatus and controlling circuit and method for controlling same
CN101447177A (en) * 2009-01-05 2009-06-03 友达光电股份有限公司 Display capable of actively regulating drive voltage, voltage compensation circuit and driving method

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