TWI514356B - Display panel and gate driver thereof - Google Patents

Display panel and gate driver thereof Download PDF

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Publication number
TWI514356B
TWI514356B TW102104559A TW102104559A TWI514356B TW I514356 B TWI514356 B TW I514356B TW 102104559 A TW102104559 A TW 102104559A TW 102104559 A TW102104559 A TW 102104559A TW I514356 B TWI514356 B TW I514356B
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Taiwan
Prior art keywords
switch
electrically
output
type transistor
signal
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TW102104559A
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Chinese (zh)
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TW201432659A (en
Inventor
Weichien Liao
Yuhsuan Li
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Au Optronics Corp
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Publication of TWI514356B publication Critical patent/TWI514356B/en

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Description

Display panel and its gate driver

The present invention relates to a display panel, and more particularly to a gate driver in a display panel.

Recently, various liquid crystal display products have become quite popular. In order to effectively increase the viewing area of a liquid crystal display, a display panel technology suitable for a narrow bezel has been continuously proposed. For example, in the case of a gate driver circuit, both the bilateral single-drive shift register circuit architecture and the shared (Co-used) shift register architecture can be seen in a display panel that is applied to a narrow bezel.

In the case of the bilateral single-drive shift register circuit architecture, the shift register circuits in the gate driver are respectively disposed on both sides outside the pixel area in the display panel, and the shift register circuit on one side Responsible for transmitting odd-level gate drive signals, and the other side of the shift register circuit is responsible for transmitting even-numbered gate drive signals, reducing the original gate driver by making full use of the available space on both sides of the pixel area. The area required for layout, which in turn achieves the purpose of a narrow border.

On the other hand, in the case of a shared shift register architecture, the gate drive A logic circuit is disposed in the actuator, and the single-stage shift register circuit can respectively output the gate drive signal to the plurality of gate lines through the logic circuit, so that the gate driver can output the function of outputting the plurality of gate drive signals. And the area required for the gate driver is also reduced.

However, the above-mentioned technology will become difficult to achieve the required specifications as the current product specifications have higher and higher resolution requirements and the frame requirements are narrower and narrower, so that the area of the final gate driver is still limited. The size of the circuit structure of the gate driver itself.

In order to solve the above problems, one aspect of the present disclosure is to provide a gate driver that reduces the area required for its layout by simplifying its internal circuit architecture.

One aspect of the present disclosure is directed to a gate driver including a plurality of serially connected driver stages, wherein the driver stage is configured to sequentially output a plurality of gate drive signals, each of the driver stages including a shift A temporary storage unit, a control unit, and a buffer unit. The shift register unit is configured to generate a shift signal. The control unit is configured to receive the power signal and perform a single inversion processing on the shift signal, wherein the control unit outputs the inverted shift signal in a normal operating state, and outputs a high level according to the power signal in the power-off state. Quasi-voltage signal. The buffer unit receives and buffers the output of the inverted signal or the high level voltage signal as one of a plurality of gate drive signals.

According to an embodiment of the invention, wherein the foregoing control unit further comprises A switch and an inverter circuit. The first switch has a first end, a second end, and a control end, wherein the control end of the first switch is electrically connected to an input unit, and the first end of the first switch is used to electrically connect the high level voltage. The inverter circuit is connected in series to the second end of the first switch, and is used for inverting the shift signal.

According to an embodiment of the invention, the control unit further includes a pull-up circuit. The pull-up circuit is electrically connected to the output end of the inverter circuit, and pulls the output end of the inverter circuit to a high level voltage according to the power signal in the power-off state.

According to an embodiment of the invention, the inverter circuit further includes a second switch and a third switch. The second switch and the third switch are connected in series to the output end of the inverter circuit, and the control unit further includes a fourth switch and a fifth switch. The fourth switch is connected in series with the third switch, and has a first end, a second end, and a control end, wherein the control end of the fourth switch receives the power signal, and the first end of the fourth switch is electrically connected to the third switch, The second end of the four switches is electrically connected to a low level voltage. The fifth switch has a first end, a second end, and a control end, wherein the control end of the fifth switch receives the power signal, the first end of the fifth switch is electrically connected to the high level voltage, and the second end of the fifth switch is electrically connected The output of the inverter circuit.

According to an embodiment of the invention, in the normal operating state, the fourth switch is turned on according to the power signal, the fifth switch is turned off according to the power signal, and in the power-off state, the fourth switch is turned off according to the power signal, and the fifth switch is powered according to the power source. The signal is turned on.

Another aspect of the present invention is directed to a gate driver A plurality of serially connected driver stages are included, each of the driver stages including an input unit, a shift register unit, a first switch, a second switch, a third switch, a fourth switch, and a fifth switch. The input unit has an output. The shift register unit has an input end and an output end, and the input end of the shift register unit is electrically connected to the output end of the input unit. The first switch has a first end, a second end, and a control end, wherein the control end of the first switch is electrically connected to the input unit, and the first end of the first switch is electrically connected to a first level voltage. The second switch has a first end, a second end, and a control end, wherein the control end of the second switch is electrically connected to the output end of the shift register unit, and the first end of the second switch is electrically connected to the first switch The second end. The third switch has a first end, a second end, and a control end, wherein the control end of the third switch is electrically connected to the output end of the shift register unit, and the first end of the third switch is electrically connected to the second switch Second end. The fourth switch has a first end, a second end, and a control end, wherein the control end of the fourth switch receives a power signal, and the first end of the fourth switch is electrically connected to the second end of the third switch, and the fourth switch The second end is electrically connected to a second level voltage. The fifth switch has a first end, a second end, and a control end, wherein the control end of the fifth switch receives the power signal, and the first end of the fifth switch is electrically connected to the first level voltage, and the fifth switch The second end is electrically connected to the first end of the third switch and the second end of the second switch.

According to still another embodiment of the present invention, the gate driver further includes a first inverter circuit and a second inverter circuit. The input end of the first inverter circuit is electrically connected to the first end of the third switch and the second end of the second switch, and the output end of the first inverter circuit is electrically connected to the second inverter The input of the circuit.

A second aspect of the present disclosure is to provide a display panel including a plurality of data lines, a plurality of gate lines, and a gate driver, wherein the gate lines are alternately arranged with the data lines.

The gate driver is electrically connected to the gate line, wherein the gate driver comprises a plurality of serially connected driving stages, and each of the foregoing driving stages comprises an input unit, a shift register unit, a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, and a third P-type transistor. The input unit has an output. The shift register unit has an input end and an output end, and the input end of the shift register unit is electrically connected to the output end of the input unit. The gate of the first P-type transistor is electrically connected to the output end of the input unit, and the source of the first P-type transistor is electrically connected to a first level voltage. The gate of the second P-type transistor is electrically connected to the output end of the shift register unit, and the source of the second P-type transistor is electrically connected to the drain of the first P-type transistor. The gate of the first N-type transistor is electrically connected to the output end of the shift register unit, and the drain of the first N-type transistor is electrically connected to the drain of the second P-type transistor. The gate of the second N-type transistor receives a power signal, the drain of the second N-type transistor is electrically connected to the source of the first N-type transistor, and the source of the second N-type transistor is electrically connected Two quasi-voltage. The gate of the third P-type transistor receives the power signal, the source of the third P-type transistor is electrically connected to the first level voltage, and the drain of the third P-type transistor is electrically connected to the first type N The drain of the crystal and the drain of the second P-type transistor.

According to an embodiment of the invention, the display panel further includes a first inverter circuit and a second inverter circuit, wherein the first inverter circuit The input end is electrically connected to the drain of the first N-type transistor and the drain of the second P-type transistor, and the output end of the first inverter circuit is electrically connected to the input end of the second inverter circuit.

Another aspect of the present disclosure is to provide a display panel including a plurality of data lines, a plurality of gate lines, and a gate driver. The gate line is alternately arranged with the aforementioned data line. The gate driver includes a plurality of serially connected driving stages for sequentially outputting a plurality of gate driving signals to the gate lines. Each of the driving stages includes a shift register unit, a control unit, and a pull-up circuit. The shift register unit is configured to generate a shift signal. The control unit is configured to output the inverted shift signal after the corresponding driving signal is outputted by the previous driving stage and the continuous inversion processing is not performed on the shift signal, wherein the control unit further includes a pull-up circuit In order to pull the output of the control unit to a high level voltage according to the power signal in the power-off state.

In summary, by applying the above embodiments, the circuit structure of the gate driver is simplified to reduce the layout area of the gate driver in the display panel, thereby achieving the requirement of a narrow bezel.

100‧‧‧ display panel

120‧‧‧Image display area

122‧‧‧ pixel array

124‧‧‧ Displaying pixels

140‧‧‧Source Driver

160‧‧‧gate driver

200‧‧‧Image display area

220‧‧‧Driver

300‧‧‧Image display area

320‧‧‧Driver

400‧‧‧Driver

420‧‧‧ input unit

440‧‧‧Shift register unit

460‧‧‧Control unit

462‧‧‧Inverter circuit

464‧‧‧ Pulling circuit

480‧‧‧buffer unit

M1~M9‧‧‧ switch

INV1‧‧‧Inverter Circuit

INV2‧‧‧Inverter Circuit

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a display panel according to an embodiment of the present invention; 2 is a schematic diagram showing the arrangement of an image display area and a gate driver in a display panel according to an embodiment of the invention; 3 is a schematic diagram showing a configuration of an image display area and a gate driver in a display panel according to another embodiment of the present invention; and FIG. 4 is a diagram showing a gate driver according to an embodiment of the invention. A schematic diagram of a driver stage; and FIG. 5 is a timing diagram showing operation of a gate driver in accordance with an embodiment of the present invention.

The embodiments are described in detail below with reference to the accompanying drawings, but the embodiments are not intended to limit the scope of the invention, and the description of structural operations is not intended to limit the order of execution thereof The structure, which produces equal devices, is within the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to the original dimensions. For ease of understanding, the same elements in the following description will be denoted by the same reference numerals.

The terms used in the entire specification and the scope of the patent application, unless otherwise specified, generally have the ordinary meaning of each term used in the field, the content disclosed herein, and the particular content. Certain terms used to describe the disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in the description of the disclosure.

As used herein, "about", "about" or "substantially" generally means that the error or range of the index value is within 20%, preferably within 10%, and more preferably It is within 5 percent. In the text Unless otherwise stated, the numerical values referred to are considered as approximations, such as the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

The terms "first", "second", etc., as used herein, are not intended to refer to the order or the order, and are not intended to limit the invention, only to distinguish the elements described in the same technical terms. Or just operate.

Secondly, the words "including", "including", "having," "containing," etc., as used herein are all terms of an open term, meaning, but not limited to.

In addition, the term "coupled" or "connected" as used herein may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, or Multiple components operate or act upon each other.

FIG. 1 is a schematic view showing a display panel according to an embodiment of the invention. As shown in FIG. 1, the display panel 100 includes an image display area 120, a source driver 140, and a gate driver 160. The image display area 120 includes a pixel array 122 and a plurality of displays formed by interleaving a plurality of data lines (eg, N data lines DL1 to DLN) and a plurality of scanning lines (eg, M scanning lines GL1 to GLM). The pixels 124 are displayed, and the display pixels 124 are disposed in the pixel array 122 described above. The source driver 140 is coupled to the data lines DL1 DL DLN, and is configured to transmit the data signals to the image display area 120 to the corresponding pixels 124 through the data lines DL1 DL DLN, and the gate driver 160 is coupled to the scan lines GL1 G GLM and used. The scan lines GL1 G GLM are sequentially driven by the output gate drive signals, and transmitted to the images through the scan lines GL1 G GLM The display area 120 is given to the corresponding pixel 124.

2 is a schematic diagram showing the configuration of an image display area and a gate driver in a display panel according to an embodiment of the invention, wherein the configuration of the image display area and the gate driver can be applied to the display as shown in FIG. In the panel 100, but not limited thereto. As shown in FIG. 2, the gate driver may include a plurality of driving stages 220. In the embodiment, the driving stages 220 are disposed on the left side of the image display area 200. In another embodiment, the driving stage 220 can also be disposed on the right side of the image display area 200. In this embodiment, the driving stage 220 drives the scan lines from the top to bottom output gate driving signals in a sequential manner, and in another embodiment, the driving stages 220 may also be in a sequential manner from bottom to top. The output gate drive signal drives the scan line.

3 is a schematic diagram showing the configuration of an image display area and a gate driver in a display panel according to another embodiment of the present invention, wherein the configuration of the image display area and the gate driver shown in FIG. 1 can be applied as shown in FIG. The display panel 100 is not limited thereto. As shown in FIG. 3, the gate driver may include a plurality of driving stages 320, wherein a portion of the driving stages 320 are disposed on the left side of the image display area 300, and the remaining driving stages 320 are disposed on the right side of the image display area 300, and The driver stages 320 on both sides output the gate drive signals in an alternating manner to drive the scan lines, which is a bilateral single-drive architecture. In one embodiment, the driver stages 320 on both sides drive the scan lines from the top to bottom output gate drive signals in an alternating manner, while in another embodiment, the driver stages 320 on both sides are alternately The lower to upper output gate drive signal drives the scan line.

Figure 4 is a diagram showing a gate drive according to an embodiment of the invention. Schematic diagram of the driver stage in the device. As shown in FIG. 4, the driver stage 400 includes an input unit 420, a shift register unit 440, a control unit 460, and a buffer unit 480, and can be applied to one of the plurality of drive stages shown in FIG. 2 or FIG. But not limited to this.

In this embodiment, the input unit 420 is configured to receive the down signal U2D (eg, the output signal of the upper driver stage) or the up signal D2U (eg, the output signal of the lower driver stage), and according to the down signal U2D or The shift signal D2U generates a control signal CS. The shift register unit 440 is configured to receive the foregoing control signal CS and generate a shift signal SS. The control unit 460 is electrically connected to the shift register unit 440 to receive the shift signal SS, and the reverse shift signal SS is subjected to a single inversion processing, that is, the control unit 460 does not perform the shift signal SS. The continuous inversion processing, wherein the control unit 460 is further configured to receive a power signal POFF to output the inverted signal after the reverse operation in a normal operating state, and output a high level voltage signal in a power-off state (eg, Figure 4 shows the high level voltage signal represented by the high level voltage VGH). The buffer unit 480 is configured to receive and buffer the output of the inverted signal SS or the high level voltage signal to drive the display panel.

It should be noted that, in practice, as shown in FIG. 2, the operation of sequentially driving the scan lines from bottom to top and the operation of sequentially driving the scan lines from top to bottom as shown in FIG. 3 can be performed according to actual needs. This is done by setting the up-shift signal D2U and the down-shift signal U2D.

Next, as shown in FIG. 4, in an embodiment, the input unit 420 may include switches M1, M2, M3, and M4, wherein the control terminals of the switches M1, M2 are respectively configured to receive the up-shift signal D2U and the down-shift signal U2D. , One end of the switches M1, M2 is used to receive the up-shift input signal D2U_STV. The control terminals of the switches M3 and M4 are respectively configured to receive the down-shift signal U2D and the up-shift signal D2U, and one of the switches M3 and M4 is configured to receive the down-shift input signal U2D_STV, and the other ends of the switches M1, M2, M3 and M4 are It is electrically connected to the output end of the input unit 420, and generates a control signal CS according to the configuration of the up-shift signal D2U and the down-shift signal U2D.

In this embodiment, the control unit 460 further includes a switch M5 and an inverter circuit 462. As shown in FIG. 4, the switch M5 has a first end, a second end, and a control end, wherein the first end of the switch M5 is electrically connected to the high level voltage VGH, and the control end of the switch M5 is electrically connected to the input unit 420. In order to receive the aforementioned control signal CS, the switch M5 can be turned on or off according to the configuration of the control signal CS to determine whether the inverter circuit 462 can operate normally. The inverter circuit 462 is connected in series to the second end of the switch M5, and when the switch M5 is turned on, the inverter circuit 462 operates normally to perform a single time on the shift signal SS output by the shift register unit 440. Inverted processing.

In this embodiment, the inverter circuit 462 includes a switch M6 and a switch M7, and the switch M6 and the switch M7 are connected in series to the output end of the inverter circuit 462 (ie, node Q), wherein the switch M6 and the switch M7 are both The first end, the second end and the control end are electrically connected to the output end of the shift register unit 440 to receive the shift signal SS. The first end of the switch M6 is electrically connected to the switch M5. The second end of the switch M6 and the control end of the switch M7 are electrically connected to the output end of the shift register unit 440.

In this embodiment, the control unit 460 further includes a pull-up circuit 464. As shown in FIG. 4, the pull-up circuit 464 is electrically connected to the aforementioned inverter The output of the circuit 462 is configured to pull the output terminal of the inverter circuit 462 to the high level voltage VGH according to the power supply signal POFF in the power-off state.

In the present embodiment, the aforementioned pull-up circuit 464 includes a switch M8 and a switch M9. The control terminal of the switch M8 is configured to receive the power supply signal POFF, the first end of the switch M8 is electrically connected to the high level voltage VGH, and the second end of the switch M8 is electrically connected to the output end of the inverter circuit 462 (ie, the node Q). Next, the switch M9 is connected in series with the switch M7, wherein the control end of the switch M9 is used to receive the power signal POFF, the first end of the switch M9 is electrically connected to one end of the switch M7, and the second end of the switch M9 is electrically connected to the low end. Quasi-voltage VGL.

In operation, when the driving stage 400 is in the normal operating state, the power supply signal POFF is in a high level state, at which time the switch M8 is turned off, the switch M9 is turned on, and the inverter circuit 462 performs a single inversion of the shift signal SS. Processing, and outputting the inverted shift signal SS to the buffer unit 480, and then the buffer unit 480 outputs the corresponding output signal SR_OUT. On the other hand, when the driver stage 400 is in a power-off state (for example, the power supply to the display panel is unexpectedly powered off or turned off), the power supply signal POFF is turned to a low level state, so that the switch M8 is turned on and the switch M9 is turned off. At this time, the inverter circuit 462 suspends operation, and the output terminal of the inverter circuit 462 (ie, the node Q) is pulled up to the high level voltage VGH through the switch M8, thereby outputting the corresponding high level voltage signal to the buffer unit 480, and then buffering. The unit 480 accordingly outputs a corresponding output signal SR_OUT for discharging the pixels in the display panel to return to the initial state.

Secondly, in the embodiment, the foregoing buffer unit 480 can include An even number of inverter circuits connected in series to increase the drive capability of a single driver stage. For example, as shown in FIG. 4, the buffer unit 480 includes an inverter circuit INV1 and an inverter circuit INV2, wherein an input end of the inverter circuit INV1 is electrically connected to an output end of the control unit 460, and an inverter INV2 The input terminal is electrically connected to the output end of the inverter circuit INV1, so that the signal outputted by the control unit 460 can be processed by the inverter circuits INV1, INV2 and then output as the output signal SR_OUT.

In practice, the plurality of switches in the control unit 460 can be a general P-type or N-type transistor or a thin film transistor (TFT). For example, the switch M5, the switch M6 and the switch M8 may be P-type transistors, and the switch M7 and the switch M9 may be N-type transistors. For example, the gate of the P-type transistor M5 is electrically connected to the output end of the input unit 420, and the source of the P-type transistor M5 is electrically connected to the high level voltage VGH; the gate electrical property of the P-type transistor M6 The output terminal of the P-type transistor M6 is electrically connected to the drain of the P-type transistor M5; the gate of the N-type transistor M7 is electrically connected to the shift register unit 440. The output terminal, and the N-type transistor is electrically connected to the drain of the P-type transistor M6; the gate of the N-type transistor M9 receives the power supply signal POFF, and the N-type transistor M9 is electrically connected to the N-type The source of the crystal M7, and the source of the N-type transistor M9 is electrically connected to the low level voltage VGL; the gate of the P-type transistor M8 receives the power supply signal POFF, and the source of the P-type transistor M8 is electrically connected to the high level voltage VGH, and the drain of the P-type transistor M8 is electrically connected to the drain of the N-type transistor M7 and the drain of the P-type transistor M6.

The following describes the operation of the driver stage in the gate driver by way of an embodiment. For the situation. Figure 5 is a timing diagram showing the operation of the driver stage in accordance with an embodiment of the present invention. For the sake of clarity and convenience of explanation, the timing diagrams shown in FIG. 4 and the timing diagrams shown in FIG. 5 are taken as an example, and it is assumed that the driver stage 400 cooperates with the timing diagram shown in FIG. To move the scan down.

First, in the normal state, the power supply signal POFF is maintained at a high level, and when the scanning operation is shifted down, the switch M3 and the switch M4 are turned on. At time t0, the input signal U2D_STV is shifted to a high level, and is transmitted through the switch M3. The M4 output is used as the control signal CS for transmission to the shift register unit 440. The shift register unit 440 receives the control signal CS, generates a corresponding shift signal SS according to the control signal CS, and transmits the shift signal SS to the control unit 460.

Then, at time t1, the scan signal U2D_STV is shifted to a low level, and the switch M5 in the control unit 460 is turned on, and the inverter circuit 462 performs a single inversion processing on the shift signal SS, and the output is inverted. The shift signal SS is sent to the buffer unit 480, and the inverter circuit INV1 and the inverter circuit INV2 connected in series in the buffer unit 480 process the inverted shift signal SS to output a corresponding output signal SR_OUT.

Moreover, at time t2, the display panel is turned to a power-off state, at which time the power supply signal POFF transitions to a low level state, and the switch M8 in the pull-up circuit 464 is turned on and the switch M9 is turned off, and the inverter circuit 462 is suspended. And the output end of the inverter circuit (ie, node Q) is pulled up to the high level voltage VGH through the switch M8, and outputs a corresponding high level voltage signal to the buffer unit 480, and then the inverter circuit serially connected in the buffer unit 480 INV1 and inverter circuit INV2 process the corresponding high level voltage signal and output phase accordingly The output signal SR_OUT is such that the pixels in the display panel are discharged to return to the initial state before the power is turned on.

According to the embodiment of the present invention, in the circuit architecture of a single driver stage in the gate driver, the shift signal only needs a single inversion processing, which simplifies the design of the driver stage circuit, and not only saves the layout of the gate driver. The required area is more in line with the current demand for narrow borders.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

400‧‧‧Driver

420‧‧‧ input unit

440‧‧‧Shift register unit

460‧‧‧Control unit

462‧‧‧Inverter circuit

464‧‧‧ Pulling circuit

480‧‧‧buffer unit

INV1‧‧‧Inverter Circuit

INV2‧‧‧Inverter Circuit

M1~M9‧‧‧ switch

Claims (9)

  1. A gate driver includes a plurality of serially connected driver stages, wherein the driver stages are used to sequentially output a plurality of gate drive signals, each of the driver stages comprising: a shift register unit for Generating a shift signal; a control unit for receiving a power signal for performing a single inversion processing on the shift signal, wherein the control unit is configured to output the inverted phase after a normal operation state Transmitting the signal, and outputting a high level voltage signal according to the power signal in a power off state; and a buffer unit for receiving and buffering the inverted output signal or the high level voltage signal And as one of the gate driving signals; wherein the control unit further comprises: a first switch having a first end, a second end, and a control end, wherein the control end of the first switch Electrically connecting an input unit, the first end of the first switch is electrically connected to a high level voltage; and an inverter circuit is connected in series to the second end of the first switch, and is used for The shift signal Inverting process.
  2. The gate driver of claim 1, wherein the control unit further comprises: a pull-up circuit electrically connected to the output end of the inverter circuit, and configured to use the power source signal in the power-off state The output of the phaser circuit is pulled up to the high level voltage.
  3. The gate driver of claim 1, wherein the inverter circuit is further The second switch and the third switch are connected in series to the output end of the inverter circuit, and the control unit further includes: a fourth switch, and the third switch string a stacking connection, and having a first end, a second end, and a control end, wherein the control end of the fourth switch is configured to receive the power signal, and the first end of the fourth switch is electrically connected to the third end a switch, the second end of the fourth switch is electrically connected to receive a low level voltage; and a fifth switch has a first end, a second end, and a control end, wherein the fifth switch The control terminal is configured to receive the power signal, the first end of the fifth switch is electrically connected to the high level voltage, and the second end of the fifth switch is electrically connected to the output end of the inverter circuit.
  4. The gate driver of claim 3, wherein in the normal operating state, the fourth switch is turned on according to the power signal, the fifth switch is turned off according to the power signal, and in the power-off state, the fourth The switch is turned off according to the power signal, and the fifth switch is turned on according to the power signal.
  5. A gate driver comprising a plurality of serially connected driver stages, each of the driver stages comprising: an input unit having an output; a shift register unit having an input and a An output end of the shift register unit is electrically connected to the output end of the input unit; a first switch having a first end, a second end, and a control end, wherein the first switch The control terminal is electrically connected to the input unit, the first end of the first switch is electrically connected to a first level voltage, and the second switch has a first end, a second end and a control end , The control end of the second switch is electrically connected to the output end of the shift register unit, the first end of the second switch is electrically connected to the second end of the first switch; and a third switch is Having a first end, a second end, and a control end, wherein the control end of the third switch is electrically connected to the output end of the shift register unit, and the first end of the third switch is electrically connected a second end of the second switch; a fourth switch having a first end, a second end, and a control end, wherein the control end of the fourth switch is configured to receive a power signal, the fourth switch The first end is electrically connected to the second end of the third switch, the second end of the fourth switch is electrically connected to a second level voltage, and the fifth switch has a first end a second terminal and a control terminal, wherein the control terminal of the fifth switch is configured to receive the power signal, and the first end of the fifth switch is configured to electrically connect the first level voltage, the fifth The second end of the switch is electrically connected to the first end of the third switch and the second end of the second switch .
  6. The gate driver of claim 5, further comprising: a first inverter circuit; and a second inverter circuit, wherein an input end of the first inverter circuit is electrically connected to the third switch The first end and the second end of the second switch, the output end of the first inverter circuit is electrically connected to the input end of the second inverter circuit.
  7. A display panel comprising: a plurality of data lines; a plurality of gate lines interleaved with the data lines; and a gate driver electrically connected to the gate lines, wherein the gate driver comprises a plurality of serially connected driver stages, each of the driver stages The method includes: an input unit having an output; a shift register unit having an input end and an output end, the input end of the shift register unit being electrically connected to the output end of the input unit; a first P-type transistor, the gate of the first P-type transistor is electrically connected to the output end of the input unit, and the source of the first P-type transistor is electrically connected to a first level voltage; a second P-type transistor, the gate of the second P-type transistor is electrically connected to the output end of the shift register unit, and the source of the second P-type transistor is electrically connected to the first P-type a drain of the transistor; a first N-type transistor, the gate of the first N-type transistor is electrically connected to the output end of the shift register unit, and the gate of the first N-type transistor is electrically Connecting a drain of the second P-type transistor; a second N-type transistor, the gate of the second N-type transistor is for receiving a power source signal, the second N-type transistor is electrically connected to the source of the first N-type transistor, and the source of the second N-type transistor is electrically connected to a second level voltage; And a third P-type transistor, the gate of the third P-type transistor is configured to receive the power signal, and the source of the third P-type transistor is electrically connected to the first level voltage, the first The drain of the three P-type transistor is electrically connected to the drain of the first N-type transistor and the drain of the second P-type transistor.
  8. The display panel as claimed in claim 7 further includes: a first inverter circuit; and a second inverter circuit, wherein an input end of the first inverter circuit is electrically connected to a drain of the first N-type transistor and the second P-type transistor The drain of the first inverter circuit is electrically connected to the input end of the second inverter circuit.
  9. A display panel includes: a plurality of data lines; a plurality of gate lines interleaved with the data lines; and a gate driver comprising a plurality of serially connected driver stages, wherein the driver stages are sequentially output a plurality of gate drive signals to the gate lines, each of the driver stages comprising: a shift register unit for generating a shift signal; and a control unit for the previous driver stage After the corresponding gate driving signal is output and the shift signal is not continuously inverted, the inverted signal is outputted, wherein the control unit further comprises: a pull-up circuit for In the power-off state, the output end of the control unit is pulled up to a high level voltage according to a power signal; a first switch has a first end, a second end, and a control end, wherein the first switch The control terminal is electrically connected to an input unit, the first end of the first switch is electrically connected to a high level voltage, and an inverter circuit is connected in series to the second end of the first switch, and is used The shift signal Inverting process.
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TWI502578B (en) 2013-12-05 2015-10-01 Au Optronics Corp Gate driver
TWI521495B (en) * 2014-02-07 2016-02-11 友達光電股份有限公司 Display panel, gate driver and control method
CN104867438B (en) * 2015-06-24 2018-02-13 合肥鑫晟光电科技有限公司 Shift register cell and its driving method, shift register and display device
TWI625710B (en) * 2017-04-28 2018-06-01 友達光電股份有限公司 Gate driving circuit and display device using the same

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