201121013 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置，特別係有關於一種以垂 直銲柱機械補強之半導體封裝堆疊結構。 【先前技術】 目前半導體產業中，隨著產品微小化與多功能需求的 增加，半導體封裝堆疊結構（Package 〇n Package, pop)201121013 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a semiconductor package stack structure mechanically reinforced by a vertical soldering post. [Prior Art] In the semiconductor industry, with the increase in product miniaturization and multi-functional demand, the package package (Package 〇n Package, pop)
在許多電子裝置的使用上已經日趨普遍。半導體封裝堆 疊結構可藉由將兩個或兩個以上之半導體封裝件堆疊成 單一半導體裝置，用以增加的電性功能，並能節省基板 上的使用空間，而具有更精密的配置。此外，半導體封 裝堆疊結構還可縮短封裝結構之間的線路長度，以縮短 訊號延遲與存取時間。基於成本考量，相較環形電路間 隔板或是在基板中央設有容晶開孔，上下堆疊之半導體 封裝件之間係以間隔銲球達到電性連接，能具有更低的 封裝成本。 如第1圖所示，一種習知半導體封裝堆疊結構1〇〇 係主要包含一第一半導體封裝件11〇、一第二半導體基 裝件120以及複數個間隔銲球13〇。該第一半導體封身 件110係包含一第一基板lu、一設於該第一基板" 上之第-晶月112,並且藉由打線電性連接該第一晶, 112與該第一基板⑴。該第二半導體封裝件⑶係包含 一第二基板121、一設於該第二基板121上之第二晶片 122,並且藉由打線電性連接該第二晶片122與該第二基 201121013 板12丨。該些間隔銲球13〇係設於該第一基板iu之周 邊與該第二基m之周邊之間，以電性連接該第一半 導體封裝# m與該第二半導體封裝件12〇，並以機械 固定該第一半導體封裝# 11〇與該第二半導體封裝件 120。在POP產品運算作動時’該第—基板⑴與該第 二基板121的翹曲度不相同 在焊接界面的斷裂。 常造成該些間隔銲球1 3 0 因此，習知半導體封裝堆疊結構僅是以間隔辉球作為 上、下封裝件電性及機械性之連接材，由於運算或作動 時不同高度之半導體封裝件通常會遭遇溫度變化而具有 不同的基㈣曲程度’故會造成半導體封裝堆疊結構的 結構破壞與間隔銲球的斷裂，甚至導致電性連接失敗。 【發明内容】 為了解決上述之問題，本發明之主要目的係在於一種 以垂直銲柱機械補強之半導體封裝堆疊結構，在經過迴 銲之後會形成貫穿上下封裝件的垂直銲柱，提供額外的 應力抵抗，以使在兩半導體封裝件周邊之間隔銲球不因 基板趣曲而斷裂》 本發明之次一目的係在於提供一種以垂直銲柱機械 補強之半導體封裝堆疊結構，能在一次既有的迴銲步驟 中達到補強整體結構強度之功效，以減少p〇p補強材料 的設置成本。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種以垂直銲柱機械補強之半 201121013 導體封裝堆疊結構，主要包含一第一半導體封裝件、一 第二半導體封裝件、複數個間隔銲球以及複數個垂直銲 柱該第_導體封裝件係包含一第-基板、-設於該 第一基板上之第一晶片，荈第一基板係具有複數個第一 貫孔。該第二半導體封裝件係包含一第二基板、一設於 該第一基板上之第二晶片，該第二基板係具有複數個第 二貫孔，並且該第一半導體封裝件係設置於該第二半導 體封裝件之上’以使該些第一貫孔對準該些第二貫孔。 該些間隔銲球係設於該第—基板之周邊與該第二基板之 周邊之間’以電性連接該第__半導體封裝件與該第二半 導體封裝件。該些垂直銲柱係貫穿該些第-貫孔與該些 第貫孔該些垂直銲柱之單位體積係大於該些間隔銲 球之單位體積，ϋ且該些垂直銲柱之水平向直徑係大於 該些第-貫孔之孔徑亦大於該些第三貫孔之孔徑該些 垂直銲柱之上下兩端分別突出於該第一基板之上表面與 該第二基板之下表面，以機械固定該第一基板與該第二 基板。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述之以垂直銲柱機械補強之半導體封裝堆疊結 構中，該些垂直銲柱係可為無電性傳遞作用之結構補強 體。 在前述之以垂直銲柱機械補強之半導體封裝堆疊結 構中，該些垂直銲柱係可具有大於該些間隔銲球之單位 201121013 結合強度。 在刖述之以垂直銲柱機械補強之半導體封裝堆疊結 構中，每-垂直銲柱係可由H结合在對應第一貫孔 之第-銲塊與一預先結合在對應第二貫孔之第二銲塊迴 銲溶合而成。 在前述之以垂直銲柱機械補強之半導體封敦堆疊社 構中’每—垂直銲柱係可由—銲㈣及在對應第-貫孔 與第二貫孔内之銲料迴銲熔合而成。 在前述之以垂直銲柱機械補強之半導體封裝堆疊結 構中’該些•垂直鲜柱係可位於該第二晶片與該些間隔鲜 球之間，且更鄰靠該些間隔銲球。 在前述之以垂直銲柱機械補強之半導體封裝堆疊結 構中，該第一基板係可具有一位在該些第一貫孔内第一 電鍍層、一第一上連接墊與一第一下連接墊，其中該第 一上連接塾與該第一下連接墊係上下連接該第一電鍍 層，用以控制該些垂直銲柱在該第一基板與該第二基板 之間的單位體積不大於該些間隔銲球之單位體積。 在前述之以垂直銲柱機械補強之半導體封裝堆疊結 構中，該第一上連接墊係可大於該第一下連接墊。 在前述之以垂直銲柱機械補強之半導體封裝堆叠結 構中’該第一半導體封裝件可更包含一第一封膠體，以 在'封該第一晶片’並且該第二晶片係可藉由複數個第二 銲線電性連接至該第二基板，並以一第二封膠體密封該 第二晶片'該些第二銲線，但不覆蓋至該第二基板之周 201121013 邊。 在前述之以垂直銲柱機械補強之半導體封裝堆疊結 構中’該第一基板之一下表面係可貼附接觸該第二封膠 體。 由以上技術方案可以看出，本發明之以垂直銲柱機械 補強之半導體封裝堆疊結構，有以下優點與功效： 一、 可藉由第一基板、第二基板與垂直銲柱之特定組合 籲 關係作為其中一技術手段，在經過迴銲之後會形成 貫穿上下封裝件的垂直銲柱，以機械固定第一基板 與第二基板，並提供額外的應力抵抗，以使在兩半 導體封裝件周邊之間隔銲球不因基板翹曲而斷裂。 二、 可藉由間隔銲球與垂直銲柱之特定組合關係作為其 中技術手段’由於垂直銲柱之上下端分別突出於 第基板之上表面與第二基板之下表面，並且垂直 銲柱具有大於間隔銲球之單位結合強度，能在一次 • 既有的迴鲜步驟中達到補強整體結構強度之功效， 以減少POP補強材料的設置成本。 【實施方式】 以下將配合所附圖示詳細說明本發明之實施例，然應 注意的是，該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基太Λσ 1» ^ 尽莱構或實施方法，故僅顯示與本案 有關之元件與組合關係，阁 圖中所顯不之元件並非以實際 實施之數目、形狀、尺+似松 寸做4比例繪製，某些尺寸比例 與其他相關尺寸比例或已隹 又匕誇張或疋簡化處理，以提供更 201121013 清楚的描述。 選置性之設計 尺寸比例為一 為複雜。 種 實際實施之數目、形狀及 ，詳細之元件佈局可能更 依據本發明之第一具體實施例，一種以垂直銲柱機械 補強之半導體封裝堆疊結構舉例說明於第2圖之截面： 意圖與第3圖之上視示意圖。該以垂直銲柱機械補強之 半導體封裝堆疊結構200係主要包含一第—半導體封裝 件210、-第二半導體封裝件22()、複數個間隔銲球㈣It has become increasingly common in the use of many electronic devices. The semiconductor package stack structure can be formed by stacking two or more semiconductor packages into a single semiconductor device for added electrical functions, and can save space on the substrate, and has a more precise configuration. In addition, the semiconductor package stack structure shortens the line length between package structures to reduce signal delay and access time. Based on the cost considerations, compared with the annular circuit board or the center of the substrate, the semiconductor package is stacked with the solder balls to achieve electrical connection, which can lower the package cost. As shown in FIG. 1, a conventional semiconductor package stack structure 1 mainly includes a first semiconductor package 11A, a second semiconductor package 120, and a plurality of spacer solder balls 13A. The first semiconductor body 110 includes a first substrate lu, a first crystal moon 112 disposed on the first substrate, and electrically connected to the first crystal 112, and the first Substrate (1). The second semiconductor package (3) includes a second substrate 121, a second wafer 122 disposed on the second substrate 121, and electrically connected to the second wafer 122 and the second substrate 201121013 board 12 by wire bonding. Hey. The spacer solder balls 13 are disposed between the periphery of the first substrate iu and the periphery of the second substrate m to electrically connect the first semiconductor package #m and the second semiconductor package 12〇, and The first semiconductor package #11〇 and the second semiconductor package 120 are mechanically fixed. When the POP product is operated, the warpage of the first substrate (1) and the second substrate 121 is different at the solder interface. Often, the spacer solder balls 1 3 0 are formed. Therefore, the conventional semiconductor package stack structure is only a spacer ball as an electrical and mechanical connecting material of the upper and lower packages, and different heights of the semiconductor package due to operation or actuation. Usually, it will encounter temperature changes and have different base (four) curvature degrees, which will cause structural damage of the semiconductor package stack structure and breakage of the spacer solder balls, and even lead to electrical connection failure. SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide a semiconductor package stack structure that is mechanically reinforced by a vertical soldering post. After reflowing, a vertical soldering post is formed through the upper and lower packages to provide additional stress. Resisting so that the solder balls around the periphery of the two semiconductor packages are not broken by the substrate. The second object of the present invention is to provide a semiconductor package stack structure that is mechanically reinforced by vertical solder columns, which can be used at one time. The effect of reinforcing the overall structural strength is achieved in the reflow step to reduce the installation cost of the p〇p reinforcing material. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a semi-201121013 conductor package stack structure which is mechanically reinforced by a vertical soldering column, and mainly comprises a first semiconductor package, a second semiconductor package, a plurality of spacer solder balls and a plurality of vertical solder columns. The _th conductor package The device comprises a first substrate, a first wafer disposed on the first substrate, and the first substrate has a plurality of first through holes. The second semiconductor package includes a second substrate, a second wafer disposed on the first substrate, the second substrate has a plurality of second through holes, and the first semiconductor package is disposed on the second semiconductor package [on the second semiconductor package] to align the first through holes with the second through holes. The spacer balls are disposed between the periphery of the first substrate and the periphery of the second substrate to electrically connect the first semiconductor package and the second semiconductor package. The vertical soldering columns extend through the first through holes and the through holes, and the unit volume of the vertical soldering columns is larger than the unit volume of the spaced solder balls, and the horizontal diameters of the vertical soldering columns are The apertures larger than the first through holes are larger than the apertures of the third through holes. The upper and lower ends of the vertical solder columns respectively protrude from the upper surface of the first substrate and the lower surface of the second substrate to be mechanically fixed. The first substrate and the second substrate. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing semiconductor package stack structure in which the vertical pillars are mechanically reinforced, the vertical pillars may be structural reinforcements having no electrical transfer effect. In the foregoing semiconductor package stack structure in which the vertical pillars are mechanically reinforced, the vertical pillars may have a bonding strength greater than the unit of the spacer balls 201121013. In the semiconductor package stack structure in which the vertical soldering column is mechanically reinforced, each of the vertical soldering posts may be combined with a first solder bump corresponding to the first through hole and a second combined with a second through hole corresponding to the first through hole. The solder bumps are reflowed together. In the above-mentioned semiconductor sealing stacking structure in which the vertical welding column is mechanically reinforced, the 'every-vertical welding column can be fused by the welding (four) and the solder reflow in the corresponding first through hole and the second through hole. In the foregoing semiconductor package stack structure in which the vertical pillars are mechanically reinforced, the vertical vertical pillars may be located between the second wafer and the spaced spacer balls, and further adjacent to the spaced solder balls. In the foregoing semiconductor package stack structure in which the vertical pillar is mechanically reinforced, the first substrate may have a first plating layer, a first upper connection pad and a first lower connection in the first through holes. a pad, wherein the first upper connecting layer and the first lower connecting pad are connected to the first plating layer to control the unit volume of the vertical soldering columns between the first substrate and the second substrate is not more than The unit volume of the spacer balls. In the foregoing semiconductor package stack structure in which the vertical pillar is mechanically reinforced, the first upper connection pad may be larger than the first lower connection pad. In the foregoing semiconductor package stack structure in which the vertical pillar is mechanically reinforced, the first semiconductor package may further include a first encapsulant to 'enclose the first wafer' and the second wafer system may be plural The second bonding wires are electrically connected to the second substrate, and the second bonding wires of the second wafer are sealed by a second sealing body, but are not covered to the side of the second substrate. In the foregoing semiconductor package stack structure in which the vertical pillar is mechanically reinforced, the lower surface of one of the first substrates can be attached to the second sealant. It can be seen from the above technical solution that the semiconductor package stack structure with mechanical reinforcement of the vertical solder column has the following advantages and effects: 1. The specific combination of the first substrate, the second substrate and the vertical solder column can be called. As one of the technical means, after the reflow, a vertical soldering post is formed through the upper and lower packages to mechanically fix the first substrate and the second substrate, and provide additional stress resistance so as to be spaced around the periphery of the two semiconductor packages. The solder balls are not broken due to warpage of the substrate. Second, the specific combination relationship between the gap solder ball and the vertical solder column can be used as a technical means' because the upper end of the vertical solder column protrudes from the upper surface of the substrate and the lower surface of the second substrate, respectively, and the vertical solder column has greater than The unit bonding strength of the spacer balls can achieve the effect of reinforcing the overall structural strength in one and the existing freshening steps to reduce the installation cost of the POP reinforcing material. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. According to the structure or implementation method, only the components and combinations related to the case are displayed. The components shown in the map are not drawn in the actual number, shape, scale, and scale. Proportion to other related sizes may have been exaggerated or simplified to provide a more clear description of 201121013. Optional design The size ratio is one for complexity. The number, shape, and detailed component layout of the actual implementation may be further in accordance with the first embodiment of the present invention, a semiconductor package stack structure mechanically reinforced by vertical solder columns is illustrated in the cross section of FIG. 2: Intention and 3rd The diagram above is a schematic view. The semiconductor package stack structure 200 mechanically reinforced by vertical solder columns mainly comprises a first semiconductor package 210, a second semiconductor package 22 (), and a plurality of spacer solder balls (4).
以及複數個垂直銲柱240。該第一半導體封裝件21〇係 包含一第一基板211、一設於該第一基板211上之第一 晶片212，該第一基板211係具有複數個第—貫孔。 在本實施例中，該第一基板211之一下表面2ub之周邊 係具有複數個第一銲墊，以供該些間隔銲球23〇之上接 合。在本實施例中，該第一晶片212係可藉由複數個打 線方式形成之第一銲線217電性連接至該第一基板 211’並以一第一封膠體218密封該第一晶片212、該些And a plurality of vertical solder columns 240. The first semiconductor package 21 includes a first substrate 211 and a first wafer 212 disposed on the first substrate 211. The first substrate 211 has a plurality of first through holes. In this embodiment, the periphery of the lower surface 2ub of the first substrate 211 has a plurality of first pads for bonding over the spacer balls 23A. In the embodiment, the first wafer 212 is electrically connected to the first substrate 211 ′ by a plurality of wire bonding methods, and the first wafer 212 is sealed by a first sealing body 218 . Some of these
第一銲線217’但不覆蓋至該第一基板211之周邊。在 不同實施例中，當該第一半導體封裝件210為整體pop 結構之最上層封裝件時，該第一封膠體218可全面覆蓋 該第一基板211之上表面211A。詳細而言，該第一基板 211係可具有一位在該些第一貫孔213内第一電鍍層 214、一第一上連接塾215與一第一下連接塾216，其中 該第一上連接塾215與該第一下連接塑* 216係上下連接 該第一電鍍層214，用以控制該些垂直銲柱240在該第 一基板211與該第二基板221之間的單位體積’以防止 201121013 該些垂直銲柱240在迴銲時產生外擴之現象，並使該些 垂直銲柱24 0於該第一基板211與該第二基板221之間 的部位呈柱狀。 該第一半導體封裝件220係包含一第二基板221、一 設於該第二基板221上之第二晶片222,該第二基板221 係具有複數個第二貫孔223’並且該第一半導體封裝件 210係設置於該第二半導體封衆件220之上，以使該些 第一貫孔2 1 3對準該些第二貫孔223。在本實施例中， 該第二晶片222係可藉由複數個第二銲線227電性連接 至該第二基板221，並以一第二封膠體228密封該第二 晶片222、該些第二銲線227，但不覆蓋至該第二基板 221之周邊。在本實施例中’該第二基板221之一上表 面22 1A之周邊係具有複數個不被該第二封膠體228覆 蓋之第二銲墊，以供該些間隔銲球230之下接合。並於 該第二基板221之一下表面221B設有複數個外接端子 φ 250，以作為對外電性連接之用。該第一基板211之該下 表面211B係可貼附接觸該第二封膠體228，以避免在迴 銲時該第一基板211與該第二基板221之間的間隙改 變。此外，該第二基板221係可具有一位在該些第二貫 孔223内第二電鍍層224、一第二上連接墊225與一第 二下連接墊226，其中該第二電鍍層224、該第二上連接 墊225以及該第二下連接墊226可具有與上述之該第一 電鍍層214、該第一上連接墊215以及該第一下連接墊 216具有相同之焊料量調整與形狀控制該些垂直銲柱 201121013 240之作用。詳細而言，該第一基板211與該第二基板 221 係可為一印刷電路板（print eircuit b〇ar(j，PCB)， 作為安裝或連接時的主要支撐體。該第一晶片212與該 第二晶片222係可為以半導體作基層之積體電路元件， 例如記憶體、邏輯元件以及特殊應用積體電路（ASIC)， 而具有相同或不同之電性功能。 睛參閱第2及3圖所示，該些間隔銲球230係設於該 鲁 第一基板211之周邊與該第二基板221之周邊之間，以 電性連接該第一半導體封裝件21〇與該第二半導體封裝 件220。更具體地’該些間隔銲球230係接合於該些第 ~塾與該些第一銲墊之間（如第2圖所示），除了能提 供電性連接之用，亦可提供該第一半導體封裝件2 1〇與 該第二半導體封裝件22〇最基本的機械連接關係。 該些垂直銲柱240係貫穿該些第一貫孔213與該些第 二貫孔223 ’該些垂直銲柱240之單位體積係大於該些 • 間隔銲球23〇之單位體積，並且該些垂直銲柱240之水 平向直徑係大於該些第一貫孔213之孔徑亦大於該些第 二貫孔223之孔徑。該些垂直銲柱240之上下兩端分別 突出於該第一基板21丨之上表面211A與該第二基板221 之下表面22 1B’以機械固定該第一基板211與該第二基 板221。在本實施例中，該些垂直銲柱24〇係可為無電 性傳遞作用之結構補強體，僅作為機械性連接該第一基 板211與該第二基板221之作用。更進一步地，該些垂 直銲柱240係可具有大於該些間隔銲球230之單位結合 [s 3 10 201121013 強度’故能提供更高於該些間隔銲球230之結構補強作 用，以提升整體結構的機械強度。具體而言，如第2與 3圖所示’該些垂直銲柱240係可位於該第二晶片222 與該些間隔銲球230之間，且更鄰靠該些間隔銲球23〇。 因此，更可防止整體結構在遭遇溫度變化時，該第一半 導體封裝件210與該第二半導體封裝件220不同的趣曲 方向所造成的破壞。在一較佳實施例中，每一垂直辉柱 秦 240係可由一預先結合在對應第一貫孔213之第—銲塊 與一預先結合在對應第二貫孔223之第二銲塊迴銲溶合 而成，詳述如後。 本發明另揭示上述以垂直銲柱機械補強之半導體封 裝堆疊結構之形成方法舉例說明於第4A至4C圖之元件 截面示意圖。 首先，如第4A圖所示，提供一第一半導體封裝件 210’其係包含一第一基板211、一設於該第一基板211 Φ 上之第一晶片212，該第一基板211係具有複數個第一 貫孔213。具體而言，該第一基板211之一下表面2ιΐβ 係可具有複數個第一銲墊，並於該些第一銲墊上接合有 複數個間隔銲球23 0。在本實施例中，該些第一貫孔2丄3 係可預先結合有複數個第一銲塊24 0A。 接著’如第4B圖所示’提供一第二半導體封裝件 220 ’其係包含一第二基板221、一設於該第二基板221 上之第二晶片222，該第二基板221係具有複數個第二 貫孔223。具體而言，該第二基板之一上表面22ia 201121013 係可八有複數個第二銲墊，並於該第二基板丨之一下 表面22 1B形成有複數個外接端子乃卜在本實施例中， 該些第一貝孔223係可預先結合有複數個第二銲塊 240B。 之後，如第4C圖所示，設置該第一半導體封裝件21〇 於該第二半導體封裝件⑽之上，並使該些第-貫孔213 對準於該些第二貫孔223。更進—步地，該些第一鲜塊 240A係同時對準於對應之該些第二銲塊⑽並且該 ，間隔銲$ 23〇對準於對應之該些第二銲塾。詳細而 言，該些第一銲塊24〇A與該些第二銲塊240B之間係可 塗佈一助焊劑或低溫焊膏，在放置該第一半導體封裝件 21〇便能使助焊劑（或低溫焊膏）接觸該些第一銲塊24〇a 與該些第二銲塊24GB，以利該些第—鲜塊24GA與該些 第二銲塊240B於後續迴銲製程中相互熔合。 最後，以迴銲方式接合該第一半導體封裳件21〇與該 第二半導體封裝件220’以使該第-半導體封裝件21〇 與該第二半導體封裝件22〇達成機械性 體而言，在迴鲜之後’紅U塊謝與=之= 些第一銲塊240B會相互熔合，而結合成為複數個貫穿 該第一半導體封裝件21G與該第二半導體封裝件22〇之 垂直銲柱240，並使得該些間隔銲球23〇接合至該第二 基板221之該些第二銲墊。此時，即可完成本發明之： 垂直銲柱機械補強之半導體封裝堆疊結構200(如第2 所示）。The first bonding wire 217' does not cover the periphery of the first substrate 211. In a different embodiment, when the first semiconductor package 210 is the uppermost package of the bulk pop structure, the first encapsulant 218 can completely cover the upper surface 211A of the first substrate 211. In detail, the first substrate 211 may have a first plating layer 214, a first upper connecting port 215 and a first lower connecting port 216 in the first through holes 213, wherein the first upper plate 216 The first plating layer 214 is connected to the first lower bonding plastic 216 to connect the first plating layer 214 to the unit volume ' between the first substrate 211 and the second substrate 221 The phenomenon that the vertical soldering posts 240 are expanded during reflowing is prevented in 201121013, and the portions of the vertical soldering posts 240 between the first substrate 211 and the second substrate 221 are columnar. The first semiconductor package 220 includes a second substrate 221, a second wafer 222 disposed on the second substrate 221, the second substrate 221 having a plurality of second vias 223' and the first semiconductor The package 210 is disposed on the second semiconductor package 220 to align the first through holes 211 with the second through holes 223. In this embodiment, the second wafer 222 is electrically connected to the second substrate 221 by a plurality of second bonding wires 227, and the second wafer 222 is sealed by a second sealing body 228. The second bonding wire 227 does not cover the periphery of the second substrate 221. In the present embodiment, the periphery of the surface 22 1A of one of the second substrates 221 has a plurality of second pads that are not covered by the second encapsulant 228 for bonding the spacer balls 230 below. A plurality of external terminals φ 250 are provided on the lower surface 221B of the second substrate 221 for external electrical connection. The lower surface 211B of the first substrate 211 can be attached to the second encapsulant 228 to avoid a change in the gap between the first substrate 211 and the second substrate 221 during reflow. In addition, the second substrate 221 may have a second plating layer 224, a second upper connection pad 225 and a second lower connection pad 226 in the second through holes 223, wherein the second plating layer 224 The second upper connection pad 225 and the second lower connection pad 226 may have the same solder amount adjustment as the first plating layer 214, the first upper connection pad 215, and the first lower connection pad 216 described above. The shape controls the role of the vertical posts 201121013 240. In detail, the first substrate 211 and the second substrate 221 may be a printed circuit board (print eircuit b〇ar (j, PCB) as a main support when mounting or connecting. The first wafer 212 and The second wafer 222 can be an integrated circuit component such as a memory, a logic component, and an application specific integrated circuit (ASIC) having a semiconductor as a base layer, and has the same or different electrical functions. As shown, the spacer solder balls 230 are disposed between the periphery of the first substrate 211 and the periphery of the second substrate 221 to electrically connect the first semiconductor package 21 and the second semiconductor package. a member 220. More specifically, the spacer solder balls 230 are bonded between the first pads and the first pads (as shown in FIG. 2), in addition to providing electrical connections, Providing a most basic mechanical connection relationship between the first semiconductor package 2 1 and the second semiconductor package 22 . The vertical solder pillars 240 extend through the first through holes 213 and the second through holes 223 ′ The unit volume of the vertical columns 240 is greater than the spacing welds The ball has a unit volume of 23 ,, and the horizontal diameter of the vertical columns 240 is larger than the apertures of the first through holes 213 and larger than the holes of the second through holes 223. The vertical columns 240 are upper and lower. The end protrudes from the upper surface 211A of the first substrate 21 and the lower surface 22 1B' of the second substrate 221 to mechanically fix the first substrate 211 and the second substrate 221. In this embodiment, the vertical The soldering post 24 can be a structure-reinforcing body that is electrically non-conductive, and functions only as a mechanical connection between the first substrate 211 and the second substrate 221. Further, the vertical soldering posts 240 can have a larger The units of the spacer balls 230 combined with [s 3 10 201121013 strength] can provide structural reinforcement higher than the spacer balls 230 to improve the mechanical strength of the overall structure. Specifically, as shown in Figures 2 and 3. The vertical soldering posts 240 can be located between the second wafer 222 and the spacer solder balls 230, and further adjacent to the spacer solder balls 23 〇. Therefore, the overall structure can be prevented from encountering temperature changes. The first semiconductor package 210 and The damage caused by the different interesting directions of the second semiconductor package 220. In a preferred embodiment, each of the vertical pillars 240 can be combined with a first solder bump and a solder joint pre-bonded to the first through hole 213. The second solder bump corresponding to the second through hole 223 is pre-bonded and fused together, as described in detail later. The present invention further discloses that the method for forming the semiconductor package stack structure mechanically reinforced by the vertical soldering column is illustrated in FIG. 4A. FIG. 4A shows a first semiconductor package 210' including a first substrate 211 and a first wafer 212 disposed on the first substrate 211 Φ. The first substrate 211 has a plurality of first through holes 213. Specifically, the lower surface of the first substrate 211 may have a plurality of first pads, and a plurality of spacer balls 230 are bonded to the first pads. In this embodiment, the first through holes 2丄3 may be combined with a plurality of first solder bumps 240A in advance. Then, as shown in FIG. 4B, a second semiconductor package 220 is provided, which includes a second substrate 221 and a second wafer 222 disposed on the second substrate 221, the second substrate 221 having a plurality of Second through holes 223. Specifically, one of the upper surfaces 22ia 201121013 of the second substrate may have a plurality of second pads, and a plurality of external terminals are formed on the lower surface 22 1B of the second substrate 在 in the embodiment. The first plurality of holes 223 may be combined with a plurality of second solder bumps 240B in advance. Then, as shown in FIG. 4C, the first semiconductor package 21 is disposed on the second semiconductor package (10), and the first through holes 213 are aligned with the second through holes 223. Further, the first fresh blocks 240A are simultaneously aligned with the corresponding second solder bumps (10) and the spacer welds $23〇 are aligned with the corresponding second solder bumps. In detail, a flux or a low-temperature solder paste may be applied between the first solder bumps 24A and the second solder bumps 240B, and the flux may be applied after the first semiconductor package 21 is placed. Or the low temperature solder paste) contacts the first solder bumps 24A and the second solder bumps 24GB, so that the first fresh bumps 24GA and the second solder bumps 240B are fused to each other in a subsequent reflow process. Finally, the first semiconductor package 21 〇 and the second semiconductor package 220 ′ are joined in a reflow manner to achieve a mechanical body between the first semiconductor package 21 〇 and the second semiconductor package 22 〇 After the re-freshing, the red bumps and the = solder bumps 240B are fused to each other, and combined into a plurality of vertical solder columns penetrating the first semiconductor package 21G and the second semiconductor package 22 240, and the spacer solder balls 23 are bonded to the second pads of the second substrate 221 . At this point, the present invention can be completed: a vertical solder column mechanically reinforced semiconductor package stack structure 200 (shown in Figure 2).
12 201121013 在本發明中，利用第一基板、第二基板與垂直銲柱之 -特定=合關係作為其中-技術手段，在經過迴銲之後會 形成貝穿上下封裝件的垂直銲柱，以機械固定該第一基 板211與該第二基板221，並提供額外的應力抵抗該 兩半導體封裝件210肖22〇穩固結合。在該兩半導體封 裝件210與22Q周邊之間隔銲球23()不因基板趣曲而斷 裂。更具體而冑’這是由於該些垂直銲柱24〇之上下兩 φ端分別突出於該第一基板211之上表面211八與該第二基 板221之下表面221B，以機械固定該第一基板2ιι與該 第二基板221 ^即使選用相同或相似的焊接材料，該些 垂直銲柱240仍具有大於該些間隔銲球23〇之單位結合 強度，能在一次既有的迴銲步驟中達到補強整體結構強 度之功效’以減少補強材料的設置成本。 依據本發明之另一變化實施例，上述以垂直銲柱機械 補強之半導體封裝堆疊結構之另一形成方法舉例說明於 # 第5A與5B圖之元件截面示意圖。同第2圖之該半導體 封裝堆疊結構主要包含一第一半導體封裝件21〇、一第 二半導體封裝件220、複數個間隔銲球23〇以及複數個 垂直銲柱240。在本實施例中，每一垂直銲柱240係可 由一銲球240C以及在對應第一貫孔213與第二貫孔223 内之銲料240A’、240B’迴銲熔合而成。其中與第一實施 例相同的主要元件將以相同符號標示，不再詳予贅述。 請參閱第5A圖所示’該第一半導體封裝件21〇係包 含一第一基板211、一設於該第一基板211上之第一晶 13 201121013 片212 ’該第一基板211係具有複數個第一貫孔213。該 第二半導體封裝件220係包含一第二基板221、一設於 該第二基板221上之第二晶片222，該第二基板221係 具有複數個第二貫孔223。在本實施例中，該些第一貫 孔213與該些第二貫孔223内係分別預先填滿銲料24〇A， 與鲜料24OB’。更進一步地，該些第二貫孔223之銲料 24〇B’上係可設置該些銲球240C，該些銲球240C係可為 自由球而未直接焊接於銲料24〇B’上，而在本實施例中 在該些間隔銲球230在迴銲之前亦為自由球，可與該些 銲球240C同時放置在該第二半導體封裝件22〇。具體而 言，在迴銲之前的植球放置步驟中，該些間隔銲球23〇 與該些銲球240C藉由預先形成之助焊劑或少量印刷銲 料、沾著於該第二基板221之上表面221A。 請參閱第5B圖所示，將該第一半導體封裝件21〇係 設置於該第二半導體封裝件22〇之上，以使該些第一貫 孔213對準該些第二貫孔223。在封裝堆疊之後與迴銲 之前，該些銲球240C係同時接觸在該些第一貫孔213 内之銲料240A’與在該些第二貫孔223内之銲料24〇b，， 以利後續迴銲製程之進行。在迴銲步驟中，該些鲜球 240C與在對應之該些第一貫孔213之銲料24〇a，與該些 第二貫孔223内之銲料240B’會迴銲熔合，之後可形成 為該些垂直銲柱240(如第2圖所示），在迴銲步驟之同 時，該些間隔銲球230亦上下接合該第一基板211與該 第二基板221。 14 20112101312 201121013 In the present invention, the first substrate, the second substrate and the vertical soldering column are used as a technical means, and after the reflow, a vertical soldering post of the upper and lower packages is formed to be mechanically The first substrate 211 and the second substrate 221 are fixed and provide additional stress against the two semiconductor packages 210. The gap solder balls 23 () at the periphery of the two semiconductor packages 210 and 22Q are not broken by the substrate. More specifically, this is because the upper and lower φ ends of the vertical soldering posts 24 突出 protrude from the upper surface 211 of the first substrate 211 and the lower surface 221B of the second substrate 221, respectively, to mechanically fix the first The substrate 2 ι and the second substrate 221 ^ even if the same or similar solder material is selected, the vertical solder pillars 240 have a unit bonding strength greater than the spacing of the solder balls 23 , which can be achieved in an existing reflow step Reinforce the effectiveness of the overall structural strength to reduce the cost of setting up the reinforcing material. According to another variant embodiment of the invention, another method of forming the semiconductor package stack structure mechanically reinforced by vertical solder columns is illustrated in the cross-sectional view of the elements of Figures 5A and 5B. The semiconductor package stack structure of FIG. 2 mainly includes a first semiconductor package 21A, a second semiconductor package 220, a plurality of spacer solder balls 23A, and a plurality of vertical solder columns 240. In this embodiment, each of the vertical soldering posts 240 is formed by a solder ball 240C and a solder reflow of the solders 240A', 240B' corresponding to the first through holes 213 and the second through holes 223. The same elements as those in the first embodiment will be designated by the same reference numerals and will not be described in detail. Referring to FIG. 5A, the first semiconductor package 21 includes a first substrate 211 and a first crystal 13 201121013 disposed on the first substrate 211. The first substrate 211 has a plurality of First through holes 213. The second semiconductor package 220 includes a second substrate 221 and a second wafer 222 disposed on the second substrate 221. The second substrate 221 has a plurality of second through holes 223. In this embodiment, the first through holes 213 and the second through holes 223 are respectively filled with solder 24A and fresh material 24OB'. Further, the solder balls 240C may be disposed on the solder 24B' of the second through holes 223, and the solder balls 240C may be free balls and not directly soldered to the solder 24B'. In the embodiment, the spacer solder balls 230 are also free balls before reflow, and can be placed in the second semiconductor package 22 at the same time as the solder balls 240C. Specifically, in the ball placement step before the reflow, the spacer balls 23 and the solder balls 240C are adhered to the second substrate 221 by a pre-formed flux or a small amount of printed solder. Surface 221A. As shown in FIG. 5B, the first semiconductor package 21 is disposed on the second semiconductor package 22A such that the first through holes 213 are aligned with the second through holes 223. After the package is stacked and reflowed, the solder balls 240C simultaneously contact the solder 240A' in the first through holes 213 and the solder 24〇b in the second through holes 223, so as to facilitate subsequent The reflow process is carried out. In the reflowing step, the fresh balls 240C and the solder 24〇a corresponding to the first through holes 213 and the solder 240B' in the second through holes 223 are reflowed and fused, and then formed into The vertical soldering posts 240 (as shown in FIG. 2) are joined to the first substrate 211 and the second substrate 221 by the spacer balls 230 at the same time as the reflow process. 14 201121013
240。其中與第一實施例相同的主要元 依據本發明之第二具體實施例，另 械補強之半導體封裝堆疊結構舉例說 210、一第二半導體封 以及複數個垂直銲柱 元件將以相同符號標 示，不再詳予贅述。 詳細而言，該第一半導體封裝件21〇係包含一第一基 板 211、 片212 ，該第 一設於該第一基板211上之第一 一基板211係具有複數個第一貫孔213。該第二半導體 封裝件220係包含一第二基板221、一設於該第二基板 22丨上之第二晶片222’該第二基板221係具有複數個第 一貫孔223。具體而言，該第一晶片212與該第二晶片 222係分別覆晶接合於該第一基板211與該第二基板 221。更進一步地，該第一晶片212與該第一基板211之 % 間係可填入一例如底膠之第一封膠體318，並於該第二 晶片2 2 2與該第二基板2 21之間可填入一例如底膠之第 二封膠體3 28。在本實施例中’該第一基板211係可具 有一位在該些第一貫孔213内第一電鍍層314、一第一 上連接墊315與一第一下連接墊316，其中該第一上連 接墊315與該第一下連接墊316係上下連接該第一電鍍 層314，用以控制該些垂直銲柱240在該第一基板211 與該第二基板221之間的單位體積不大於該些間隔銲球 230之單位體積。此外，該第一上連接墊315係可大於 15 201121013 該第一下連接墊316。更進一步地，該第二基板221係 同樣可具有一位在該些第二貫孔223内第二電鑛層 3 24、一第二上連接墊3 25與一第二下連接墊326，並藉 由該第二上連接墊3 25與該第二下連接墊3 26 —同限制 該些垂直銲柱24 0於該第一基板211與該第二基板221 之間的單位體積。例如，可調整該第二下連接墊326係 可大於該第二上連接墊325，多餘銲料可突出地形成於240. The main element in the same manner as the first embodiment is in accordance with the second embodiment of the present invention. The mechanically-enhanced semiconductor package stack structure 210, a second semiconductor package, and a plurality of vertical pillar elements will be denoted by the same symbols. I will not go into details here. In detail, the first semiconductor package 21 includes a first substrate 211 and a sheet 212. The first substrate 211 disposed on the first substrate 211 has a plurality of first through holes 213. The second semiconductor package 220 includes a second substrate 221 and a second wafer 222' disposed on the second substrate 22, and the second substrate 221 has a plurality of first holes 223. Specifically, the first wafer 212 and the second wafer 222 are respectively flip-chip bonded to the first substrate 211 and the second substrate 221 . Further, the first wafer 212 and the first substrate 211 may be filled with a first encapsulant 318 such as a primer, and the second wafer 2 2 2 and the second substrate 2 21 A second encapsulant 3 28 such as a primer can be filled in between. In the present embodiment, the first substrate 211 may have a first plating layer 314, a first upper connection pad 315 and a first lower connection pad 316 in the first through holes 213. An upper connection pad 315 and the first lower connection pad 316 are connected to the first plating layer 314 to control the unit volume between the first substrate 211 and the second substrate 221 It is larger than the unit volume of the spacer solder balls 230. Additionally, the first upper connection pad 315 can be greater than 15 201121013 the first lower connection pad 316. Further, the second substrate 221 may have a second electric ore layer 324, a second upper connection pad 325 and a second lower connection pad 326 in the second through holes 223, and The second upper connection pad 325 and the second lower connection pad 3 26 together limit the unit volume between the first substrate 211 and the second substrate 221 . For example, the second lower connection pad 326 can be adjusted to be larger than the second upper connection pad 325, and excess solder can be formed prominently on the
該第二下連接墊326，以控制該些垂直銲柱240在該第 一基板211與該第二基板221之間的柱體形狀。 以上所述，僅是本發明的較佳實施例而已，並非對本 發：作任何形式上的限制，雖然本發明已以較佳實施例 ，路如上…:而並非用以限定本發明任何熟悉本項技 ，者在不脫離本發明之技術範圍内，所作的任何簡單 修改、等效性變化與修德 ,, 内。 興U飾，均仍屬於本發明的技術範圍 L圖式簡單說明】 第1圖：為習知玷—# .、、 以銲球連接之半導體封裝堆 構之截面示意圖。 第2圖：依據本發明之第 ^ ^ ^ ^ 具體實施例的一種以垂 枉機械補強之半 圖。 導體封裝堆疊結構之截面 第3圖：依據本發明之第 械補強之半導體封裝地：垂直銲 第4A至4C圖、裝隹且結構之上視示意I 圃依據本發明之第— ，、體實施例的以 16 201121013 銲柱機械補強之半導體封裝堆疊結構之元件截 面示意圖。 第5 A至5B圖：依據本發明之第一具體實施例的一種以 垂直銲柱機械補強之半導體封裝堆疊結構繪示 在另一變化例形成方法中之元件截面示意圖。 第6圖：依據本發明之第二具體實施例的一種以垂直銲 柱機械補強之半導體封裝堆疊結構之截面示意 圖。 【主要元件符號說明】 100半導體封裝堆疊結構 110第一半導體封裝件 111第一基板 112第一晶片 120第二半導體封裝件 121第二基板 122第二晶片 130間隔銲球 200以垂直銲柱機械補強之半導體封裝堆疊結構 210第一半導體封裝件 211第一基板 211A上表面 211B下表面 2 1 2第一晶片 2 1 3第一貫孔 214第一電鍍層 215第一上連接墊 216第一下連接墊 217第一銲線 218 第一封膠體 220第二半導體封裝件 221第二基板 221A上表面 221B下表面 222第二晶片 223第二貫孔 17 201121013 " 224第二電鍍層 225第二上連接墊 ' 226第二下連接墊 227第二銲線 228第二封膠體 230 間隔銲球 240垂直銲柱 240A第一銲塊 240B 第二銲塊 240A’銲料 240B’銲料 240C銲球 250外接端子 300以垂直銲柱機械補強之半導體封裝堆疊結構 ^ 314第一電鍍層 315第一上連接墊 316第一下連接墊 318 第一封膠體 324第二電鍍層 325第二上連接墊 326第二下連接墊 328 第二封膠體The second lower connection pad 326 controls the shape of the pillars between the first substrate 211 and the second substrate 221 of the vertical pillars 240. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been described in the preferred embodiments, the invention is not limited to the present invention. Any simple modifications, equivalent changes, and repairs made by those skilled in the art without departing from the scope of the invention. Xing U ornaments are still within the technical scope of the present invention. L is a brief description of the drawings. Fig. 1 is a schematic cross-sectional view of a semiconductor package stack connected by solder balls. Fig. 2 is a half elevational view of a mechanical reinforcement according to the first embodiment of the present invention. Cross section of conductor package stack structure Fig. 3: Semiconductor packaged ground according to the invention: vertical soldering 4A to 4C, mounting and top view of the structure I 圃 according to the invention - A cross-sectional view of a component of a semiconductor package stack structure that is mechanically reinforced by a 16 201121013 solder post. 5A to 5B are views showing a cross-sectional view of an element in another variation forming method in accordance with a semiconductor package stack structure mechanically reinforced by a vertical soldering post according to a first embodiment of the present invention. Figure 6 is a cross-sectional view showing a semiconductor package stack structure mechanically reinforced by a vertical solder column in accordance with a second embodiment of the present invention. [Main component symbol description] 100 semiconductor package stack structure 110 first semiconductor package 111 first substrate 112 first wafer 120 second semiconductor package 121 second substrate 122 second wafer 130 spacer solder ball 200 mechanical reinforcement with vertical solder columns Semiconductor package stack structure 210 first semiconductor package 211 first substrate 211A upper surface 211B lower surface 2 1 2 first wafer 2 1 3 first through hole 214 first plating layer 215 first upper connection pad 216 first lower connection Pad 217 first bonding wire 218 first colloid 220 second semiconductor package 221 second substrate 221A upper surface 221B lower surface 222 second wafer 223 second through hole 17 201121013 & 224 second plating layer 225 second upper connection Pad '226 second lower connection pad 227 second bonding wire 228 second encapsulant 230 spacer solder ball 240 vertical soldering post 240A first solder bump 240B second solder bump 240A 'solder 240B' solder 240C solder ball 250 external terminal 300 Vertical soldering rod mechanically reinforced semiconductor package stack structure 314 first plating layer 315 first upper connection pad 316 first lower connection pad 318 first gel 324 second plating layer 325 second upper connection pad 326 second lower connection pad 328 second sealant
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