200810049 九、發明說明： 【發明所屬之技術領域】 本發明係有！卜種晶片封裝結構，特別是—種可重新分 配（redistribution)之晶片封裝結構及其製法。 【先前技術】 立體式封裝目前大《兩财式，㈣是封壯躲(paekage 〇n Packages)以及封裝内封裝（Packageinpackage，pip) p〇i^ ，，典型的3D封裝，將兩_立封裝完成的封裝體以製程技術加 乂隹且巾ΡιΡ則是將-個單獨且未上錫球的封裝體藉由一個間隙壁 (spacer)疊至晶片上’再一起進行封膠的封裝。其中，p〇p藉由獨 立的兩個封裝艇封裝觸試後再以表_著方式疊合，可減少製程 風險，進而提高產品良率。 立第1八圖、帛1B®與第1C圖所示為習知p〇p製作之流程剖面示 思圖’如第1A圖與第1B圖所示，第一封裝體1〇〇與第二封裝體2〇〇 於其載板110與載板210下設置有複數個焊球⑽與蟬球23〇。封膠 體120與封膠體220分別設置於載才反11〇與載板21〇上，且封膠體12〇 與封膠體220内係分別具有晶片（圖上未示）包覆於其内。第一封裝 體100與第二封裝體2〇〇利用表面黏著技術將焊球13〇對準焊墊212 上下融接第一封裝體1〇〇與第二封裝體200。由於，焊球130與焊墊 212為不同材質，除了有準確對位外，材質間連接不良也是一問題。 另外’在加熱過程中，因不同材料間之熱膨脹係數不同所引起的翹曲 (Warpage)現象，連接不良更可能導致爆板(p〇pc⑽)現象。 【發明内容】 鑑於上述問題，本發明目的之一係提供一種堆疊式封裝 結構及其製法，封裝體與封裝體間利用焊球互相融接，可達 200810049 =極佳的連接效果並有效克服習知不同材料間連接不良之問 、去=明目的之一係提供一種晶堆疊式封裝結構及並事 疊“之之載板上下f、面設置焊球供封袭體堆 f1 ^ ν σ工困難度並解決加熱過程中因不同材料 3…、魏健不騎服的祕現线爆板财。 ’、 為了達到上述目的，本發明一實施例之一種堆 二：’包括··一第一封裝體’係具有一載板，其_‘球二 ===’·複^咖焊球，係設置於第,體之載板上表 第具有—載板，且第二封裝體係用以堆疊於 體上數轉輕置於她下絲，且第 、分卿—刪之紐蝴輔助輝球互 1置於偷卞衣體係、具有一載板，其中複數個焊球 面:Ϊ二二;：置複數個輔助焊球於第， 下具有—載板，其中複數個焊球設置於載板 了表面’以及利用-表面黏著程序，係將第二封裝體之載板^ = ;Γί:=二口裝體之載板上表面的輔助焊球互相對位融接，用以 將弟一封裝體堆疊於第一封裝體上。 【實施方式】 第2圖所示為根據本發 圖，此晶片封裝結構包括-第-封裝^^此構第一:;：：mf =且複f轉球2】設置於載㈣下表面。另，;裝二 匕括至y —晶片51設置於載板η卜本 載板11上密封此曰片51、w/ 且一封膠體41係設置於 于此曰曰片5卜減個輔助焊球31設置於第一封裝體1〇 6 200810049 =載板y上表面。一第二封裝體20用以堆疊於第一封裝體1〇上。 第—封衣體20具有一載板12且複數個焊球22設置於載板12下表 面另，第二封裝體20包括至少一晶片52設置於載板12上表面， 且一封膠體42係設置於載板12上密封此晶片仏其中，第二封裝體 2〇之载板12下表面的焊球22係分別與第一封裝體1〇之載板u上表 面的輔助焊球31互相對位堆疊。 :」啊不為根據本發明堆4式封裝結構另一實施例之剖面 不思圖，於本實施财，堆疊式封裝結射肋堆疊兩個社封裝體 =片封裝結構。請參照第3圖，獨於前述實施例，於本實施例中， 球32設置於第二封裝體2G之載板12上表面，且此晶 構更包括—第三封裝體3G用以堆疊於第二封裝體20上。第 ;:=30 ,有一載板13且複數個焊球23設置於載板13下表面。 健13^1衣體％包括複數個晶片，如晶片53與晶片54，設置於 Ϊΐ ίί二且—_體43係設置於載板13上密封晶片53與晶 二封f;20之體3〇之載板13下表面的焊球23係分別與第 、豆之载板12上表面的辅助焊球32互相對位堆疊。 接績上述說明，第4A圖、第4 發明堆疊式封裝結構製法邻八 :f C圖所不為根據本 示，首先，隸:仏本剖面示意圖。如第4A圖所 丁百先ki、一第一封裝體1〇， 載板η ’於載板u上表面設置至上體^具有: 體41用以密封此晶片 曰曰月51 6又置-封膠 面，同時並設置她她^ 個焊球21於載板11下表 «^10 11" 二封裝體20具有一載^ 了 、仏一第二封裝體20，此第 u52，<罢 ’於載板12上表面設置至少一曰 片52,故置一封膠體42用以密封此 置V日日 焊球22於載板12下表面。㈣ ^ 其中設置複數個 施例中，利用一表面黏著程 圖努第4B圖，於一實 的焊球22分別與第載板12下表面 扳1上表面的輔助焊球31互相 7 200810049 對位融接，用以將第二封 第2圖所示之晶片封襄結構。$於第一封裝體10上即可完成如 接續上述說明，請參照繁 辅助嬋球32於第二封裝體2 ; 中，設置複數個 =;第三封裝體3。，此第=二第載Π所示’ =上表面設置晶片53 —有=;於 以密封此晶片53與晶月54甘丄 置封知體43用 下表面H 4B H ^ 置複數辦球23於載板13 序，將第三封裝體30之载板u = —表面點著程 之載板！2上表面的辅助_ 32 t =㈣23分別與第二封裝體 3〇堆疊於第-封穿體二，互相對位融接，用以將第三封裝體 且、弟-封衣體20上即可完成如第3圖所示之晶片封裝結構。 根據上述，本發明之特徵係__材質之取 ^體Γ的堆疊接合與電性連接之用。因為相同材質相容性極ft :曾有連接不良之蘭產生，可解料知不·料的連制題，儘需 空制焊球之用量，即可維持封裝體與封裝體間的堆疊高度。 ^綜合上述，本發明之封裝體與封裝體間係利用焊球互相 喊接’可達到極佳的連接效果並有效克服習知不同材料間連 接不良之問題’藉由預先於封裝體之載板上下表面設置焊球 供封裝體堆疊連接之用，可減少加工困難度並解決加熱過程 中因不同材料間之瓣脹係數不同起馳曲現象或爆板現象。 以上所述之實施例僅係為說明本發明之技術思想及特 點，其目的在使熟習此項技藝之人士能夠瞭解本發明之内容 並據以實施，當不能以之限定本發明之專利範圍，即大凡依 本發明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本 發明之專利範圍内。 8 200810049 【圖式簡單說明】 第1A圖、第1B圖與第1C圖所示為習知PoP製作之流程剖面示意圖。 第2圖所示為根據本發明堆疊式封裝結構一實施例之剖面示意圖。 第3圖所示為根據本發明堆疊式封裝結構另一實施例之剖面示意 圖。 第4A圖、第4B圖與第4C圖所示為根據本發明堆疊式封裝結構製 法之部分流程剖面示意圖。 【主要元件符號說明】 100 第一封裝體 110 載板 120 封膠體 130 焊球 200 第二封裝體 210 載板 220 封膠體 230 焊球 10 第一封裝體 11 載板 12 載板 13 載板 20 第二封裝體 9 200810049 21 焊球 22 焊球 23 焊球 30 第三封裝體 31 輔助焊球 32 輔助焊球 41 封膠體 42 封膠體 43 封膠體 51 晶片 52 晶片 53 晶片 54 晶片 10200810049 IX. Description of the invention: [Technical field to which the invention pertains] The present invention is related to! A chip package structure, in particular, a redistributable chip package structure and a method of fabricating the same. [Prior Art] The three-dimensional package is currently "two-funded, (four) is paekage 〇n Packages and package inpackage (pip) p〇i^, a typical 3D package, two _ vertical package The finished package is coated with process technology and the package is a package of a single package that is not soldered onto the wafer by a spacer spacer. Among them, p〇p is assembled by a separate package of two packaged boats and then stacked in a table-like manner to reduce process risk and thereby improve product yield. 1st, 8th, 1B, and 1C are flow diagrams of a conventional p〇p process. As shown in Figs. 1A and 1B, the first package 1 and 2 The package body 2 is provided with a plurality of solder balls (10) and a ball 23 下 under the carrier board 110 and the carrier board 210. The encapsulant 120 and the encapsulant 220 are respectively disposed on the carrier 11 and the carrier 21, and the encapsulant 12 and the encapsulant 220 respectively have a wafer (not shown) coated therein. The first package body 100 and the second package body 2 align the solder balls 13 〇 with the solder pads 13 to the first package body 1 and the second package body 200 by surface adhesion. Since the solder balls 130 and the solder pads 212 are made of different materials, in addition to accurate alignment, poor connection between materials is also a problem. In addition, in the heating process, due to the warpage caused by the difference in thermal expansion coefficient between different materials, the connection failure is more likely to cause the explosion (p〇pc(10)) phenomenon. SUMMARY OF THE INVENTION In view of the above problems, one of the objects of the present invention is to provide a stacked package structure and a method for manufacturing the same, which can be fused by a solder ball between a package and a package, up to 200810049 = excellent connection effect and effectively overcome Knowing the problem of poor connection between different materials, one of the purposes of the purpose is to provide a crystal-stacked package structure and to stack the "on-and-down f, surface set solder balls for the seal body pile f1 ^ ν σ work difficulties And solve the problem of heating in the process of different materials 3..., Wei Jian does not ride the secret line. ', in order to achieve the above purpose, a stack of two embodiments of the present invention: 'including · a first package The body ' has a carrier plate, and the _'ball 2 ==='· ^ 咖 焊 solder ball is disposed on the first, the carrier board has a carrier plate, and the second package system is used for stacking The number on the body is lightly placed on her lower thread, and the first and second divisions - the new ones are added to the sneak sneaker system, and have a carrier board, in which a plurality of welding spheres: Ϊ二二; A plurality of auxiliary solder balls have a carrier plate at the bottom and a plurality of solder balls The surface of the carrier plate and the surface-bonding process are used to bond the auxiliary solder balls on the surface of the carrier of the second package to the opposite side of the carrier plate of the second package. The first package is stacked on the first package. [Embodiment] FIG. 2 shows that according to the present invention, the chip package structure includes a first package and a first package: first:;:mf = and f ball 2] is disposed on the lower surface of the carrier (4). In addition, the device is mounted on the carrier plate n to seal the blade 51, w/ and a gel 41 is disposed on the carrier. The cymbal 5 minus the auxiliary solder ball 31 is disposed on the first package body 〇6 200810049 = the upper surface of the carrier y. A second package body 20 is used for stacking on the first package body 1 第. The body 20 has a carrier 12 and a plurality of solder balls 22 are disposed on the lower surface of the carrier 12. The second package 20 includes at least one wafer 52 disposed on the upper surface of the carrier 12, and a gel 42 is disposed on the carrier. The wafer 12 is sealed on the board 12, and the solder balls 22 on the lower surface of the carrier 12 of the second package 2 are respectively associated with the upper surface of the carrier u of the first package 1 The solder balls 31 are stacked opposite each other. : "There is no cross-sectional view of another embodiment of the stack 4 package structure according to the present invention. In this implementation, the stacked package junction ribs are stacked with two social packages = Package structure. Referring to FIG. 3, in the embodiment, the ball 32 is disposed on the upper surface of the carrier 12 of the second package 2G, and the crystal structure further includes a third package 3G for stacking. On the second package body 20. The first ::=30 has a carrier 13 and a plurality of solder balls 23 are disposed on the lower surface of the carrier 13. The body 13% includes a plurality of wafers, such as a wafer 53 and a wafer 54, which are disposed on the Ϊΐ ί 2 and the body 43 is disposed on the carrier 13 to seal the wafer 53 and the crystal 2; The solder balls 23 on the lower surface of the carrier 13 are stacked opposite to the auxiliary solder balls 32 on the upper surface of the carrier board 12 of the beans. According to the above description, the method of manufacturing the stacked package structure of the 4th and 4th inventions is not shown in the following: first, the schematic diagram of the cross section. As shown in FIG. 4A, the first package body 1〇, the carrier plate η′ is disposed on the upper surface of the carrier plate u to the upper body and has: a body 41 for sealing the wafer, and the sealing surface is sealed. At the same time, and set her her solder balls 21 on the carrier board 11 below the table «^10 11" The second package 20 has a load, and a second package 20, this u52, < At least one cymbal 52 is disposed on the upper surface of the plate 12, so that a colloid 42 is placed to seal the V-day solder ball 22 on the lower surface of the carrier 12. (4) ^ In the case of setting a plurality of embodiments, using a surface adhesion method No. 4B, the auxiliary solder balls 31 on the upper surface of the lower surface of the first carrier 12 are respectively aligned with each other. The fusion is used to seal the structure of the second wafer shown in FIG. The first package body 10 can be completed as described above. Referring to the conventional auxiliary ball 32 in the second package body 2, a plurality of = third package bodies 3 are provided. , the second surface is shown as 'the upper surface of the wafer 53 - there is =; in order to seal the wafer 53 and the crystal moon 54 丄 知 知 43 43 43 43 43 43 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 In the carrier 13 sequence, the carrier plate of the third package 30 is u = the carrier of the surface point! 2 The auxiliary of the upper surface _ 32 t = (4) 23 and the second package 3 分别 are respectively stacked on the first-packing body 2, and are mutually aligned, for the third package and the body-sealing body 20 The chip package structure as shown in FIG. 3 can be completed. According to the above, the feature of the present invention is that the material is stacked and electrically connected. Because the same material compatibility is extremely ft: there is a poor connection of blue, can solve the problem of knowing the material, and the amount of empty solder balls is needed to maintain the stack height between the package and the package. . ^In summary, the package and the package of the present invention are mutually connected by solder balls to achieve an excellent connection effect and effectively overcome the problem of poor connection between different materials by the carrier board in advance of the package. Solder balls are arranged on the upper and lower surfaces for stacking and connecting the packages, which can reduce the difficulty of processing and solve the phenomenon of bulging or blasting due to different swell coefficients between different materials during heating. The embodiments described above are merely illustrative of the technical spirit and the features of the present invention, and the objects of the present invention can be understood by those skilled in the art, and the scope of the present invention cannot be limited thereto. That is, the equivalent variations or modifications made by the spirit of the present invention should still be included in the scope of the present invention. 8 200810049 [Simple description of the drawings] Figures 1A, 1B and 1C show schematic flow diagrams of conventional PoP fabrication. 2 is a cross-sectional view showing an embodiment of a stacked package structure according to the present invention. Figure 3 is a cross-sectional view showing another embodiment of a stacked package structure in accordance with the present invention. 4A, 4B and 4C are schematic cross-sectional views showing a part of the process of the stacked package structure according to the present invention. [Main component symbol description] 100 First package 110 Carrier plate 120 Sealant 130 Solder ball 200 Second package 210 Carrier plate 220 Sealant 230 Solder ball 10 First package 11 Carrier plate 12 Carrier plate 13 Carrier plate No. 2 package 9 200810049 21 solder ball 22 solder ball 23 solder ball 30 third package 31 auxiliary solder ball 32 auxiliary solder ball 41 sealant 42 sealant 43 sealant 51 wafer 52 wafer 53 wafer 54 wafer 10