201108365 •、發明說明： 【發明所屬之技術領域】 本發明係關於光通訊的技術領域，特別是指用以收發光訊 號的光電元件晶片結構及光電元件。 【先前技術】 光電元件係由一底座與·一光電晶片組合而成。其中底座可 以是金屬盤體(metal stem)與金屬接腳的組合，例如T〇_can Header ’或是非金屬盤體與金屬接腳的組合，例如Leadframe Header。其次底座上可配置一載體(subm〇um)承載光電晶片， 且光電晶片的電極透過接腳與電路板上的電路連接。 上述光電晶片的電極可位在相對面，例如其一位在光電晶 片上方表面，另一位在光電晶片下方表面；當光電晶片配置在 載體(Submount)上，位在下方表面的電極可與載體接觸並形成 電性連結；載體更進一步作為打線墊(b〇undingpad)，使得一導 線可連接一接腳(電極)與載體；至於位在光電晶片上方表面的 電極也可藉一導線與另一接腳(電極)電性連接。值得注意的 是，載體與底座的表面需形成不導電的狀態。 圖la與圖lb顯示光電晶片的二個電極位在不同面；以 PIN-TIA架構的光電元件為例，光電晶片2〇〇位在一異質基板 /載體205上，且其組合配置在一底座2〇1 ;其中光電晶片2〇〇 電性連接-轉阻放大器(TIA)2〇2，且光電晶片·與底座2〇1 形成絕緣且可供操作；‘然而異質基板2G5的價格較高且體積盘 面積較大’因此導致光電晶片的電容提高且降低頻率^ 應。 s 圖lc與圖Id顯示另一種使光電晶片2〇〇能夠絕緣地配置 在底座201上且供操作的方式。其主要是在一同質的半絕緣基 板(semi-insulathig substrate，SI 基板)206 上磊晶生成 p+n 結 構的晶層’並藉由勉刻技術形成二個電極2〇3、2〇4 ;= 質半絕緣基板206同樣存在成本高的缺失，而且 度很薄(通常僅約數個微米(um)，所以須搭配精密的钱刻製p 3 201108365 以預防N+晶層不慎被餘穿而造成元件無法運作。 另外美國專利6,586,718揭露-縣電^， 一 板上組成。-1—晶層= 是以根據以上所述’傳統ΡΪΝ·ΤΙΑ _的光電 電晶片與底座間形成絕緣，使用異質基板會導 降低；而使用同質半絕緣基板除了成本高外 f乍Γ侧製程而導致製程參數須相當精;，ί高了 ΐ 【發明内容】 ❿ 本發明的目的之-係在提供—種光電元件，係、包含一底座 搭配-光電晶^其中底座的預定區域具有一絕緣構造用以承 載光電晶片’錯此使光電元件具有高頻寬 /或高良率的功效。 ^㈣做 為滿足上述的功效，本發明的光電晶片 =度二，的同質基座(Ν+基座)，且一晶=造= ΐίΐ 具有二個電極且位在同侧及具有相同金屬201108365 • Description of the Invention: Technical Field of the Invention The present invention relates to the technical field of optical communication, and more particularly to a photovoltaic element wafer structure and a photovoltaic element for receiving a light-emitting signal. [Prior Art] The photovoltaic element is a combination of a base and an optoelectronic wafer. The base may be a combination of a metal stem and a metal pin, such as a T〇_can Header' or a combination of a non-metallic disk and a metal pin, such as a Leadframe Header. Secondly, a carrier (subm〇um) can be disposed on the base to carry the photoelectric wafer, and the electrodes of the photovoltaic wafer are connected to the circuit on the circuit board through the pins. The electrodes of the above photoelectric wafer may be located on opposite sides, for example, one bit is on the upper surface of the photovoltaic wafer, and the other is on the lower surface of the photovoltaic wafer; when the photovoltaic wafer is disposed on the submount, the electrode on the lower surface may be combined with the carrier Contacting and forming an electrical connection; the carrier is further used as a wire pad (b〇undingpad), such that a wire can be connected to a pin (electrode) and a carrier; and the electrode located on the upper surface of the photovoltaic chip can also borrow a wire and another The pins (electrodes) are electrically connected. It is worth noting that the surface of the carrier and the base needs to be in a non-conductive state. 1a and lb show that the two electrode positions of the photovoltaic wafer are on different sides; taking the photoelectric element of the PIN-TIA structure as an example, the photovoltaic chip 2 is clamped on a hetero-substrate/carrier 205, and the combination thereof is disposed on a base. 2〇1; wherein the photovoltaic chip 2 is electrically connected-transimpedance amplifier (TIA) 2〇2, and the photovoltaic wafer is insulated from the base 2〇1 and is operable; however, the price of the heterogeneous substrate 2G5 is high and The larger the volume of the disk, thus resulting in an increase in the capacitance of the photovoltaic wafer and a reduction in frequency. s Figure 1c and Figure Id show another way in which the optoelectronic chip 2 can be placed insulatively on the base 201 and operated. It is mainly formed by epitaxially forming a p+n crystal layer on a semi-insulath substrate (SI substrate) 206 and forming two electrodes 2〇3, 2〇4 by engraving technique; = The semi-insulating substrate 206 also has a high cost loss, and the degree is very thin (usually only about a few micrometers (um), so it must be matched with sophisticated money to p 3 201108365 to prevent the N+ crystal layer from being accidentally worn. The component is inoperable. In addition, U.S. Patent No. 6,586,718 discloses - county electric ^, a board composition. -1 - crystal layer = is based on the above-mentioned 'traditional ΡΪΝ ΤΙΑ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The use of a homogeneous semi-insulating substrate, in addition to the high cost, the process of the process must be quite fine; ί高高ΐ [Summary] ❿ The object of the present invention is to provide a photoelectric element The system includes a base pair-photovoltaic crystal, wherein the predetermined area of the base has an insulating structure for carrying the photovoltaic chip. This causes the photoelectric element to have a high frequency width/high yield. ^(4) To satisfy the above effects The photonic wafer of the present invention has a homogenous pedestal (Ν+ pedestal), and a crystal = = = ΐίΐ has two electrodes and is located on the same side and has the same metal
釔構，輔以一低介電常數材料層(L0W κ材料層，如BCB 電容的麟，或在底部耻S0G造成與底座絕緣的 二m使光電元件的製作具有高頻寬、低成本、易製作及 /或咼良率的功效。 ，又底座魏緣構造除了可直接承載上述光電^外，其更 可，配-辅助接腳，且以該辅助接腳來承載光電晶片；如此可 ίί電晶片與底座間不具導電特性，而且藉由調整輔助接腳的 二達到调整光電晶片的高度，以及讓輔助接腳成為斷 路狀悲或作為電極。 』祕？f電晶片一般為Ρ4_Ν的檢光二極體，亦可為雷射二 極體或發光二極體。 其，底座可具有一環狀的延伸牆部位在底座的盤體周 且彳、伸牆部與一蓋體結合形成光電元件，藉此達到組五… 4 201108365 簡便的功效。 上述的目的；功效，以及本發明的其他目的、功效，可八 別藉由以下實施例並搭配圖式逐一說明。 刀 【實施方式】 圖2及圖3揭露一種光電元件的底座1〇結構，其具有一 金屬盤體(metal stem) 12、複數支可作為電極的電極'接 14a〜14c及一支接地接腳14d ;其中各接腳14a〜Md的一 嵌入該金屬盤體12 ;特別是，電極接腳14a〜14c可搭配一非 導電材料16，例如玻璃、塑膠材料，或其他類似性質& 使得金屬盤體12與各接腳14a〜14c形成不導電狀態。 一更進一步，金屬盤體12具有一第一面(盤面)&，及一 二，(底面)19相對第一面18，例如圖中的上表面及下表面； -嵌孔22形成在第-面18與第二面19之間且位於第一面18 ，中央區域；-絕緣構造24，由絕緣材料製成的嵌入件，組 ί 1嵌ΐ ΐ J或藉嵌人射出(inSert讀㈣)*式形成於嵌孔 。'、邑緣構造24可以全部或部份的體積位於盤體12的 =18與第二面19之間，且該絕緣構造24用以承載光電晶 /1 z〇 〇 免由ΐ別是’絕緣構造24具有一第—端24a及―第二端24b， 二^12如可相鄰且平齊於第—面18,且第-端2知承載 = 述的絕緣構造24可為—獨立的絕緣件或絕緣 =電極26a* 26b位於同—側的光電晶片％，且將光 =片、26配置在絕緣構造24的第一端此，則導線撕和挪 電極 =和26b與接腳⑷和14C ;此狀態下的光 電H與底座10的金屬盤體12成為不導電的斷路狀態。 >；26开t施1列提f 一種創新的底座10結構且能夠與光電晶 曰片緣效果，其有別於傳統底座需藉域體承載光電 曰曰片或疋在光電晶片上形成絕緣層的結構形離。 圖知揭露光電元件30可包含上述的底^及光電晶y 5 201108365 26’以及更包含一蓋體(cap)32組設在底座1〇上；其中蓋體32 一端具有開孔32a ’且開孔32a可配置一光學裝置34，例如透 鏡或玻璃片，或開孔32a處無配置任何元件或裝置。上述的開 孔32a或光學裝置34係相對光電晶片26。 々又圖4a顯示絕緣構造24的第一端24a係凸出金屬盤體12 的第一面18;因此光電晶片26位在絕緣構造24的第一端24a ^了與金屬盤體12形成絕緣外，更可搭配第一端24a的凸出 高度而改變與裝置34或開孔32a的距離，藉此調整耦光效率。 根據上述實施例的教示，圖4b顯示，絕緣構造24的第一 端24a可以凹彳氏於金屬盤體12的第一面18。 再者圖4a或圖4b中，絕緣構造24的第二端24b可以凸 出、齊平或凹入該金屬盤體12的第二面19 ;或參照以下的實 施例的說明。 圖5及圖6顯示一個大面積的嵌孔52開設在底座4〇的金 屬盤體42上，特別是嵌孔52的面積包括金屬盤體42的中央 區巧及鄰近的邊緣的區^(;纟隨構造Μ可組設於嵌孔％内， 或藉射出方式形成於嵌孔52内。值得注意的是，電極接腳 44a〜44c位在嵌孔52的範圍内且一端結合該絕緣構造54 ;又 光電晶片56配置在絕緣構造54的第一端5如。 上述金屬盤體42與各電極接腳44a〜44c及接地接腳 樹(見圖5)可先組合，然後將組合料 及模具内，搭配嵌入射出方式，將絕緣材料注入嵌孔52内以 形成絕緣構造54 ’同時利用絕緣構造科結合各電極接腳 此外可以利用射出製程的合模壓力，使接地接腳咖 ”金屬盤體42結合，或另外針對接地接 結合金屬«42。 zn 外圖6中顯示絕緣構造54的第二端54b齊平金屬盤體 ΐ的面*或嵌孔52的孔緣；'然而根據前述說明可知，The structure is complemented by a layer of low dielectric constant material (L0W κ material layer, such as BCB capacitor lining, or two m m insulated from the base at the bottom shame S0G to make the photovoltaic element fabrication high-frequency, low-cost, easy to manufacture and / or the effect of the yield. The base Wei edge structure can directly carry the above-mentioned photoelectric, and it can be equipped with an auxiliary pin, and the auxiliary chip is used to carry the photoelectric chip; There is no conductive property between the bases, and the height of the optoelectronic wafer is adjusted by adjusting the auxiliary pins, and the auxiliary pins are broken or used as electrodes. The secret chip is generally a Ρ4_Ν illuminating diode. It can also be a laser diode or a light-emitting diode. The base can have a ring-shaped extension wall at the periphery of the disk body of the base, and the 彳, the wall portion and a cover body are combined to form a photoelectric element, thereby achieving Group 5... 4 201108365 Simple Efficacy The above-mentioned purpose, efficacy, and other objects and effects of the present invention can be explained one by one by the following embodiments and with the drawings. Knives [Embodiment] Figs. 2 and 3 A base 1 structure of a photovoltaic element is disclosed, which has a metal stem 12, a plurality of electrodes '14a-14c as electrodes, and a grounding pin 14d; wherein the pins 14a to Md are The metal disk body 12 is embedded; in particular, the electrode pins 14a-14c can be combined with a non-conductive material 16, such as glass, plastic material, or the like, to form the metal disk 12 and the pins 14a-14c. In a non-conducting state, the metal disk body 12 has a first surface (disk surface) & and a second surface (bottom surface) 19 opposite to the first surface 18, such as the upper surface and the lower surface in the drawing; 22 is formed between the first face 18 and the second face 19 and is located at the first face 18, the central region; - the insulating structure 24, an insert made of an insulating material, the set ί 1 embedded ΐ J or by the embedded person (inSert read (4)) * is formed in the through hole. ', the edge structure 24 may be all or part of the volume between the disk 18 = 18 and the second face 19, and the insulating structure 24 is used to carry the photoelectric crystal /1 z〇〇 is distinguished by the fact that the 'insulating structure 24 has a first end 24a and a second end 24b, Adjacent and flush with the first face 18, and the first end 2 knows the load bearing = the insulating structure 24 can be - independent insulating member or insulating = electrode 26a * 26b located on the same side of the photovoltaic wafer %, and light = The sheet 26 is disposed at the first end of the insulating structure 24, and the wire is torn and the electrode=26b and the pins (4) and 14C; the photoelectric H in this state and the metal disk 12 of the base 10 become a non-conductive open circuit state. >; 26 open t 1 1 extract f An innovative base 10 structure and can be combined with the edge of the photoelectric wafer, which is different from the traditional base needs to carry the photoelectric diaphragm or the crucible on the optoelectronic wafer The structure of the insulating layer is separated. The photo-electric component 30 can include the above-mentioned bottom and photo-crystal y 5 201108365 26' and further includes a cap 32 disposed on the base 1 ;; wherein the cover 32 has an opening 32a ' at one end and opens The aperture 32a can be configured with an optical device 34, such as a lens or glass sheet, or without any components or devices disposed at the aperture 32a. The above-described opening 32a or optical device 34 is opposed to the optoelectronic wafer 26. 4a shows that the first end 24a of the insulating structure 24 protrudes from the first side 18 of the metal disk body 12; thus the optoelectronic wafer 26 is positioned at the first end 24a of the insulating structure 24 to be insulated from the metal disk body 12. The distance from the device 34 or the opening 32a can be changed with the protruding height of the first end 24a, thereby adjusting the coupling efficiency. In accordance with the teachings of the above embodiments, Figure 4b shows that the first end 24a of the insulating construction 24 can be recessed from the first side 18 of the metal disk body 12. Further, in Fig. 4a or Fig. 4b, the second end 24b of the insulating structure 24 may be convex, flush or recessed into the second side 19 of the metal disk body 12; or reference to the description of the following embodiments. 5 and 6 show that a large-area insertion hole 52 is formed in the metal disk body 42 of the base 4, and particularly, the area of the insertion hole 52 includes the central portion of the metal disk body 42 and the area of the adjacent edge. The structure can be formed in the embedded hole % or formed in the insertion hole 52 by means of injection. It is noted that the electrode pins 44a to 44c are located in the range of the insertion hole 52 and the end is combined with the insulation structure 54. The optoelectronic chip 56 is disposed at the first end 5 of the insulating structure 54. The metal disc 42 and the electrode pins 44a to 44c and the grounding pin tree (see FIG. 5) may be combined first, and then the composite material and the mold are assembled. In combination with the embedded injection method, the insulating material is injected into the through hole 52 to form the insulating structure 54'. At the same time, the insulating structure is combined with the electrode pins, and the clamping pressure of the injection process can be utilized to make the grounding pin "metal plate 42". Bonding, or otherwise bonding to the grounding metal «42. zn The second end 54b of the insulating structure 54 is shown in Figure 6 to flush the face of the metal disk body* or the hole edge of the hole 52; however, according to the foregoing description,
f *7知也可以凸出或凹入該金屬盤體42的第二面49;或 參照以下的實施例的說明。 [S 201108365 更2 光電兀件60由底座40與光電晶片56組合且 組成；特別是，絕緣構造54的第一端54a 體成形的-凸部55 ;該凸部55凸出金層盤體4 盤體且f2^^組設在凸部％上。如此光電晶片56 β μ ΛΑ m緣，且光電晶片56可藉此調整盘蓋體 上的光㈣4 64相触置而提絲級率。 、 ^前，實施例的教示’光學裝置Μ是組設在開孔必 透鏡或玻璃片；此外，開孔62&處也可無配置任 -她t根獅述實施例的教示，® 7b顯示舰緣構造54的第 的第-二二以具凹空57。該凹空57可低於金屬盤體42 的第一面48，且光電晶片56配置在凹空57内。 _ΐΐΪΐ緣構造24、54可利用第一端24a、54a的凹空57 或凹低於第:=和：且第一端⑽、地可以平齊、凸出 助接=:=絕，構造24的抽向》輔 罢乐位置71及一第二位置72,其中第一位 第一面24的第一端24a且相鄰金屬盤體12的 到調整光電晶片26所處高度的目的。弟面18精此達 第二圖处所揭示的結構中，輔助接腳70的 7° 的威 ===== 7 201108365 =:=丨也可以被設計成平齊、凸出或凹低金屬盤 ^光電晶片26的二個電極位在相同側，例如位在上方 側’則形成斷路的辅助接腳70不會影響元件的電極特方 的長，另’其主要是調整或改變輔助接腳70 去ϋί八弟二位置72與其他電極i4a、i4c的端部處在相 平位置；當底座iG或其構成之光電元件組設在 欠辅助接腳7〇可與電路連接而形成通路。特別是， ί㈣極位在上、τ側，則下綱電極可與辅助接 腳電性連接，並以該輔助接腳70作為電極。 射8C中的底座1〇是選用圖2、圖3所顯示的結構， 5 ^ ⑷〜…與絕緣構造24為相離；然而亦可選用圖 f 6所揭不的底座4〇結構，並依上 ，”組設於絕緣構造54的軸向且使得各_44a〜4= ^插入絕緣構造54内。 ，9a及圖％顯示金屬盤體81上開設一喪孔幻，且一絕 1山t 83敗入嵌孔82内；特別是，複數電極接腳8如〜84c的 83 ’且錢極接腳咖〜咖_部具有電 ’义導體85(見第％圖）。上述電的良導體％可以是金。 山此外更有一金屬薄膜87配置或鍍設在絕緣構造幻的第一 ^ 3=表面，且使金屬薄膜87與金屬盤體81形成電性相連。 薄膜87的周邊具有缺空88用以對應各接腳84a〜84c，藉 得金屬薄膜87與各接腳84a〜84c形成電性相離狀態。至 f光電晶片86則配置於金屬膜87上；若光電晶片86有一電 底面且與金屬薄膜87接觸，則該金屬薄膜87可作為打 綠區域。 Ί 8 201108365 j Μ λα^閱圖咖b，嵌孔82可被製作成錐形孔狀，而且絕緣構 以山π。卜形製作成與嵌孔82形狀相符’因此絕緣構造83置 入敗孔82内可據此達驟密的結合及定位效果。 〜f t %所揭示之實施例與圖9a、9b之實施例的不同在 ^金屬溥膜87上開設有一開孔89 ;光電元件％位在該開 且配置在絕緣構造83上。至於金屬薄膜87可選擇是 否與金屬盤體81電性相連。f *7 can also be projected or recessed into the second face 49 of the metal disk 42; or reference is made to the description of the following embodiments. [S 201108365 More 2 Photoelectric element 60 is composed of and combined with the base 40 and the optoelectronic wafer 56; in particular, the first end 54a of the insulating structure 54 is formed by a convex portion 55; the convex portion 55 protrudes from the gold layer disk 4 The disk body and the f2^^ group are disposed on the convex portion %. Thus, the optoelectronic wafer 56 has a β μ ΛΑ m edge, and the optoelectronic wafer 56 can thereby adjust the light level by the light (4) 4 64 phase contact on the disk cover. Before ^, the teachings of the embodiment 'optical device Μ is set in the aperture lens or glass piece; in addition, the opening 62 & can also be configured without any - she teaches the example of the lion, the ® 7b display The first - twenty-two of the rim structure 54 has a recess 57. The recess 57 can be lower than the first face 48 of the metal disk body 42 and the optoelectronic wafer 56 is disposed within the recess 57. The rim structure 24, 54 may utilize the recess 57 of the first end 24a, 54a or the recess lower than the first: = and: and the first end (10), the ground may be flush, the convex assist =: = absolute, the configuration 24 The auxiliary strike position 71 and a second position 72 are drawn, wherein the first end 24a of the first first face 24 and the adjacent metal disk body 12 serve the purpose of adjusting the height of the photovoltaic wafer 26. In the structure disclosed in the second figure, the 7° of the auxiliary pin 70===== 7 201108365 =:=丨 can also be designed as a flush, convex or concave low metal plate ^ The two electrode positions of the optoelectronic chip 26 are on the same side, for example, on the upper side, the auxiliary pin 70 forming an open circuit does not affect the length of the electrode of the component, and the other is to adjust or change the auxiliary pin 70. Ϋί八八二位置72 is in a leveling position with the ends of the other electrodes i4a, i4c; when the base iG or its constituent photovoltaic element group is disposed at the under-auxiliary pin 7〇, it can be connected to the circuit to form a path. In particular, when the ί (4) pole is on the upper side and the τ side, the lower electrode can be electrically connected to the auxiliary pin, and the auxiliary pin 70 is used as an electrode. The base 1 in the 8C is selected from the structure shown in Fig. 2 and Fig. 3, and 5^(4)~... is separated from the insulating structure 24; however, the base 4〇 structure not shown in Fig. 6 can also be selected, and The upper part is disposed in the axial direction of the insulating structure 54 such that each of the _44a~4=^ is inserted into the insulating structure 54. The 9a and the figure % show a hole illusion on the metal disk 81, and one is a mountain. 83 is defeated into the insertion hole 82; in particular, the plurality of electrode pins 8 such as 83' of 84c and the money poles of the coffee makers have an electric conductor 85 (see the figure %). % may be gold. In addition, a metal film 87 is disposed or plated on the first surface of the insulating structure, and the metal film 87 is electrically connected to the metal disk 81. The periphery of the film 87 has a short space. 88 is used to correspond to each of the pins 84a to 84c, so that the metal film 87 is electrically separated from the pins 84a to 84c. The photo-electric wafer 86 is disposed on the metal film 87; if the photovoltaic chip 86 has an electric bottom surface And in contact with the metal film 87, the metal film 87 can be used as a greening area. Ί 8 201108365 j Μ λα^图图咖b, inlay 82 It is made into a tapered hole shape, and the insulating structure is made of a mountain π. The shape of the pad is made to conform to the shape of the hole 82. Therefore, the insulating structure 83 is placed in the hole 82 to achieve a close combination and positioning effect. The embodiment disclosed in FIG. 9 differs from the embodiment of FIGS. 9a and 9b in that an opening 89 is formed in the metal tantalum film 87; the photovoltaic element is located on the opening and disposed on the insulating structure 83. As for the metal film 87, the metal film 87 can be selected. Whether it is electrically connected to the metal disk 81.
圖9e係根據圖9d的結構加以演化，其特別處在於：一凸 部831凸出地形成在絕緣構造83表面且穿過金屬膜87的開孔 89 ;光電晶片86配置在凸部831的端部。 圖9f揭露絕緣構造83的周邊可進一步延伸形成一延伸牆 部8严；該延伸牆部832的一端為具有開放口 833的開放端7 一蓋體834組設在延伸牆部832的開放端，藉此可構成光電元 件的組態。 此外延伸牆部832具有一缺口 832a，如此一來，打線用 之尖嘴容易靠近元件；同樣的道理亦可用於圖1〇a，1〇b，12a， 12b及圖13a所示的結構中。 ’ ’ 再者，辅助接腳70可組設在絕緣構造83的軸向，其第一 位置71可承載光電晶片86，且調整輔助接腳7〇的長度或高 度，可進而達成調整光電晶片86所處高度的效果；又輔助接 腳70的第二位置72伸出絕緣構造83長度若相對其他接腳 84a、84c成為懸空狀，也就是輔助接腳7〇的第二位置72比電 極接腳84a、84c的自由端更接近盤體81的第二面81a，則未 來使用該光電元件時，輔助接腳70可以不位於電路上而形成 斷路；若第二位置72伸出絕緣構造83的長度或位置與其他接 腳84a、84c的端部（自由端)相當，則輔助接腳7〇可作為電極 且用來連接電路。 此外，若要輔接接腳70的長度足以連接電路，但又要使 其與光電晶片86形成絕緣或斷路，可以在光電晶片86的基庫 之下配置一個絕緣層構造’例如旋制氧化矽(Spin 〇n glas^， 9 201108365 I 腳7G ’如此可達到上述的要求。 所處高度的目的。達到調整光電晶片86 適用於圖％及圖9d所揭示之^&、延伸牆部832結構也 體92圖的 ‘对圖_露之;本實施例與第 薄膜於絕緣構造93表面。—在於·本實施例無配置金屬 ώ； I, . ™ 又’、位置’可以達到調整光電晶片96的 和電二r:屬=一 屬或絕緣材料製成之絕緣構造24、54要==J結合非金 結構外，亦有其_成、=54和83 ’然而除了上述的 為凸撐構造紐形成在絕緣構造％上且 (MPD) ^ 93b 104二4U'揭露-非金屬盤體_，以及複數電極接腳 104^:6；且設山在非金屬盤體1〇0的轴向。其中各接腳 面配於非金屬盤體⑽的第一面1〇1且表 1〇〇的ίί的良導體105。又金屬膜107係配置在非金屬盤體 曰Η 1ΠΑ ΛΛ’且光電晶片1〇6組設在金屬膜107上。如此光電 :m的電極可藉導線(未顯示〉與接腳104a、104c電性連 膜1〇7電性連接光電晶片106的一電極，再以 、、’ ‘，、、不)連接金屬薄膜107與一接腳i〇4a或i〇4c，藉土5 ] 201108365 形成電性連接。 此外在圖lla中，若將電極接腳1〇4a、1〇仆或1〇4 電的良¥體1〇5與金屬膜107連接在一起 以 線Fig. 9e is evolved according to the structure of Fig. 9d, in particular, a convex portion 831 is convexly formed on the surface of the insulating structure 83 and passes through the opening 89 of the metal film 87; the photovoltaic wafer 86 is disposed at the end of the convex portion 831 unit. FIG. 9f discloses that the periphery of the insulating structure 83 can be further extended to form an extended wall portion 8; one end of the extended wall portion 832 is an open end 7 having an open opening 833, and a cover 834 is disposed at an open end of the extended wall portion 832. Thereby, the configuration of the photovoltaic element can be formed. Further, the extension wall portion 832 has a notch 832a, so that the tip of the wire is easily brought close to the component; the same principle can be applied to the structures shown in Figs. 1a, 1b, 12a, 12b and Fig. 13a. Further, the auxiliary pin 70 can be disposed in the axial direction of the insulating structure 83, and the first position 71 can carry the optoelectronic chip 86, and the length or height of the auxiliary pin 7〇 can be adjusted, thereby further adjusting the optoelectronic chip 86. The second position 72 of the auxiliary pin 70 extends beyond the length of the insulating structure 83. If the length is opposite to the other pins 84a, 84c, that is, the second position 72 of the auxiliary pin 7 is more than the electrode pin. The free ends of 84a, 84c are closer to the second face 81a of the disk body 81. When the photovoltaic element is used in the future, the auxiliary pin 70 may not be located on the circuit to form an open circuit; if the second position 72 extends beyond the length of the insulating structure 83 Or the position is equivalent to the end (free end) of the other pins 84a, 84c, the auxiliary pin 7 can be used as an electrode and used to connect the circuit. In addition, if the length of the auxiliary pin 70 is sufficient to connect the circuit, but is to be insulated or broken from the optoelectronic chip 86, an insulating layer structure can be disposed under the base of the optoelectronic chip 86, such as spin-on yttrium oxide. (Spin 〇n glas^, 9 201108365 I foot 7G 'This can meet the above requirements. The purpose of the height. The adjustment of the optoelectronic chip 86 is suitable for the ^ & extension wall 832 structure disclosed in Figure % and Figure 9d Also, the figure is shown in Fig. 92; the present embodiment and the film are on the surface of the insulating structure 93. - In this embodiment, there is no metal iridium; I, TM and 'position' can be adjusted to adjust the photovoltaic chip 96. And the second genus = a genus or an insulating material made of insulating material 24, 54 to ==J combined with non-gold structure, also has its _, =54 and 83 ' However, in addition to the above is a convex structure The neon is formed on the insulating structure % and (MPD) ^ 93b 104 2 4U' exposes the non-metallic disk body _, and the plurality of electrode pins 104^:6; and the mountain is in the axial direction of the non-metallic disk body 1〇0. Each of the pin faces is provided on the first side of the non-metallic disk body (10) 1〇1 and the sheet 〇〇 ίί good The body 105 is further disposed on the non-metal disk 曰Η 1ΠΑ ΛΛ ' and the optoelectronic chip 1 〇 6 is disposed on the metal film 107. Thus, the electrode of the photoelectric: m can be wired (not shown) and the pin 104a 104c electrically connected to the film 1〇7 electrically connected to an electrode of the photovoltaic wafer 106, and then, the combination of the metal film 107 and a pin i〇4a or i〇4c, by the soil 5] 201108365 Electrical connection is formed. In addition, in FIG. 11a, if the electrode pin 1〇4a, 1〇1 or 1〇4 electric good body 1〇5 is connected with the metal film 107, the line is connected.
=讓f極獅购、馳_績錢^ J 上開的不同處在於:金屬薄讀 上開《又有開孔108，光電晶片106組設在開孔】μ# 且位在非金屬盤體觸的表面。4開孔⑽的耗圍内 ===電晶請咖凸部⑽具有調： 值得注意的是’凸部109具有絕緣特性，因 上成用以承载光電晶片106的絕緣構造，而 緣構造可以齊平、凸出或凹低於 圖12a揭露非金屬盤體刚的周邊可 =伸牆!，延仲牆部丨1。的-端為具有開 知」山盍體112組設在該延伸牆部11〇的開放端；盆次蓋體 或僅僅獅跡(匈玻璃， 而· 顯示-辅助接腳7G配置在非金屬盤體1⑻的軸 接腳70的一端凸出非金屬盤體100的第一面101且 輔助接腳^片蓋體112組設在延伸牆部110的開放端； 片ί面1G1的長度或高度可用以調整光電晶 片06的而度’藉此使光電晶片1〇6接近蓋體112 助接腳7G也作為光電晶請的―電極，歧形 在圖12a與圖12b所揭露的實施例中，非金屬盤體獅士 11 201108365 第一面101上可配置一金屬薄膜107。 m .圖^非金屬盤體励的延伸牆部11G上配置一蓋辦= Let f lion buy, Chi _ performance money ^ J on the difference is: metal thin read on the "open hole 108, photovoltaic wafer 106 set in the opening hole] μ # and in the non-metallic disk Touch the surface. 4 inside the hole of the opening (10) === electro-crystal, the convex portion (10) has a tone: It is worth noting that the convex portion 109 has an insulating property, and the edge structure can be used to carry the insulating structure of the photovoltaic wafer 106, and the edge structure can be Flush, convex or concave lower than the perimeter of the non-metallic disk body as shown in Fig. 12a can be = wall extension! The end of the scorpion body 112 is located at the open end of the extension wall 11 ;; the basin cover or only the lion trace (Hungarian glass, and · display - auxiliary pin 7G is arranged in the non-metallic plate One end of the shaft pin 70 of the body 1 (8) protrudes from the first face 101 of the non-metallic disk body 100 and the auxiliary pin cover body 112 is assembled at the open end of the extended wall portion 110; the length or height of the slice 1G1 is available In order to adjust the degree of the photovoltaic wafer 06, the photo-electric wafer 1〇6 is brought close to the cover body 112. The auxiliary pin 7G also serves as an electrode for the photo-crystal, which is in the embodiment disclosed in FIGS. 12a and 12b. Metal plate body 11 201108365 The first side 101 can be equipped with a metal film 107. m. Figure 2. Non-metallic disk body-extended extension wall 11G is equipped with a cover
^ ίο 1〇4"1〇4C 電極接腳104b可以形成斷路，或是作ϊ-ί 咖12咖糊_編於：本實^ 圖13b揭露的組態與圖13a所揭露的組態不同處 ，極接腳104a〜l〇4c嵌入非金屬盤體励的方 光雷 片106為·二極體並且電性連接一轉阻放大器(TIA先= 電極懸空狀態，所以電極接腳_將為斷路 Χ θ 所顯示的結構形式，底座的製作可以選用圖 c及圖13d所顯示的形式，其可先製作具錢當之各 :連續金屬帶或金屬片；進而利用射出成型Ϊ &’^开iiri04a〜104c的一端(如圖13c)或靠合處(如圖 體⑽。如此可使非金屬無⑽與各接 腳104a〜104c的射出成型更加方便。 以圖13d為例，形成連續帶狀或片狀的底座結構後可以 ，，二的針對每-個底座進行配置光電晶片1%、匹配元件及 未顯不）；然後再進行裁切，藉此形成單一顆粒狀 7L件。 傳統的光電元件的方式是先製作出單一的底座，然後再逐 二，定體積很小的底座及配置光電晶片與打線；其中底座要逐 :m·:本發明可以使複數底座構成連續帶狀或大面 作設備夾持與定位，所以本發明可解決傳統 配置先電晶片與打線時所產生的不便性。 ^據圖13b〜13d所揭露内容的教示，關於非金屬盤體励 :十接腳KMa〜胸的組合可減圖…、咏、以〜既圖所 的形式及其均等形式。其中在非金屬盤體励上可配置一 金屬膜107。 201108365 又圖13f及圖13h揭露接腳84a〜84e配置 與絕緣構造93所組_齡賴的水付向。料 93上具有-金屬薄膜87 ’與金屬盤體92可電性相連。、' 在上述實施例中提及絕緣構造24、54、83和 在金屬盤體12、42、81、和92卜报忐一伽想— a J稽目开 或搭配輔助接腳70形成-個獨立“緣部件；=緣^絕 ^ I和Γ Γ面可以齊平、凸出或凹下二該金 然而除了上述的架構外，圖14a顯示絕緣 斜狀，-光學元件/光 配置在％面122成傾斜狀；又圖14b及圖14^ ίο 1〇4"1〇4C electrode pin 104b can form an open circuit, or as a ϊ-ί 咖 12 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The pole pins 104a~l〇4c are embedded in the non-metallic disk body-excited square light ray plate 106 as a diode and electrically connected to a transimpedance amplifier (TIA first = electrode floating state, so the electrode pin _ will be open circuit Χ θ The structure shown, the base can be produced in the form shown in Figure c and Figure 13d, which can be made with money: continuous metal strip or metal sheet; and then use injection molding Ϊ & '^ open iiri04a~ One end of 104c (as shown in Fig. 13c) or the joint (such as the body (10). This makes the non-metal without (10) and the injection of each of the pins 104a~104c more convenient. Figure 13d as an example, forming a continuous strip or sheet After the base structure can be configured, the second one is configured for each of the bases, and the matching components are not shown; and then the cutting is performed, thereby forming a single granular 7L piece. The conventional photoelectric element The way is to make a single base, then two by one, set the volume The small base and the configuration of the optoelectronic chip and the wire; wherein the base is to be: m·: the invention can make the plurality of bases form a continuous strip or a large surface for device clamping and positioning, so the invention can solve the traditional configuration of the first electric wafer and the wire Inconvenience caused by the time. According to the teachings of the contents disclosed in Figures 13b to 13d, the combination of the non-metallic disk body: the ten-pin KMa~ chest can be reduced by ..., 咏, ～ A uniform form, wherein a metal film 107 can be disposed on the non-metallic disk body. 201108365 and FIG. 13f and FIG. 13h disclose the arrangement of the pins 84a to 84e and the water structure of the insulating structure 93. - The metal film 87' is electrically connectable to the metal disk body 92. 'In the above embodiment, the insulating structures 24, 54, 83 are mentioned and the metal disk bodies 12, 42, 81, and 92 are reported. — a J is opened or matched with the auxiliary pin 70 to form an independent “edge component; = edge ^ ^ ^ ^ and Γ Γ face can be flush, convex or concave two gold, except for the above structure, 14a shows the insulation is oblique, - the optical element / light arrangement is inclined on the % plane 122; Figure 1 4b and Figure 14
120應用其凸出陳體121及平整的表面125可分配置= 兀件學/光學裝置123和124;圖McUlf紹铋me配置先子 二個柱趙⑵和126且分二=:先構學=具J ，14e揭露絕緣構造12()更可具有凹空、= 件/光學裝置128配置。 i供先干兀 由圖14a〜14e所教示，絕緣構造12〇上可以且 ^體二f *凹空127，且其端面可以形成丄 狀’更可以在絕緣構造120的柱體⑵、126 ; 足光電元件所縣的歧雜，细料應^此滿. :用來降低回流損耗(_ los心 則可為一濾光片（filter)或為Mp 以圖/予 元件/光㈣置⑵可為VCSEL，耐光學 124為MPD，至於位在光學元件/峨置 13 201108365 件/光學裝置為濾光片；再以圖14d為例，光 ⑵為VCSEL，而另一光學元件/光學裝置子裝置 然而圖14a〜14e中的各光學元件/光學裝置123、124與128 可以局部或全部由光電晶片取代。 /、 ^述實施例所提及的光電^可取㈣前技術中所揭露 =光電晶Μ，並且配置在本發明所揭露的底座上，藉此組成光 電元件。然而更可以採用以下所揭露之光電晶片結構。 圖15a揭露一光電晶片146(可取代前述光電晶片26、56、 86、％或106)的構成係一包含有第二極性的晶層構造15〇藉 遙晶而形成在-具有第-極性的基座13〇上。前述的第一極性 與第二極性為相異的極性，例如圖中所示的晶層 :=，也可再包含有1晶層或其它功能之=1 座130為N+基座。 根據上述的構成方式’本發明也可以採用晶層構造15〇 3 N晶層來搭配p基座。然而不論採用那一種形式組合，美 座130厚度皆要遠大於晶層構造I%中的晶層厚度。 P ° m no 具有複數蟲晶層⑽層構造150係長 ^基座130的第-侧130a;其次二個具有相同金屬構成之 ，極131矛口 132形成在晶層構造150的同側，例如圖中= 上方側。 再者高掺雜的可導電基座130具有較大的厚度，1 ，50〜lGGGum之間，而通常落在7〇〜施m之間， =支縣礎，所以可導座13G的厚度可叹傳統 =度的數十倍至數百倍之間，但隨著製術的進步，厚^曰 未來有可能再朝向薄型化發展，並能兼顧厚實支撐 ^ =刻技術形成獨立的電極131來作為打線墊:刻J 可導電基座’仍可以使打線墊保持電轉性，是 例所揭露的找“M6結構做餘㈣上的雜。此= !的可導電基座130的第二側(底面M鳥並無相同材質之半 201108365 緣或不導電基座。 此外，二電極131和132為具有相同導電金屬的結構，通 书為蕭特基金屬，特別是由Ti/Pt/Au堆疊的金屬結構，其中 * Ti(具有與半導體較佳的黏附力)通常為10-lOOnm、Pt(為一個 . barrier金屬，於某些實施例中，可無此層)通常為50-200nm， 而Au(供後續打線或連結之用)通常為1〇〇_2〇〇〇nm，但若結合 電鍍的製程，Au的厚度將可達數um以上。上述的鈦金屬可 以由鉻(Cr)取代，使電極131或132的金屬架構成為Cr/Au或 是Cr/Pt/Au架構。 上述的晶層的厚度為：P型晶層通常約100 nm〜2000 _ nm、I型晶層通常約5〇〇nm〜5000 nm ° 圖15a的光電晶片結構係可特別地搭配圖2、3、4a、4b、 5、6、7a、7b、8a、8b、9c、9d、9e、10a、10b(例如在輔助接 腳為斷路狀態下）、lib、11c、12a、13b、14a〜14e圖所揭露的 底座，因這些底座都特別使用一個絕緣構造，或是具有與其它 接腳腳位不在同平面的輔助接腳，所以使用本發明之低成本的 N+基座130，且搭配具有相同材質的p電極132和n電極13i， 可以使光電晶片146不透過載體而置放於底座上，藉此達到降 低成本與元件電容，以及增進高頻響應的特性。 • 請參閱第15b圖，本實施例與圖15a所顯示之實施例的 不同在於.一絶緣層133位在可導電基座130的一側，例如旋 ， 制氧化矽(Spin on glass，SOG )。此結構形態可適用於圖2〜He 的各式底座或是傳統的基座(如la或lc所示），此時可免除異 質基板(載體205)的使用’但亦可視需要予以保留。 圖15c除了更詳細的顯示PIN架構外，更加入一低介電常 數層(Low-K Layer) 134位在P電極的下方，且填充於p磊晶詹 被餘刻掉的區域内，或低介電常數層134位於二個電極13ι、 132之間’藉此可以降低元件的電容值。該低介電常數層 可由一厚膜(Thick Film)取代。 圖15a〜15c所揭露的光電晶片146為因應每一個具絕緣表° 15 201108365 造的底座而設計’且光電晶片146搭配各底座可構成一種具新 穎及進步性的光電元件。 圖15d與圖15c的差別在於可導電基座130的底面具有一 . 絕緣層I%。另外在圖15c至圖15j的晶層構造中皆有一絕緣 保護層137。 * . 延續圖15c、15d之實施例内容，光電晶片的架構可以是 圖15e〜15j所顯示的架構’·其中圖15e、15f揭露為一種擴散型 (diffliSi〇ntype)PlN架構，可具有低介電常數層134或厚層；圖 15g〜15j揭露一種平台型(mesatype)PIN架構，其配置有低介電 常數層134或厚層，其介電常數或厚層的厚度係以降低電容值 攀 20%以上為設計標準。 又圖15h至圖15j，其揭露P晶層與j晶層之間可有一介 面晶層138。該介面晶層138為未攙雜或低攙雜的InP或InA1As 層。此為尚能隙材質，用以降低漏電流，一般厚度介於⑽〜 200 nm之間。 上述的低介電常數層134或厚層可以是s〇G塗層或是旋 佈介電層(spin on dielectric，SOD)或CVD介電材料。 圖15k顯示一種可用於檢光二極體(Ph〇t〇_Di〇de，pD)的光 電b曰片160結構。光電晶片16〇包含一晶層構造161長晶在一 • 基座162上。晶層構造161包含P-I-N+晶層，且基座162為半 絕緣基座或是不導電基座，例如磷化銦(lnp)或砷化鎵(GaAs)。 * 其次，二個電極163和164(或打線墊)位在晶層構造161的同 側。更進一步而言’二個電極163和164可以不在同一水平高 度’但由俯視方向則可見到二個電極。 同 該電極(打線墊)163係電性連接N+晶層，而另一電極 J塾)164電性連接P晶層。特別是，電極164的構造為具有侧 土(side wall)構造’也就是電極164經由晶層構造161的側邊， 位於基座162之上’另—端以少數部份面積電性連接該 p明|，如此可以有效降低二個電極(打線墊)163和164之間 201108365 更進一步’可在電極164與晶層構造161及基座162 配置-個絕緣層165。其次，根據前述實施例的教示，該 極163和164可以具有相同的金屬架構。 〜一 圖16a、16b顯示以PIN-TIA光電元件架構為例，1中 座142具有一絕緣構造144(關於絕緣構造的結構形^ / 述的底座結構），光電晶月M6配置於絕緣構造144，並使 ίί，」30位在絕緣構造144表面，藉此使得光電晶片I46與 42形成絕緣。此外二電極13卜132藉導線135 ^且 放大器130電性連接(見圖16b)。 ^轉 根據上述實施例的教示，該二電極和和也可以與 八=的至少—部份職電性連接；前崎稱之紐連接係 接λ導線相連電極接腳’或是利用導線由電極透 β二匕被動兀件，轉阻放大器、電容等等元件，間接連接 連接23;。惟不論直接胡接形式電極與電極接腳電性 上述實施例所使用的可導電基座13〇為一種同 1 半絕緣紐，—該可導電基座;與絕 ίϋΐϋ形態可以滿足光電元件146與底座142形成 =緣要求免除載_需求，因此具有降低成本提高頻寬的功 時，，:以_形成電極⑶ 達到i程參數=生= 可達成調整4晶片接目一^71凸出絕緣構造144即 腳70盥光雷曰H 片M6具有絕緣層133 ;所以輔助辞 ”先電4146麟絕緣層133形躺路，此外光電] 17 201108365 片146與底座142也形成斷路。 ，發_可導電基座13G除了是具有摻_ N型 ^也相是具有摻雜的P型基座且結合p㈣晶層， 圖15a〜15c、1知及17的PIN結構將反置。 上開實施例的教示，底座可以是—金屬盤體結合複 2 j腳絕緣構造的嵌人件嵌人金屬盤體；其中絕緣 的嵌入件形成獨立絕緣部件。 =底座可以是-金屬龍，及_絕緣構造的嵌入金屬盤 $結合複數電極接腳所構成。其中該絕緣構造形為獨立絕緣 αίίί座係—非金屬盤體結合複數電極接腳，且絕緣構造 為非金屬盤體的一部份或全部。 上述各實施例所揭露的電極接腳數量僅為說明之用； 上的接腳數量為2〜ό，亦可視需求增加。 不 =明所揭露的各底座，包含Τ(3.架構或導線架架 f ’具有絕緣構造，且可以搭配光電晶片形成光電元件， ί電^ 傳統f冓，即一半絕緣基板上具有P-I-N蟲晶 二二電曰曰片亦可以疋本案所提出的新晶片發明設計，即前述 ^例所揭露的架構，其中光電晶片構造為—可導電基雜+ ίΪΐίϋΐίί層，且基座的第二側(底面)無相同材質 μ αα η 電土座’再者以相同的金屬層構造做為光電晶 片的Ρ電極與Ν電極且同位於同一側；此外也可以在可 基座的第二側(底面)具s〇G或s〇D或CVD介電材料。而該 晶片可再搭配Low K(BCB或SQG)材料的設計可進一步的再 降低電容值，提高頻寬。 丹120 application of its convex body 121 and flat surface 125 can be divided into configuration = elementary learning / optical devices 123 and 124; Figure McUlf Shao 铋me configuration of the first two columns Zhao (2) and 126 and two = = first construction = J, 14e reveals that the insulating construction 12 () may have a configuration of recessed, = piece / optical device 128. i for the first dry 兀 兀 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 The phoenix of the foot photoelectric element is fine, and the fine material should be full. : Used to reduce the return loss (_ los heart can be a filter or Mp to / to the component / light (four) can be (2) For VCSEL, the optical resistance 124 is MPD, as for the optical component/device 13 201108365/optical device is a filter; then, for example, in Fig. 14d, the light (2) is a VCSEL, and the other optical component/optical device sub-device However, each of the optical elements/optical devices 123, 124, and 128 in Figures 14a to 14e may be partially or entirely replaced by an optoelectronic wafer. /, The optoelectronics referred to in the embodiments are disclosed in the prior art. And disposed on the base disclosed in the present invention, thereby constituting the photovoltaic element. However, the photovoltaic wafer structure disclosed below may be further employed. Figure 15a discloses an optoelectronic wafer 146 (which may replace the aforementioned optoelectronic wafer 26, 56, 86, %) Or 106) is a layer structure comprising a second polarity 15〇 Formed on the susceptor 13 having a first polarity by a remote crystal. The first polarity and the second polarity are different polarities, for example, the crystal layer shown in the figure: =, and may further include 1 The crystal layer or other function of the =1 seat 130 is an N+ pedestal. According to the above configuration, the present invention can also be used to form a 15 〇 3 N crystal layer to match the p pedestal. However, regardless of the combination of the form, the beauty The thickness of the seat 130 is much larger than the thickness of the crystal layer in the crystal layer structure I%. P ° m no has a plurality of layers (10) layer structure 150 series length ^ the first side 130a of the base 130; the second two have the same metal composition The pole 131 spoke 132 is formed on the same side of the crystal layer structure 150, for example, the upper side of the layer. Further, the highly doped conductive base 130 has a large thickness, between 1, 50 and l GGGum, and usually It falls between 7〇~施m, = the base of the county, so the thickness of the 13G can be sighed from the tens of times to hundreds of times of the traditional = degree, but with the progress of the system, the future It is possible to develop toward a thinner shape, and to take into account the thick support ^ = engraving technology to form an independent electrode 131 as a wire pad: engraved J The conductive pedestal 'can still maintain the electrical continuity of the wire mat. It is disclosed in the example of the M6 structure. (4) The second side of the conductive base 130 (the bottom surface of the M bird does not have the same material). In addition, the two electrodes 131 and 132 are structures having the same conductive metal, and the book is a Schottky metal, in particular, a metal structure stacked by Ti/Pt/Au, where * Ti( Having a preferred adhesion to the semiconductor) is typically 10-100 nm, Pt (which is a barrier metal, in some embodiments, may be absent), typically 50-200 nm, and Au (for subsequent bonding or bonding) It is usually 1 〇〇 2 〇〇〇 nm, but if combined with the plating process, the thickness of Au can reach several um or more. The above titanium metal may be replaced by chromium (Cr) such that the metal structure of the electrode 131 or 132 becomes Cr/Au or a Cr/Pt/Au structure. The thickness of the above crystal layer is: the P-type crystal layer is usually about 100 nm to 2000 _ nm, and the I-type crystal layer is usually about 5 〇〇 nm to 5000 nm °. The photovoltaic wafer structure of FIG. 15a can be specifically matched with FIGS. 2 and 3. , 4a, 4b, 5, 6, 7a, 7b, 8a, 8b, 9c, 9d, 9e, 10a, 10b (for example, when the auxiliary pin is in an open state), lib, 11c, 12a, 13b, 14a to 14e The disclosed base uses the low-cost N+ base 130 of the present invention with the same material because the bases are particularly insulated or have auxiliary pins that are not in the same plane as the other pins. The p-electrode 132 and the n-electrode 13i can be placed on the submount without the optical chip 146 being permeable to the carrier, thereby achieving the characteristics of reducing cost and component capacitance, and enhancing high-frequency response. • Referring to Fig. 15b, this embodiment differs from the embodiment shown in Fig. 15a in that an insulating layer 133 is located on one side of the conductive substrate 130, such as spin on glass (SOG). . This configuration can be applied to various bases of Figures 2 to He or a conventional pedestal (as shown by la or lc), in which case the use of the hetero-substrate (carrier 205) can be dispensed with, but can be retained as needed. Figure 15c, in addition to showing the PIN structure in more detail, adds a low dielectric constant layer (Low-K Layer) 134 bit below the P electrode, and is filled in the area where p epitaxy is left over, or low. The dielectric constant layer 134 is located between the two electrodes 13i, 132 'by which the capacitance value of the element can be lowered. The low dielectric constant layer can be replaced by a thick film. The optoelectronic wafer 146 disclosed in Figures 15a to 15c is designed for each of the bases made of insulating sheets 15 201108365 and the optoelectronic wafers 146 can be combined with the bases to form a novel and progressive optoelectronic component. The difference between Fig. 15d and Fig. 15c is that the bottom surface of the conductive substrate 130 has an insulating layer I%. Further, in the crystal layer structure of Figs. 15c to 15j, there is an insulating protective layer 137. Continuation of the embodiment of Figures 15c, 15d, the architecture of the optoelectronic chip may be the architecture shown in Figures 15e~15j'. wherein Figures 15e, 15f are disclosed as a diffuse type PlN architecture, which may have a low-medium Electrical constant layer 134 or thick layer; Figures 15g~15j disclose a mesa type PIN architecture configured with a low dielectric constant layer 134 or a thick layer, the dielectric constant or the thickness of the thick layer to reduce the capacitance value More than 20% are design standards. 15h to 15j, it is disclosed that there may be a dielectric layer 138 between the P layer and the j layer. The interfacial layer 138 is an undoped or low doped InP or InA1As layer. This is a gap energy material to reduce leakage current. The thickness is generally between (10) and 200 nm. The low dielectric constant layer 134 or thick layer described above may be a s〇G coating or a spin on dielectric (SOD) or CVD dielectric material. Figure 15k shows a photo-electric b-chip 160 structure that can be used for a photodiode (Ph〇t〇_Di〇de, pD). The optoelectronic wafer 16A includes a crystal layer structure 161 grown on a pedestal 162. The seed layer structure 161 comprises a P-I-N+ crystal layer, and the pedestal 162 is a semi-insulating pedestal or a non-conductive pedestal such as indium phosphide (lnp) or gallium arsenide (GaAs). * Second, the two electrodes 163 and 164 (or wire pads) are located on the same side of the crystal layer structure 161. Further, the two electrodes 163 and 164 may not be at the same level of height but two electrodes may be seen from the top view. The electrode (wire pad) 163 is electrically connected to the N+ crystal layer, and the other electrode J塾) 164 is electrically connected to the P crystal layer. In particular, the electrode 164 is configured to have a side wall configuration, that is, the side of the electrode 164 via the crystal layer structure 161, which is located above the pedestal 162. The other end is electrically connected to the p by a small portion of the area. Thus, this can effectively reduce the two electrodes (wire pads) between 163 and 164. 201108365 Further, an insulating layer 165 can be disposed on the electrode 164 and the crystal layer structure 161 and the pedestal 162. Second, the poles 163 and 164 may have the same metal architecture in accordance with the teachings of the previous embodiments. ~A Figures 16a, 16b show a PIN-TIA optoelectronic device architecture as an example. The 1st holder 142 has an insulating structure 144 (the structure of the structure of the insulating structure), and the photocell M6 is disposed in the insulating structure 144. And ίί," 30 positions on the surface of the insulating structure 144, thereby insulating the photovoltaic wafers I46 and 42. In addition, the two electrodes 13 132 are electrically connected by the wires 135 ^ and the amplifiers 130 (see Fig. 16b). According to the teachings of the above embodiments, the two electrodes and the sum may also be connected with at least a part of the electrical connection of the eight=; the front of the front is connected with the λ wire connected to the electrode pin' or by the wire through the electrode匕2匕 passive components, transimpedance amplifiers, capacitors, etc., indirectly connected to the connection 23; However, regardless of the direct connection of the electrode and the electrode of the electrode, the conductive base 13 used in the above embodiment is a one-and-a-half insulation, the conductive base; The base 142 is formed to eliminate the load _ demand, so that it has the function of reducing the cost and increasing the bandwidth, and: forming the electrode (3) to reach the i-path parameter = raw = achievable adjustment 4 wafer connection - 71 protruding insulation structure 144, that is, the foot 70, the light thunder, the H piece M6 has the insulating layer 133; therefore, the auxiliary word "the first electric 4146 lining insulation layer 133-shaped lying road, in addition to photoelectricity" 17 201108365 piece 146 and the base 142 also form an open circuit. The pedestal 13G has a P-type pedestal with a doped N-type phase and a doped P-type pedestal, and the PIN structure of FIGS. 15a to 15c, 1 and 17 will be reversed. The teaching of the above embodiment The base may be an inlaid metal plate body embedded with a metal disk body and a composite 2 j foot insulation structure; wherein the insulating insert forms an independent insulating component. The base may be a metal dragon, and the embedded metal disk of the insulating structure. $ combined with a plurality of electrode pins. The insulating structure is formed as an independent insulating layer. The non-metallic disk body is combined with a plurality of electrode pins, and the insulating structure is a part or all of the non-metal disk body. The number of electrode pins disclosed in the above embodiments is only For the purpose of description; the number of pins on the 2~ό can also be increased according to the requirements. Not = the exposed bases, including Τ (3. Architecture or lead frame f ' has an insulating structure, and can be formed with optoelectronic wafers Optoelectronic components, ί ^ 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 一半 一半 一半 一半 一半 一半 一半 一半 一半 一半 一半 一半 一半 一半 一半 一半 一半 一半 一半 PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN It is a conductive layer and the second side (bottom surface) of the pedestal has no the same material μ αα η electric earth seat 'the same metal layer structure as the Ρ electrode and the Ν electrode of the photovoltaic wafer and the same Located on the same side; alternatively, it can be s〇G or s〇D or CVD dielectric material on the second side (bottom surface) of the susceptor. The design of the wafer can be further combined with the design of Low K (BCB or SQG) material. Re-reducing the capacitance value Improve bandwidth. Dan
带r、Ϊ内f所提及的『斷路』、『絕緣』係指一端以正常的 =或^訊號輸入後，另一端不易取得此訊號之輸出。而本 ，明3及的Ρ_Ι·Ν+結構省略在某些實施例中存在的n緩衝 :二未攙，或低，雜的InP或InAlAs I ’不論是否具緩衝 0或增加/、它使元件特性更佳化的蠢晶層設計應仍屬本發^ S 18 201108365 均等的範圍。 另外本發明的絕緣構造的第一面可對應金屬盤體的第一 面成為凸出、齊平或凹低狀構造；同理本發明的絕緣構造 應金屬盤體的第二面成為凸出、齊平或凹人 本專利欲均等之範圍。 疋 ^卜本發^施例所提及的絕緣構造之最佳設計係位在 …、搭配之金屬健的幾何t ^。齡屬細上關設的開孔 可以位在與其搭配之非金屬盤體的幾何中心，但不以此為限。 槿的光ί晶片係以N型可導電基板搭配晶層 構xe的P sb層為例，·然而亦可等效的置換為p型可 晶層的光電晶片，所以p型基板搭配“ 層的構造亦屬本專利欲均等之範圍。 又本發明可依實際的產品需求，在可導電基 間配置有-異質基板(載體），藉此調整光電晶片驗置亥底座之 、^乃本發明之難實關以及設計圖式，惟較 以及没計®賴是糊綱’並非祕關 ，:凡以均等之技藝手段、或為下述「申請專 範圍而實施者，均不脫離本發明之範嘴而為申請 【圖式簡單說明】 圖la係習知ΡΙΝ-ΤΙΑ結構一的示意圖。 圖lb係習知PIN-TIA結構一的另一示意圖。 圖lc係習知PIN-TIA結構二的示意圖。 圖Id係習知PIN-TIA結構二的另一示意圖。 圖2係本發明第一實施例的平面示意圖。 圖3係本發明第一實施例的剖面示意圖。 明第-實施儀絕賴^端凸出且結合蓋體的 發㈣-實關晚緣構造—端町且結合蓋體t 1 9 t. Ο 201108365 圖5係本發明第二實施例的平面示意圖。 圖6係本發明第二實施例的剖面示意圖。 實關魏輯造題合蓋體的 、1^^發㈣二實施儀絕緣構造—端凹下且結合蓋體的 圖8a係本發明第三實施例具辅助 圖8b係本發明第三實施例之輔助接 且為斷路狀態的結構示賴。 &凸出承載光電晶片The "open circuit" and "insulation" mentioned in the r and the inner f are the ones that are input with a normal = or ^ signal, and the other end is not easy to obtain the output of this signal. However, the structure of Ρ Ι Ν Ν 省略 省略 省略 省略 省略 省略 省略 省略 省略 省略 省略 省略 省略 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构The design of the stupid layer with better characteristics should still be within the scope of this issue. In addition, the first surface of the insulating structure of the present invention may have a convex, flush or concave low structure corresponding to the first surface of the metal disk; and the insulating structure of the present invention is such that the second surface of the metal disk is convex, The scope of the patent is equal to the scope of the patent.最佳 ^卜本发^ The best design of the insulation structure mentioned in the example is in the metal geometry of .... Openings that are close to the age can be placed in the geometric center of the non-metallic disk that they are paired with, but not limited to. The 光 光 ί wafer is based on the N-type conductive substrate with the P sb layer of the crystal structure xe, but can also be equivalently replaced by the p-type crystallizable optoelectronic wafer, so the p-type substrate is matched with the “layer” The structure is also in the scope of equalization of the patent. The invention can be configured with a heterogeneous substrate (carrier) between the conductive substrates according to the actual product requirements, thereby adjusting the photoelectric wafer to detect the base of the sea, and the invention is Difficult to implement and design drawings, but it is not a secret. It is not a secret. Anyone who uses equal skill or the following "application for a specific scope does not deviate from the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS [FIG. 1] A schematic diagram of a conventional PIN-ΤΙΑ structure 1. Figure lb is another schematic diagram of a conventional PIN-TIA structure 1. Figure lc is a schematic diagram of a conventional PIN-TIA structure 2. Figure 1 is another schematic view of a conventional PIN-TIA structure 2. Figure 2 is a schematic plan view of a first embodiment of the present invention. Figure 3 is a schematic cross-sectional view of a first embodiment of the present invention. The hair that protrudes at the end and combines with the cover (four) - the real-time structure of the closed-end - Fig. 5 is a schematic plan view of a second embodiment of the present invention. Fig. 6 is a schematic cross-sectional view showing a second embodiment of the present invention. FIG. 8a is a third embodiment of the present invention, and FIG. 8b is an auxiliary structure of the third embodiment of the present invention and is in an open state. Projection optoelectronic wafer
本發明第三實關之_獅—灿 且作為電極狀態的結構示意圖。 戰九電日曰片 圖9a係本發明第四實施例的平面示意圖。 圖％係本發明第四實施例的剖面示意圖。 圖9c係本發明第五實施例的平面示意圖。 圖9d係本發明第五實施例的剖面示意圖。 圖^f系本發明根據第五實施例於絕緣構造上形成一凸部的剖 面不意圖。 σ 輔助接腳配置在絕緣構造轴 圖l〇a係本發明第六實施例結合一蓋體的結構示竟圖。 圖l〇b係本發明依第六實施例結合蓋體且一輔助、接腳组設在 絕緣構造軸向承載光電晶片的結構示意圖。 圖l〇c係本發明依第六實施例更具有支撐構造結合光學裝置 的結構示意圖。 圖11a係本發明第七實施例的結構示意圖。 圖lib係本發明根據第七實施例的結構使光電晶片位在金屬 薄膜開孔範圍且配置在非金屬盤體表面的結構示意圖。 圖11c係本發明根據第七實施例的結構使光電晶片位在非金 屬盤體之凸部端部的結構示意圖。 圖12a係本發明根據第七實施例的結構使底座具有延伸踏告 20 201108365 且結合一蓋體的結構示意圖。 ^ί/冰發日細絲七實❹赌構舰座具枝伸牆部 、·、σ 5盍體，以及具有辅助接腳的結構示意圖。 圖13a係本發明第八實施例且結合 圖13b係本發明第九實施例的外觀圖。構丁*』 本發明之底座與各電極接腳的組合形成連續片狀構 之雜與各電極接腳的組合形成連續片狀構 ί圖 13e縣發明之各雜接腳财平方向結合底座的組合示 =3f係本發明之各電極接腳以水平方向結合底座的組合示意 圖 圖 圖 ί圖淡係本發明之各電極接腳以水平方向結合底座的組合示 圖14c係本發明之絕绫播構一 =::=¾，構五。 圖15b係本發明之光電晶片結構二。 [: ί圖 13g #本發明之各電極接_水平方向結合底座的組合示 =3h係本伽之各電極接腳以水平方向結合底座的組合示 =3i係本發明之各電極接_水平方向結合底座的組合示意 1¾•係本㈣之各電極接腳财平額結合底座的組合示意 21 201108365 圖15c係本發明之光電晶片結構三。 圖15d係本發明之光電晶片結構四。 圖15e係本發明之光電晶片結構五。 圖15f係本發明之光電晶片結構六。 圖15i係本發明之光電晶片結構七。 圖15j係本發明之光電晶片結構八。 圖15k係本發明之光電晶片結構九。 圖16a係本發明之光電晶片結構一與底座結合的示意圖。 圖16b係本發明之光電晶片結構一與底座、轉阻放大器結合的The third embodiment of the present invention is a schematic diagram of the structure of the lion-can and the electrode state.九九电日片 Figure 9a is a plan view of a fourth embodiment of the present invention. Figure % is a schematic cross-sectional view showing a fourth embodiment of the present invention. Figure 9c is a plan view showing a fifth embodiment of the present invention. Figure 9d is a schematic cross-sectional view showing a fifth embodiment of the present invention. Fig. 15 is a cross-sectional view showing a convex portion formed on an insulating structure according to the fifth embodiment of the present invention. σ Auxiliary pin arrangement in the insulating structure axis FIG. 1A is a structural diagram showing a structure in which a cover body is combined with a cover body according to a sixth embodiment of the present invention. Figure 〇b is a schematic view showing the structure of the present invention in combination with the cover body and an auxiliary and pin assembly in the axial direction of the insulating structure. Figure 1〇c is a schematic view showing the structure of the present invention having a support structure in combination with an optical device according to the sixth embodiment. Figure 11a is a schematic view showing the structure of a seventh embodiment of the present invention. Figure lib is a schematic view showing the structure of the present invention in accordance with the structure of the seventh embodiment in which the photovoltaic wafer is positioned in the opening of the metal film and disposed on the surface of the non-metallic disk. Fig. 11c is a schematic view showing the structure of the photovoltaic wafer at the end of the convex portion of the non-metallic disk according to the structure of the seventh embodiment of the present invention. Figure 12a is a schematic view showing the structure of the seventh embodiment of the present invention with the base having an extension 20 201108365 and incorporating a cover. ^ί/冰发日丝丝七实❹ 构 构 舰 具 具 具 枝 、 、 、 、 、 、 、 、 σ σ σ σ σ 。 σ 。 。 。 σ 。 。 。 。 。 。 Figure 13a is an eighth embodiment of the present invention and in conjunction with Figure 13b is an external view of a ninth embodiment of the present invention. The combination of the base and the electrode pins of the present invention forms a continuous sheet-like structure and a combination of the electrode pins to form a continuous sheet structure. The 13a county invention has various miscellaneous joints in the same direction. Combination display = 3f is a schematic diagram of the combination of the electrode pins of the present invention in the horizontal direction, and the combination of the electrode pins of the present invention in the horizontal direction. FIG. 14c is a perfect broadcast of the present invention. Construct one =::=3⁄4, construct five. Figure 15b is a photovoltaic wafer structure 2 of the present invention. [: Fig. 13g # Combination of each electrode of the present invention _ horizontal direction combined with the base = 3h is the combination of the electrode pins of the local gamma in the horizontal direction combined with the base = 3i is the electrode of the present invention _ horizontal direction The combination of the combination of the bases indicates that the combination of the electrode pins of the present invention (4) is combined with the base. 21 201108365 Fig. 15c is a photovoltaic wafer structure 3 of the present invention. Figure 15d is a photovoltaic wafer structure 4 of the present invention. Figure 15e is a photovoltaic wafer structure 5 of the present invention. Figure 15f is a photovoltaic wafer structure 6 of the present invention. Figure 15i is a photovoltaic wafer structure 7 of the present invention. Figure 15j is a photovoltaic wafer structure VIII of the present invention. Figure 15k is a photovoltaic wafer structure 9 of the present invention. Figure 16a is a schematic view of the photovoltaic wafer structure of the present invention in combination with a base. Figure 16b shows the structure of the optoelectronic wafer of the present invention combined with a base and a transimpedance amplifier.
示意圖。 圖17係本發明之光電晶片結構二與底座結合的示意圖。 【主要元件符號說明】schematic diagram. Figure 17 is a schematic view showing the combination of the photovoltaic wafer structure 2 of the present invention and the substrate. [Main component symbol description]
10底座 14d接地接腳 19第二面 24a第一端 26a電極 3〇光電元件 34光學裝置 44a〜44c接腳 54絕緣構造 55凸部 60光電元件 7〇輔助接腳 81金屬盤體 83絕緣構造 832延伸牆部 834蓋體 86光電晶片 89開孔 12金屬盤體 16非導電材料 22嵌孔 24b第二端 26b電極 32蓋體 40底座 48第二面 54a第一端 56光電晶片 62蓋體 71第一位置 81a第二面 83a第一端 832a 缺口 i4a〜14c電極接腳 18第一面 24絕緣構造 26光電晶片 28a〜28b導線 32a開孔 42金屬盤體 52嵌孔 54b第二端 57凹空 62a開孔 64光學裝置 72第二位置 82嵌孔 831凸部 833開放口 84a〜84c電極接腳 85電的良導靜 87金屬薄膜 88凹空 92金屬盤體 93絕緣構造 22 20110836510 base 14d grounding pin 19 second surface 24a first end 26a electrode 3 〇 photovoltaic element 34 optical device 44a~44c pin 54 insulation structure 55 convex part 60 photoelectric element 7 〇 auxiliary pin 81 metal disk 83 insulation structure 832 Extension wall portion 834 cover 86 photovoltaic wafer 89 opening 12 metal disk 16 non-conductive material 22 perforation 24b second end 26b electrode 32 cover 40 base 48 second surface 54a first end 56 optoelectronic chip 62 cover 71 A position 81a second face 83a first end 832a notch i4a-14c electrode pin 18 first face 24 insulation structure 26 optoelectronic wafer 28a-28b wire 32a opening 42 metal disk 52 hole 54b second end 57 recess 62a Opening 64 Optical Device 72 Second Position 82 Insert 831 Projection 833 Open Port 84a~84c Electrode Pin 85 Conductive Conductor Static 87 Metal Film 88 Hollow 92 Metal Disc 93 Insulation Structure 22 201108365
123光學元件/光學裴置 124光學元件/光學裝置125表面 205異質基板/載體206半絕緣基板 128光學元件/光學裝置13〇可導電基違 93a支撐構造 95蓋體 104a〜l〇4c接腳 107金屬薄膜 110延伸牆部 114光學裝置 122端面 127凹空 130a第一侧 132電極 135導線 138介面晶層 146光電晶片 161晶層構造 164電極 201底座 93b光學襞置 96光電晶片 1〇5電的良導體 108開孔 111開放口 120絕緣構造 130b第二側 133絕緣層 136轉阻放大器 142底座 150晶層構造 162基座 165絕緣層 202轉阻放大器 94延伸牆部 1〇〇非金屬盤體 106光電晶片 109凸部 112蓋體 121柱體 126柱體 131電極 134低介電常數層 137絕緣保護層 144絕緣構造 160光電晶片 163電極 200光電晶片 203、204 電極123 optical element / optical device 124 optical element / optical device 125 surface 205 heterogeneous substrate / carrier 206 semi-insulating substrate 128 optical element / optical device 13 〇 conductive base violation 93a support structure 95 cover body 104a ~ l 〇 4c pin 107 Metal film 110 extension wall portion 114 optical device 122 end surface 127 recess 130a first side 132 electrode 135 wire 138 interface crystal layer 146 photoelectric wafer 161 crystal layer structure 164 electrode 201 base 93b optical device 96 photoelectric chip 1 〇 5 electric good Conductor 108 opening 111 opening 120 insulating structure 130b second side 133 insulating layer 136 transimpedance amplifier 142 base 150 crystal layer structure 162 pedestal 165 insulating layer 202 transimpedance amplifier 94 extended wall portion 1 non-metallic disk body 106 photoelectric Wafer 109 convex portion 112 cover body 121 cylinder 126 cylinder 131 electrode 134 low dielectric constant layer 137 insulating protective layer 144 insulating structure 160 photoelectric wafer 163 electrode 200 photoelectric wafer 203, 204 electrode
23twenty three