JP2005129689A - Semiconductor photo detector and light receiving module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor photo detector and light receiving module which can be applied with sufficient bias voltage even when a strong optical signal is inputted, is stable and is reduced in noise. <P>SOLUTION: The semiconductor photo detector is such that a photo diode 51 for converting an optical signal to an electric signal and a resistance element 53 inserted in series to the photo diode 51 are integrated together, and is equipped with a bypass diode 52 connected in parallel to the resistance element 53. The photo diode 51 has a multilayer structure wherein an n<SP>+</SP>-InGaAs layer, an i-InGaAs layer, and a p<SP>+</SP>-InGaAs layer are laminated in order on an InP substrate. The bypass diode 52 has the same multilayer structure, and is simultaneously formed in a manufacturing process of the photo diode 51. The resistance element 53 or a capacitive element 54 is integrally formed on the InP substrate. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor light receiving element that receives an optical signal and converts it into an electrical signal, and an optical receiving module using the same.

With the recent development of optical communication, communication optical devices are required to have high transmission speed, high reliability, high integration, and the like. In a semiconductor optical device, for example, as disclosed in Patent Document 1, a technique is known in which a PIN photodiode having a mesa structure formed on an InP substrate and a resistor, a capacitor, or another semiconductor element are integrated. . In this Patent Document 1, for example, a structure is shown in which one end of a built-in resistor integrated with a cathode of a photodiode is connected, and a node at this connection point is drawn out to the outside of the element. By connecting a bypass capacitor to the externally drawn electrode, a built-in resistor and an external capacitor constitute a smoothing circuit, and stabilization of the bias power supply supplied to the photodiode and low noise are realized.
JP-A-9-213988

  In optical communication technology, the telecom field (long-distance optical communication field) is going to exceed 10 Gbps and the datacom field is going to exceed 1 Gbps. Along with such an increase in transmission speed, the weakening of optical signals (higher sensitivity of the light receiving device) is also progressing. In order to cope with the weakening of the optical signal and the high-speed response of the optical signal, the light receiving area of the light receiving element is reduced to reduce the junction capacitance and increase the response speed of the light receiving element.

  In order for the light receiving device to respond accurately and stably to such weakening and high speed of the optical signal, the bias power source of the light receiving element must be highly stabilized and reduced in noise. In the photodiode disclosed in Patent Document 1, the resistance value of the built-in resistor in the light receiving element is increased, and the time constant of the smoothing circuit formed by the resistor and the external capacitor is increased to be supplied to the light receiving element. The bias power supply is stabilized.

However, when the resistance value of the built-in resistor is increased, the voltage drop caused by the photocurrent generated in the light receiving element is also increased. As a result, when a strong optical signal is input, a sufficient bias voltage is not applied to the light receiving element. When a sufficient bias voltage is not applied, the light / electric conversion efficiency of the light receiving element is lowered, and the S / N ratio (signal / noise ratio) is deteriorated.
The present invention has been made in view of the above circumstances, and provides a stable and low-noise semiconductor light-receiving element and an optical receiver module capable of applying a sufficient bias voltage even when a strong optical signal is input. Is an issue.

A semiconductor light receiving element according to the present invention is a semiconductor light receiving element in which a photodiode for converting an optical signal into an electric signal and a resistance element inserted in series with the photodiode are integrated, and a bypass connected in parallel to the resistance element. The configuration includes a diode. This photodiode is formed with a layer structure in which an N ⁺ -InGaAs layer, an i-InGaAs layer, and a P ⁺ -InGaAs layer are sequentially stacked on an InP substrate, and a bypass diode is also formed with the same layer structure. Are formed at the same time. In addition, the resistor element or the capacitor element is integrated and integrated on the InP substrate.
An optical receiver module according to the present invention is mounted on a stem base together with a preamplifier integrated circuit that amplifies an electric signal by placing the above-described semiconductor light receiving element on a die cap capacitor, and the light receiving surface of the semiconductor light receiving element It is set as the structure which is equipped with the condensing lens which condenses these, and accommodates in a housing | casing.

In the present invention, even if the resistance value of the built-in resistor is increased and the time constant of the smoothing circuit is increased by providing a bypass diode connected in parallel with the built-in resistor, it flows through the built-in resistor when a strong optical signal is input. The current can be bypassed. As a result, a voltage drop due to the built-in resistor can be suppressed to a forward voltage (about 0.7 to 0.8 V) of the bypass diode, and a sufficient bias voltage can be applied to the photodiode.
Further, since the bypass diode can be formed simultaneously with the manufacturing process of the photodiode by adopting the same layer structure as that of the photodiode, the bypass diode can be provided without requiring an extra process for the bypass diode. it can.

  An embodiment of the present invention will be described with reference to the drawings. FIG. 1A is a plan view of a semiconductor light receiving element according to the present invention, and FIG. 1B is a diagram illustrating a circuit configuration in the semiconductor light receiving element. In the figure, 51 is a photodiode (PD element), 52 is a bypass diode (BD element), 53 is a resistive element, 54 is a capacitive element, 60a, 60b, 60c and 60d are electrode pads, and 100 is a semiconductor light receiving element.

  The semiconductor light receiving element 100 according to the present invention is, for example, a square chip having a side of about 450 μm, and a photodiode 51 (hereinafter referred to as a PD element) having a light receiving diameter of about 100 μmφ is formed at the center, and adjacent thereto. A bypass diode 52 (hereinafter referred to as a BD element) having a diameter of about 30 μmφ is formed. At the four corners of the chip, electrode pads 60a to 60d that form electrical connections with external elements are formed, and a resistive element 53 and a capacitive element 54 are formed between them. The PD element 51 is preferably provided in the center of the chip from the viewpoint of optical coupling efficiency, but the position, shape, size, etc. of other elements are not limited as long as the function of the PD element 51 is not impaired.

  The planar shape of the PD element 51 is preferably rectangular from the viewpoint of the manufacturing process. However, since the cross section of the incident beam of light is generally circular, if the light receiving surface of the PD element 51 is rectangular, its four corners are optical. Inactive region. On the other hand, as a matter of course, each of the semiconductor layers constituting the PD element is also doped with impurities as necessary in the four corner regions, resulting in an increase in junction capacitance. For this reason, only the junction capacitance is increased, and an optically inactive region is generated. Therefore, it can be said that at least the light receiving surface of the PD element 51 is preferably circular.

  The electrode pads 60 a to 60 d are, for example, 60 d electrode pads connected to the anode of the PD element 51, and electrode pads commonly connected to the cathode of the PD element 51 and one of the capacitor element 54 and one of the resistance elements 53. Is 60b. Further, an electrode pad that is commonly connected to the anode of the BD element 52 and the other of the resistance element 53 is 60c, and an electrode pad that connects the other of the capacitive element 54 is 60a.

  By allocating the connection between each element and the electrode pad as described above, a circuit configuration as shown in FIG. 1B is obtained. That is, the resistance element 53 and the BD element 52 are connected in parallel, and the cathode side is also connected in common with the electrode pad 60 b on the cathode side of the PD element 51. By connecting the commonly connected electrode pad 60b to an external external bypass capacitor, a smoothing circuit can be formed with the resistor element 53 in the chip.

  On the other hand, the electrode pad 60d on the anode side of the PD element 51 is connected to a preamplifier of an external circuit, and a photocurrent is taken out by photocarriers generated in the PD element corresponding to the optical signal. An external bias power source is connected to the electrode pad 60 c where one of the resistance elements 53 and the anode side of the BD element 52 are commonly connected, and a predetermined bias voltage is applied to the PD element 51. On the other hand, the electrode pad 60a to which the capacitive element 54 is connected is also connected to an external circuit. Normally, a smoothing circuit excellent in high-frequency characteristics can be configured by the resistance element 53 which is grounded.

  It is also possible to take out a signal corresponding to the optical signal input from the electrode pad 60a connected to the capacitive element 54. That is, when taking out a signal from the electrode pad 60d, the PD element 51 can be used as a photoconductive device, and when taking out a signal from the electrode pad 60a via the capacitive element 54, It can be used as a photoelectric device (Photo Voltaic Device). When used as the latter photoelectric device, the electrode pad 60d on the anode side of the PD element 51 may be grounded, and a change in equivalent resistance due to input light may be detected as a ratio to the integrated resistance.

Next, the structure of each element will be described with reference to FIGS. 2A is a cross-sectional view illustrating a structural example of the PD element 51 and the BD element 52 according to the present invention, FIG. 2B is a cross-sectional view illustrating another example, and FIG. 3 illustrates a structural example of a resistance element. FIG. 4 is a cross-sectional view illustrating an example of the structure of the capacitor. In the figure, 2 is a substrate, 3 and 3 'are N ⁺ layers, 4 and 4' are i layers, 5 and 5 'are P ⁺ layers, 6 is a protective film, 7a, 7a', 7b, and 7c are electrodes, 8 , 11 is an insulating film, 9a, 9b, 12 are wiring conductors, and 10 is a thin film metal resistance.

As shown in FIG. 2A, the substrate 2 is, for example, a semi-insulating InP substrate doped with iron (Fe), on which a first mesa-shaped N ⁺ layer 3 and an i layer are formed. 4. The second mesa-shaped P ⁺ layer 5 is laminated in a three-layer structure. The first mesa-shaped N ⁺ layer 3 is formed of N ⁺ -InGaAs lattice-matched to InP of the substrate. The i layer 4 is formed of i-InGaAs and is a layer to which impurities are not added intentionally, and is usually N-type and has a carrier concentration of about 10 ¹⁴ cm ⁻³ due to the influence of residual impurities. The second mesa-shaped P ⁺ layer 5 is made of, for example, P ⁺ -InGaAs doped with zinc (Zn), and the mesa diameter is smaller than the first mesa diameter.

The entire surfaces of the N ⁺ -InGaAs layer 3, i-InGaAs layer 4, and P ⁺ -InGaAs layer 5 are protected by an i-InP protective film 6. The i-InP protective film 6 has the same characteristics as the i-InGaAs layer 4. The protection of the surface of these three layers by the protective film 6 of InP is because the characteristics of the bonding interface between the InGaAs material and the inorganic insulating film, particularly the silicon nitride (SiN) film, are poor, and many interface states are generated there. This is to prevent a leak current between the N ⁺ -InGaAs layer 3 and the P ⁺ -InGaAs layer 5 from being generated through these interface states. The optical signal enters the upper surface of the second mesa through the InP protective film 6, passes through the P ⁺ -InGaAs layer 5 with almost no attenuation, and is absorbed by the i-InGaAs layer 4.

Electron-hole pairs are generated by the light absorbed by the i-InGaAs layer 4, and a reverse bias (N ⁺ -InGaAs layer 3 is at a high potential) is applied between the P ⁺ -InGaAs layer 5 and the N ⁺ -InGaAs layer 3. By applying voltage, electrons drift to the N ⁺ -InGaAs layer 3 and holes drift to the P ⁺ -InGaAs layer 5 to generate a photocurrent. If a reverse bias is applied between the P ⁺ -N ⁺ layers, that is, a bias voltage that makes the N ⁺ layer 3 have a high potential, this electric field is almost consumed by the i-layer 4. The P ⁺ layer 5 side of the i-layer 4 is at a low potential and the N ⁺ layer 3 side is at a high potential, so that the photocarriers generated in the i-layer 4 reach each electrode to be accelerated, enabling high-speed operation. Become.

The diameter of the second mesa is set to about 30 μmφ to several hundred μmφ. In general, the P ⁺ -InGaAs layer 5 and the N ⁺ -InGaAs layer 3 constitute a parallel plate type capacitor with the i-InGaAs layer 4 interposed therebetween. This capacitor is a parasitic capacitance that prevents high-speed operation of the device. Therefore, when this mesa diameter is increased, coupling with incident light becomes easy, but the parasitic capacitance increases accordingly, and it becomes impossible to respond to a high-speed optical signal. However, when the mesa diameter is smaller than 30 μmφ, the optical coupling efficiency is remarkably lowered, and the arrangement of optical components for condensing and the restriction on the positional accuracy become severe.

  Openings are provided in the InP protective film 6 at the top of the second mesa corresponding to the anode side of the PD element 51 and the top of the first mesa corresponding to the cathode side, and electrodes are respectively formed in the openings. Is done. Hereinafter, an electrode provided on the anode side of the PD element 51 is referred to as a P electrode 7a, and an electrode provided on the cathode side is referred to as an N electrode 7b. As the N electrode 7b, an alloy of AuGe / Ni is formed, and the P electrode 7a is formed in a ring shape, and a laminated metal of Pt / Ti / Pt / Au is used.

  The outer surface of the InP protective film 6 is covered with an SiN insulating film 8 to protect the entire PD element 51. The thickness of the SiN insulating film 8 is preferably about 100 nm to 200 nm, and if it is thicker than this, a protective function such as preventing moisture from entering from the outside is enhanced, but the thermal expansion coefficient between the insulating film 8 and the semiconductor material is high. If they are different, mechanical stress is generated between the two materials, which adversely affects the light receiving characteristics of the PD element 51. Further, due to the impurities in the SiN insulating film 8, a part of incident light may be absorbed and the sensitivity of the PD element 51 may be deteriorated.

The BD element 52 in the present invention is preferably formed with the same layer structure as the PD element 51. However, it is desirable that the diameter of the BD element 52 be about 30 μmφ and smaller than the PD element 51. That is, the InP substrate 2 is laminated in a three-layer structure of a first mesa-shaped N ⁺ layer 3 ′, an i layer 4 ′, and a second mesa-shaped P ⁺ layer 5 ′. The first mesa-shaped N ⁺ layer 3 ′ is formed of N ⁺ -InGaAs lattice-matched to InP of the substrate. The i layer 4 ′ is formed of i-InGaAs and is a layer to which impurities are not added intentionally, and is usually N-type and has a carrier concentration of 10 ¹⁴ cm ⁻³ due to the influence of residual impurities. The second mesa-shaped P ⁺ layer 5 ′ is formed of zinc (Zn) -doped P ⁺ -InGaAs, and the mesa diameter is smaller than the first mesa diameter.

  By making the layer structure of the BD element 52 the same as the stacked structure of the PD element 51 and the material, thickness, carrier concentration, etc., the BD element 52 is simultaneously formed in the manufacturing process of the PD element 51. This eliminates the need to add a new manufacturing process for the BD element 52. Further, unlike the PD element 51, the BD element 52 does not need to react to incident light. Rather, it is not preferable that excessive carriers are generated by the incident light to generate noise components. For this reason, the diameter of the second mesa is reduced, and the P electrode 7a ′ is formed on the entire surface of the mesa so as to completely block the incidence of light and to prevent reaching the i-InGaAs layer 4 ′. To.

  FIG. 2B is a structural example in which only the PD element 51 and the BD element 52 are prevented from becoming high. In the structure of FIG. 2A, the i-InGaAs layer 4 is formed thick because it absorbs light, and is generally about 2 μm. Since other resistor elements and capacitor elements to be described later are about several hundred nm, only the PD element 51 and the BD element 52 protrude, which is not preferable from the viewpoint of chip protection. Accordingly, in FIG. 2B, a concave portion having a depth of about 2 μm is first formed on the thick InP substrate 2, and a PD element 51 and a BD element 52 (BD element is omitted in the figure) are formed in the concave portion. Is. The layer structure of the PD element 51 is the same as that in the case of FIG. The concave portion can be easily formed by ordinary wet etching. By using this configuration, the height of the PD element 51 and the BD element 52 can be kept constant as a whole, and can be prevented from protruding.

  In FIG. 2B, the wiring to the electrode 7a of the PD element 51 is an air bridge wiring as shown by the wiring conductor 9a. When air bridge wiring is not used, the wiring is led to the bottom of the recess along the side wall of the PD element 51 in the form shown by the wiring conductor 9b, and then lifted to the substrate surface along the side wall of the recess, It is drawn to the electrode pads (see FIG. 1) provided at the four corners.

However, once the wiring is pulled down to the bottom of the concave portion, the wiring length becomes long, and the bottom of the concave portion is in a state where the N ⁺ -InGaAs layer 3 is covered with the InP protective film 6 and the insulating film 8. Furthermore, since the N ⁺ -InGaAs layer 3 is electrically grounded via a bypass capacitor, if the wiring passes over this, it is also affected by a large parasitic capacitance, and passes the signal at high speed. It is an unsuitable structure. Therefore, by using an air bridge wiring and having a structure in which the wiring does not pass through the bottom of the recess, it is possible to provide a semiconductor light receiving element that can sufficiently cope with high-speed signals.

  FIG. 3 is a diagram illustrating a cross-sectional structure of the resistance element 53. An insulating film 8 is formed on the InP substrate 2, and a thin film metal resistor 10 having a thickness of about 30 nm made of, for example, NiCrSi is formed thereon. The insulating film 8 is the same as the inorganic insulating film 8 that covers the PD element 51 and the like. On the thin film metal resistor 10, an insulating film 11 different from the insulating film 8 is formed. The thickness of the insulating film 11 is preferably about 200 nm, and the sheet resistance of the thin film metal resistor 10 is about 120Ω / □. In addition to NiCrSi, rare earth metal silicide compounds such as NiCr, Ti, W, Ta, and Mo can also be used as the material of the thin film metal resistor 10. Further, a pure metal such as Al can be used as the thin film metal resistor 10 if it is made an extremely thin film of 10 nm or less.

  A wiring conductor 12 is formed on the thin film metal resistor 10. The wiring conductor 12 is made of, for example, a multilayer metal of Ti / Pt / Au, and the thickness of the metal layer is, for example, about 100 nm / 40 nm / 200 nm, respectively. Since the thin film metal resistor 10 has a small sheet resistance value, when a large resistance value is required, metal resistors having a large aspect ratio can be obtained in a staggered manner. In the example shown in FIG. 1A, four resistance elements having a plurality of aspect ratios are electrically connected by the wiring conductor 12 to obtain a resistance of about 3 kΩ.

  FIG. 4 is a diagram showing a cross-sectional structure of the capacitive element 54. An opening is provided in the insulating film 8 on the InP substrate 2, and a C electrode 7c is formed in the opening. This electrode serves as the lower electrode of the capacitive element 54, and is formed of the same material as that of the P electrode 7a of the PD element 51 at the same time as the P electrode 7a is formed. On the C electrode 7c, another insulating film 11 having a thickness different from that of the insulating film 8 and having a thickness of about 200 nm is formed. This insulating film 11 is the same as the insulating film 11 covering the thin film metal resistor 10 of FIG. 3, and is formed at the same time. The insulating film 11 is provided with an opening, and the wiring conductor 12 is electrically connected to the C electrode 7c through the opening.

Further, another wiring conductor 12 is also formed in a region facing the C electrode 7c with the insulating film 11 interposed therebetween so as not to contact the wiring conductor 12. A parallel plate type capacitive element 54 is formed by the three-layer structure of the C electrode 7 c, the insulating film 11, and the wiring conductor 12. The capacitance value is determined by the dielectric constant and thickness of the insulating film 11. When SiN is used as the insulating film 11, the dielectric constant is a value of about 3.8 to 4.0, and the thickness is also about 200 nm because it also serves as an insulation for wiring. Under these conditions, a capacitive element of about 0.18 fF / μm ² can be fabricated in the chip of the semiconductor light receiving element.

  Although depending on the size of the chip, it is possible to integrate up to a pF (several tens of μm square) MIM capacitor (Metal-Insulator-Metal capacitor) in this form. Since both the capacitive element 54 and the resistive element 53 described with reference to FIG. 3 are integrated in the chip, the wiring length of both can be shortened (about several tens of nanometers), and smoothing excellent in high frequency characteristics can be achieved. A circuit can be constructed.

  As described above, by integrating and integrating the PD element 51, the BD element 52, the resistor element 53, and the capacitor element 54 as a semiconductor light receiving element in one chip, a semiconductor that can stably and accurately respond to weak and high-speed optical signals. A light receiving element can be obtained. Next, an outline of a method for manufacturing the above-described semiconductor light receiving element will be described.

  5 to 6 are diagrams illustrating an example of a method for manufacturing the semiconductor light receiving element illustrated in FIG. 2A, and FIG. 7 is a diagram illustrating a manufacturing example corresponding to the example of FIG. In the drawings showing these manufacturing examples, the formation of the BD element 52 is omitted because it is formed in the same form as the PD element 51 at the same time. The reference numerals in the figure are the same as those used in FIGS.

FIG. 5A is a diagram for explaining an example of manufacturing a semiconductor substrate. As the substrate, a semi-insulating InP substrate 2 doped with 0.7 to 0.8 wtppm of iron (Fe) is used. On this semi-insulating InP substrate 2, an N ⁺ -InGaAs film 3A doped with 5.0 × 10 ¹⁸ cm ^{−3 of} Si has a thickness of 300 nm, and an i-InGaAs film 4A not intentionally doped with impurities has a thickness of about A P ⁺ -InGaAs film 5A doped with 2 μm and 2.0 × 10 ¹⁹ cm ^{−3 of} Zn is sequentially grown to a thickness of 300 nm. For this film growth, a known method such as OMVPE (Organometallic Vapor Phase Epitaxy) can be used.

  In the case of manufacturing the element of the example of FIG. 2B, a recess is formed in advance in the region where the PD element and the BD element are manufactured on the thick InP substrate 2 by a depth of about 2 μm. Etching can use wet etching to prevent the side surfaces of the recesses from becoming steep with respect to the substrate surface. And after forming a recessed part in the board | substrate 2, the film | membrane of each layer mentioned above is made to grow in order on a substrate surface.

After the semiconductor substrate having the layer structure shown in FIG. 5A is manufactured, an etching mask is formed on the P ⁺ -InGaAs film 5A with a photoresist or the like, and the second substrate is formed as shown in FIG. A mesa is formed by etching. The shape of the mask is preferably circular or octagonal as shown above. The diameter of the mesa is determined by the relationship between the light receiving efficiency and the response speed of the PD element, but in order to obtain a response speed of 10 Gbps, 30 μmφ to 50 μmφ is generally used.

In the etching, the etching time is adjusted so as to remove both the P ⁺ -InGaAs film 5A and the i-InGaAs film 4A, that is, remove all the i-InGaAs film 4A in the region other than the second mesa. If i-InGaAs remains, the contact resistance with the N electrode 7b formed on the N ⁺ -InGaAs layer 3 increases. As the etchant, a well-known phosphoric acid-based etchant (mixed solution of phosphoric acid, hydrogen peroxide solution, and water) can be used.

  After removing the etching mask for forming the second mesa, as shown in FIG. 5C, an i-InP protective film 6A not intentionally doped with an impurity having a thickness of about 200 μm is formed on the entire surface of the substrate. . This protective film 6 covers and protects the entire top and sides of the second mesa. When a protective film other than a semiconductor is used for InGaAs that constitutes a mesa, a large number of interface states are formed at the interface, and a leak current is generated through this level. By using the i-InP protective film 6, the generation of interface states can be suppressed.

After forming the InP protective film 6A, an etching mask is formed so as to cover the entire second mesa, and the N ⁺ -InGaAs film 3A is etched to form the first mesa. By this etching, all of the N ⁺ -InGaAs film 3A other than the PD element and the BD element portion is removed, so that the PD element and the BD element are electrically insulated. In the example of FIG. 2B, all of the N ⁺ -InGaAs film other than the substrate recess is removed in this step. After the first mesa is formed and an etching mask is formed, as shown in FIG. 5D, the whole is covered with a SiN insulating film 8 having a thickness of about 200 nm to provide protective insulation. Since the SiN insulating film 8 can be formed at a relatively low temperature by using a known method such as plasma CVD, the influence on the PD element can be reduced.

  As described above, the main part of the PD element and the BD element is manufactured through the etching twice and the formation of the protective film 6 and the insulating film 8. Thereafter, an electrode, a wiring conductor and the like are produced. FIG. 6 corresponds to the semiconductor light receiving element of FIG. 2A, and FIG. 7 corresponds to the semiconductor light receiving element of FIG.

As shown in FIG. 6A, first, in order to form the N electrode 7b, a resist pattern having an opening in the N electrode formation region is formed. In accordance with this pattern, the SiN insulating film 8 is etched by a method such as RIE (Reactive Ion Etching), and then the InP protective film 6 is etched with a chlorine-based solution while leaving the above pattern, and the N ⁺ -InGaAs layer 3 N The surface of the electrode formation region is exposed. An AuGe eutectic alloy is deposited as a raw material on this exposed surface and the entire patterned resist surface, and then Ni is continuously deposited. The thickness of each metal is 100 to 150 nm for AuGe and 30 to 50 nm for Ni. After vapor deposition, the resist pattern is removed to lift off the metal adhering to the resist, leaving the metal pattern only in the opening. Thereafter, heat treatment (alloying) is performed at about 400 ° C. for 1 minute, whereby the N electrode 7b is formed.

  Next, as shown in FIG. 6B, in order to form the P electrode 7a, a resist pattern having an opening in the P electrode formation region at the top of the second mesa is formed. At this time, not only the pattern of the P electrode 7a but also a pattern in which an opening is provided in a region of an electrode serving as a lower electrode of the capacitive element (hereinafter referred to as C electrode 7c). Based on this resist pattern, the SiN insulating film 8 and the InP protective film 6 are etched. A method such as RIE can be used for etching the SiN insulating film 8, and a chlorine-based etchant can be used for etching the InP protective film 6.

After an electrode opening is formed in the SiN insulating film 8 and the InP protective film 6, a multilayer metal of Pt / Ti / Pt / Au is used as a buried P electrode 7a in the opening by a lift-off method. This multi-layer metal exhibits ohmic characteristics for P ⁺ -InGaAs without being subjected to heat treatment. At the same time, since the metal is mainly Au, it can be used as one C electrode 7c of the MIM capacitor (capacitance element).

  Next, as shown in FIG. 6C, a thin film metal resistor 10 is formed. A resist pattern having an opening is formed in the thin film metal resistance forming region, and the underlying SiN insulating film 8 is etched to a depth of about 30 nm to 50 nm. Since the entire thickness of the SiN insulating film 8 is about 200 nm, the depth of this etching is not a problem as long as the etching amount is such that the InP substrate 2 under the SiN insulating film is not exposed. Thereafter, with the resist pattern remaining, a metal resistance material such as NiCrSi is applied by a well-known thin film technique, and patterning is performed by lift-off to obtain the thin film metal resistance 10.

  Thus, the fabrication of the element integrated in the semiconductor light receiving element chip is completed. Thereafter, as shown in FIG. 6D, a wiring conductor 9c for electrically connecting each element and an electrode pad (not shown) for taking out a signal to the outside or applying a bias voltage from the outside are formed. To do. First, a second SiN insulating film 11 different from the insulating film 8 is formed to a thickness of about 300 nm on the entire surface by a known method such as plasma CVD. A resist pattern having openings in the electrical connection regions of the N electrode 7b of the PD element and the BD element, the thin film metal resistor 10 and the C electrode 7c of the capacitor element is formed on the SiN insulating film 11. Then, the SiN insulating film 11 is etched according to the pattern by a method such as RIE, so that the surfaces of the electrodes and the electrical connection regions are exposed.

  Thereafter, after removing the resist once, the wiring conductor 12 is formed as shown in FIG. The resist at this time is preferably a multilayer resist because the wiring conductor 12 is formed by a lift-off method. That is, a shape in which the lower layer resist is undercut with respect to the upper layer resist is preferable. In accordance with the etched pattern, the wiring conductor 12 having a thickness of each of Ti / Pt / Au layers of 100 nm / 50 nm / 300 nm is lifted off by the above-described method. These wiring conductors 12 also serve as the lead wiring for the resistance element 53, the lead wiring for the lower electrode of the capacitor element 54, and the upper electrode. By the above process, the semiconductor light receiving element shown in the plan view of FIG.

  Next, an example of a manufacturing method for the semiconductor light receiving element using the air bridge wiring of FIG. 2B will be described with reference to FIG. First, as shown in FIG. 7A, in order to form a wiring conductor 9d for leading out the P electrode 7a, a resist pattern having an opening on the P electrode surface is formed. A Ti / Au metal layer 15 is formed in a thickness of about 50 nm / 100 nm on the opening and the resist 13. Since the resist 13 is flattened and applied so as to fill the recess formed in the InP substrate 2, no stepped portion is formed on the resist surface.

  Next, as illustrated in FIG. 7B, the wiring conductor 9 d is formed again with a new resist 14 without removing the resist 13. The new resist 14 has an opening in the wiring conductor forming portion, and the Ti / Au metal layer 15 previously formed is exposed at the bottom of the opening. Thereafter, Au electroplating is performed on the entire surface of the wafer. The plated metal is deposited only on the portion where the metal layer 15 is exposed and becomes the wiring conductor 9d, but is not deposited on the resist.

  When the resist 14 is removed with a solvent after the plating is finished, the wiring conductor 9d formed in the opening of the resist 14 and the Ti / Au metal layer 15 on the resist 13 are exposed. Thereafter, the metal layer 15 on the resist 13 other than the wiring conductor 9d formed thick by plating removes Au by a method such as milling and removes all Ti by a method such as RIE using a fluorine-based gas. When the Au of the metal layer 15 is milled, the Au of the wiring conductor formed by plating is also milled. However, even if all of the Au on the resist 13 is milled, the wiring conductor 9d is It remains in a sufficient thickness that does not impair the function. Next, after the metal layer 15 is removed, the resist 13 is exposed. Finally, the air bridge wiring as shown in FIG. 7C can be formed by removing the resist 13 including the portion where the recess of the InP substrate 2 is filled.

  Next, a light receiving module using the semiconductor light receiving element described above will be described. FIG. 8 is a diagram for explaining the outline of the light receiving module according to the present invention, in which 100 is a semiconductor light receiving element, 110 is a stem base, 120 is a housing, 130 is a condensing lens, 140 is a lead pin, and 150 and 155 are dies. A cap (parallel plate capacitor), 160 is a preamplifier IC, and 170 is a glass sealing part.

  The light receiving module is configured to mount the above-described semiconductor light receiving element 100 according to the present invention on the stem base 110 and receive an optical signal collected by the condenser lens 130 supported by the housing 120. The stem base 110 is formed of a metal disk or the like having a thickness of about 0.3 mm, and a first die cap 150 and a second die cap 155 constituting a parallel plate capacitor are provided on the inner surface thereof. The die caps 150 and 155 are, for example, rectangular and the lower surface is formed of a grounded electrode, the upper surface is formed of a plurality of divided electrodes, and the semiconductor light receiving element is formed on one of the upper surface electrodes of the central die cap 150. 100 is mounted. By using such a mounting form, a die cap, a light receiving element, a preamplifier IC, and the like can be efficiently mounted on the stem base 110 having a limited mounting area.

  The stem table 110 includes a plurality of lead pins, for example, five of 140a to 140e, and four of these lead pins are electrically insulated and fixed by a glass sealing portion 170 or the like. The remaining one lead pin can be directly fixed to the stem base 110 and set to the ground potential. Insulated lead pins protruding from the stem base 110 to the inside (upper surface) are electrically connected to the mounted components.

  The housing 120 can be made of a metal made of Kovar (Fe-29Ni-17Co alloy) having a thickness of about 0.2 mm. A condensing lens 130 is provided at the center of the housing 120 so that an optical signal emitted from an end face such as an optical fiber (not shown) can be efficiently received by the light receiving surface of the semiconductor light receiving element 100. Collect light. In the figure, an example using a spherical lens is shown, but not only a spherical lens but also a non-spherical lens, a Fresnel lens, and the like can be used. The material of the housing is not limited to metal, and may be formed of resin.

  For joining the stem base 110 and the housing 120, resistance heating, laser welding, or the like can be used. When the housing 120 is made of resin, an adhesive can also be used. Further, whether the casing 120 is made of metal or resin, a sleeve for receiving a ferrule that determines the optical axis of the optical fiber is attached to the upper surface side. The sleeve and the housing 120 are also joined by laser welding or an adhesive. A ferrule attached to the tip of the optical fiber is inserted into the sleeve, and after adjusting the optical axis of the optical fiber and the optical axis of the light receiving surface of the semiconductor light receiving element 100 while actually emitting light from the end of the optical fiber, laser welding is performed. By optically bonding with an adhesive or the like, optical coupling with the optical fiber is achieved.

  A preamplifier IC 160 that amplifies a current-converted optical signal is mounted adjacent to the semiconductor light receiving element 100. As the preamplifier IC 160, either an IC mainly made of Si or an IC mainly made of a compound semiconductor such as GaAs can be used. The signal amplified by the preamplifier IC 160 is converted into a complementary signal and drawn out from the opposing lead pins 140a and 140b to the outside of the module. Some pads of the preamplifier IC 160 are directly wire-bonded on the stem base 110 to be ground potential. The other plurality of pads are connected to one lead pin 140c for power supply via one of the divided electrodes on the first die cap 150.

  The upper surface electrode of the die cap 150 is divided into a plurality of electrodes, one of which is connected to a common terminal (see 60b in FIG. 1) of the semiconductor light receiving element 100, and a smooth rectifier circuit is connected to the resistance element 53. The bias power supply applied to the PD element 51 is stabilized and the noise is reduced. Further, the other divided electrodes can be used as a bypass capacitor for the power supply to the preamplifier IC 160. That is, the power supply of the preamplifier IC 160 can be bypassed by connecting the lead pin 140c with the bonding wire first to one of the divided electrodes and then connecting the same electrode and the power supply pad of the preamplifier IC 160 with the bonding wire. .

  The second die cap 155 mounted on the stem base 110 is used to bypass the anode terminal (see 60c in FIG. 1) of the BD element 52 of the semiconductor light receiving element 100. That is, one of the lead pins and the surface electrode of the second die cap 155 are connected by a bonding wire, and then the surface electrode and the anode terminal of the BD element 52 are connected. By adopting such a configuration, the power supplied to the semiconductor light receiving element 100 can be bypassed, and a smoothing circuit including a resistance element built in the semiconductor light receiving element 100 and a part of the first die cap 150, In addition, the power supply to the semiconductor light receiving element 100 can be further stabilized and the noise can be further reduced.

  The size of the light receiving module described above is generally compliant with, for example, TO-5, which is a standard for packages used in semiconductor devices, but it is also of a unique size with a smaller diameter. Can be used.

It is a figure which shows the top view of the semiconductor light receiving element by this invention, and the circuit structure in an element. It is sectional drawing explaining the outline of the semiconductor light receiving element by this invention. It is a figure explaining an example of the resistive element integrated in a semiconductor light receiving element. It is a figure explaining an example of the capacitive element integrated in a semiconductor light receiving element. It is a figure explaining the first half part of the manufacturing method of the semiconductor light receiving element by this invention. It is a figure explaining the latter half part of the manufacturing method of the semiconductor light receiving element by this invention. It is a figure explaining the latter half part of the other manufacturing method of the semiconductor light receiving element by this invention. It is a figure explaining an example of the light reception module by this invention.

Explanation of symbols

2 ... substrate, 3, 3 '... N ⁺ layer, 4, 4' ... i layer, 5, 5 '... P ⁺ layer, 6 is protective film, 7a, 7a', 7b, 7c ... electrode, 8, 11 ... Insulating film, 9a, 9b, 9c, 9d, 12 ... wiring conductor, 10 ... thin film metal resistor, 13, 14 ... resist, 15 ... metal layer, 51 ... photodiode (PD element), 52 ... bypass diode (BD element) 53 ... resistive element, 54 ... capacitance element, 60a, 60b, 60c, 60d ... electrode pad, 100 ... semiconductor light receiving element, 110 ... stem base, 120 ... housing, 130 ... condensing lens, 140 ... lead pin, 150, 155 ... Die cap (parallel plate capacitor), 160 ... Preamplifier IC, 170 ... Glass sealing part.

Claims (8)

  A semiconductor light receiving element in which a photodiode for converting an optical signal into an electric signal and a resistance element inserted in series with the photodiode are integrated, and includes a bypass diode connected in parallel to the resistance element. A semiconductor light receiving device characterized.   The semiconductor light-receiving element according to claim 1, wherein the bypass diode has the same layer structure as that of the photodiode.   3. The semiconductor light receiving element according to claim 1, wherein the resistance element is a thin film metal resistance.   3. The semiconductor light receiving element according to claim 1, wherein a capacitive element is integrated. 2. The semiconductor light receiving element according to claim 1, wherein the photodiode has a structure in which an N ⁺ -InGaAs layer, an i-InGaAs layer, and a P ⁺ -InGaAs layer are sequentially stacked on a semi-insulating InP substrate. The semiconductor light receiving element according to claim 5, wherein the P ⁺ -InGaAs layer is replaced with a P ⁺ -InP layer.   7. The semiconductor light receiving element according to claim 5, wherein the bypass diode has the same layer structure as that of the photodiode and is simultaneously manufactured in the same process.   A semiconductor light-receiving element according to claim 1 is mounted on a stem base together with a preamplifier integrated circuit that amplifies an electric signal by placing the semiconductor light-receiving element on a die cap capacitor. A light receiving module comprising a condensing lens for condensing light and housed in a housing.

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