JP6988103B2 - Manufacturing method of semiconductor devices, semiconductor devices - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device used for, for example, optical communication, and a semiconductor device manufactured by the manufacturing method.

Patent Document 1 discloses a planar type photodiode having an anode electrode and a cathode electrode on the same surface. This photodiode can be used as a backside incident type, is easy to mount, and can be speeded up by reducing the element capacity. A TIA (transimpedance amplifier) is used as a detection circuit for such a photodiode. An electronic circuit is formed by combining a TIA with a capacitor and a resistor. External capacitors and resistors, which are separate components from photodiodes, are usually used in electronic circuits. However, in order to reduce the size of the device, a capacitor using a MIM (Metal-Insulator-Metal) structure may be mixed with a photodiode as implemented in an integrated circuit, or a capacitor having a pn junction formed in a semiconductor portion may be used. It is known that it is mixed with a photodiode.

Patent Document 2 discloses a semiconductor light receiving device in which a light receiving layer of a photodetector and a waveguide for guiding light to the light receiving layer are formed on the same substrate. Patent Document 2 also discloses that a light receiving device in which a photodetector and a bypass capacitor are formed in a semiconductor portion is formed by an epitaxial method. A pin diode is used as a bypass capacitor.

Japanese Unexamined Patent Publication No. 2016-25095 Japanese Unexamined Patent Publication No. 2001-127333

It is rare to use the light receiving element alone, and it is often used by connecting an external capacitor to the light receiving element. Therefore, the light receiving element disclosed in Patent Document 1 is often mounted in a package together with an external capacitor. In order to reduce the number of parts, it is preferable to mount the light receiving element and the capacitor on the same substrate.

MIM-structured capacitors used in integrated circuits and the like are a general technique and easy to form, but the insulating film material that can be used is limited. Therefore, it is difficult to provide a large-capacity capacitor by the MIM structure. Since it is necessary to increase the area of the capacitor in order to increase the capacity of the capacitor, it becomes difficult to secure the assembly space. Further, in Patent Document 2, since the pn junction adjacent to the light receiving element is formed by epitaxial growth, the process becomes complicated and the construction period and cost increase.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device capable of mounting a light receiving element and a capacitor on the same substrate while avoiding adverse effects. ..

The method for manufacturing a semiconductor device according to the present invention includes a step of forming an n-type light absorbing layer on a substrate, a step of forming a window layer on the light absorbing layer, and a solid inside the window layer. A step of forming a p-type first diffusion layer in contact with the light absorption layer by phase diffusion or gas phase diffusion, and a p-type first diffusion layer in contact with the light absorption layer by solid phase diffusion or gas phase diffusion in the window layer. 2 A step of forming a diffusion layer, a step of forming an isolation groove on the upper surface side of the substrate, an anode electrode electrically connected to the first diffusion layer, and a cathode electrically connected to the substrate. By forming an electrode, a light receiving element portion having a pn junction between the first diffusion layer and the light absorption layer is formed, and the first electrode electrically connected to the second diffusion layer and the substrate are electrically connected. A step of forming a capacitor portion having a pn junction between the second diffusion layer and the light absorption layer by forming a second electrode connected to the above, and as the isolation groove, the said around the second diffusion layer. A step of forming a through groove that penetrates the window layer and the light absorption layer to expose the substrate is provided, and the light receiving element portion and the capacitor portion are electrically isolated by the isolation groove. It is a feature.

The semiconductor device according to the present invention includes a substrate, a light receiving element portion formed on the substrate, and a capacitor portion formed next to the light receiving element portion of the substrate, and the light receiving element portion is p. The capacitor portion has a pn junction in which the first diffusion layer of the type and the light absorption layer of the n type are in contact with each other, and the capacitor portion has a pn junction in which the second diffusion layer of the p type and the light absorption layer of the n type are in contact with each other. The thickness of the first diffusion layer and the second diffusion layer are different, and an isolation groove for electrically isolating the light receiving element portion and the capacitor portion is provided on the upper surface side of the substrate, and the second diffusion groove is used as the isolation groove. A through groove is formed around the diffusion layer so as to penetrate the light absorbing layer and expose the substrate .

Other features of the invention will be clarified below.

According to the present invention, since the p-type layer that provides the pn junction of the capacitor portion is formed by the diffusion method, the light receiving element and the capacitor can be mixedly mounted on the same substrate while avoiding adverse effects.

It is sectional drawing of the semiconductor device which concerns on Embodiment 1. FIG. It is a bottom view of the semiconductor device of FIG. It is a top view of the semiconductor device of FIG. It is a top view of the CAN package. It is a circuit diagram of the CAN package of FIG. It is a figure which shows the light absorption layer and the window layer. It is a figure which shows the formation method of the 1st diffusion layer. It is a figure which shows the formation method of the 2nd diffusion layer. It is a figure which shows the isolation groove, the cathode groove, and the insulating film. It is a figure which shows the electrode. It is a figure which shows an electrode, a metal mask, and a low reflection film. It is sectional drawing of the semiconductor device which concerns on Embodiment 2. FIG. It is a bottom view of the semiconductor device of FIG. It is a top view of the semiconductor device of FIG. It is a top view of the CAN package. It is a circuit diagram of the CAN package of FIG. It is sectional drawing of the semiconductor device which concerns on Embodiment 3. FIG. It is a bottom view of the semiconductor device of FIG. It is sectional drawing of the semiconductor device which concerns on Embodiment 4. FIG. It is a bottom view of the semiconductor device of FIG. It is a top view of the CAN package. It is sectional drawing of the semiconductor device which concerns on Embodiment 5. FIG. It is a top view of the semiconductor device of FIG. It is a bottom view of the semiconductor device of FIG. It is a top view of the CAN package.

The method for manufacturing a semiconductor device and the semiconductor device according to the embodiment of the present invention will be described with reference to the drawings. The same or corresponding components may be designated by the same reference numerals and the description may be omitted.

Embodiment 1.
FIG. 1 is a cross-sectional view of the semiconductor device 10 according to the first embodiment. The semiconductor device 10 includes a light receiving element unit 10A and a capacitor unit 10B. The left side of the broken line is the light receiving element portion 10A, and the right side of the broken line is the capacitor portion 10B. The light receiving element unit 10A is an avalanche photodiode (APD). The capacitor portion 10B is a type of capacitor that uses the depletion layer generated in the reverse-biased pn junction as the electric capacity. The upper surface of the semiconductor device 10 in FIG. 1 is referred to as a “back surface”, and the lower surface is referred to as a “front surface”. The light receiving element unit 10A is a back surface incident type light receiving element unit in which light is incident from the back surface side.

The semiconductor device 10 includes a substrate 11. The substrate 11 is, for example, an n-type InP substrate. The substrate 11 is preferably an n-type or an insulating type InP. A light absorption layer 12 is formed under the substrate 11. The light absorption layer 12 is formed of, for example, n-type InGaAs. A window layer 14 is formed below the light absorption layer 12. The window layer 14 is formed of, for example, an n-type InP. A first diffusion layer 16A and a second diffusion layer 16B are formed on the window layer 14. The first diffusion layer 16A and the second diffusion layer 16B are p-type regions formed by thermally diffusing a p-type dopant in the window layer 14. The first diffusion layer 16A and the second diffusion layer 16B are P-type InP layers.

Both the first diffusion layer 16A and the second diffusion layer 16B are in contact with the light absorption layer 12 and the window layer 14. The thicknesses of the first diffusion layer 16A and the second diffusion layer 16B are different. The thickness of the first diffusion layer 16A is the same as the thickness of the window layer 14. The second diffusion layer 16B is formed thicker than the window layer 14. The second diffusion layer 16B is formed by thermally diffusing a p-type dopant not only in the window layer 14 but also in the light absorption layer 12.

Isolation grooves I1, I2, and a cathode groove C1 are formed on the surface of the semiconductor device 10. An insulating film 30 is formed on the surface of the semiconductor device 10. The insulating film 30 is also formed on the inner walls of the isolation grooves I1 and I2 and the cathode groove C1. The insulating film 30 is made of, for example, SiN, SiO ₂ or SiON.

The anode electrode 18 is formed so as to be in contact with the first diffusion layer 16A. The first electrode 20 is formed so as to be in contact with the second diffusion layer 16B. The cathode electrode 22 is formed along the insulating film 30 formed in the cathode groove C1. The cathode electrode 22 is connected to the substrate 11 by being formed in the opening of the insulating film 30. The anode electrode 18, the first electrode 20, and the cathode electrode 22 are exposed from the insulating film 30. The anode electrode 18, the first electrode 20, and the cathode electrode 22 are formed in a laminated structure using, for example, Ti and Au. Such laminated structures include Ti / Au, Ti / Pt / Au, Pt / Ti / Pt / Au. Note that / means lamination, and the material at the left end is in contact with the semiconductor or the insulating film.

A metal mask 40 and a second electrode 42 are formed on the back surface of the semiconductor device 10. The metal mask 40 has a shape that opens immediately above the anode electrode 18 on the back surface of the light receiving element portion 10A. Therefore, the metal mask 40 is not formed directly above the anode electrode 18. The metal mask 40 is formed of a laminated structure using, for example, Ti and Au. Such laminated structures include AuGe / Ni / Ti / Pt / Au, AuZn / Ti / Pt / Au. The metal mask 40 is provided mainly for shading. The second electrode 42 is provided directly above the first electrode 20. The second electrode 42 is formed of, for example, the same material as the first electrode 20, AuGe / Ni / Ti / Pt / Au, or the like.

A low reflection film 44 is formed on the back surface of the semiconductor device 10. The low reflection film 44 functions as an antireflection film. The low-reflection film 44 is formed on the back surface of the semiconductor device 10 while exposing the above-mentioned metal mask 40 and the second electrode 42. The low-reflection film 44 has, for example, a laminated structure of _{Si and SiO 2.} Such laminated structures include Si / SiO ₂ and Si / SiO ₂ / Si / SiO ₂ .

FIG. 2 is a bottom view of the semiconductor device 10 of FIG. The isolation groove I1 is formed in an annular shape so as to surround the anode electrode 18. The cathode electrode 22 is a quadrangle when viewed from the bottom. The light receiving element portion 10A has a planar structure having the anode electrode 18 and the cathode electrode 22 on the same surface. The anode electrode 18 and the cathode electrode 22 are formed on the surface side of the substrate 11. The cross-sectional view taken along the line AA'of FIG. 2 is the light receiving element portion 10A of FIG. The isolation groove I2 is formed in an annular shape so as to surround the first electrode 20. The cross-sectional view taken along the line BB'of FIG. 2 is the capacitor portion 10B of FIG.

FIG. 3 is a plan view of the semiconductor device 10 of FIG. The metal mask 40 is formed on most of the back surface of the light receiving element portion 10A, but has a circular opening in a part thereof. An optical signal is incident on this opening from the outside. The second electrode 42 is formed substantially in the center of the capacitor portion 10B.

Returning to the description of FIG. The arrow in FIG. 1 indicates the light incident on the light receiving element portion 10A. The low-reflection film 44 suppresses the reflection of incident light, and the metal mask 40 blocks incident light from other than directly above the anode electrode 18. When light reaches the pn junction where the p-type first diffusion layer 16A and the n-type light absorption layer 12 or the window layer 14 in the light receiving element portion 10A are in contact with each other, electrons and holes are generated. As each carrier flows through the anode electrode 18 and the cathode electrode 22, a current flows through the light receiving element portion 10A.

In the capacitor portion 10B, the p-type second diffusion layer 16B is in contact with the n-type light absorption layer 12 and the window layer 14 to provide a pn junction. When a voltage is applied to the first electrode 20 and the second electrode 42 to reverse bias the pn junction, a depletion layer is generated at the pn junction interface. This depletion layer can provide electrical capacity. Since the capacitor portion 10B is electrically isolated from the light receiving element portion 10A, the capacitor portion 10B can be used as a normal capacitor. Therefore, it is possible to eliminate the need for an external capacitor that is conventionally provided next to the photodiode.

FIG. 4 is a plan view of the CAN package 50 on which the semiconductor device 10 is mounted. A submount 52, a TIA (transimpedance amplifier) 54, and a capacitor 56 are fixed to the CAN package 50 by soldering. The semiconductor device 10 is fixed to the submount 52 with the back surface having the light receiving region facing up. This made it possible to use the semiconductor device 10 as a backside incident type light receiving element. A wiring pattern 52a is formed on the submount 52. The wiring pattern 52a is mainly used for electrical connection with an electrode on the surface side of the semiconductor device 10. Five lead wires 58 are fixed to the CAN package 50. One lead wire is on the back side of the TIA 54. The wire 60 connects each device to the lead wire 58. For example, the bonding pad of the capacitor 56 and the lead wire 58 for the power supply are connected by the wire 60, and the signal output unit of the TIA 54 and the lead wire 58 are connected by the wire 60.

FIG. 5 is a circuit diagram of the CAN package 50 of FIG. The capacitor portion 10B of the semiconductor device 10 is used as a bypass capacitor of the TIA 54. By using the capacitor unit 10B as a bypass capacitor for the TIA 54, power supply noise for the TIA 54 can be cut. The capacitor 56, which is an external capacitor, is a bypass capacitor of the light receiving element portion 10A.

A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 6-11. First, the light absorption layer 12 and the window layer 14 are formed. FIG. 6 is a diagram showing that the light absorption layer 12 is formed on the substrate 11 and the window layer 14 is formed on the light absorption layer 12.

Next, the first diffusion layer 16A is formed. FIG. 7 is a diagram showing a method of forming the first diffusion layer 16A. A ZnO film 16a as a diffusion source is formed on the window layer 14 by using a photoplate making technique, an etching technique, and a thin film forming technique such as thin film deposition or sputtering. Then, the substrate 11 and the ZnO film 16a are heat-treated to diffuse Zn. As a result, the p-type first diffusion layer 16A in contact with the light absorption layer 12 is formed in the window layer 14. The first diffusion layer 16A can be formed by solid phase diffusion or gas phase diffusion.

Next, the second diffusion layer 16B is formed. FIG. 8 is a diagram showing a method of forming the second diffusion layer 16B. The second diffusion layer 16B is formed in the same manner as the first diffusion layer 16A. That is, a ZnO film 16b as a diffusion source is formed on the window layer 14 by using an etching technique and a thin film forming technique such as thin film deposition or sputtering. Then, the substrate 11 and the ZnO film 16b are heat-treated to diffuse Zn. As a result, the p-type second diffusion layer 16B in contact with the light absorption layer 12 is formed in the window layer 14. The second diffusion layer 16B can be formed by solid phase diffusion or vapor phase diffusion.

The first diffusion layer 16A and the second diffusion layer 16B may be formed by solid phase diffusion by forming a doped oxide film or polycrystalline silicon other than the ZnO film on the window layer 14 and heat-treating the window layer 14. When the first diffusion layer 16A and the second diffusion layer 16B are formed by vapor phase diffusion, a layer containing impurities at a high concentration is formed in the window layer 14 using a gas containing impurities, and then the substrate 11 is heated to a high temperature. Heat for a long time to introduce impurities to the desired depth.

The electric capacity of the capacitor portion 10B can be set to an arbitrary value depending on the depth to which the second diffusion layer 16B is formed. That is, the thickness of the second diffusion layer 16B determines the electric capacity of the capacitor portion 10B. If the second diffusion layer 16B is made thicker, d of C = εS / d can be made smaller, so that the electric capacity can be made larger. For example, when d of 1.7 μm is 0.1 μm, an electric capacity of 39 pF can be provided. The thickness of the second diffusion layer 16B can be controlled by adjusting conditions such as the temperature and time of thermal diffusion. The thickness of the second diffusion layer 16B may be matched with the thickness of the window layer 14, or the thickness of the second diffusion layer 16B may be larger than the thickness of the window layer 14.

Next, a groove and an insulating film are formed. FIG. 9 is a diagram showing isolation grooves I1 and I2, a cathode groove C1, and an insulating film 30. Isolation grooves I1 and I2 and a cathode groove C1 are formed by using a photoengraving technique and an etching technique. Next, the insulating film 30 is formed on the entire surface of the wafer. The isolation grooves I1 and I2 and the cathode groove C1 are provided for the purpose of dividing the light absorption layer 12 into a plurality of regions and isolating them. The isolation groove I2 is a through groove that penetrates the window layer 14 and the light absorption layer 12 around the second diffusion layer 16B to expose the substrate 11. Another epi layer may be formed between the substrate 11 and the light absorption layer 12.

Next, an electrode is formed on the surface side of the substrate. FIG. 10 is a diagram showing that the anode electrode 18, the first electrode 20, and the cathode electrode 22 are formed. The anode electrode 18, the first electrode 20, and the cathode electrode 22 are formed on the surface side of the substrate 11 by using a photoplate making technique, an etching technique, and a thin film forming technique. The cathode electrode 22 is formed so as to come into contact with the exposed substrate 11 by forming a cathode groove C1 penetrating the window layer 14 and the light absorption layer 12. A semiconductor layer for lowering the contact resistance may be provided between the first diffusion layer 16A and the anode electrode 18 and between the second diffusion layer 16B and the first electrode 20.

Next, an electrode, a metal mask, and a low-reflection film are formed on the back surface side of the substrate 11. FIG. 11 is a diagram showing that the second electrode 42, the metal mask 40, and the low reflection film 44 are formed on the back surface side of the substrate 11. First, the low-reflection film 44 is formed on the entire back surface side of the substrate 11. Then, the second electrode 42 and the metal mask 40 are formed by using the photoplate making technique, the etching technique, and the thin film forming technique. The material, layer thickness or number of layers of the low-reflection film 44 may be changed according to the target wavelength and reflectance. In this way, the semiconductor device 10 having the light receiving element portion 10A and the capacitor portion 10B is completed.

By forming an anode electrode 18 electrically connected to the first diffusion layer 16A and a cathode electrode 22 electrically connected to the substrate 11, light receiving light having a pn junction between the first diffusion layer 16A and the light absorption layer 12. The element portion 10A is formed. By forming the first electrode 20 electrically connected to the second diffusion layer 16B and the second electrode 42 electrically connected to the substrate 11, the second diffusion layer 16B and the light absorption layer 12 form a pn junction. The capacitor portion 10B to have is formed.

Isolation grooves I1 and I2 and a cathode groove C1 may be formed before forming the first diffusion layer 16A and the second diffusion layer 16B. However, in this case, the diffusion source films of the first diffusion layer 16A and the second diffusion layer 16B have irregularities due to the influence of the grooves. Therefore, there may be a place where the semiconductor surface and the diffusion source film do not adhere to each other, and the p-type region front may not be uniform. That is, the impurity profiles of the first diffusion layer 16A and the second diffusion layer 16B may not be as intended. Therefore, it is necessary to pay attention to the dimensions of the first diffusion layer 16A and the second diffusion layer 16B.

In the semiconductor device 10 according to the first embodiment of the present invention, a light receiving element portion 10A and a capacitor portion 10B provided next to the light receiving element portion 10A are formed on the substrate 11. In the first embodiment of the present invention, since the first diffusion layer 16A and the second diffusion layer 16B are formed in separate steps, the thicknesses of the first diffusion layer 16A and the second diffusion layer 16B can be freely adjusted. That is, it is possible to provide the first diffusion layer 16A and the second diffusion layer 16B having different depths from the surface of the window layer 14. In particular, by forming the second diffusion layer 16B by diffusion, the thickness thereof can be freely adjusted and a required electric capacity value can be obtained. Although it is shown in FIG. 1 that the second diffusion layer 16B is formed thicker than the first diffusion layer 16A, the thickness of the second diffusion layer 16B may be matched with the thickness of the first diffusion layer 16A. Then, the second diffusion layer 16B may be made thinner than the first diffusion layer 16A.

Further, in the first embodiment of the present invention, the first diffusion layer 16A and the second diffusion layer 16B are formed by a diffusion method instead of epitaxial growth. Therefore, the semiconductor device 10 can be manufactured easily and at low cost as compared with the case of epic growth. The electric capacity can be obtained by the depletion layer formed by applying a reverse bias to the pn junction between the second diffusion layer 16B and the light absorption layer 12 and the window layer 14. When the p-type carrier concentration of the pn junction is 1E18 cm ^-3 and the n-type carrier concentration is 2E15 cm ^-3 , a depletion layer of 1.7 μm can be obtained by applying a bias of 3.3 V. This depletion layer corresponds to 2.3 pF if the pattern is φ200 μm.

Generally, the relative permittivity of alumina used for an external capacitor is 10. The light absorption layer 12 of the capacitor portion 10B according to the first embodiment is made of InGaAs and has a relative permittivity of 14. Since the electric capacity of the capacitor unit 10B is calculated by εS / d, increasing ε means that the electric capacity can be increased. Further, by mounting the capacitor portion 10B in a semiconductor device having the light receiving element section 10A, it is possible to eliminate or reduce the number of external capacitors externally attached to the semiconductor device 10. By reducing the number of external capacitors, the number of parts that need to be assembled can be reduced. Further, the semiconductor device 10 and the submount 52 can be enlarged by the amount that the external capacitor is reduced. If the area S of the capacitor portion 10B is increased, the electric capacity C calculated by εS / d can be increased. For example, if S, which was φ200 μm, can be increased to φ1000 μm, an electric capacity of 57 pF can be provided.

Further, as shown in FIG. 2, the maximum value of the electric capacity can be limited by forming the isolation groove I2 around the first electrode 20. By providing the isolation groove I2, the electric capacity can be adjusted only by the depth of the second diffusion layer 16B, so that the electric capacity can be stabilized.

The method for manufacturing a semiconductor device and the semiconductor device according to the first embodiment of the present invention can be variously modified without losing their characteristics. The light receiving element unit 10A may be a light receiving element other than an avalanche photodiode (APD). For example, a photodiode (PD) or a PIN photodiode may be used as the light receiving element unit 10A. The order of formation of the first diffusion layer 16A and the second diffusion layer 16B may be interchanged. In the first embodiment, the first diffusion layer 16A and the second diffusion layer 16B having different thicknesses have been described, but when the depths of the first diffusion layer 16A and the second diffusion layer 16B from the window layer 14 surface are equalized, , The first diffusion layer 16A and the second diffusion layer 16B can be formed in the same process. The substrate 11 may be an insulating type InP instead of an n-type InP, and if an n-type InP layer is formed between the substrate 11 and the light absorption layer 12, the same effect as that of the first embodiment can be obtained. These modifications can be applied to the semiconductor device manufacturing method and the semiconductor device according to the following embodiments. Since the semiconductor device manufacturing method and the semiconductor device according to the following embodiments have much in common with the first embodiment, the differences from the first embodiment will be mainly described.

Embodiment 2.
FIG. 12 is a cross-sectional view of the semiconductor device 70 according to the second embodiment. The semiconductor device 70 includes two capacitor units 10B ₁ and 10B ₂ . The light receiving element unit 10A, the capacitor unit 10B _1, and the capacitor unit 10B ₂ are mounted on one substrate 11 in a mixed manner. The capacitor unit 10B ₁ can be used, for example, as a bypass capacitor for the TIA 54, and the capacitor unit 10B ₂ can be used, for example, as a power supply bypass capacitor for the light receiving element unit 10A. The capacitor unit B ₂ makes it possible to cut power supply noise for the light receiving element unit 10A. By forming a plurality of isolated capacitor portions in the semiconductor device 70, it is possible to further reduce the number of external capacitors.

FIG. 13 is a bottom view of the semiconductor device 70. The cross-sectional view taken along the line CC is the capacitor portion 10B ₁ in FIG. 12, and the cross-sectional view taken along the line BB is the capacitor portion 10B ₂ in FIG. FIG. 14 is a plan view of the semiconductor device 70.

FIG. 15 is a plan view of the CAN package 50 including the semiconductor device 70. The two capacitor portions of the semiconductor device 70 are connected to separate lead wires 58 by wires 60. FIG. 16 is a circuit diagram of the CAN package 50 of FIG. The capacitor unit 10B ₁ is used as a bypass capacitor for the light receiving element unit 10A. The capacitor portion 10B ₂ is used as a bypass capacitor for the TIA 54. This eliminates the need for an external capacitor.

Embodiment 3.
FIG. 17 is a cross-sectional view of the semiconductor device 80 according to the third embodiment. Unlike the semiconductor device 10 of the first embodiment, no isolation groove is provided around the capacitor portion 10B. This can simplify the manufacturing process. When it is not necessary to accurately control the upper limit of the depletion layer generated at the pn junction surface between the second diffusion layer 16B of the capacitor portion 10B and the light absorption layer 12 and the window layer 14, the periphery of the capacitor portion 10B is described above. Isolation groove can be omitted. FIG. 18 is a bottom view of the semiconductor device 80. No groove is formed on the bottom surface of the capacitor portion 10B. The plan view of the semiconductor device 80 according to the third embodiment is the same as that of FIG. The plan view of the CAN package provided with the semiconductor device 90 is omitted because the semiconductor device 10 in FIG. 4 is replaced with the semiconductor device 80.

Embodiment 4.
FIG. 19 is a cross-sectional view of the semiconductor device 90 according to the fourth embodiment. The capacitor portion 10B of the semiconductor device 90 has a first electrode 20 and a second electrode 92 formed on the surface side thereof. The second electrode 92 is formed so as to come into contact with the substrate 11 along the cathode groove C2 that penetrates the window layer 14 and the light absorption layer 12 and exposes the substrate 11. The low reflection film 44 and the metal mask 40 are formed on the back surface side of the substrate 11, and the second electrode is not formed.

FIG. 20 is a bottom view of the semiconductor device 90. A first electrode 20 and a second electrode 92 of the capacitor portion 10B are provided on the bottom surface. A first electrode 20, a second electrode 92, an anode electrode 18, and a cathode electrode 22 are provided on the bottom surface of the semiconductor device 90. The plan view of the semiconductor device 90 is the same as that in FIG. FIG. 21 is a plan view of the CAN package 50 including the semiconductor device 90. The four electrodes on the bottom surface of the semiconductor device 90 are individually connected to the wiring pattern 52a of the submount 52. The cathode potential, which is the potential of the second electrode 92 of the capacitor portion 10B, is given by the wiring pattern 52a of the submount 52. Since it is not necessary to directly connect to the semiconductor device 90, defects due to wiring damage or the like can be suppressed.

Embodiment 5.
FIG. 22 is a cross-sectional view of the semiconductor device 100 according to the fifth embodiment. The semiconductor device 100 adopts a front surface incident type structure instead of the back surface incident type structure of the first embodiment. The upper surface of the semiconductor device 100 of FIG. 22 is referred to as a front surface, and the lower surface is referred to as a back surface. The semiconductor device 100 has an anode electrode 102 on the surface side. The anode electrode 102 is in contact with the first diffusion layer 16A. A first electrode 20 and a second electrode 92 are formed on the surface side of the capacitor portion 10B. A metal mask 104 is formed on the back surface side of the light receiving element portion 10A and the capacitor portion 10B.

FIG. 23 is a plan view of the semiconductor device 100. The anode electrode 102 is formed in an annular shape. When light is incident on the region surrounded by the anode electrode 102, the light is detected by the light receiving element unit 10A. FIG. 24 is a bottom view of the semiconductor device 100. The back surface side of the light receiving element portion 10A is covered with a metal mask 104. A circular metal mask 104 is provided in the center of the back surface of the capacitor portion 10B.

FIG. 25 is a plan view of the CAN package 50 on which the semiconductor device 100 is mounted. The semiconductor device 100 is fixed to the submount 52 with the surface side on which the window layer 14 is located facing up, and is used as a surface incident type. The circuit diagram of the CAN package 50 in FIG. 25 is the same as that in FIG. 5, and is omitted. The semiconductor device manufacturing method and the features of the semiconductor device according to each embodiment described so far may be used in combination.

10 Semiconductor device, 11 Substrate, 12 Light absorption layer, 14 Window layer, 18 Anode electrode, 20 1st electrode, 22 Cathode electrode, 42 2nd electrode, 50 CAN package

Claims (10)

The process of forming an n-type light absorption layer on the substrate and
The step of forming the window layer on the light absorption layer and
A step of forming a p-type first diffusion layer in contact with the light absorption layer by solid phase diffusion or gas phase diffusion in the window layer.
A step of forming a p-type second diffusion layer in contact with the light absorption layer by solid phase diffusion or gas phase diffusion in the window layer.
The step of forming an isolation groove on the upper surface side of the substrate and
A light receiving element portion having a pn junction between the first diffusion layer and the light absorption layer by forming an anode electrode electrically connected to the first diffusion layer and a cathode electrode electrically connected to the substrate. By forming a first electrode electrically connected to the second diffusion layer and a second electrode electrically connected to the substrate, the pn by the second diffusion layer and the light absorption layer is formed. The process of forming a capacitor portion with a junction and
The isolation groove includes a step of forming a through groove that penetrates the window layer and the light absorption layer and exposes the substrate around the second diffusion layer.
A method for manufacturing a semiconductor device, characterized in that the light receiving element portion and the capacitor portion are electrically isolated by the isolation groove. Before SL substrate is n-type, the cathode electrode is formed to contact the substrate exposed by forming a through groove together with the isolation trench in the light absorbing layer and the window layer,
The method for manufacturing a semiconductor device according to claim 1, wherein the substrate has a front surface and a back surface, and the anode electrode and the cathode electrode are formed on the front surface side. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate is an n-type or an insulating type InP, and the light absorption layer is InGaAs. The second diffusion layer and the first diffusion layer forms a ZnO film on the window layer, any one of claims 1 to 3, characterized in that formed by heat treatment in the ZnO film The method for manufacturing a semiconductor device according to the above. The method for manufacturing a semiconductor device according to any one of claims 1 to 4 , wherein the depths of the first diffusion layer and the second diffusion layer from the surface of the window layer are different. The depths of the first diffusion layer and the second diffusion layer from the surface of the window layer are equal.
The method for manufacturing a semiconductor device according to any one of claims 1 to 4 , wherein the first diffusion layer and the second diffusion layer are formed in the same step. The method for manufacturing a semiconductor device according to any one of claims 1 to 6 , wherein two second diffusion layers are formed and two capacitor portions are provided. The method for manufacturing a semiconductor device according to claim 3, wherein the second electrode is brought into contact with the exposed substrate by forming a through groove in the window layer and the light absorption layer. The method for manufacturing a semiconductor device according to any one of claims 1 to 8 , wherein the anode electrode is formed in an annular shape on the first diffusion layer. With the board
The light receiving element portion formed on the substrate and
A capacitor portion formed next to the light receiving element portion of the substrate is provided.
The light receiving element portion has a pn junction in which a p-type first diffusion layer and an n-type light absorption layer are in contact with each other.
The capacitor portion has a pn junction in which a p-type second diffusion layer and an n-type light absorption layer are in contact with each other.
The thickness of the first diffusion layer and the second diffusion layer are different,
An isolation groove for electrically isolating the light receiving element portion and the capacitor portion is provided on the upper surface side of the substrate .
A semiconductor device characterized in that, as the isolation groove, a through groove is formed around the second diffusion layer so as to penetrate the light absorption layer and expose the substrate.

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