M409531 五、新型說明： 【新型所屬之技術領域】 本創作係關於光通訊的技術領域，特別是指用以收發光訊 號的光通訊晶片結構。 【先前技術】 光電元件係由一底座與一光電晶片組合而成。其中底座可 以是金屬盤體(metal stem)與金屬接腳的組合，例如T〇can Header，或是非金屬盤體與金屬接腳的組合，例如Leadframe Header。其次底座上可配置一載體(subm〇unt)承載光電晶片， 且光電晶片的電極透過接腳與電路板上的電路連接。 上述光電晶片的電極可位在相對面，例如其一位在光電晶 片上方表面，另一位在光電晶片下方表面；當光電晶片配置在 載體(Submount)上，位在下方表面的電極可與载體接觸並形成 電f生連、纟σ，載體更進一步作為打線塾(b〇un(jing pa(j)，使得一導 線可連接-接聊㉟極)與載體；至於位在光電晶片上方表面的 電極也可藉一導線與另一接腳(電極)電性連接。值得注意的 是，載體與底座的表面需形成不導電的狀態。 圖la與圖lb顯示光電晶片的二個電極位在同一面，例如 —個電極皆位在光電晶片的上方表面；以piN_TIA架構的光電 疋件為例，光電晶片200位在一異質基板/載體2〇5上，且其 組合配置在一底座201 ;其中光電晶片2〇〇電性連接一轉阻放 大器(TIA)202，且光電晶片2〇〇與底座2〇1形成絕緣且可供操 3 M409531 作，然而異質基板205的價格較高且體積與面積較大，因此導 . 致光電晶片200的電容提高且降低頻率響應。 冑1C與圖1_示另一種使光電晶片200能夠絕緣地配置 V 在底座201上且供操作的方式。其主要是在-同質的半絕緣基 ， 板(semi-insulating sub伽te，SI 基板)206 上磊晶生成 M_N 結 構的sa層，並藉由餘刻技術形成二個電極2〇3、2〇4 ;然而同 質半絕緣基板2〇6同樣存在成本高的缺失，而且N+晶層的厚 • 度很薄(通常僅約數個微米㈣，所以須搭配精密的姓刻製程 以預防N+晶層不慎被蝕穿而造成元件無法運作。 另外美國專利6,586,718揭露-種光電晶片，其揭露在一 同質的半絕緣基板上蟲晶生成層；其中N晶層容易因敍 刻過度而被飯穿。 是以根據以上所述’舰pin_tia賴的找元件要使光 電晶片與底座間形成絕緣，使用異質基板會導致成本高且頻寬 •.降低；而使用同質半絕緣基板除了成本高外，還會因為讲晶 層薄不易控制蚀刻製程而導致製程參數須相當精準 作的困難度。 : 【新型内容】 本創作的目的之-係在提供—種光軌K轉具有 月b夠讓使用該晶片之光電元件具有高頻寬、低成本、易製作及 /或高良率的功效。 更進一步而言’本創作之晶片結構係特別設計成一端具有 4 較大厚度且可導電的同質基座(N+基座）、半絕緣基座或不導電 基座，且一晶層構造位於該基座上；該晶片更具有二個電極且 位在同側及具有相同金屬結構；輔以一低介電常數材料層 (Low K材料層，如BCB或s〇G)降低電容的設計，或在底部 鋪上SOG造成與底座絕緣的設計，藉此可讓使用該晶片之光 電元件具有高頻寬、低成本、易製作及/或高良率的功效。 該光電晶片一般為p_I_N架構的檢光二極體，亦可為雷 射二極體或發光二極體。 上述的目的；功效，以及本創作的其他目的、功效，可分 別藉由以下實施例並搭配圖式逐一說明。 【實施方式】 圖2及圖3揭露-種光電元件的底座1()結構，其具有一 金屬盤體(metal stem) 12、複數支可作為電極的電極接腳 14a〜14c及一支接地接腳14d;其中各接腳丨如〜Md的一端可 嵌入該金屬盤體12 ;特別是，電極接腳14a〜14c可搭配一非 導電材料16，例如玻璃、歸材料，或其他類她質的材料， 使知金屬盤體12與各接腳i4a〜14c形成不導電狀態。 更進-步，金屬盤體12具有-第一面(盤面)18，及一第 二面(底面)19相對第-面18，例如圖中的上表面及下表面； -嵌孔22形成在第-面18與第二面19之間且位於第一面以 的中央區域；-絕緣構造24 ’由絕緣材料製成的嵌入件，組 設於嵌孔22喊藉狀射邶刪mQlding)对形成於嵌孔 M409531 22内-e緣構& 24可以全部或部份的體齡於盤體η的第 :㈣與第二面19之間’且該絕緣構造則以承載光電晶 片26 〇 特別是，絕緣構造24具有—第—端24a及-第二端24b， 其中第-端24a可相鄰且平齊於第一㈣，且第一端⑽承載 光電晶片26。上述的絕緣構造2何為—獨立的絕緣件或絕緣 部位。 選用電極26a和26b位於同一側的光電晶片％，且將光 電晶片26配置在絕緣構造24的第—端2如，則導線撕和娜 可分別連接電極26a和26b與接㈣&和Mc ;此狀態下的光 電曰曰片26與底座1〇的金屬盤體12成為不導電的斷路狀態。 上述實施例提供-種創新的底座1〇結構且能夠與光電晶 片26形成輯效果，其翻於傳絲座錢由麵承載光電 曰曰片或是在光電晶片上形成絕緣層的結構形態。 圖4a揭露光電元件30可包含上述的底座1〇及光電晶片 26以及更包含一蓋體(caP)32組設在底座1〇上；其中蓋體32 鳊具有開孔32a ’且開孔32a可配置一光學裝置34，例如透 鏡或玻璃片，或開孔32a處無配置任何元件或裝置。上述的開 孔32a或光學裝置34係相對光電晶片％。 又圖4a顯示絕緣構造24的第一端24a係凸出金屬盤體12 的第一面18;因此光電晶片26位在絕緣構造24的第一端24a 除了與金屬盤體12形成絕緣外，更可搭配第一端24a的凸出 6 M409531 高度而改變與裝置34或開孔32a的距離，藉此調整輛光效率。 根據上述實施_教示，圖4b顯示，構造24的第一 • 端24a可以凹低於金屬盤體12的第一面18。 " 再者圖4a或圖4b中’絕緣構造24的第二端⑽可以& . 出、齊平或凹人該金屬舰12的第二面19 ;或參照以下的實 施例的說明。 圖5及圖6顯示-個大面積的嵌孔52開設在底座4〇的金 _ 屬盤體42上；特別是嵌孔52的面積包括金屬盤體42的中央 區域及鄰近的邊緣的區域；絕緣構造54可組設於嵌孔52内， 或藉射出方式形成於嵌孔52心值得注意的是，電極接腳 44a〜44c位在嵌孔52的範圍内且一端結合該絕緣構造％ ;又 光電晶片56配置在絕緣構造54的第一端5如。 上述金屬盤體42與各電極接腳44a〜44c及接地接腳 _(見圖5)可先組合，然後將組合體導人適#_出成形機具 » 及模具内，搭配欲入射出方式，將絕緣材料注入嵌孔52内以 形成絕緣構造54，同時利用絕緣構造54結合各電極接腳 44a〜44c ’·此外可以利用射出製程的合模壓力，使接地接腳4如 與金屬盤體42結合，或另外針對接地接腳44d進行沖壓使其 結合金屬盤體42。 此外圖6中顯示絕緣構造54的第二端54b齊平金屬盤體 42的第二面49或嵌孔52的孔緣；然而根據前述說明可知， 第二端54b也可以凸出或凹入該金屬盤體42的第二面49 ;或 7 M409531 參照以下的實施例的說明。 圖7a顯示一光電元件60由底座40與光電晶片56組合且 ' 更搭配一蓋體62而組成；特別是，絕緣構造54的第一端54a " 具有—體成形的—凸部55 ;該凸部55凸出金屬盤體42的第 . 一面48，且光電晶片56組設在凸部55上。如此光電晶片％ 與金屬盤體42形成絕緣，且光電晶片56可藉此調整與蓋體 62上的光學裝置64相對位置而提高輕光效率。 • 根據前述實施例的教示，光學裝置64是組設在開孔62a 内，其可以是透鏡或玻璃片；此外，開孔62a處也可無配置任 何元件或裝置。 又根據前述實施例的教示，圖7b顯示該絕緣構造54的第 -端54a可以具有一凹空57。該凹空57可低於金屬盤體42 的第一面48,且光電晶片56配置在凹空57内。 上述的絕緣構造24、54可利用第-端24a、54a的凹空57 • 來承載光電晶片26和56,且第-端24a、54a可以平齊、凸出 或凹低於第一面18、48。 圖8a顯示一輔助接腳7〇配置在絕緣構造％的轴向。輔 ； 助接腳70具有一第一位置71及一第二位置72，其中第一位 ^ 置71可露出絕緣構造24的第一端24a且相鄰金屬盤體12的 第面18’第一位置72可穿出絕緣構造24的第二端挪；光 電晶片26配置在第一位置71上。 圖8b顯示輔助接腳7〇的第一位置71可以明顯的凸出絕 8 的第一面18,藉此達 緣構造24的第-端24a，或金屬盤體12 到調整光電晶片26所處高度的目的。 第二由圖與圖此所揭示的結構中，輔助接腳70的 72明顯與電極接腳14a、⑷的端部不處於相當(相 )的水平位置的部份長度剪斷所以當 % :嶋成蝴漁辦 、第-位置72會形成懸空而不與電路連接，進而形成斷路。 根蹄述之絕緣構造24和54之第1 %和地可以平 ^凸^鳴繼12^18_概念，輔助接 L i—位置71也可以被設計成平齊、凸出或凹低金屬盤 體12之第一面18。 上述的光電晶片26可為習知以N+為基座的晶片，且宜兩 個電極使科同金制及位在上、下側；由於光電晶片^下 側㈣極與輔助接腳7G的第—位置71接觸所以可利用第一 位置71作為打線位置。 若光電晶片26❾二個電極位在相同側，例如位在上方 側’則形麵路的伽獅％騎影響元件的電極特性。 圖8C揭露另—實施例，其主要是調整或改變輔助接腳70 =長度’使其第二位置72與其他電極14a、14e的端部處在相 田或相同的水平位置；當底座1G或其構成之光電元件組設在 ’ _接腳7G可與電料接而碱祕。特別是， 光電晶片26的電極位在上、下側’貞1m_電極可與輔助接 腳70電性連接，並以該_接腳％作為電極。 圖8a〜圖8c中的底座10是選用圖2、圖3所顯示的結構， 所以各接腳Ha〜14d與絕輯造24為相離；然而亦可選用圖 5、圖6所揭示的底座4〇結構，並依上述實施例所教示，將輔 助接腳70組設於絕輯造54的軸向且使得各接腳咖〜44c的 一端插入絕緣構造54内。 圖9a及圖％顯示金屬盤體81上開設一嵌孔幻，且一絕 緣構每83喪入喪孔82 0 ;特別是，複數電極接腳恤〜84c的 一端穿過概構造83，且各電極接腳咖〜撕_部具有電 的良導體85(見第％圖）。上述電的良導體85可以是金。 此外更有一金屬薄膜87配置或鍍設在絕緣構造83的第- 端83a表面，且使金屬薄膜87與金屬盤體81形成電性相連。 金屬/專膜87的周邊具有缺空88用以對應各接腳84&〜84c，藉 此使知·金屬溥膜87與各接腳84a〜84c形成電性相離狀態。至 於光電晶片86則配置於金屬膜87上；若光電晶片86有一電 極位於底Φ且與金屬丨|膜87接觸，該金屬薄膜87可作為打 線區域。 再參閱圖％ ’嵌孔82可被製作成錐形孔狀，而且絕緣構 ie 83的外形製作成與嵌孔82形狀相符，因此絕緣構造83置 入嵌孔82内可據此達到緊密的結合及定位效果。 圖9c 9d所揭示之實施例與圖％、9b之實施例的不同在 於·金屬溥膜87上開設有一開孔89 ;光電元件86位在該開 M409531 孔89内且配置在絕緣構造83上。至於金屬薄膜87可選擇是 否與金屬盤體81電性相連。 圖9e係根據圖9d的結構加以演化，其特別處在於：一凸 邛831凸出地形成在絕緣構造83表面且穿過金屬膜^的開孔 89，光電晶片86配置在凸部831的端部。 圖9f揭露絕緣構造83的周邊可進一步延伸形成一延伸牆 ㈣2 ;該延伸牆部832的一端為具有開放口咖的開放端； -蓋體834組設在延伸牆部832的開放端，藉此可構成光電元 件的組態。 此外延伸牆部832具有—缺口伽，如此-來，打線用 之尖嘴容易靠近元件；同樣的道理亦可用於圖l〇a,戰12a， 12b及圖13a所示的結構中。 再者’辅助接腳70可組設在絕緣構造83的軸向，其第一 位置71可承载光電晶# 86，且調整獅接腳％的長度或高 度’可進而達成調整光電晶片86所處高度的效果；又輔助接 腳70的第二位置72伸出絕緣構造83長度若相對其他接腳 84a、84c成為懸空狀’也就是輔助接腳7〇的第二位置π比電 極接腳84a、84c的自由端更接近盤體81的第二面81&，則未 來使用該光電元件時，_猜7G可叫位於電路上而形成 斷路；若f二健72伸$縣構造83的姐或錄與其他接 腳咖、阶的端部（自由端)相當，則輔助接腳70可作為電極 且用來連接電路。 11 此外’若要輔接腳接70的長度足以連接電路，但又要使 其與光電⑼86形舰緣顿路’可以在域“ 86的基座 之下配置-個絕緣層構造，例如旋制氧化石夕(sph 〇n喊 SOG)，並接觸輔助接腳70，如此可達到上述的要求。 圖9f所揭露的輔助接腳7〇的第一位置7ι明顯凸出 薄膜:7或金缝體81 面，因此可達剩整光電晶片％ 所處门度的目的此外，圖9f所揭露的延伸牆部結構也 適用於圖9b及圖9d所揭示之底座結構。 圖l〇a揭露具有延伸牆部94的絕緣構造93嵌設在金屬盤 體92的軸向’且一蓋體95結合延伸牆部94 ;本實施例斑第 圖所揭露之實施例的不同處在於：本實施例無配置金屬 薄膜於絕緣構造93表面。 圖揭露該辅助接腳7〇組設在絕緣構造％的軸向，且 機輔助接腳70的長度與位置，可崎_整光電晶片％的 、或位獅效果，其次根據前賴明，獅接腳％可視需 求而等效於光電晶片96的—電極，或與之形成斷路。 以上說明的盤體12、42和81主要由金屬構造並結合非金 ^緣材料製成之絕緣構造24、M和幻；然而除了上述的 、，，。構外，亦有其他構成結構。 圖10c揭露更有—切構造咖形成在絕緣構造93上且 =出狀。—光學裝置93b組設在捕構造93a上且相對光電 日日96。上述的光學裳置娜可以是滤光片或監控檢光器 M409531 (MPD)’而支撐構造93a可以是一對凸出的柱體、環體或是其 他足以支撐光學裝置93b或提供光學裝置93b安裝位置的構 - 造。 " 圖Ua揭露一非金屬盤體100，以及複數電極接腳 - i〇4a〜104c組設在非金屬盤體1〇〇的軸向。其中各接腳 104a〜104c的一端可凸出於非金屬盤體1〇〇的第一面ι〇ι且表 面配置有電的良導體1〇5。又金屬膜1〇7係配置在非金屬盤體 # 1〇0的表面，且光電晶片106組設在金屬膜107上。如此光電 晶片106的電極可藉導線(未顯示)與接腳1〇4a、1〇如電性連 接；或金屬薄膜107電性連接光電晶片1〇6的一電極，再以一 導線(未顯示)連接金屬薄膜107與一接腳1〇4a或1〇4c，藉此 形成電性連接。 此外在圖11a中，若將電極接腳i〇4a、1〇4b或i〇4c上的 電的良導體1〇5與金屬臈1〇7連接在一起，則可以不使用導線 . 就可以讓電極接腳104a、1〇4b或104c與光電晶片106形成電 性連通。 圖lib所顯示之結構與圖lla的不同處在於：金屬薄膜⑺了 上開設有i孔·;光電晶片組設在開孔108的範圍内 且位在非金屬盤體100的表面。 圖lie所顯示之結構與圖llb之不同處在於：非金屬盤體 1⑼具有一體的凸部109 ;凸部1〇9高出第一面1〇1且可穿過 開孔108用以承載光電晶片106。是以凸部109具有調整光電 晶片106高度的功能。 值得注意的是，凸部109具有絕緣特性，因此可等同於前 述實施例的縣構造。進-步可推知，在非金屬盤體⑽上可 以將其中央區域定義成用以承载光電晶片廳的絕緣構造，而 且根據本創作的前述，絕緣構造可㈣平、凸出或凹低於 非金屬盤體1〇〇的第一面1〇1。 圖12a揭露非金屬盤體⑽的周邊可延伸形成—環狀構造 的延伸牆部11〇，延伸牆部no的—端為具有開放口 m的開 放端；-蓋體112組設在該延伸牆部11G關放端；其次蓋體 112 -端可具有-光學裝置114，例如(球形)透鏡、(平面)玻璃， 或僅僅是一個開孔且無配置任何元件。 圖12b顯不-輔助接腳70配置在非金屬盤體1〇〇的轴 向；辅助接腳70的一端凸出非金屬盤體1〇〇的第一面ι〇ι且 承載光電晶片106 ;蓋體112組設在延伸牆部11〇的開放端； 輔助接腳70凸出第-面101的長度或高度可用以調整光電晶 片1〇6的高度’藉此使光電晶片106接近蓋體112的光學裝置 114。此外輔助接腳70也作為光電晶片1〇6的一電極或^形 成斷路狀態。 / 在圖12a與圖12b所揭露的實施例中，非金屬盤體1〇〇的 第一面101上可配置一金屬薄膜1〇7。 圖13a揭露非金屬盤體1〇〇的延伸牆部11〇上配置—蓋體 112 ;複數電極接腳104a〜104c嵌入非金屬盤體1〇〇的轴向； M409531 光電晶片106或其他的光電/電子元件，配置在其中一電極接 腳104b上’且該電極接腳104b可以形成斷路，或是作為一電 -極。本實施例與圖12b所示實施例的相異處在於：本實施例無 金屬薄膜。 圖13b揭露的組態與圖13a所揭露的組態不同處在於：各 電極接腳104a〜l〇4c嵌入非金屬盤體1〇〇的方向；此外光電晶 片106為PIN二極體並且電性連接一轉阻放大器(tia);其中 電極接腳104c成懸空狀態，所以電極接腳1〇和將為斷路。 根據圖13b所顯示的結獅式，底座的製作可以選用圖 13c及圖13d所顯示的形式’其可先製作具有適當之各電極接 腳104a〜1〇4c的連續金屬帶或金屬片；進而利用射出成型方 式，於各電極接腳104a〜刚c的一端(如圖13c)或靠合處(如圖 13d)成形-非金屬盤體刚。如此可使非金屬盤體觸與各接 腳104a〜104c的射出成型更加方便。 以圖13d為例，形成連續帶狀或片狀的底座结構後可以 再逐-的針對每-個底座進行配置光電晶片1〇6、匹配元件及 打線(未顯示）；然後再進行裁切，藉此形成單一顆粒狀的光電 元件。 傳統的光電元件的方式是先製作出單一的底座，然後再逐 -固定體積彳M、的底座她置规晶4與打線；其巾底座要逐 -定位不容易；而本創作可以使複數底座構成連續帶狀或大面 積的片狀’方便製作設備夾持與定位，所以本創作可解決傳統 配置光電晶片與打線時所產生的不便性。 根據圖13b〜13d所揭露内容的教示，關於非金屬盤體1〇〇 與各接腳104a〜104c的組合可推及圖13e、13g、13i〜丨此圖所 顯式的形式及其鱗形式。其巾在非金體丨⑻上可配置一 金屬膜107。 又圖13f及圖13h揭露接腳84a〜84c配置在金屬盤體％ 與絕緣構造93所組成的混合架構的水平方向。其中絕緣構造 93上具有一金屬薄膜87，與金屬盤體％可電性相連。 在上述實施例中提及絕緣構造24、54、83和93可藉自身 在金屬盤體12、42、8卜和92上形成-個獨立的絕緣部件， 或搭配辅助接腳70形成一個獨立的絕緣部件；更進一步，絕 緣構造24、54、83和93的端面可以齊平、凸出或凹下於該金 屬盤體12、42、8卜和92的表面，且光電晶片％、兄、％ 和96可以配置在獨立的絕緣部件上。 肩除了上述的架構外’圖14a顯示絕緣構造12〇可具有 柱體m且端面⑵為傾斜狀，一光學元件/光學裝置123係 配置在端面成傾斜狀；又圖14b及圖Me顯示絕緣構造 120應用其凸㈣讀121及平整的表面125可分職置光學 元件/光學裝置⑵和124’·圖14d揭露絕緣構造12〇可具有二 個柱體121和126且分別配置光學元件/光學裝置123和、124^ 揭露絕緣構造12〇更可具有凹空π且供光學元件境 學裝置128配置。 M409531 由圖LMe所教示，絕緣構造⑽上可以具有一或多個 柱121、126及凹空127，且其端面可以形成傾斜面或平面 狀’更可以在絕緣構造120的柱體⑵、126、凹空127及表 面125配置光學元件/峨置123、跑互相對應，藉此滿 足光電讀所要求的光電特性，利用前述條件的任—結合，可 設計用來降_流雛(咖mlGSS)，较顧及監控檢光二極體 (Momtot photodiode)產生賴蝴或監控的需求。M409531 V. New description: [New technical field] This creation is about the technical field of optical communication, especially the optical communication chip structure for receiving illuminating signals. [Prior Art] A photovoltaic element is a combination of a base and an optoelectronic wafer. The base may be a combination of a metal stem and a metal pin, such as a T〇can Header, or a combination of a non-metallic disk and a metal pin, such as a Leadframe Header. Secondly, a carrier can be disposed on the base to carry the photoelectric wafer, and the electrodes of the photovoltaic chip are connected to the circuit on the circuit board through the pins. The electrodes of the above photoelectric wafer may be located on opposite sides, for example, one bit is on the upper surface of the photovoltaic wafer, and the other is on the lower surface of the photovoltaic wafer; when the photovoltaic wafer is disposed on the submount, the electrode on the lower surface may be loaded with The body contacts and forms an electric f-connection, 纟σ, and the carrier further acts as a wire 塾 (b〇un (jing pa (j), such that a wire can be connected - chat 35 poles) and the carrier; as for the upper surface of the photovoltaic wafer The electrode can also be electrically connected to another pin (electrode) by a wire. It is worth noting that the surface of the carrier and the base needs to be in a non-conducting state. Figures 1a and 1b show the two electrode positions of the photovoltaic chip. The same surface, for example, an electrode is located on the upper surface of the photovoltaic wafer; taking the photoelectric element of the piN_TIA structure as an example, the photovoltaic wafer 200 is located on a hetero-substrate/carrier 2〇5, and the combination thereof is disposed on a base 201; The optoelectronic chip 2 is electrically connected to a transimpedance amplifier (TIA) 202, and the optoelectronic chip 2 is insulated from the base 2〇1 and can be operated by M M M M M M M M M M M M M M M M M M M M M M M M M Large area, Thus, the capacitance of the optoelectronic wafer 200 is increased and the frequency response is reduced. 胄1C and FIG. 1 - show another way in which the optoelectronic wafer 200 can be insulatively disposed on the base 201 and operated. It is mainly in-homogeneous A semi-insulating sub-plate (semi-insulating sub-te), a layer of sa formed on the M_N structure, and two electrodes 2〇3, 2〇4 are formed by a residual technique; however, a semi-insulating substrate 2〇6 also has a high cost loss, and the thickness of the N+ crystal layer is very thin (usually only a few micrometers (four), so it must be matched with a precise surname process to prevent the N+ crystal layer from being inadvertently etched and the component cannot be In addition, U.S. Patent No. 6,586,718 discloses an optoelectronic wafer which exposes a cryptogenic layer on a homogeneous semi-insulating substrate; wherein the N-crystalline layer is easily worn by the etched over. Lai's component is to insulate between the optoelectronic chip and the base. The use of a heterogeneous substrate results in high cost and bandwidth reduction. The use of a homogeneous semi-insulating substrate, in addition to the high cost, is also difficult to control the etching due to the thin layer. The process results in a process that requires considerable precision. : [New content] The purpose of this creation is to provide a type of track K-turn with a monthly b to allow the use of the chip's optoelectronic components with high frequency, low cost, Easier to make and/or high yield. Further, 'The wafer structure of this creation is specially designed to have 4 large thickness and electrically conductive homogenous base (N+ base), semi-insulated base or non-conductive a pedestal, and a crystal layer structure is disposed on the susceptor; the wafer further has two electrodes and is located on the same side and has the same metal structure; and is supplemented by a layer of low dielectric constant material (Low K material layer, such as BCB or s〇G) Reduce the design of the capacitor, or put the SOG on the bottom to insulate the base, so that the optoelectronic components using the chip can have high frequency, low cost, easy fabrication and/or high yield. The optoelectronic wafer is generally a photodetector diode of the p_I_N structure, and may also be a laser diode or a light emitting diode. The above-mentioned purpose; efficacy, and other purposes and effects of the present invention can be explained one by one by the following embodiments and with the drawings. [Embodiment] FIG. 2 and FIG. 3 disclose a structure of a base 1 () of a photovoltaic element, which has a metal stem 12, a plurality of electrode pins 14a to 14c which can serve as electrodes, and a ground connection. a foot 14d; wherein one end of each pin, such as ~Md, can be embedded in the metal disk body 12; in particular, the electrode pins 14a-14c can be combined with a non-conductive material 16, such as glass, recycled material, or other like The material is such that the metal disk body 12 and each of the pins i4a to 14c are in a non-conductive state. Further, the metal disk body 12 has a first surface (disk surface) 18, and a second surface (bottom surface) 19 opposite the first surface 18, such as the upper surface and the lower surface in the drawing; - the through hole 22 is formed in a central region between the first face 18 and the second face 19 and located at the first face; the insulating member 24' is an insert made of an insulating material, which is assembled in the insert hole 22 and is called a mQlding) Formed in the embedded hole M409531 22, the -e edge structure & 24 may be all or part of the body age between the (4) and the second surface 19 of the disk body η and the insulating structure is to carry the photovoltaic wafer 26 〇 Yes, the insulating structure 24 has a first end 24a and a second end 24b, wherein the first end 24a can be adjacent and flush with the first (four), and the first end (10) carries the optoelectronic wafer 26. The above insulation structure 2 is a separate insulating member or an insulating portion. Selecting the photo-wafer % of the electrodes 26a and 26b on the same side, and arranging the optoelectronic wafer 26 at the first end 2 of the insulating structure 24, for example, the wire tearing and the connecting of the electrodes 26a and 26b and the bonding (4) & and Mc; The photoelectric cymbal sheet 26 in the state and the metal disk body 12 of the base 1 are in a non-conductive open state. The above embodiments provide an innovative base 1 structure and can form a synergistic effect with the photovoltaic wafer 26, which is turned over to the structure of the wire carrier to carry the photovoltaic wafer or to form an insulating layer on the photovoltaic wafer. 4a, the photocell 30 can include the above-mentioned base 1 and optoelectronic wafer 26 and further include a cover (caP) 32 disposed on the base 1; wherein the cover 32 has an opening 32a' and the opening 32a can be An optical device 34, such as a lens or glass sheet, is disposed, or no components or devices are disposed at the opening 32a. The opening 32a or the optical device 34 described above is relative to the photovoltaic wafer. 4a shows that the first end 24a of the insulating structure 24 protrudes from the first side 18 of the metal disk body 12; therefore, the first end 24a of the optoelectronic wafer 26 in the insulating structure 24 is insulate from the metal disk body 12, The distance to the device 34 or the opening 32a can be varied with the height of the protrusion 6 M409531 of the first end 24a, thereby adjusting the light efficiency of the vehicle. In accordance with the above-described implementations, Figure 4b shows that the first end 24a of the configuration 24 can be recessed below the first face 18 of the metal disk body 12. " Again, the second end (10) of the 'insulating construction 24 of Figure 4a or Figure 4b can & out, flush or recess the second side 19 of the metal ship 12; or refer to the description of the following embodiments. 5 and 6 show that a large-area insertion hole 52 is formed in the gold-plated disk 42 of the base 4; in particular, the area of the insertion hole 52 includes a central region of the metal disk 42 and an area adjacent to the edge; The insulating structure 54 may be disposed in the insertion hole 52 or formed in the insertion hole 52 by means of injection. It is noted that the electrode pins 44a to 44c are located in the range of the insertion hole 52 and one end is combined with the insulation structure %; The optoelectronic wafer 56 is disposed at a first end 5 of the insulating construction 54. The metal disk body 42 and the electrode pins 44a to 44c and the grounding pin _ (see FIG. 5) can be combined first, and then the combination body is guided into the forming tool and the mold, and the mode is intended to be incident. The insulating material is injected into the insertion hole 52 to form the insulating structure 54 while the respective electrode pins 44a to 44c' are combined by the insulating structure 54. Further, the clamping pressure of the injection process can be utilized to make the grounding pin 4 and the metal disk 42 Bonding or otherwise stamping the grounding pin 44d to bond the metal disk body 42. In addition, the second end 54b of the insulating structure 54 is shown in FIG. 6 to flush the second face 49 of the metal disk body 42 or the edge of the through hole 52; however, as can be seen from the foregoing description, the second end 54b can also be convex or recessed. The second face 49 of the metal disk 42; or 7 M409531 is referred to the description of the following embodiments. Figure 7a shows that a photovoltaic element 60 is comprised of a base 40 in combination with an optoelectronic wafer 56 and is more closely associated with a cover 62; in particular, the first end 54a " of the insulative construction 54 has a body-shaped projection 55; The convex portion 55 protrudes from the first side 48 of the metal disk body 42, and the photovoltaic wafer 56 is assembled on the convex portion 55. Thus, the photovoltaic wafer % is insulated from the metal disk body 42, and the photovoltaic wafer 56 can thereby adjust the position relative to the optical device 64 on the cover 62 to improve the light efficiency. • In accordance with the teachings of the previous embodiments, the optical device 64 is assembled within the aperture 62a, which may be a lens or a piece of glass; further, no components or devices may be provided at the aperture 62a. Further in accordance with the teachings of the previous embodiments, Figure 7b shows that the first end 54a of the insulating construction 54 can have a recess 57. The recess 57 can be lower than the first face 48 of the metal disk body 42 and the optoelectronic wafer 56 is disposed within the recess 57. The insulating structures 24, 54 described above can utilize the recesses 57 of the first ends 24a, 54a to carry the optoelectronic wafers 26 and 56, and the first ends 24a, 54a can be flush, convex or concave below the first face 18, 48. Figure 8a shows an auxiliary pin 7〇 disposed in the axial direction of the insulation construction %. The auxiliary pin 70 has a first position 71 and a second position 72, wherein the first position 71 can expose the first end 24a of the insulating structure 24 and the first surface 18' of the adjacent metal disk body 12 is first The position 72 can be passed through the second end of the insulating formation 24; the optoelectronic wafer 26 is disposed in the first position 71. Figure 8b shows that the first position 71 of the auxiliary pin 7〇 can be clearly projected out of the first face 18 of the shoe 8, thereby reaching the first end 24a of the edge structure 24, or the metal disk body 12 to the adjustment optoelectronic wafer 26 High purpose. In the structure disclosed by the figures and figures, the 72 of the auxiliary pin 70 is obviously cut off from the length of the portion where the ends of the electrode pins 14a, (4) are not at the corresponding (phase) horizontal position, so when % : 嶋In the butterfly fishing, the first position 72 will form a dangling without connecting with the circuit, thereby forming an open circuit. The 1st and the ground of the insulating structure 24 and 54 of the root hoof can be flattened and convex, followed by the 12^18_ concept, and the auxiliary connection L i-position 71 can also be designed as a flush, convex or concave low metal disk body. The first side of 12 is 18. The above-mentioned optoelectronic chip 26 may be a conventional N+-based wafer, and it is preferable that two electrodes are made of the same gold and positioned on the upper and lower sides; since the lower side (four) of the photovoltaic chip and the auxiliary pin 7G are - Position 71 is in contact so that the first position 71 can be utilized as the wire position. If the two electrodes of the optoelectronic chip 26 are on the same side, for example, on the upper side, then the gamma lion ride of the profiled surface affects the electrode characteristics of the component. Figure 8C discloses another embodiment, which primarily adjusts or changes the auxiliary pin 70 = length ' such that the second position 72 is at the same horizontal position as the ends of the other electrodes 14a, 14e; when the base 1G or The photoelectric element group formed in the '_ pin 7G can be connected to the electric material and is alkaline. In particular, the electrode sites of the optoelectronic wafer 26 are electrically connected to the auxiliary pin 70 on the upper and lower sides, and the _ pin % is used as the electrode. The base 10 in FIGS. 8a to 8c is a structure shown in FIG. 2 and FIG. 3, so that the pins Ha 14 14d are separated from the masterpiece 24; however, the bases disclosed in FIG. 5 and FIG. 6 may also be selected. 4 〇 structure, and in accordance with the teachings of the above embodiments, the auxiliary pins 70 are assembled in the axial direction of the master 54 and one end of each of the pins 44c is inserted into the insulating structure 54. 9a and FIG. 10 show that a metal hole 81 has a hole-embedded phantom, and an insulating structure has 83 holes into the hole 82 0; in particular, one end of the plurality of electrode-studs 〜84c passes through the general structure 83, and each The electrode pin coffee ~ tear _ part has a good conductor 85 (see Figure %). The good electrical conductor 85 described above may be gold. Further, a metal film 87 is disposed or plated on the surface of the first end 83a of the insulating structure 83, and the metal film 87 is electrically connected to the metal disk 81. The periphery of the metal/film 87 has a void 88 for corresponding to each of the pins 84 & 84c, whereby the metal tantalum film 87 is electrically separated from the pins 84a to 84c. The photovoltaic wafer 86 is disposed on the metal film 87. If the photovoltaic wafer 86 has an electrode located at the bottom Φ and is in contact with the metal ruthenium film 87, the metal thin film 87 can serve as a wiring region. Referring again to the figure, the 'insert hole 82' can be formed into a tapered hole shape, and the outer shape of the insulating structure 83 is formed to conform to the shape of the insertion hole 82. Therefore, the insulating structure 83 is placed in the insertion hole 82 to thereby achieve a tight bond. And positioning effects. The embodiment disclosed in Fig. 9c 9d differs from the embodiment of Figs. 9 and 9b in that an opening 89 is formed in the metal ruthenium film 87; the photovoltaic element 86 is positioned in the opening M409531 hole 89 and disposed on the insulating structure 83. As for the metal film 87, it is optional whether or not it is electrically connected to the metal disk 81. Figure 9e is an evolution according to the structure of Figure 9d, in particular: a tenon 831 is convexly formed on the surface of the insulating structure 83 and passes through the opening 89 of the metal film, and the optoelectronic chip 86 is disposed at the end of the convex portion 831. unit. Figure 9f discloses that the periphery of the insulating structure 83 can be further extended to form an extension wall (4) 2; one end of the extension wall portion 832 is an open end having an open mouth; - a cover 834 is disposed at the open end of the extension wall portion 832, whereby It can constitute the configuration of the optoelectronic component. Further, the extension wall portion 832 has a notch gamma, so that the tip of the wire is easily brought close to the component; the same principle can be applied to the structure shown in Fig. 1a, Wars 12a, 12b and Fig. 13a. Furthermore, the auxiliary pin 70 can be disposed in the axial direction of the insulating structure 83, and the first position 71 can carry the photoelectric crystal #86, and the length or height of the lion pin can be adjusted to further adjust the position of the photovoltaic chip 86. The second position 72 of the auxiliary pin 70 extends beyond the length of the insulating structure 83. If the length is opposite to the other pins 84a, 84c, that is, the second position π of the auxiliary pin 7 is higher than the electrode pin 84a. The free end of the 84c is closer to the second side 81& of the disc 81, and when the optoelectronic component is used in the future, the guessing 7G can be called on the circuit to form an open circuit; if the f-two 72 is extended to the county or 83 of the county structure 83 The auxiliary pin 70 acts as an electrode and is used to connect the circuit, as is equivalent to the other pin (step) (free end). 11 In addition, 'if the length of the auxiliary pin 70 is sufficient to connect the circuit, but to make it and the photoelectric (9) 86-shaped ship's edge can be configured under the base of the domain "86" - an insulating layer structure, such as spinning The above requirements are met by the oxidized stone spur (Sph 〇n shouting SOG) and contacting the auxiliary pin 70. The first position 7 ι of the auxiliary pin 7 图 disclosed in Fig. 9f clearly protrudes from the film: 7 or gold seam 81 face, thus achieving the goal of the remaining photovoltaic wafer %. In addition, the extended wall structure disclosed in Figure 9f is also applicable to the base structure disclosed in Figures 9b and 9d. Figure l〇a discloses an extended wall The insulating structure 93 of the portion 94 is embedded in the axial direction of the metal disk 92 and a cover 95 is coupled to the extended wall portion 94. The embodiment disclosed in the first embodiment of the present embodiment is different in that the embodiment has no metal. The film is on the surface of the insulating structure 93. The figure shows that the auxiliary pin 7〇 is disposed in the axial direction of the insulating structure, and the length and position of the machine auxiliary pin 70 can be used to form a photocell or a lion effect. Secondly, according to the former Lai Ming, the lion's pin is equivalent to the optoelectronic chip 9 according to the needs. The electrode of 6, or the formation of an open circuit therewith. The disk bodies 12, 42 and 81 described above are mainly constructed of metal and combined with the insulating structure 24, M and illusion made of non-golden material; however, in addition to the above, Further, there are other constituent structures. Fig. 10c discloses that a more-cut structure is formed on the insulating structure 93 and is out of shape. The optical device 93b is disposed on the catching structure 93a and is opposite to the photoelectric day 96. The skirt may be a filter or monitor photodetector M409531 (MPD)' and the support structure 93a may be a pair of protruding cylinders, rings or other sufficient to support the optical device 93b or provide the optical device 93b mounting position. Figure Ua discloses a non-metallic disk body 100, and a plurality of electrode pins - i〇4a to 104c are disposed in the axial direction of the non-metallic disk body 1 。. One end of each of the pins 104a to 104c It can protrude from the first surface of the non-metallic disk body 1〇〇 and has a good conductor 1〇5 on the surface. The metal film 1〇7 is disposed on the surface of the non-metal disk body #1〇0. And the photovoltaic wafer 106 is assembled on the metal film 107. Thus, the electrodes of the photovoltaic wafer 106 can be borrowed The wire (not shown) is electrically connected to the pins 1〇4a, 1〇; or the metal film 107 is electrically connected to an electrode of the photovoltaic chip 1〇6, and then connected to the metal film 107 by a wire (not shown). The foot 1〇4a or 1〇4c is used to form an electrical connection. In addition, in Fig. 11a, if the electrical conductors 〇5 and metal 臈 on the electrode pins i〇4a, 1〇4b or i〇4c are used 1〇7 is connected together, and the electrode pins 104a, 1〇4b or 104c can be electrically connected to the optoelectronic wafer 106 without using wires. The structure shown in Fig. lib differs from that of Fig. 11a in that: metal The film (7) is provided with an i-hole; the photovoltaic chip group is disposed in the range of the opening 108 and is located on the surface of the non-metallic disk body 100. The structure shown by the diagram lie differs from that of FIG. 11b in that the non-metallic disk body 1 (9) has an integral convex portion 109; the convex portion 1〇9 is higher than the first surface 1〇1 and can pass through the opening 108 for carrying photoelectric Wafer 106. The convex portion 109 has a function of adjusting the height of the photovoltaic wafer 106. It is to be noted that the convex portion 109 has an insulating property and thus can be equivalent to the county structure of the foregoing embodiment. Further, it can be inferred that the central region of the non-metallic disk body (10) can be defined as an insulating structure for carrying the photovoltaic wafer hall, and according to the foregoing description of the present invention, the insulating structure can be (four) flat, convex or concave below The first side of the metal disk body 1 is 1〇1. Fig. 12a discloses that the periphery of the non-metallic disk body (10) can be extended to form an annular wall structure 11〇, the end of the extension wall portion is an open end having an open port m; the cover body 112 is assembled on the extension wall The portion 11G is closed; the second cover 112-end may have an optical device 114, such as a (spherical) lens, (planar) glass, or just an opening and without any components. Figure 12b shows that the auxiliary pin 70 is disposed in the axial direction of the non-metallic disk body 1; one end of the auxiliary pin 70 protrudes from the first surface of the non-metallic disk body 1 and carries the photovoltaic wafer 106; The cover body 112 is disposed at an open end of the extension wall portion 11A; the length or height of the auxiliary pin 70 protruding from the first surface 101 can be used to adjust the height of the photovoltaic wafer 1〇6 to thereby bring the photovoltaic wafer 106 close to the cover body 112. Optical device 114. Further, the auxiliary pin 70 is also formed as an electrode or an open state of the photovoltaic chip 1?6. In the embodiment disclosed in Figs. 12a and 12b, a metal film 1〇7 may be disposed on the first side 101 of the non-metallic disk body 1〇〇. FIG. 13a discloses that the extension wall portion 11 of the non-metallic disk body 1〇〇 is disposed on the cover body 112; the plurality of electrode pins 104a to 104c are embedded in the axial direction of the non-metal disk body 1; M409531 photoelectric wafer 106 or other photoelectric / Electronic component, disposed on one of the electrode pins 104b' and the electrode pin 104b can form an open circuit or as an electric pole. The difference between this embodiment and the embodiment shown in Fig. 12b is that this embodiment has no metal film. The configuration disclosed in FIG. 13b differs from the configuration disclosed in FIG. 13a in that each of the electrode pins 104a to 104c is embedded in the direction of the non-metallic disk body 1; in addition, the photovoltaic wafer 106 is a PIN diode and is electrically A transimpedance amplifier (tia) is connected; wherein the electrode pins 104c are in a floating state, so the electrode pins 1 and will be open. According to the lion-like type shown in Fig. 13b, the base can be fabricated in the form shown in Fig. 13c and Fig. 13d, which can be used to make a continuous metal strip or metal sheet with appropriate electrode pins 104a~1〇4c; By the injection molding method, a non-metallic disk body is formed at one end (as shown in Fig. 13c) or at the joint (Fig. 13d) of each of the electrode pins 104a to 104b. This makes it easier to inject the non-metallic disk body into the respective pins 104a to 104c. Taking FIG. 13d as an example, after forming a continuous strip or sheet-like base structure, the photovoltaic wafers 1〇6, matching components, and wire bonding (not shown) can be disposed for each base one by one; and then cut, Thereby, a single granular photovoltaic element is formed. The traditional way of optoelectronic components is to make a single base first, and then to fix the volume 彳M, the base is placed on the base 4 and the wire; the base of the towel is not easy to locate one by one; and the creation can make the plural base The continuous strip shape or large-area sheet shape is convenient for the clamping and positioning of the manufacturing device, so the creation can solve the inconvenience caused by the conventional configuration of the photovoltaic wafer and the wire bonding. According to the teachings of the contents disclosed in FIGS. 13b to 13d, the combination of the non-metallic disk body 1 and the pins 104a to 104c can be derived from the form shown in FIG. 13e, 13g, 13i~ . The towel may be provided with a metal film 107 on the non-gold body (8). 13f and 13h disclose that the pins 84a to 84c are disposed in the horizontal direction of the hybrid structure composed of the metal disk body % and the insulating structure 93. The insulating structure 93 has a metal film 87 electrically connected to the metal disk body. It is mentioned in the above embodiments that the insulating structures 24, 54, 83 and 93 can form a separate insulating member on the metal disk bodies 12, 42, 8 and 92, or form an independent pair with the auxiliary pins 70. Insulating member; further, the end faces of the insulating structures 24, 54, 83, and 93 may be flush, convex, or concave on the surface of the metal disk bodies 12, 42, 8 and 92, and the photovoltaic wafer %, brother, % The and 96 can be configured on separate insulation components. In addition to the above-described structure, FIG. 14a shows that the insulating structure 12A can have a cylinder m and the end surface (2) is inclined, and an optical element/optical device 123 is disposed on the end surface in an inclined shape; and FIG. 14b and FIG. 120 applies its convex (four) read 121 and flat surface 125 to separate optical components/optical devices (2) and 124'. FIG. 14d discloses an insulating structure 12A having two cylinders 121 and 126 and respectively arranging optical elements/optical devices 123 and 124^ disclose that the insulating structure 12A can have a recess π and is configured for the optical component device 128. M409531 is taught by the diagram LMe, the insulating structure (10) may have one or more columns 121, 126 and a recess 127, and the end faces thereof may form an inclined surface or a planar shape, and may be in the column (2), 126 of the insulating structure 120, The concave space 127 and the surface 125 are arranged with the optical elements/devices 123, and run to correspond to each other, thereby satisfying the photoelectric characteristics required for photoelectric reading, and any combination of the foregoing conditions can be designed to reduce the flow of the chicks (coffee mls). More attention is paid to the need to monitor the detection or monitoring of the Momtot photodiode.
以圖14 4例’光學元件/光學裝置123可為-面射型雷 射VCSEL或檢光二極體(非;以圖咐為例光學元件 /光學裝置124可為-面射型雷射，而另一光學元件/光學裝置 123則可為-滤光片（fl㈣或為卿；又以圖⑷為例，光學 元件/光學f置！23可為VCSEL，㈣—絲元件/光學裝置 124為卿，至於位在光學元件/光學褒置123上方的光學元14] The 'optical element/optical device 123 can be a surface-emitting laser VCSEL or a photodetector diode (not; for example, the optical element/optical device 124 can be a surface-emitting laser, and The other optical component/optical device 123 can be a filter (fl(iv) or qing; in the figure (4) as an example, the optical component/optical f! 23 can be a VCSEL, (4)-the wire component/optical device 124 is qing As for the optical element above the optical element / optical device 123
件/光學裝置域W ;再_ 14d為例，光學元件/光學裝置 123為VCSEL ’而另-光學元件/光學裝£ 124為。 然而圖14a〜14e中的各光學元件/光學裝置123、124與128 可以局部或全部由光電晶片取代。 上述實施例所提及的光電晶片可取用先前技術中所揭露 的光電晶t並且配置在本創作簡露的底座上，藉此組成光 電元件。然而更可以採用以下所揭露之光電晶片結構。 圖15a揭露一光電晶片146(可取代前述光電晶片26、56、 86、96或1〇6)的構成係一包含有第二極性的晶層構造15〇藉 17 M409531 蟲晶而形成在-具有第-極性的基^ 13G上^前述的第一極性 與第一極性為相異的極性’例如圖中所示的晶層構造〗刈上包 含有P晶層’也可再包含们晶層或其它魏之獅晶層；基 座130為N+基座。 根據上述的構成方式，本創作也可以採用晶層構造15〇包 含N晶層來搭配P基座。然而不論採用那一種形式組合，基 座130厚度皆要遠大於晶層構造15〇中的晶層厚度。 圖153係以卩晶層搭配]^基座為例。基座13〇為高換雜 的可導電基座(N+基座）；具有複數蠢晶層的晶層構造15〇係長 晶在基座130的第-侧130a;其次二個具有相同金屬構成之 電極131和132形成在晶層構造15〇的同側，例如圖中所示的 上方側。 再者高掺雜的可導電基座no具有較大的厚度，其厚度可 以是5〇〜io〇0um之間，而通常落在7〇〜7〇〇聰之間以具有厚 實的支樓賊，所以可導座m的厚度可岐傳統n晶 層厚度的針倍至數百倍之間，但隨㈣織躺進步，厚度 =來有可能再朝向薄型化發展，並能兼顧厚實支樓的需求；在 藉敍刻技術形細立的電極131來作為打線墊時，即使侧到 可導電基座13G，仍可以使打線墊保持電極特性，是以本實施For example, the optical component/optical device 123 is VCSEL' and the other optical component/optical device is 124. However, each of the optical elements/optical devices 123, 124, and 128 in Figures 14a through 14e may be partially or fully replaced by an optoelectronic wafer. The optoelectronic wafers mentioned in the above embodiments can be taken from the photonic crystals t disclosed in the prior art and disposed on the base of the present invention, thereby constituting the photovoltaic elements. However, the photovoltaic wafer structure disclosed below can be used. Figure 15a illustrates a configuration of an optoelectronic wafer 146 (which may replace the aforementioned optoelectronic wafer 26, 56, 86, 96 or 〇6). A crystal layer structure 15 comprising a second polarity is formed by the 17 M409531 worm crystal. The first polarity of the first polarity is the same as the polarity of the first polarity. For example, the crystal layer structure shown in the figure includes a P layer, and may further comprise a layer or Other Wei lion layers; the base 130 is an N+ pedestal. According to the above configuration, the present invention can also be used with a crystal layer structure 15 〇 containing an N crystal layer to match the P pedestal. However, regardless of which combination of forms is used, the thickness of the base 130 is much greater than the thickness of the layer in the 15" layer structure. Figure 153 shows a case where the twin layer is matched with the ^ base. The pedestal 13 is a highly interchangeable conductive base (N+ pedestal); a crystal layer structure having a plurality of stray layers 15 长 is grown on the first side 130a of the susceptor 130; the second two are formed of the same metal The electrodes 131 and 132 are formed on the same side of the crystal layer structure 15A, such as the upper side shown in the drawing. Furthermore, the highly doped conductive base no has a large thickness, and the thickness thereof may be between 5 〇 and io 〇 0 um, and usually falls between 7 〇 and 7 〇〇 以 to have a thick branch thief. Therefore, the thickness of the guide seat m can be between the needles of the thickness of the conventional n-layer layer and hundreds of times, but with the progress of (4) weaving, the thickness = may be further developed toward thinning, and can take into account the thick branch. Demand; when the electrode 131 is used as the wire pad, even if it is side-to-conductive base 13G, the wire pad can maintain the electrode characteristics.
例所揭露的光電晶片H6結構保有製程控制上的彈性。此外N 型的可導電基座⑽的第二側(底面)13%並無相同材質之半絕 緣或不導電基座。 18 此外’二電極131和132為具有相同導電金屬的結構，通 常為蕭特基金屬，特別是由Ti/Pt/Au堆疊的金屬結構，其中 Τι(具有與半導體較佳的黏附力)通常為 10-100nm、Pt(為一個 barrier金屬，於某些實施例中，可無此層)通常為5〇_2〇〇nm， 而Au(供後繽打線或連結之用)通常為1〇〇_2〇〇〇nm，但若結合 電鍍的製程，Au的厚度將可達數um以上。上述的鈦金屬可 以由鉻(Cr)取代，使電極131或132的金屬架構成為Cr/Au或 是Cr/Pt/Au架構。 上述的晶層的厚度為：P型晶層通常約1〇〇 nm 〜2000 nm、I型晶層通常約500nm〜5000nm。 圖15a的光電晶片結構係可特別地搭配圖2、3、4a、4b、 5、6、7a、7b、8a、8b、9c、9d、9e、10a、10b(例如在輔助接 腳為斷路狀態下）、lib、iic、i2a、13b、Ha〜He圖所揭露的 底座，因這些底座都特別使用一個絕緣構造，或是具有與其它 接腳腳位不在同平面的輔助接腳，所以使用本創作之低成本的 N+基座130,且搭配具有相同材質的p電極丨32和N電極131， 可以使光電晶片146不透過載體而置放於底座上，藉此達到降 低成本與元件電容，以及增進高頻響應的特性。 睛參閲第15b圖，本實施例與圖i5a所顯示之實施例的 不同在於：一第一絕緣層133位在可導電基座13〇的一側，例 如旋制氧化石夕(Spin on glass, SOG )。此結構形態可適用於圖 2〜14e的各式底座或是傳統的基座(如la或lc所示），此時可 免除異質基板(載體205)的使用，但亦可視需要予以保留。 圖15c除了更詳細的顯示pm架構外，更加入一低介電常 數層(Low-K Layer) 134位在P電極的下方，且填充於p磊晶層 被蝕刻掉的區域内，或低介電常數層134位於二個電極131、 132之間’藉此可以降低元件的的電容值。該低介電常數層I% 可由一厚膜(Thick Film)取代。 圖15a〜15c所揭露的光電晶片146為因應每一個具絕緣構 造的底座而設計，且光電晶片146搭配各底座可構成—種具新 穎及進步性的光電元件。 圖15d與圖15c的差別在於可導電基座130的底面具有— 第一絕緣層133。另外在圖15c至圖15j的晶層構造中皆具有 一第二絕緣層137。 延續圖15c、15d之實施例内容，光電晶片的架構可以是 圖15e〜15j所顯示的架構；其中圖I5e、15f揭露為一種擴散型 (diffiisiontype)PIN架構，可具有低介電常數層134或厚層；圖 15g〜15j揭露一種平台型(mesatype)PIN架構’其配置有低介電 常數層134或厚層，其介電常數或厚層的厚度係以降低電容值 20%以上為設計標準。 又圖15h至圖15j，其揭露P晶層與I晶層之間可有一高 能隙介面晶層138。該高能隙介面晶層138為未攙雜或低纔雜 的InP或InAlAs層。此為高能隙材質，用以降低漏電流，一般 厚度介於10 nm〜200 nm之間。 上述的低介電常數層134或厚層可以是SOG塗層或是旋 佈介電層(spin on dielectric，SOD)或CVD介電材料。 圖15k顯示一種可用於檢光二極體(Photo-Diode，PD)的光 電晶片160結構。光電晶片160包含一晶層構造161長晶在一 基座162上。晶層構造161包含P-I-N+晶層，且基座162為半 絕緣基座或是不導電基座，例如磷化銦(InP)或砷化鎵(GaAs) 材質。其次’二個電極163和164(或打線墊)位在晶層構造161 的同側。更進一步而言，二個電極163和164可以不在同一水 平高度’但由俯視方向則可見到二個電極。 該電極(打線塾)163係電性連接N+晶層，而另一電極(打 線墊)164電性連接p晶層。特別是，電極164的構造為具有側 壁(side wall)構造，也就是電極164經由晶層構造161的側邊， 其一端位於基座162之上’另一端以少數部份面積電性連接該 P晶層，如此可以有效降低二個電極(打線墊)163和164之間 的電容值。 更進一步，可在電極164與晶層構造161及基座162之間 配置個第二絕緣層165。其次，根據前述實施例的教示，該 二電極163和164可以具有相同的金屬架構。 又，請參閱第15L圖，本創作所揭露的各光電晶片的晶層 構造具有一抗反射鍍膜139 ;通常這個抗反射鍍膜Π9係對應 位於晶片或第二極性上方的主動區(即欲接受待入射光源訊號 的區域)139a;抗反射鍍膜139的厚度大約是待入射的光源波 M409531 長的四分之一，據此可以提高待入射光源注入元件的效率。 另外’前面實施例所提及的二電極26a和26b、131和132 及163和164，所描述該二電極位於同側，係指由俯視方向可 以見到二個電極。 圖16a、16b顯示以PIN-TIA光電元件架構為例，其中底 座142具有一絕緣構造144(關於絕緣構造的結構形式詳見上 述的底座結構）’光電晶片146配置於絕緣構造144，並使可導 電基座130位在絕緣構造144表面，藉此使得光電晶片146與 底座142形成絕緣。此外二電極131、132藉導線135與轉阻 放大器136電性連接(見圖i6b)。 根據上述實施例的教示’該二電極也可以與複數電極接腳 中的至少一部份形成電性連接；前面所稱之電性連接係包含由 電極和直接以導線減電極接腳，或是個導線由電極透過其 它主/被動元件，轉阻放大器、電容等等元件，間接連接到電 極接腳；惟不論直接或間接形式均屬電極與電極接腳電性連接 之範疇。 上述實施例所使用的可導電基座13〇為一種同質基座，其 成本低於傳統使用的半絕緣基板，*且該可導電基座⑽與絕 緣構造144的組合形態可以滿足光電元件146與底座142形成 絕緣要求免除賴的需求’因此具有降低成本提高頻寬的功 效。 其次可導電基座130的厚度大，所以在_形成電極i3i 22 時’即使侧到可導電基座130也不易產生姓穿的情形因此 侧控制為簡便，達到製程參數彈性化及高良率的功效。 再參閱圖16a’可—步地配置一辅助接腳(或為PIN接腳)7〇 在絕緣構造144的軸向；輔助接腳7〇的第一端71可承載光電 晶片146’且當輔助接腳7〇的第一端力凸出絕緣構造144即 可達成調整光電晶片146高度的目的。 圖Π顯示同樣以ΡΙΝ·ΤΙΑ架構為例，本實施例與前實一 加例的不同在於.光電晶片146具有第一絕緣層;所以輔 助接腳70與光電晶片146_第〜絕緣層133形成斷路此 外光電晶片146與底座142也形成斷路。 本創作的可導電基座130除了是具有摻雜的Ν型基座 外，也可以是具有摻雜的Ρ型基座且結合卩型蟲晶層此時， 圖15a〜15c、16a及17的PIN結構將反置。 又根據上開實施例的教示，底座可以是一金屬盤體結合複 數電極接腳’且-絕緣構造的嵌入件叙入金屬盤體；其中絕緣 的嵌入件形成獨立絕緣部件。 另外底座可以是一金屬盤體，及一絕緣構造的嵌入金屬盤 體且結合複數雜接腳所構成。其中舰緣構造形成為獨立絕 緣部件。 再者底座係一非金屬盤體結合複數電極接腳，且絕緣構造 為非金屬盤體的一部份或全部。 上述各實施例所揭露的電極接腳數量僅為說明之用；實際 23 上的接腳數量為2〜6，亦可視需求增加。 本創作所揭露的各底座，包含T〇_can架構或導線架架 構，具有絕緣構造，且可以搭配光電晶片形成光電元件，其中 光電晶片可以是傳齡構’即—半絕緣基板上具有p_〗_N蠢晶 層，光電晶片亦可以是本案所提出的新晶片創作設計，即前述 實施例所揭露的架構，其中光電晶片構造為—可導電基座阶 基座)上具有Ρ_Ι·>^晶層’且基座的第二側(底面)無相同材質 之半絕緣或不導電基座，再者以相同的金屬層構造做為光電晶 片的Ρ電極與Ν電極且同位於同一側；此外也可以在可導電 基座的第二側(底面)具SOG或SOD或CVD介電材料。而該 晶片可再搭配Low K(BCB或SOG)材料的設計可進一步的再 降低電容值，提高頻寬。 本創作内容所提及的『斷垮』、『絕緣』係指一端以正常的 電壓或電流訊號輸入後，另一端不易取得此訊號之輸出。而本 創作所提及的P-I_N+結構省略在某些實施例中存在的^緩衝 層、未攙雜或低攙雜的InP或inAlAs層，不論是否具緩衝 層或增加其它使元件特性更佳化的磊晶層設計應仍屬本創作 均專的範圍。 另外本創作的絕緣構造的第一面可對應金屬盤體的第一 面成為凸出、齊平或凹低狀構造；同理本創作的絕緣構造的第 二面對應金屬盤體的第二面成為凸出、齊平或凹入狀構造也是 本專利欲均等之範圍。 24 M409531 此外本創作實〜例所提及_緣構造之最佳設計係位在 ’、’、搭配之金屬健的幾何巾^。*金臈上賴設的開孔 ' 可雖在與其搭配之非觸龍_何中心，但不以此為限。 其a本創作的光電晶#細N射導電紐搭配晶層 . 構造的P晶層為例：細亦可等效的置換為P型可導電基板 搭配晶層構造的N晶層的光電晶片，所以p型基板搭配n晶 層的構造亦屬本專利欲均等之範圍。 • X本創作可依實際的產品需求，在可導電基座與該底座之 間配置有一異質基板(載體），藉此調整光電晶片的位置。 以上乃本創作之較佳實施例以及設計圖式，惟較佳實施例 以及设計圖式僅是舉例說明，並非用於限制本創作技藝之權利 範圍’凡以均等之技藝手段、或為下述「申請專利範圍」内容 所涵蓋之權利範圍而實施者，均不脫離本創作之範嘴而為申請 人之權利範圍。 ，【圖式簡單說明】 圖la係習知pin-TIA結構一的示意圖。 圖lb係習知Ριν·τια結構一的另一示意圖。 圖lc係習知ριν·ΤΙΑ結構二的示意圖。 圖Id係習知pin_tia結構二的另一示意圖。 圖2係本創作第一實施例的平面示意圖。 圖3係本創作第一實施例的剖面示意圖。 圖4a係本創作第一實施例的絕緣構造一端凸出且結合蓋體的 25 結構示意圖。 體的 :::作第—實施例的絕緣構造-端凹下且結合蓋 圖5係本創作第二實施綱平面示意圖。 圖6係本創作第二實施例的剖面示意圖。 施例的絕緣構造—端凸出且結合蓋體的 圖％係本創作第二實 結構示意圖。 妹！ Η實酬的絕緣構造—端町且結合蓋體的 結構示意圖。 圖如係本創作第三實施例具辅助接腳的結構示意圖。 圖奶係本創作第三實施例之輔助接腳一端凸出承載光電晶片 且為斷路狀態的結構示意圖。 圖c係本創作第二實施例之輔助接腳一端凸出承載光電晶片 且作為電極狀態的結構示意圖。 圖9a係本!彳作第四實施例的平面示意圖。 圖％係本!彳作第四實施例的剖面示意圖。 圖9c係本創作第五實施例的平面示意圖。 圖9d係本創作第五實施例的剖面示意圖。 圖9e係本創作根據第五實施例於絕緣構造上形成一凸部的剖 面示意圖。 圖9f係本創作根據第五實施例一輔助接腳配置在絕緣構造轴 向且結合一蓋體的結構示意圖。 26 圖10a係本創作第六實施例結合一蓋體的結構示意圖。 圖l〇b係本創作依第六實施例結合蓋體且一辅助接腳組設在 絕緣構造軸向承載光電晶片的結構示意圖。 圖10c係本創作依第六實施例更具有支樓構造結合光學裝置 的結構示意圖。 圖11a係本創作第七實施例的結構示意圖。 圖lib係本創作根據第七實施例的結構使光電晶片位在金屬 薄膜開孔細且配置在非金屬麵表面的結構示意圖。 圖11c係、本創作根據第七實施例的結構使光電晶片位在非金 屬盤體之凸部端部的結構示意圖。 圖12a係本創作根據第七實施例的結構使底座具有延伸牆部 且結合一蓋體的結構示意圖。 圖12b係本創作根據第七實施例的結構使底座具有延伸牆部 結合蓋體，以及具有輔助接腳的結構示意圖。 圖13a係本創作第八實關且結合蓋咖結構示意圖。 圖13b係本創作第九實施例的外觀圖。 圖13c係本創作之底座與各電極接腳的組合形成連續片狀構 造的示意圖。 圖13d係本創作之底座與各電極接腳的組合形成連續片狀構 造的另一示意圖。 圖13e係本創作之各電極接聊以水平方向結合底座的組合示 意圖。 27 圖13f係本_之各電極接腳以水平方向結合底座的組合示意 圖。 圖1¾係本創作之各電極接腳以水平方向結合底座的組合示 意圖。 圖13h係本創作之各電極接腳以水平方向結合底座的組合示 意圖。 圖係本幻作之各電極接腳以水平方向結合底座的組合示意 圖。 一 圖1¾係本解之各電極接聊以水平方向結合底座的組合示意 圖。 圖13k係本創作之各電極接腳以水平方向結合底座的植合示 意圖。 圖14a係本創作之絕緣構造的可實施結構一。 圖14b係本創作之絕緣構造的可實施結構二。 圖14c係本創作之絕緣構造的可實施結構三。 圖14d係本創作之絕緣構造的可實施結構四。 圖14e係本創作之絕緣構造的可實施結構五。 圖15a係本創作之光電晶片結構一。 圖15b係本創作之光電晶片結構二。 圖15c係本創作之光電晶片結構三。 圖15d係本創作之光電晶片結構四。 圖15e係本創作之光電晶片結構五。 28The photovoltaic wafer H6 structure disclosed in the example maintains flexibility in process control. In addition, the second side (bottom surface) of the N-type electrically conductive pedestal (10) has 13% of a semi-insulated or non-conductive pedestal of the same material. In addition, the 'two electrodes 131 and 132 are structures having the same conductive metal, usually Schottky metal, especially a metal structure stacked by Ti/Pt/Au, wherein Τι (having better adhesion to the semiconductor) is usually 10-100 nm, Pt (which is a barrier metal, in some embodiments, may be absent) is typically 5 〇 2 〇〇 nm, and Au (for later bonding or bonding) is usually 1 〇〇. _2 〇〇〇 nm, but if combined with the plating process, the thickness of Au will be several um or more. The above titanium metal may be replaced by chromium (Cr) such that the metal structure of the electrode 131 or 132 becomes Cr/Au or a Cr/Pt/Au structure. The thickness of the above crystal layer is such that the P-type crystal layer is usually about 1 〇〇 nm to 2000 nm, and the I-type crystal layer is usually about 500 nm to 5000 nm. The optoelectronic wafer structure of Figure 15a can be specifically matched to Figures 2, 3, 4a, 4b, 5, 6, 7a, 7b, 8a, 8b, 9c, 9d, 9e, 10a, 10b (for example, when the auxiliary pin is open) Bottom, lib, iic, i2a, 13b, and Ha~He are the bases disclosed. Because these bases use an insulating structure or have auxiliary pins that are not in the same plane as other pins, The low-cost N+ pedestal 130 is created, and the p-electrode 丨 32 and the N-electrode 131 having the same material can be used to place the photo-electric wafer 146 on the pedestal without passing through the carrier, thereby reducing cost and component capacitance, and Improve the characteristics of high frequency response. Referring to Figure 15b, this embodiment differs from the embodiment shown in Figure i5a in that a first insulating layer 133 is located on one side of the conductive substrate 13〇, such as Spin on glass. , SOG). This configuration can be applied to the various bases of Figures 2 to 14e or a conventional pedestal (as shown by la or lc), in which case the use of a heterogeneous substrate (carrier 205) can be dispensed with, but it can be retained as needed. Figure 15c, in addition to showing the pm structure in more detail, adds a low-k layer 134 bit under the P electrode and filled in the area where the p-layer is etched away, or low-medium The electrical constant layer 134 is located between the two electrodes 131, 132 'by which the capacitance value of the element can be lowered. The low dielectric constant layer I% can be replaced by a thick film. The optoelectronic wafer 146 disclosed in Figures 15a to 15c is designed for each of the insulatively constructed bases, and the optoelectronic wafer 146 can be combined with the bases to form a novel and progressive optoelectronic component. The difference between Fig. 15d and Fig. 15c is that the bottom surface of the conductive substrate 130 has a first insulating layer 133. Further, in the crystal layer structure of Figs. 15c to 15j, there is a second insulating layer 137. Continuing the embodiments of FIGS. 15c, 15d, the architecture of the optoelectronic wafer may be the architecture shown in FIGS. 15e-15j; wherein FIGS. 15e, 15f disclose a diffiision type PIN architecture, which may have a low dielectric constant layer 134 or Thick layers; Figures 15g to 15j disclose a mesa type PIN architecture that is configured with a low dielectric constant layer 134 or a thick layer, the dielectric constant or the thickness of the thick layer being designed to reduce the capacitance by more than 20%. . 15h to 15j, it is disclosed that there may be a high energy gap interface layer 138 between the P crystal layer and the I crystal layer. The high energy gap interface layer 138 is an undoped or low impurity InP or InAlAs layer. This is a high-gap material to reduce leakage current, typically between 10 nm and 200 nm. The low dielectric constant layer 134 or thick layer described above may be a SOG coating or a spin on dielectric (SOD) or CVD dielectric material. Figure 15k shows a structure of a photovoltaic wafer 160 that can be used in a photo-diode (PD). Photovoltaic wafer 160 includes a crystal layer structure 161 grown on a pedestal 162. The seed layer structure 161 comprises a P-I-N+ crystal layer, and the pedestal 162 is a semi-insulating pedestal or a non-conductive pedestal such as indium phosphide (InP) or gallium arsenide (GaAs). Next, the two electrodes 163 and 164 (or wire pads) are positioned on the same side of the crystal layer structure 161. Further, the two electrodes 163 and 164 may not be at the same level 'but two electrodes are visible from the top view. The electrode (wire 塾) 163 is electrically connected to the N+ crystal layer, and the other electrode (wire pad) 164 is electrically connected to the p crystal layer. In particular, the electrode 164 is configured to have a side wall configuration, that is, the electrode 164 is via the side of the crystal layer structure 161, one end of which is located above the pedestal 162. The other end is electrically connected to the P by a small portion of the area. The crystal layer can effectively reduce the capacitance between the two electrodes (wire pads) 163 and 164. Further, a second insulating layer 165 may be disposed between the electrode 164 and the crystal layer structure 161 and the susceptor 162. Second, according to the teachings of the foregoing embodiments, the two electrodes 163 and 164 may have the same metal structure. Moreover, referring to FIG. 15L, the crystal layer structure of each photovoltaic wafer disclosed in the present application has an anti-reflection coating 139; generally, the anti-reflection coating Π9 corresponds to an active region located above the wafer or the second polarity (ie, to be accepted) The area of the incident light source signal 139a; the thickness of the anti-reflective coating 139 is about a quarter of the length of the light source wave M409531 to be incident, thereby improving the efficiency of the injection of the light source to be incident. Further, the two electrodes 26a and 26b, 131 and 132 and 163 and 164 mentioned in the previous embodiment are described on the same side, meaning that two electrodes can be seen from the top view. 16a, 16b show an example of a PIN-TIA optoelectronic device architecture in which the pedestal 142 has an insulating structure 144 (see the pedestal structure described above for the structure of the insulating structure). The optoelectronic wafer 146 is disposed in the insulating structure 144 and is The conductive pedestal 130 is positioned on the surface of the insulating construction 144 whereby the optoelectronic wafer 146 is insulated from the pedestal 142. In addition, the two electrodes 131, 132 are electrically connected to the transimpedance amplifier 136 via a wire 135 (see Figure i6b). According to the teachings of the above embodiments, the two electrodes may also be electrically connected to at least a portion of the plurality of electrode pins; the electrical connection referred to above includes the electrodes and the direct electrode-reducing pins, or The wires are indirectly connected to the electrode pins through the electrodes through other active/passive components, transimpedance amplifiers, capacitors, etc., but the direct or indirect forms are the electrical connection between the electrodes and the electrode pins. The conductive base 13A used in the above embodiment is a homogeneous base, which is lower in cost than the conventionally used semi-insulating substrate, and the combined form of the conductive base (10) and the insulating structure 144 can satisfy the photoelectric element 146 and The base 142 forms the requirement that the insulation is free of the need to 'replace the cost and increase the bandwidth. Secondly, the thickness of the conductive base 130 is large, so that when the electrode i3i 22 is formed, it is difficult to generate a surname even if it is laterally connected to the conductive base 130. Therefore, the side control is simple, and the process parameters are elasticized and the yield is high. . Referring again to FIG. 16a', an auxiliary pin (or PIN pin) 7 is disposed in the axial direction of the insulating structure 144; the first end 71 of the auxiliary pin 7A can carry the optoelectronic chip 146' and when assisted The first end of the pin 7〇 protrudes from the insulating structure 144 to achieve the purpose of adjusting the height of the optoelectronic wafer 146. The figure shows that the ΡΙΝ·ΤΙΑ architecture is also taken as an example. The difference between this embodiment and the previous embodiment is that the photo-wafer 146 has a first insulating layer; therefore, the auxiliary pin 70 and the photo-wafer 146_the insulating layer 133 are formed. In addition, the photovoltaic wafer 146 and the base 142 also form an open circuit. The conductive substrate 130 of the present invention may be a doped crucible base and may be combined with a serpentine layer in addition to a doped crucible base. At this time, FIGS. 15a-15c, 16a and 17 The PIN structure will be reversed. Further in accordance with the teachings of the above embodiments, the base may be a metal disk body in combination with a plurality of electrode pins ' and the insulatively constructed insert member is incorporated into the metal disk body; wherein the insulative insert forms a separate insulating member. Alternatively, the base may be a metal disk body and an insulatively embedded metal disk body combined with a plurality of miscellaneous legs. The ship's edge structure is formed as an independent insulating component. Further, the base is a non-metallic disk body combined with a plurality of electrode pins, and the insulation structure is a part or all of the non-metal disk body. The number of electrode pins disclosed in the above embodiments is for illustrative purposes only; the number of pins on the actual 23 is 2 to 6, which may also be increased as needed. Each of the bases disclosed in the present invention includes a T〇_can structure or a lead frame structure, has an insulating structure, and can be used to form a photovoltaic element with an optoelectronic wafer, wherein the photovoltaic wafer can be of the age-setting structure, that is, a semi-insulating substrate having p_ _N stupid layer, the optoelectronic chip can also be the new wafer creation design proposed in the present invention, that is, the structure disclosed in the foregoing embodiment, wherein the optoelectronic wafer is constructed as a conductive base pedestal having Ρ_Ι·> The layer 'and the second side (bottom surface) of the pedestal have no semi-insulating or non-conductive pedestal of the same material, and the same metal layer structure is used as the Ρ electrode of the photovoltaic wafer and the Ν electrode and are located on the same side; The SOG or SOD or CVD dielectric material may be provided on the second side (bottom surface) of the electrically conductive pedestal. The chip can be combined with the design of Low K (BCB or SOG) material to further reduce the capacitance and increase the bandwidth. The term "breaking" and "insulation" as used in this creation refers to the fact that one end is input with a normal voltage or current signal, and the other end is not easy to obtain the output of this signal. The P-I_N+ structure referred to in this creation omits the buffer layer, undoped or low-noise InP or inAlAs layer present in some embodiments, whether or not having a buffer layer or adding other features that optimize component characteristics. The design of the epitaxial layer should still be within the scope of this creation. In addition, the first side of the insulating structure of the present invention may be convex, flush or concave low-profile corresponding to the first surface of the metal disk; the second side of the insulating structure of the present invention corresponds to the second side of the metal disk The formation of a convex, flush or concave configuration is also the scope of the patent to be equal. 24 M409531 In addition, the best design of the _ edge structure mentioned in this example is in the ',', matching metal-strength geometric towel ^. *The opening of the plaque on the plaque is available in the center of the non-contact dragon _, but not limited to it. The photo-crystal crystal of the present invention is a fine N-ray conductive bond with a crystal layer. The structure of the P-crystal layer is as an example: a thin or equivalently replaceable P-type conductive substrate with a crystal layer of an N-layer photovoltaic wafer, Therefore, the configuration of the p-type substrate together with the n-crystalline layer is also within the scope of the patent to be equal. • This creation allows a heterogeneous substrate (carrier) to be placed between the conductive base and the base to adjust the position of the optoelectronic wafer. The above is a preferred embodiment and a design of the present invention, but the preferred embodiments and the design drawings are merely illustrative and are not intended to limit the scope of the present invention. The scope of the rights covered by the contents of the "Scope of Application for Patent Application" is not subject to the scope of this creation and is the scope of the applicant's rights. [Simplified Schematic Description] Figure la is a schematic diagram of a conventional pin-TIA structure 1. Figure lb is another schematic diagram of the structure 1 of the conventional Ριν·τια. Figure lc is a schematic diagram of a conventional ριν·ΤΙΑ structure 2. Figure Id is another schematic diagram of a conventional pin_tia structure 2. Figure 2 is a plan view showing the first embodiment of the present creation. Figure 3 is a schematic cross-sectional view showing the first embodiment of the present creation. Fig. 4a is a schematic view showing the structure of the insulating structure of the first embodiment of the present invention which protrudes at one end and is combined with the cover. Insulation structure of the first embodiment: the end structure is recessed and the cover is attached. FIG. 5 is a schematic plan view of the second embodiment of the present invention. Figure 6 is a schematic cross-sectional view showing a second embodiment of the present invention. The insulating structure of the embodiment - the end of the projection and the combination of the cover body is the second real structural schematic of the present invention. sister!绝缘 的 的 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘FIG. 3 is a schematic structural view of an auxiliary pin according to a third embodiment of the present invention. Fig. 3 is a schematic view showing the structure of the auxiliary pin of the third embodiment of the present invention which protrudes to carry the photovoltaic chip and is in an open state. Figure c is a schematic view showing the structure of the auxiliary pin of the second embodiment of the present invention which protrudes to carry the photovoltaic wafer and is in the state of the electrode. Figure 9a is a plan view of the fourth embodiment. Figure % is a cross-sectional view of the fourth embodiment. Figure 9c is a plan view showing a fifth embodiment of the present creation. Figure 9d is a schematic cross-sectional view of a fifth embodiment of the present invention. Fig. 9e is a schematic cross-sectional view showing the formation of a convex portion in an insulating structure according to the fifth embodiment. Fig. 9f is a schematic view showing the structure in which the auxiliary pin is disposed in the axial direction of the insulating structure and combined with a cover according to the fifth embodiment. Figure 10a is a schematic view showing the structure of a sixth embodiment of the present invention in combination with a cover. Figure 1b is a schematic view showing the structure of the present invention in which the cover body is combined with the cover body and an auxiliary pin group is disposed in the insulating structure to axially carry the photovoltaic wafer. Fig. 10c is a schematic view showing the structure of the present invention having a branch structure combined with an optical device according to the sixth embodiment. Figure 11a is a schematic view showing the structure of the seventh embodiment of the present creation. Fig. lib is a schematic view showing the structure in which the photovoltaic wafer is thinned in the metal film and disposed on the surface of the non-metal surface according to the structure of the seventh embodiment. Fig. 11c is a schematic view showing the structure of the photovoltaic wafer at the end of the convex portion of the non-metallic disk according to the structure of the seventh embodiment. Fig. 12a is a schematic view showing the structure of the seventh embodiment in which the base has an extended wall portion and is coupled to a cover. Fig. 12b is a schematic view showing the structure of the seventh embodiment in which the base has an extension wall portion combined with the cover body and the auxiliary pin. Fig. 13a is a schematic diagram of the eighth embodiment of the present invention combined with the structure of the lid. Figure 13b is an external view of a ninth embodiment of the present creation. Figure 13c is a schematic illustration of the combination of the base of the present invention and the respective electrode pins forming a continuous sheet structure. Figure 13d is another schematic view of the combination of the base of the present invention and the respective electrode pins forming a continuous sheet structure. Fig. 13e is a schematic illustration of the combination of the electrodes of the present invention in a horizontal direction in combination with the base. 27 Figure 13f is a schematic diagram showing the combination of the electrode pins of the present embodiment in the horizontal direction. Figure 126 is a schematic illustration of the combination of the electrode pins of the present invention in a horizontal direction in combination with the base. Figure 13h is a schematic illustration of the combination of the electrode pins of the present invention in a horizontal direction in combination with the base. The figure is a schematic diagram of the combination of the electrode pins of the present invention in a horizontal direction combined with the base. Figure 13⁄4 is a schematic diagram of the combination of the electrodes in the horizontal direction and the base in the horizontal direction. Fig. 13k is a schematic illustration of the integration of the electrode pins of the present invention with the base in a horizontal direction. Figure 14a is an implementable structure 1 of the insulating construction of the present invention. Figure 14b is an implementable structure 2 of the insulating construction of the present invention. Figure 14c is an implementable structure 3 of the inventive insulating construction. Figure 14d is an implementable structure 4 of the inventive insulating construction. Figure 14e is an implementable structure 5 of the inventive insulating construction. Figure 15a is a photovoltaic wafer structure 1 of the present invention. Figure 15b is a photovoltaic structure 2 of the present invention. Figure 15c is a photovoltaic wafer structure III of the present invention. Figure 15d is a photovoltaic wafer structure 4 of the present invention. Figure 15e is a photovoltaic wafer structure 5 of the present invention. 28