TW201044522A - Interconnect structure for a semiconductor device and related method of manufacture - Google Patents
Interconnect structure for a semiconductor device and related method of manufacture Download PDFInfo
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- TW201044522A TW201044522A TW99108290A TW99108290A TW201044522A TW 201044522 A TW201044522 A TW 201044522A TW 99108290 A TW99108290 A TW 99108290A TW 99108290 A TW99108290 A TW 99108290A TW 201044522 A TW201044522 A TW 201044522A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Description
201044522 .. · 1 六、發明說明: 【發明所屬之技術領域】 本發明主題之實施方式大致上係關於適合用於半導體 裝置之互連結構。更具體而言,本發明主題之實施方式係 關於用於半導體裝置互連結構之彈性應力吸收器。 【先前技術】 先前技術包括用於將半導體晶片連接至電路板、其他 裝置、基板等多種技術及互連結構。例如,經常使用焊珠 〇 (solder bead)將倒裝晶片(fHp chip)連接至外部電路。 該等焊珠通常設置於倒裝晶片之導電凹槽或端點且經回焊 以形成用於連接至外部裝置(如電路板)之珠粒。該等焊珠 通常由錯或錯合金形成最近,以銀取代錯以減少廢棄晶 片對環境所產生的任何影響。 肖於形成焊料連接之另—製程為生餘狀互連件且在 該柱狀互連件頂面形成焊珠。該柱狀互連件通常設置於半 〇導體裝置之接觸墊上且向上延伸。可製作具有非常小節距 之柱狀互連件的陣列以適應高密度應用。之後,該陣列之 焊珠可使用回焊技術與外部電路麵接。 當使用柱狀互連件時,外部電路所施加的任何力會傳 互連件。該柱狀互連件轉而將該力傳導至於該 柱牛與該裝置之間之麵接處 設^晶片之焊珠(使用傳統技術)相比,柱狀互如牛^ 更二基底,從而使施加於該半導體裝置上的應力更大。 所以成之應變可能會以各種非所欲之方式顯現出來,如某 94855 3 201044522 些材料之裂化或剝離。 【發明内容】 本發明提供具有裝置基板之半導體裝置。該半導體裝 置包括形成為疊置於該裝置基板上之導電墊;形成為疊置 於該導電墊上且密封一空腔之導電平臺,其中,該導電平 臺具有從該導電墊延伸離開之邊緣部分及在該邊緣部分上 面之頂蓋部分;以及設置於該空腔中之緩衝材料。 本發明亦提供具有裝置基板之半導體裝置結構。該半 導體裝置結構包括形成為疊置於該裝置基板上之導電接觸 墊、設置於該接觸墊上並經調適成回應於力而彈性變形之 彈性塊、實質上圍繞該彈性塊且與該彈性塊耦接以及與該 接觸墊電耦接之導電平臺、設置於該平臺上面而與該平臺 電耦接且延伸至一末端之導電柱狀互連件、以及形成於該 末端上之焊珠。 本發明亦提供形成用於裝置基板之接觸平臺之方法。 該方法包括提供具有導電接觸元件、在該導電接觸元件上 面之鈍化層、以及延伸穿過該純化層且終止於該導電接觸 元件之凹槽之半導體裝置結構;以彈性材料至少部分地填 充該凹槽以獲得經填充之凹槽;從該經填充之凹槽選擇性 地去除一部分彈性材料以形成位於該凹槽中之彈性墊,該 彈性墊疊置於該導電接觸元件上且與該鈍化層分隔開;以 及於該凹槽中形成導電平臺以使該導電平臺至少部分圍繞 該彈性墊。 此發明内容係用於簡要說明概念之選集,該等概念將 94S55 201044522 , 4於下文中進-步詳細說明。此發明内容非意欲指出所 、之發明主題的賴徵或基本特徵,亦非意制作^ 主張之發明主題的範園之輔助。 ^ 【實施方式】 以下詳細說明僅於本f上說明而非意欲限制該 之實施方式或該等實施方式之應用及使用。本文中所 術語“例示性,’意指“用作實例、例子或例證,,。作 示性之任意實施不必然被解讀為更優於或更有利於其他實 施之實施。再者,本文非意欲限於任何揭示於上文之 領域、先前技術、發明内容或下文之實施方式之= 示理論。 4暗 供、” ^ , 丨'丁'仴义什取郎點或 徵被祕I一起。除非明白地另行說明, 、接,,意指-個元件/節點/特徵直接或間接地連: (或直接或間接連通於)另—個元件/節點/特徵,.且= 0與直接機械連接相連接。應理軸接的元件/節點^ 相施加影響。因此,雖然第1圖圖解揭示了元件的= =性方案(scheme),但是所揭示主題之實施 ^ 其他的元件、裝置、特徵或組件。 、TJ不 “調整(adjust)’’ 〜__宜-▲ 描述為可調整的或已調整的。、除:白::二或特徵 所敘述之“調整,,意指定位、改進 ^仃說明’為 件或元件或組件之一部分以適應環境及實1^疋件邊 情況下,若對於實施方式所處環境為合適或有i要於貝 3 94855 5 201044522 正後7G件或組件或元件^件之—部分. 或狀況可维持不變化 。於某些情況下W、狀態及/ =件她仏改一新:置= 或最二描述減小效應 移動或狀況時,該組件或特 果'性一或效應之降=反藉:可= 定二 此非意欲限制本發明。例如,“上部,,、“下部,,号“上 ^方等術每係指附圖甲之方向,而附圖中之參 ::,係致但為隨意者。該等術語可包括上述特別提到 該等。司5吾之衍生物以及相似舶來詞。類似地,除 文中另行說明’涉及結構之術語“第一,,、“第二,,及 其他該隸钱非麵切或順序。 為了間潔起見,關如^ ,兹 兄關於+導體裝置製造之傳統技術可能 於此詳細說明。再者’本文所述之多種工作及製程步驟 併入於具有本文未詳細彳㈣之其他步驟或功能之更複雜 P步驟或1程特別地,製造半導體系電晶體之多個步驟 廣泛a ’ m此’為了簡潔起見,多個傳統步驟僅簡單 明或將全部省略而不提供習知製程細節。 6 94855 201044522 * 本文所揭示之技術及工藝可用以製造用於任何數量 - 的半導體系裝置(如電晶體裝置、二極體、開關、傳輸線等) 之互連件。另外,發明主題係關於控制塌陷晶片連接 (controlled collapse chip connection),其經常使用於 倒裝晶片,且包括於下述之半導體裝置結構之說明中。 對於使用柱狀互連件技術之半導體裝置而言,與緩衝 墊或彈性墊類似之彈性應力吸收器可位於該柱狀互連件下 方以減少傳送至該半導體裝置之環繞區域之應力。該彈性 D應力吸收器較宜包括至少一個導電部分,藉此實現該半導 體裝置與該柱狀互連件之間的電連接。於較佳實施方式中, 彈性部分係併入至互連結構;該彈性部分在遭受應力時可 發生彈性形變。因此,該柱狀互連件所接收之力及應力在 傳送至該半導體裝置之前會被吸收。 第1圖係具有複數個互連結構60之半導體裳置5〇之 透視圖。互連結構飞0可用於將半導體裝置5〇與其他組件 〇或外部電路麵接。互連結構60可提供耦接點’該耦接點不 僅機械地將組件耦接在一起,亦提供導電通道,透過該導 電通道,半導體裝置50之特徵可藉由如外部電路板操作。 其他裝置亦可與半導體裝置50耦接。 雖然基於例示之目的顯示一定數量的互連結構,惟 不同實施例的確切數量可不同。另外,熟知本領域之技術 人員將認識到額外的互連結構60可存在於半導體裝置5〇 之多種實施例中。再者,當對實施例適合時,不同集中度、 排列、群組及形狀可用於互連結構6〇。 94855 7 201044522 第2圖係一個互連結構loo之詳細示意圖。互連結構 100除了別的元件還包括導電柱狀互連件18〇及在柱狀互 連件180頂面之焊珠190。柱狀互連件18〇較佳於導電平 臺160與互連結構1〇〇耦接。其他層、特徵及/或組件可形 成在柱狀互連件180及/或焊珠190周圍,但為了簡潔而予 以省略。另外,如上所述,其他互連結構可存在於單個半 導體裝置上。 第3圖係沿著第2圖之線3-3所取得的互連結構1〇〇 之橫截面示意圖。互連結構1〇〇較佳包括,但不限於:裂 置基板102'導電接觸元件或接觸墊11〇、第一層絕緣材料 (如氮化物層)120、第二層絕緣材料(如氧化物層)13〇、彈 性塊140、黏合層150、導電平臺160、柱狀互連件180及 焊珠190。導電平臺160可包括邊緣部分162及頂蓋部分 170 〇 本文所述之裝置基板102表示半導體裝置50之一部 分’該半導體裝置50包括功能裝置特徵、導電線路、互連 栓、電路元件等。換言之,裝置基板102包括任意操作特 徵及元件,以及相關之電連接及導電線路。例如,裝置基 板102可包括不同材料的任何數量的層,如半導體材料 層、介電質材料層、導電金屬層等。該等不同材料層可用 以形成主動裝置(如電晶體)、電接觸、夾層連接及其他通 常會發現於半導體裝置之特徵。為了說明之簡要,不於圖 中繪示裝置基板102之詳細特徵(每個裝置的特徵互相不 同)。 8 94855 201044522 用廣乏羽Π°2可包括半導體材料,該半導體材料可使 …之=及製程步驟(如關於摻雜、光微影法及圖 .案化_、㈣生長、材料沉積 及步驟)處理,此處將不詳細 t-化專之技術 ^ 1月裝置基板102可使用絕 緣體覆矽上(SOI)基板來實現,其一 :體=士,該絕緣體材料轉而由載體晶片(未顯示)支 ’裝置基板102可使用塊财基板代 ο 替SOI基板來貫現。 雖然可使用任意適當的半導體材料,但是本實施例 中,裝置基板102中之半導體材料係包括石夕材料,其中, 本文所述之術語“石夕材料,,包括普通單晶石夕及通常用於半 導體工業之相對純的梦材料,以及與其他元素(如鍺、碳等) 混合之石夕。另外,裝置基板1G2可包括鍺、_化嫁等。 導電墊110可形成為覆蓋於襄置基板102上。實際上, 導電墊110相當於互連結構⑽的-個電節點、端口 (p〇rt) ❹或連接點,且導電整110表示用於互連結構1〇〇之電界面。 例如,導電墊110可為形成於裝置基板1〇2上之電晶體裝 置之源極、閘極或汲極所用之接觸區域。導電墊110可使 用任意所欲之技術及/或製程形成。較佳地,導電墊110 包括導電金屬材料,如純銅或銅合金。然而’可視實施例 之需要而使用其他導電材料,如紹及無合金、銀及銀合金 等。雖然導電墊110係顯示為沿著裝置基板1〇2延伸一定 長度,但導電墊110之確切尺寸可視實施例之不同而改 變。再者,可將多於一個之柱狀互連件180與單個導電墊 9 94855 201044522 110輕接。 氮化物層120及氧化物層130位於導電墊110上方且 圍繞邊緣部分162。氮化物層120可由任意適當的氮化物 化合物(包括石夕氮化物)形成。如下文更詳細之說明,氮化 物層120定義至少凹槽(如含有導電平臺160之凹槽132) 之一部分。氮化物層120可沿著導電墊11〇以所欲之程度 延伸,以與互連結構丨00之其他特徵適當地作用。氮化物 層120可具有約4000至5000埃(Angstrom)之厚度。於某 些實施例中,氮化物層12〇視需要可更薄或更厚。 氧化物層130至少部分覆蓋於氮化物層12〇上,且其 形狀與氮化物層12〇之形狀一致。因此,氧化物層13〇較 佳為與氮化物層120類似地定義相同凹槽132之至少一部 刀氧化物層130可由任意適當的材料形成,如氧化矽或 低k材料。氧化物層130可具有約4000至5000埃之厚度, 准於某些實施例中,氧化物層丨3〇視需要可更薄或更厚。 、氮化物層120及氧化物層130可作為電絕緣體。另外, 雖然揭示了兩個鈍化層’但更多或更少的純化層可存在於 不同實施例中選擇用;^該實施例之互連結構⑽中。因此, 某些實施方式可具有單個鈍化層,而其他實施方式可具有 兩個或更多個鈍化層。 彈性部分或彈性塊14〇可形成為覆蓋導電墊11(^如 圖所示,彈性塊140位於導電平臺16〇下方之空腔中。於 =些實施例中,彈性塊140直接形成於導電塾110上且與 導電墊110相鄰接。較佳地,彈性塊14〇由具有線形彈性 94855 10 201044522 應力/應變機械特性之材料構成。因此,可適當地設計或組 ^ 構彈性塊以使其在非負載狀態下保持不變形之形狀 ‘(如矩形塊)。然而,當力施加於彈性塊140時,彈性塊14〇 可回應於該力而發生彈性變形,當去除力時,彈性塊14〇 恢復至其未變形之形狀。因此,彈性塊14〇就像彈簧或緩 衝墊,可透過彈性形變吸收應力。因此,彈性塊14〇可稱 為緩衝塊、緩衝材料、應力吸收組件等等。 因此,彈性塊I40較佳由顯現該等機械特性以及易於 成形之材料形成。該等類型的材料之其中一種為聚醯亞胺, 較佳為易於製造之光敏聚醯亞胺。再者,彈性塊140可視 需要實現為具有由不同材料形成的複數個不同層、部分或 區域之複合結構。彈性塊140係繪示為直方角柱,惟不需 為特定尺度或比例。因此,可視需要使用其他尺寸及尺度。 較佳地,彈性塊140具有實質上四邊形之形狀。 彈性塊140可具有厚度(即高度,從導電墊11〇上方 〇測量之延伸度)。較佳地’彈性塊14〇之最大高度比氮化物 層120與氧化物層130之總厚度小一適當的間隙,以讓具 有所欲厚度之頂蓋部分17〇可形成。因此,祕塊14〇較 佳具有小於圍繞之氮化物層12〇與氧化物層13〇之總高度 之高度。於某些實施例t,彈性塊140具有約6〇〇 二 埃之範圍内的厚度。另外,彈性塊14〇較佳與氮
及氧化物層⑽隔開。於某些實施例中,此間隔可為 至800奈米之範圍内。 勹^4UU 黏合層150可有助於將導電平臺16〇黏合至彈性塊 94855 11 201044522 140及導電墊110,如下文更詳細之說明。因此,黏合層 150位於導電平臺160與彈性塊14〇之間以及導電平臺16〇 與導電塾110之間。如第3圖所示,黏合層15〇較佳為形 成於氮化物層120及氧化物層13〇之凹槽中,且覆蓋彈性 塊140以及位於導電平臺16〇之邊緣部分162下方之導電 墊110部分。因此,彈性塊14〇之上表面及侧表面可由黏 合層150覆蓋。 黏合層I50可包括鉻或鉻合金,或其他促進彈性塊14〇 與用^導f墊110之材料之間之黏合並能允許導電於其間 之材料(如銅及/或鋼合金)。黏合層15〇可藉由濺鍍製程形 成,以讥積於互連結構1〇〇上。黏合層15〇可具有實質上 均勻之厚度’如20至40埃之間,但是該厚度在不同的實 施例中可不同。 電平臺160較佳為形成於導電墊no及彈性塊“ο 上方。導電平臺160包括邊緣部分162及頂蓋部分170。 邊緣部分162較佳為圍繞彈性塊14〇之彈性塊14〇之整個 高度。項蓋部分no較佳為覆蓋邊緣部分162及彈性塊 140 ’並费封彈性塊14〇所在之空腔。如第3圖所示,凹槽 132相當於由頂蓋部分17〇、邊緣部分162及導電墊 所定義之空間。於某些實施例中,邊緣部分162可延伸至 導電平臺160之最大高度,而頂蓋部分17〇僅為直接在彈 性塊140頂面之部分。因此,在不同的實施例中,導電平 臺160之各部分不同,但仍具有相同功能以及實質上相同 的特徵。導電墊110透過該黏合層與導電平臺丨6〇電耦接。 94855 12 201044522 邊緣部力162較佳為形成於彈性塊HO及氮化物層 _ 120及氧化物層130之間之空間中。如圖所示,邊緣部分 ‘ 162可形成於黏口層150之頂面。於將黏合層150自導電 塾11〇之表面去除之其他實施例中,邊緣部& 162可直接 形成於導電塾、U〇之表面上。黏合層⑽仍可形成彈性塊 140之側壁與邊緣#分162之間之表面。邊緣部分脱較 宜向上延伸以與頂蓋部分Π0輕接。 了頁蓋部分no可形成於彈性塊14〇之頂面上,且如上 所述’於某些實施例中,頂蓋部分17〇亦形成於邊緣部分 62之頂面上頂蓋科170較佳為被調適成覆蓋彈性塊 140之實質上平坦之崎,且與導電墊⑽實質上平行地 延伸。頂蓋部分170之厚度在不同實施例中可不同。邊緣 部分162與頂蓋部分no之於導電塾11〇上方之組合高度 較佳為實質上等於氮化物層12Q及氧化物層1別之高度。 因此,彈性塊140、黏合層150及導電平臺16〇之組合較 〇佳為填滿顯示於氮化物層12〇及氧化物層13〇中之四槽。 頂蓋部分170具有外邊緣及内邊緣。該外邊緣或外邊 界為頂蓋部分170之最大延伸限度。頂蓋部分17()横跨彈 性塊140而由邊緣部分162支撐。因此,該内邊緣為由彈 性塊1=之外邊緣所界定之邊界,且在該内邊界或内邊緣 内,頂蓋部分170係透過黏合層150由彈性塊140支浐 邊緣=卩分162及頂盍部分170較佳由高導電金屬材 構成,如銅、鋁、銀、金或其合金。邊緣部分162及頂蓋 部分170可整體形成一個連續的或整體的元件,或可形成 94855 13 201044522 兩個連接或耦接在一起的不同元件。 柱狀互連件180可形成於導電平臺16〇之頂面上。如 圖所示,柱狀互連件180較佳具有實質上圓柱形之形狀。 柱狀互連件180可直接形成於頂蓋部分17〇上、或在柱狀 互連件180與頂蓋部分17〇之間形成一個或多個另外的導 電層。較佳地,柱狀互連件180由高導電金屬材料形成, 如銅、鋁或其合金。實際上,柱狀互連件18〇、導電平臺 160及導電墊11〇皆可由相同材料形成。 另外參照第4圖,可以看到柱狀互連件1別及頂蓋部 分170之頂視圖,其中頂蓋部分17〇之内邊緣172以虛線 標出。可以看出,柱狀互連件18〇在其基底具有外徑、外 邊緣184或外邊界,其中該基底與導電平臺16〇耦接。柱 狀互連件180之外邊緣184可當成柱狀互連件18〇與頂蓋 部为170之間之接觸面積之底面積(f〇〇tprint)。較佳地, 柱狀互連件180之外邊緣184係被定義或界定為全部位於 頂蓋部分170之内邊緣172内。因此,柱狀互連件18〇較 佳為在全部於彈性塊丨4〇上之區域與頂蓋部分17〇耦接。 因此’於較佳f施例中,柱狀互連件18〇之接觸表面沒有 任σ卩刀叹置成覆蓋於邊緣部分162上。其他實施例可具 有其他組構。 柱狀互連件180可由其他材料圍繞,如其他純化或導 電層及/或墊(視所實施的裝置或電路之需要)。柱狀互連件 m可在其相對於㈣墊11Q之頂部具有束端182。視所使 用的連接技術之需要,末端182可為光滑者或具有紋理。 94855 14 201044522 诨珠190可形成於末端182上或柱狀互連件⑽ .焊珠190可由錯、銀、錫或任意其他所欲之材料構成:。 . 來自互連結構1〇〇與外部電路之間之連接之應力、。 來自熱膨脹差之應力可於焊珠190處被接收且傳送通f 狀互連件180。傳送通過柱狀互連件⑽之應力 = 施加於導電平臺⑽上或由導電平臺16〇所接收或經歷。 因為導電平臺160與彈性塊14〇_,扭力及壓縮 應力可傳送至彈性塊140。彈性塊14〇可回應於所接 應力而發生彈性變形,藉此吸收所接收之應力且抑制 互連結構1GG之傳送。因此’可其他特徵與接收自 件以及熱膨脹之應力隔離以保護該等特徵。 f 5圖至第15圖係顯示用於半導體裝置之例示 連結構之形成之橫截面示意圖。上述互連結構⑽可 下述製程製造。應理解不同實施例之形成可包括任意數玲 的其他或替代步驟,此處將不再贅述該等步驟。另^卜蕙 〇於標4 5®至第15圖之某些特徵之數字與上述特徵之1 字相同,惟在適當時增加300錢目。如下所述,亦可f 有其他的特徵及/或變形。 ' 第5圖為處於在前端處理之後及形成互連結構之 狀態之半導體裝置。第5圖為顯示形成裝置基板4〇2 電墊410、氮化物層420及氧化物層43〇之後之整體製、生 製程之中間狀態°裝置基板402可包括不同材料之任= 量的層(如半導體層、電介質層、導電金屬層等)及併入: 徵(如主動裝置(如電晶體)、電接觸、失層連接以及其他通 94855 15 201044522 常用於半導體裝置之特徵)。另外’雖然揭示了具體的化合 物’如氧化物、氮化物,但亦可使用其他材料,如低k及 超低k電介質材料。氮化物420及氧化物430層可用作某 些製程之終止指示器或終止層(如下所述)。 當獲得第5圖所示之結構之後,可選擇性地去除材料 以形成凹槽432,如第6圖所示。使用廣泛習知之製程技 術選擇性地自氮化物420及氧化物430層去除材料。例如, 適當的圖案化蝕刻遮罩可形成於430之上表面上,且該银 刻遮罩可用於選擇性地姓刻氧化物層430及氮化物層420 以定義凹槽432。較佳地,材料之去除係向下延伸至導電 墊410。實際上,裝置基板402可能需要複數個(如數十個、 數百個、數千個或更多個)互連結構。因此,雖然第6圖僅 顯示用於一互連結構之一個凹槽432,但是為了對應複數 個互連結構’實際中的實施例可於氮化物層420及氧化物 層430 #刻凹槽陣列。因此,此處及下文所述之用於製造 彈性塊及導電平臺之製程步驟可用於製造任意數量的半導 體裝置結構。 形成凹槽432之後,能以彈性材料5〇〇至少部分地填 充凹槽432(如第7圖所示)。如上所述,彈性材料5〇〇可 為光敏聚醢亞胺,其適合對應後續製程步驟。 於某些實施例中’彈性材料500藉由適當的沉積技術 形成’如塗覆技術(如旋塗)。較佳地’保形地沉積彈性材 料500以使其完全填滿凹槽432。因此,在沉積步騾過程 申,可將一些量之彈性材料500沉積於氧化物43〇層上方。 94855 16 201044522 # 第7圖說明了此過量的材料5〇1(稱為“過量層,,)如何覆 j 蓋於氧化物層I30上。至少部分填充凹槽432之彈性材料 500的沉積係導致經填充之凹槽532。 該實施例繼續進行一個或多個光微影步驟。關於這 點,第8圖揭示了光微影曝光步驟,在該梦驟中彈性材料 500(其為光敏材料)曝露至具有預定圖案之輻射(如光)。例 如在其上定義有適當的光遮罩之圖案化玻璃層510的選擇 ❹=曝光裴置可設置在彈性材料5〇〇上。如圖所示,電磁波
曰*之適§的部分之光512(不必為可見来)巧·通過圖案化玻 墙層训指向互連結構。 W '經碉整之光514將會依照設置於圖案化玻璃層51〇上 案之设計而穿過圖案化玻璃層510。經調整之光514 ^特擇11通過或視需要過滤特定波長而具有改變自光512 性材眾所周知,經調整之光514可調整被曝光之敏彈 性去^之特性。例不性實施例使用兩俩光微影步驟以選擇 肆中=性材料500之一部分。如第8圖所示,在第一步 532之^整之光514被傳送至彈性材料500於填充凹槽 適當的如第9圖所示’被曝光的彈性材料500再以9 532之彈^"劑化學作用顯影,以除去一些位於填充凹槽 因初始注意第9圖所%示之凹槽632表示 步驟而去除之彈性材料的部分。 *第受第二曝光及顯影步称。 獲得經調敕夕丄弟—圖案化玻璃層560之第二曝光可 ι之光562,而經調整之光562係沿著填充四槽 94855 17 201044522 532之邊緣被提供至彈性材料_。在以經調整 使彈性材料500曝光之後,將兮暖本 & 一 ,兀•心傻將該曝先之材料顯影以形成第 10圖所示之彈性塊540。 應理解雖肋例示性實施例缘示了在沿著凹槽7扣之 邊緣去除彈性材料_之前絲於凹槽咖之彈性材料 500之寬層’但是可以相反順序實施操作以實現第1〇圖所 不之相同結果。另外’雖崎示及說明了雙曝光光微影製 程,但亦可使用以循序漸進之選擇性照射及/或控制之濃度 以選擇性去除彈性材料剛之單個光微影製程。再者,在 某些實施财,雙曝絲微程可包括在兩個照射步驟 之後之僅單個之顯影步驟。用於選擇性去除彈性材料讥〇 之確切技術在不同實施例中可不同,但較佳為導致形成與 氮化物120及氧化物130層隔開之彈性塊44〇(如第1〇圖 所示)。 在形成彈性塊之後’該實施例之方法接著附加黏合層 450(如第11圖所示)。黏合層45〇可使用任意所欲之技術 沉積’包括CVD或PVD(包括濺鍍法)。較佳地,黏合層45〇 圍繞彈性塊440。如上所述,黏合層450亦可形成於於凹 槽732中之導電墊41〇之頂面上。亦可產生黏合層材料之 一些過量層451。沿著導電墊410形成之黏合層450之部 分可選擇性地被去除。 如第12圖所示,在形成黏合層450之後,導電材料 530可形成於彈性塊440上方。導電材料530通常為金屬 材料。於較佳實施例中’導電材料530包括銅或其合金。 18 94855 201044522 或者道導電材料53G可包括,但不限純或其合金。 PVD#】材料530可藉由適當的沉積技術形成,如⑽或 4 。較佳地,保形地沉積彈性材料50〇以使1完全 $滿凹槽632、732,而同時圍繞彈性塊44〇及在祕塊糊 材料530之某些過量層531可形成於彈性材料5〇〇 之過量層5〇1及黏合層45〇之過量層451上。黏合層棚 較佳促進及有助於彈性塊彻與導電材料53()之間之輕接。 Ο 〇 在几積導電材料53〇之後,可將多餘材料自互連結構 ;〇〇、去除(如第13圖所示)。更具體地,彈性材料之過量層 邰刀501、黏合層之過量層451及導電材料之過量層mi 可藉由研磨過量層5G1、531從氧化層上去除。關於這 點,可使用氧化層430作為終止層、終止標記、終端層或 端點指標而藉由化學機械研磨/平坦化(CMP)去除覆蓋層部 分。在CMP製程之後,剩餘導電材料53〇包括邊緣部分4犯 及頂蓋部分470 ’:其共同形成導電平臺460。導電平臺460 具有上表面472。較佳地,導電平臺460之高度與周圍之 氮化物420及氧化物430層之高度匹配。 如第14圖所示,在去除製程之後,可在導電平臺46〇 上形成導電柱狀互連件480。柱狀互連件480較佳設置於 了貝蓋部分470之上表面472上。柱狀互連件480可用任何 適合之方式形成,包含已知之沉積技術及選擇性移除技術。 柱狀互連件480可根據傳統裝置製造及半導體封裝技術製 造’此處將不再詳細說明該等傳統技術。較佳地,柱狀互 連件480與導電平臺460輕接。另外’如圖所示,柱狀互 94855 19 201044522 連件48G較宜疊置於彈性塊⑽i,且未延伸成疊置於邊 緣部分462上。 如第15圖所示,在生成柱狀互連件之後’焊珠49〇 可形成於柱狀互連件480上。焊珠490可使用任意所欲之 技術形成’以將其定位於柱狀互連件480之末端482上。 焊珠490可以多種技術(包括回焊製程)成形,以有助於其 與外部組件及/或電路之連接性。 雖然前面已詳細說明至少一個例示性實施例,但應了 解存在大量的變形例。亦應了解此處所述之例示性實施例 非意欲以任何方式限制所主張的發明主題之範圍、應用或 組構。相反,前述詳細說明將為熟知本領域之技術人員提 供方便的用於實施說明之實施例之路線圖。應理解在不背 離申請專利範圍所定義之範圍之條件下可進行元件之功能 及設置之多種改變,該等改變包括在申請該專利時所習知 的等同物及可預見的等同物。 【圖式簡單說明】 可藉由參照詳細說明及申請專利範圍並結合下列附圖 更完整的理解本發明主題,其中’相似的參考數字在整個 附圖中係指相似的元件。 第1圖係具有應力吸收互連結構之群組之半導體裝置 之只施方式之透視圖; 第2圖係具有彈性應力吸收器之互連結構之透視圖; 第3圖係第2圖之互連結構之橫截面示意圖; 第4圖係第2圖之互連結構之頂視圖; 20 94855 201044522 1 第5圖至第14圖係顯示包括彈性應力吸收器之例示 性互連結構之形成的橫截面示意圖;以及 第15圖係在形成該彈性應力吸收器後之該互連結構 之橫截面示意圖。 【主要元件符號說明】 50 半導體裝置 60、100、400 互連結構 ❹ 102 、 402 裝置基板 110 接觸墊 120 、 420 氮化物層 130、 430 氧化物層 132 ' 432 、532 、 632 、 732 凹槽 140 、 440 彈性塊 150、 450 黏合層 160 、 460 導電平臺 162、 462 邊緣部分 170 、 470 頂蓋部分 172 内邊緣 180 、 480 導電柱狀互連件 182 、 482 末端 184 外邊緣 190 、 490 焊珠 410 導電墊 451 過量層 472 上表面 500 彈性材料 501 ' 531 過量層 510 圖案化玻璃層 512 光 514 、 562 經調整之光 530 導電材料 560 第二圖案化玻璃層 21 94855
Claims (1)
- 201044522 七、申請專利範圍: 1. 一種半導體裝置⑽,其包括裝置基板⑽)及互連結 構(60),該互連結構(6〇)包括: 形成為疊置於該裝置基板(102)上之導電墊⑽); 形成為疊置於該導電墊(110)上且密封-空腔之導 電平臺(160),其中,該導電平臺〇6〇)具有從該導電墊 ⑴0)延伸離開之邊緣部分⑽)及在該邊緣部分⑽) 之上面之頂蓋部分(170);以及 »又置於該空腔中之緩衝材料(14〇)。 2, 如申請專利範圍第1項之半導體裝置⑽,其進-步& 括設置於該導電塾⑴0)與該邊緣部分(162)之間、以及 該缓衝材料⑽)與該頂蓋部分⑽)之間之黏合層 (150)。 3, ^申請專利範圍第2項之半導體裝置(5〇),其中,該黏 合層(150)進一步設置於該緩衝材料⑽)與該邊緣部 分(162)之間。 4. 如申請專利範圍第!項之半導體裝置⑽,其進一步包 ❹ 括形成為至少部分叠置於該導電平臺(16〇)上且與該導 電平臺(16G)f H接之導電她互連件(18〇)。 5. 如申清專利範圍第4項之半導體裳置(⑹,其中,該導 電柱狀互連件(18〇)具有橫截面邊緣(丨84),該橫截面邊 緣(184)全部疊置於該缓衝材料(14〇)上。 94855 22
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US8895358B2 (en) * | 2009-09-11 | 2014-11-25 | Stats Chippac, Ltd. | Semiconductor device and method of forming cavity in PCB containing encapsulant or dummy die having CTE similar to CTE of large array WLCSP |
US9013037B2 (en) * | 2011-09-14 | 2015-04-21 | Stmicroelectronics Pte Ltd. | Semiconductor package with improved pillar bump process and structure |
US8916481B2 (en) | 2011-11-02 | 2014-12-23 | Stmicroelectronics Pte Ltd. | Embedded wafer level package for 3D and package-on-package applications, and method of manufacture |
US8779601B2 (en) | 2011-11-02 | 2014-07-15 | Stmicroelectronics Pte Ltd | Embedded wafer level package for 3D and package-on-package applications, and method of manufacture |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4400865A (en) * | 1980-07-08 | 1983-08-30 | International Business Machines Corporation | Self-aligned metal process for integrated circuit metallization |
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US5334804A (en) * | 1992-11-17 | 1994-08-02 | Fujitsu Limited | Wire interconnect structures for connecting an integrated circuit to a substrate |
US5615824A (en) * | 1994-06-07 | 1997-04-01 | Tessera, Inc. | Soldering with resilient contacts |
US6727579B1 (en) * | 1994-11-16 | 2004-04-27 | Formfactor, Inc. | Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures |
JPH1012621A (ja) | 1996-06-26 | 1998-01-16 | Casio Comput Co Ltd | 突起電極の構造及びその形成方法 |
EP1271640A3 (en) | 1996-07-12 | 2003-07-16 | Fujitsu Limited | Mold for manufacturing semiconductor device |
US6222280B1 (en) * | 1999-03-22 | 2001-04-24 | Micron Technology, Inc. | Test interconnect for semiconductor components having bumped and planar contacts |
JP2000299338A (ja) | 1999-04-14 | 2000-10-24 | Sony Corp | 突起電極を有するベアチップic及び突起電極の形成方法 |
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US7298030B2 (en) * | 2003-09-26 | 2007-11-20 | Tessera, Inc. | Structure and method of making sealed capped chips |
US7294929B2 (en) * | 2003-12-30 | 2007-11-13 | Texas Instruments Incorporated | Solder ball pad structure |
US20080108221A1 (en) * | 2003-12-31 | 2008-05-08 | Microfabrica Inc. | Microprobe Tips and Methods for Making |
US7187078B2 (en) * | 2004-09-13 | 2007-03-06 | Taiwan Semiconductor Manufacturing Co. Ltd. | Bump structure |
JP2006278417A (ja) | 2005-03-28 | 2006-10-12 | Fujikura Ltd | 半導体装置及び半導体装置の製造方法 |
TWI320588B (en) * | 2006-12-27 | 2010-02-11 | Siliconware Precision Industries Co Ltd | Semiconductor device having conductive bumps and fabrication methodthereof |
TW200836275A (en) * | 2007-02-16 | 2008-09-01 | Chipmos Technologies Inc | Packaging conductive structure and method for manufacturing the same |
US7994638B2 (en) * | 2007-05-11 | 2011-08-09 | Panasonic Corporation | Semiconductor chip and semiconductor device |
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US20100244267A1 (en) | 2010-09-30 |
US8513109B2 (en) | 2013-08-20 |
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US20110171822A1 (en) | 2011-07-14 |
SG184726A1 (en) | 2012-10-30 |
WO2010111081A1 (en) | 2010-09-30 |
CN102365735B (zh) | 2014-03-19 |
TWI520282B (zh) | 2016-02-01 |
US7932613B2 (en) | 2011-04-26 |
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