TW201037777A - Bonding wire - Google Patents

Bonding wire Download PDF

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Publication number
TW201037777A
TW201037777A TW099102279A TW99102279A TW201037777A TW 201037777 A TW201037777 A TW 201037777A TW 099102279 A TW099102279 A TW 099102279A TW 99102279 A TW99102279 A TW 99102279A TW 201037777 A TW201037777 A TW 201037777A
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TW
Taiwan
Prior art keywords
coating layer
wire
copper
bonding wire
bonding
Prior art date
Application number
TW099102279A
Other languages
Chinese (zh)
Inventor
Tsuyoshi Hasegawa
Original Assignee
Tatsuta System Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tatsuta System Electronics Co Ltd filed Critical Tatsuta System Electronics Co Ltd
Publication of TW201037777A publication Critical patent/TW201037777A/en

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    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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  • Wire Bonding (AREA)

Abstract

The purpose of the present invention is to so improve the bonding strength as to be suitable for the increased speed of working even at a low working stage temperature of about 150 DEG C. Bonding wire (P) for connecting an electrode (a) of an integrated circuit element and conductor wiring (c) of a circuit wiring board by means of a ball bonding method. Temper heat treatment is performed to obtain bonding wire having a thickness 0.04 to 0.09[mu]m of a coating layer (2) in such a manner that the coating layer (2) consisting of one or more kinds of gold, platinum, palladium, and silver is formed on the entire outer peripheral surface of a core (1) consisting of copper of not less than 99.99% by mass, that after the adhesion of the core (1) and the coating layer (2) is enhanced by applying diffusion heat treatment to the coated wire thereof, the wire is elongated up to wire diameter L: not less than 12[mu]m and not more than 50.8[mu]m, and further that tensile elongation becomes not less than 8%. The bonding wire with the configuration is connected to the electrode and the conductor wiring with sufficient bonding strength, preventing work from being stopped even under the high-speed work at low temperatures.

Description

201037777 六、發明說明: 【發明所屬之技術領域】 本發明係關於用以藉由球形接合法連接Ic、LSI、電晶 體等積體電路元件上之電極,與導線架 '陶瓷基板、印刷 基板等電路配線基板之導體配線的接合導線及其製造方 法。 【先前技術】 此種利用球形接合法之連接方法,一般為圖1(a)〜(h)所 示之態樣,係由該圖(a)所示之將導線p插通於毛細管i〇a而 於其前端形成球(FAB : Free Air Ball電弧燒球外之狀態, 打開夾具10b,將毛細管10a朝積體電路元件上之電極&amp;下 - 降。此時,將球(FAB)b捕捉於毛細管10a内,並接合於毛 細管10a之中心。 當球b接觸於作爲目標之電極&amp;時(毛細管1〇a到達電極 a),毛細管10a將夹住球1),對球b賦予熱.加重超音波,藉 Q 此固相接合球b與電極a,形成ist接合而與電極a接著(圖 1(b)) 〇 若形成1st接合,則毛細管10a在上升至一定高度後(同圖 , (C)),將移動至導體配線正上方(同圖(d)〜(e))。此時, 為形成穩定之迴路,有實施令毛細管1〇a作特殊移動而對 導線P賦與「折線」之動作的情形(參照同圖(d)之鏈線至實 線)。 到達導體配線c之正上方之毛細管1〇a朝導體配線c下 降,將導線P壓接於導體配線(2nd目標)c(同圖(e)〜(f))。與 I46061.doc 201037777 :同時,對該壓接部位賦與熱.加重·超音波,藉此使導線p :形、’從而形成將導線P接合於導體配線。上之針縫式接 —、及於其後步驟可確保尾部之尾部接合(圖1⑴)。 形成4兩種接合後,毛細管10a以殘留導線P之狀態上 升且於毛細官10a之前端確保一定長度之尾部後,關閉 夾’、1 〇b(夾住導線p),從尾部接合之部份拉掉導線p(圖 ⑽。此時,由於尾部接合暫時固定導線p,因此形成尾 部接合之導線P不與毛細管10a—同上升。 e l〇a上升至所需高度時將停止,且於該毛細管 前端所確保之導線P之前端部份,以放電棒g施加高電壓而 飛 '火化(放電)’以其熱溶化導線p,使得該熔化之導線 '、“藉由表面張力變成近似球狀之球&amp;而凝固(圖1⑻)。 藉由X上之作用元成—個循環’其後以相同之作用,進 行藉由球形接合法連接電極a與導體配線c。 利用該球形接合法之連接中,接合導線P主要係使用金 Λ仁由於金仏較而,因此近年來使用的是銅純度為 9貝里%以上之廉價的銅線。此時,由於裸銅之狀態容 胃H表®之氧化’因此如圖2所示,乃使詩包含銅線 之芯材1被覆耐氧化金屬2者。 作為該被覆金屬(被覆層)2,係採用金(Μ)、銘⑻、纪 ㈣、銀(Ag)、錦㈤)等(專利文獻卜3)。 先前技術文獻 特許文獻 [專利文獻1]日本特開2GG3-133361號公報 146061.doc 201037777 [專利文獻2]曰本特開2〇〇4_64〇33號公報 [專利文獻3]日本特開2〇〇7_12776號公報 該金屬被覆之包含銅線之接合導線p中,隨著近年來電 . +零件之小型化等所致之㈣電路元件間之極小化,需要 - 更加減小上述球b,因此亦期望接合導線p為小徑者,為此 令其直徑L為50 μηι“下較佳(專利文獻丨段落〇〇〇9第12〜14 行)。 〇 又,積體電路元件之對於電極a之連接中,B求b向下成 搶狀(逆圓錐狀),則將上述球b向電極a壓接時,會有因嗜 球^之尖銳端而損傷電極a之虞,因此儘可能令球b為正圓/ 球#乂佳。為提局該球b之正圓球度,係令上述被覆層2之厚 '度t為芯線直徑的0.001以下(專利文獻1請求項”,或同^ 地令被覆層2之厚度以0.001〜〇.〇2 μηι(專利文獻3請求項 1) ’再或者以高於芯材i之銅之熔點的耐氧化金屬形成被 覆層2(專利文獻2段落0014)。 〇 再者,若在以有機基板為基底之BGA(Ball Grid AlTay, 球柵陣列)等中升高加熱溫度(台座溫度),則會產生龜曲而 V致接合性顯著惡化。因此,業已推出各種方案,例如於 熱處理後進行拉線之加工等(專利文獻3段落、〇〇54 等)’即使在降低上述導線P及電極a或導體配線ci接合時 之加熱溫度(台座溫度),例如降低至丨5〇〇c左右的情形下, 亦可保證充分之接合強度。 【發明内容】 發明所欲解決之問題 】4606】.doc 201037777 如上所述,以耐氧化金屬被覆銅、線而成之接合導線p, 迄今為止雖_出各種技術上的努力而得到相應好評但 基於近年來之低成本化’進—步要求伴隨作業之高速化之 接合強度的提高。 本發明係以對應其要求為目的。 解決問題之技術手段 為達成上述目的’本發明採用上述所有各種方法,令接 合導線P之線徑匕為12㈣以上50.8 _以下,且於包含純度 為99.99質量%以上之銅之芯⑻的外周全表面,形成利用 金、始、|巴、銀中之!種以上而成之厚度_ ^〜⑽ 之被覆層2。 7接合導線P之線徑[為5〇 8 μιη以下之理由為,上述專 利文獻i中係令其直徑W5G μηι以下,但m8陣以 下’以不改變50 μιη以下之程度即可更加減小上述球^ 又’令線控L之下限為12 _以上之理由為當其小於u μηι時,於接合前操作者將難以將導線p插通於毛細管 l〇a,從而導致作業性降低。 令芯材1之銅純度為99_99質量%以上,係為保證鋼之高 導電性。 被覆層2之厚度1越薄,球b之硬度越低,Si晶片(電極a) 損傷之可能性職’但若㈣,則針縫式接合在接合時合 使芯材1之銅露出之程度增大,細堇能顯現出不具有被 覆層2之銅導線程度之針縫式接合之接合性。例如,由後 述實施例與比較例之實驗結果可瞭解,有產生2次以上機 146061.doc 201037777 器停止之y# 夫。因此’由該實施例與比較例之實驗結果考 慮’破覆層2之厚度t設為0.02 μηι以上。 ❹ 士再者在台座溫度為150 °C左右之低溫下進行球形接合 ^由連續接合性之實驗結果可知厚度係設為〇 〇4 _以 上,更佳為大於〇.〇4 _。其理由為,若降低台座溫度, 則了使針縫式接合之接合所需之加重增大,且在被覆層2 之厚=為0.02 μιη以上而小於㈣叫之範圍時,會使芯材 之銅路出之程度增大,而有損害連續接合性之虞。 、另方面,右被覆層2較厚,則會增大球b之硬度,從而 增以晶片(電極a)損傷之可能性。因此,由後述實施例與 比車乂例之實驗結果考慮,令被覆層2之厚度⑽㈣以 下0 J被覆金屬為金、舶、纪及銀之理由為,一般而言將該 等貴金屬作為電子材料之被覆材且比較容易獲取。該等金 屬之純度亦與芯材i之銅相同’以99 99 f量%以上較佳。 〇 被覆層2可以該等貴金屬中之丨種形成,亦可以續以上之 金屬形成多層。 由上可知,該接合導線P所採用之構成係:其用以利用 球形接合法連接積體電路元件之電極&amp;與電路配線基板之 導體配線〇的線徑L為12 μιη以上50.8 μιη以下,芯材i包含 純度為99.99質量%以上之銅,並於其怒材周 面’藉由金H、銀中之i種以上形成厚度為王〇·〇: μηι〜0.09 μηι的被覆層2。 該構成中,台座溫度為15〇t左右之低溫之球接合用招 146061.doc 201037777 合導線中’其被覆層之厚度t為G.G4〜〇.09μηι。 此等構成之接合導線ρ之製造方法可採用各種方法,例 如’可採用於包含純度為99.99質量%以上之銅之芯⑻之 外周全表面,藉由金、始、,巴、銀中之i種以上形成被覆 層2—’且對其被覆線進行擴散熱處理而提高芯材與被覆層 之密接性後,將其拉線至線徑為12 _以上5〇8㈣以下, 再進行精煉熱處理以使拉伸伸長率成8 %以上,使被覆層2 之厚度t為〇.〇2〜〇.〇9 μπι之構成。 ▲該等構成中’被認為更佳的是,令上述被覆層2為熔點 兩於上述銅之熔點之鈀或鉑。 、如上述’ ^以高於;^'#1之銅之溶點的耐氧化金屬形成 被覆層2,則確認會加強·之正圓球度,本發明者認為其 理由係,藉由放電令銅炫融成正圓球時,其溶融部份會因 表面張力而沿導線攸至正上方,但當被覆層2亦溶融時, 該欣行將變得不佳,導致難以成為正圓球。此問題在 〇·〇2〜0.09 μπι厚度之被覆層2時更爲顯著。 又纪與翻中,纪旎令球b成為正圓球之條件之範圍(界 限)較廣。認為此原因為鈀之熔點與鉑之熔點相比,其更 接近銅之熔點。即,當於被覆層2使用鉑時,因放電令銅 熔融後直至鉑熔融為止會有時間差產生。若於被覆層2使 用鈀,則熔融之時間差縮小,因而更容易成爲正圓球。 另,上述純銅之熔點為1083t,金之熔點為1〇64t,鈀 之熔點為1554^,銀之熔點為962。(;,鉑之熔點為1772^。 另又確認,令被覆層2之厚度t為〇.〇4 μηι以上時,即使台 14606J.doc 201037777 座溫度為150°C之情形,機器故障亦較少,尤其係將鈀採 用於被覆層2,且令被覆層2之厚度t為〇·05 μιη以上時,即 使台座溫度為更低溫之1 3 5。(:時,亦不會引起機器故障。 此原因爲,在鈀被覆層2之情形中,如上所述,與基於銅 與鈀之熔融時間差縮小,從而更容易成為正圓球之相乘效 果所故。 再者,若令上述芯材之銅純度為99.999質量%以上則 由後述實施例與比較例之實驗結果可瞭解,Si晶片(電極甸 之損傷之可此性降低。此係藉由令銅純度為99·999質量% 以上,而可更加降低FAB硬度之故。 再者,被覆層2係藉由電解鍍敷、無電解鍍敷、蒸鍍法 等周知的方法形成,一般而言, 依次貫通稱作模頭之工具,而加 而§,導線P係將大線徑之銅棒[Technical Field] The present invention relates to an electrode for connecting an integrated circuit component such as Ic, LSI or transistor by a ball bonding method, and a lead frame 'ceramic substrate, a printed substrate, etc. A bonding wire of a conductor wiring of a circuit wiring board and a method of manufacturing the same. [Prior Art] The connection method using the ball bonding method is generally the one shown in Figs. 1(a) to (h), and the wire p is inserted into the capillary i as shown in the figure (a). a, forming a ball at the front end thereof (FAB: Free Air Ball, the state outside the arc ball, opening the jig 10b, and lowering the capillary 10a toward the electrode &amp; on the integrated circuit component. At this time, the ball (FAB) b is captured. In the capillary 10a, and joined to the center of the capillary 10a. When the ball b is in contact with the target electrode &amp; (the capillary 1 〇a reaches the electrode a), the capillary 10a will clamp the ball 1) to impart heat to the ball b. The supersonic wave is aggravated, and the solid phase bonding ball b and the electrode a are joined by Q, and the ist is joined to the electrode a (Fig. 1(b)). If the 1st junction is formed, the capillary 10a rises to a certain height (the same figure, (C)), will move directly above the conductor wiring (same figure (d) ~ (e)). In this case, in order to form a stable circuit, there is a case where the capillary 1〇a is specifically moved to apply a "fold line" to the wire P (refer to the chain line to the solid line in the same figure (d)). The capillary 1a reaching the positive direction of the conductor wiring c is lowered toward the conductor wiring c, and the conductor P is crimped to the conductor wiring (2nd target) c (Figs. (e) to (f)). At the same time as I46061.doc 201037777: heat is applied to the crimping portion, and the ultrasonic wave is applied to the conductor portion to form the conductor P to be bonded to the conductor wiring. The stitching on the top and the subsequent steps ensure the tail of the tail is joined (Fig. 1(1)). After the formation of the four types of joints, the capillary 10a rises in the state of the residual wire P and ensures a certain length of the tail at the front end of the capillary 10a, and then closes the clip ', 1 〇b (clamps the wire p), and the portion joined from the tail Pull off the wire p (Fig. 10). At this time, since the tail joint temporarily fixes the wire p, the wire P forming the tail joint does not rise with the capillary 10a. When el〇a rises to the desired height, it stops, and the capillary is stopped. The front end portion of the wire P secured by the front end is applied with a high voltage by the discharge rod g to fly 'ignite (discharge)' to thermally melt the wire p, so that the melted wire ', becomes a spherical shape by the surface tension The ball &amp; and solidifies (Fig. 1 (8)). By the action of the element on X, a cycle is followed by the same action, and the electrode a and the conductor wiring c are connected by a ball bonding method. In the case where the bonding wire P is mainly used, the golden glutinous rice is used because of the gold bismuth. Therefore, in recent years, an inexpensive copper wire having a copper purity of 9 or more is used. In this case, due to the state of the bare copper, the stomach H table® Oxidation' is therefore shown in Figure 2. In the case where the core material 1 of the copper wire is coated with the oxidation resistant metal 2, the coated metal (coating layer) 2 is made of gold (Μ), Ming (8), Ji (4), silver (Ag), and Jin (5)). [Patent Document 3] [Patent Document 3] [Patent Document 1] Japanese Patent Laid-Open Publication No. Hei. No. 2 GG3-133361 No. 146061. doc. In the case of the metal-covered bonding wire p including the copper wire, the miniaturization of the electric components, the miniaturization of the components, and the like, the minimization of the circuit elements is required to further reduce the above-mentioned For the ball b, it is also desirable that the bonding wire p is a small diameter, and for this reason, the diameter L is 50 μηι "better (Patent Document 丨 Paragraph 9, lines 12 to 14). Further, in the connection of the integrated circuit element to the electrode a, B is required to be b-shaped downward (reversely conical), and when the ball b is pressed against the electrode a, there is a sharp end due to the ball While the electrode a is damaged, it is preferable to make the ball b a perfect circle/ball. In order to improve the true sphericity of the ball b, the thickness 'degree t of the coating layer 2 is 0.001 or less of the diameter of the core wire (the request of Patent Document 1), or the thickness of the coating layer 2 is 0.001 to 0.001. 〇.〇2 μηι (Patent Document 3, claim 1) 'The coating layer 2 is formed by an oxidation-resistant metal higher than the melting point of copper of the core material i (Patent Document 2, paragraph 0014). When the heating temperature (mount temperature) is increased in a BGA (Ball Grid AlTay) or the like in which the substrate is a substrate, the tortuosity is generated and the V-bonding property is remarkably deteriorated. Therefore, various proposals have been made, for example, after heat treatment. The processing of the wire drawing (paragraphs of the patent document 3, 〇〇54, etc.)' decreases the heating temperature (the pedestal temperature) when the wire P and the electrode a or the conductor wire ci are joined, for example, to about 丨5〇〇c. In this case, sufficient joint strength can be ensured. [Explanation] Problems to be solved by the invention] 4606].doc 201037777 As described above, the bonding wire p made of copper and wire coated with oxidation resistant metal has been Various technical efforts In order to achieve the above object, the present invention has been made in response to the demand for the improvement of the joint strength in accordance with the recent demand for cost reduction. By using all of the above methods, the wire diameter 匕 of the bonding wire P is 12 (four) or more and 50.8 Å or less, and the outer peripheral surface of the copper core (8) containing the purity of 99.99% by mass or more is formed to utilize gold, the beginning, the |bar, and the silver. In the case of the coating layer 2 having a thickness of _ ^ 〜 (10), the wire diameter of the bonding wire P is 5 〇 8 μηη or less, and the above-mentioned patent document i has a diameter of W5G μηι or less, but Below the m8 array, the ball can be further reduced by not changing the degree of 50 μm or less. The reason why the lower limit of the wire control L is 12 _ or more is that when it is smaller than u μηι, the operator will have difficulty before joining. The wire p is inserted into the capillary l〇a, resulting in a decrease in workability. The copper purity of the core material 1 is 99 to 99% by mass or more to ensure high electrical conductivity of the steel. The thinner the thickness 1 of the coating layer 2, the ball b The lower the hardness The Si wafer (electrode a) is likely to be damaged. However, if the stitch bonding is performed, the degree of copper exposure of the core material 1 is increased at the time of bonding, and the fine copper can exhibit copper without the coating layer 2. The bonding property of the stitch bonding of the wire degree. For example, it can be understood from the experimental results of the examples and the comparative examples described later that there are two or more machines 146061.doc 201037777 stop y#. Therefore, by this embodiment and The experimental results of the comparative example consider that the thickness t of the fracture layer 2 is set to 0.02 μηι or more. In addition, the ball joint is performed at a low temperature of about 150 ° C at the pedestal temperature. The results of the continuous bond test show that the thickness is set. It is 〇〇4 _ or more, and more preferably 〇.〇4 _. The reason for this is that if the temperature of the pedestal is lowered, the weighting required for the bonding of the stitch bonding is increased, and when the thickness of the coating layer 2 is 0.02 μm or more and less than the range of (4), the core material is caused. The extent of the copper road is increased, and there is a flaw in the continuous joint. On the other hand, if the right coating layer 2 is thick, the hardness of the ball b is increased, thereby increasing the possibility of damage of the wafer (electrode a). Therefore, considering the results of the later-described embodiment and the experimental results of the vehicle, the reason why the thickness of the coating layer 2 (10) and (4) is less than 0 J is that the metal is gold, ship, and silver, and generally the noble metal is used as the electronic material. The coated material is relatively easy to obtain. The purity of these metals is also the same as that of the core material i, and is preferably 99 99 f or more. The ruthenium coating layer 2 may be formed of the ruthenium species among the noble metals, or may be formed of a plurality of layers of the above metals. As can be seen from the above, the bonding wire P has a configuration in which the wire diameter L of the electrode connecting the integrated circuit component by the ball bonding method and the conductor wiring wire of the circuit wiring substrate is 12 μm or more and 50.8 μm or less. The core material i contains copper having a purity of 99.99% by mass or more, and a coating layer 2 having a thickness of Wang〇·〇: μηι to 0.09 μηι is formed on the circumferential surface of the anger material by one or more of gold H and silver. In this configuration, the temperature of the slab is about 15 〇t, and the thickness t of the coating layer is G.G4 to 〇.09μηι. 146061.doc 201037777. The manufacturing method of the bonding wires ρ of such a configuration may be carried out by various methods, for example, 'the entire surface of the copper core (8) having a purity of 99.99% by mass or more may be used, by the gold, the first, the bar, the silver After forming the coating layer 2'' and performing diffusion heat treatment on the coated wire to improve the adhesion between the core material and the coating layer, the wire is drawn to a wire diameter of 12 Å or more and 5 〇 8 (four) or less, and then subjected to a refining heat treatment. The tensile elongation is 8% or more, and the thickness t of the coating layer 2 is 〇.〇2 to 〇.〇9 μπι. It is considered that in the above composition, it is preferable that the coating layer 2 is palladium or platinum having a melting point of two or more of the melting point of the copper. When the coating layer 2 is formed by the oxidation-resistant metal of the copper melting point of the above-mentioned '^', the positive spherical sphericity is confirmed to be strengthened, and the inventors believe that the reason is that the discharge is made by the discharge order. When the copper is melted into a perfect sphere, the molten part will be twisted up to the top of the wire due to the surface tension, but when the coating layer 2 is also melted, the Xinxing will become poor, making it difficult to become a perfect sphere. This problem is more remarkable when the coating layer 2 of 厚度·〇2 to 0.09 μπι thickness is used. In the case of the squad and the middle, the scope (limitation) of the condition that the ball is a perfect ball is wider. This reason is considered to be that the melting point of palladium is closer to the melting point of copper than the melting point of platinum. That is, when platinum is used for the coating layer 2, a time difference occurs after the copper is melted by the discharge until the platinum is melted. When palladium is used for the coating layer 2, the time difference of melting is reduced, and it is more likely to become a perfect sphere. Further, the melting point of the above pure copper is 1083 t, the melting point of gold is 1 〇 64 t, the melting point of palladium is 1554 Å, and the melting point of silver is 962. (;, the melting point of platinum is 1772^. It is also confirmed that when the thickness t of the coating layer 2 is 〇.〇4 μηι or more, even if the temperature of the table 14606J.doc 201037777 is 150 °C, the machine failure is less. In particular, when palladium is used for the coating layer 2, and the thickness t of the coating layer 2 is 〇·05 μm or more, even if the pedestal temperature is lower than 135 ((:, no machine failure occurs). The reason is that in the case of the palladium coating layer 2, as described above, the difference in melting time between copper and palladium is reduced, and it is more likely to be a synergistic effect of the perfect sphere. Further, if the core material is copper When the purity is 99.999 mass% or more, it is understood from the experimental results of the examples and comparative examples described later that the Si wafer (the damage of the electrode is reduced). This is because the purity of the copper is 99.999 mass% or more. Further, the coating layer 2 is formed by a known method such as electrolytic plating, electroless plating, or vapor deposition, and generally, a tool called a die is sequentially inserted, and §, wire P is a large diameter copper rod

合'丨王’從时獲得更穩定之接合性。 此時,若由鈀形成被覆層 貝J可令芯材之銅純度為 146061.doc 201037777 99.999質量%以上,令該被覆層之厚度(為〇〇5〜〇〇9^111。 發明之效果 本發明係如上所述’故可獲得具有穩定之接合強度之於 純銅被覆責金屬而成之接合導線。 【實施方式】 製作表1所示之實施例1〜45及比較例i〜13,且進行該接 合導線P之1st接合部之Si晶片(電極a)之損傷程度及連續 接合性之試驗。 即’首先,準備銅純度為99.99質量%之純銅(表1中: 顿)與銅純度為99.999質量%之純銅(表1中:5&gt;^)之〇2〜〇.8 mm直徑的銅線’藉由電解鍍敷法於該銅線上被覆、 Pd、Pt及Ag之貴金屬,在捲回該被覆線而通過退火爐後, 藉由再次以捲取用捲轴捲繞進行連續擴散熱處理。退火爐 係使用具有爐長為1 m之爐芯管之電爐,於爐芯管流動以 氮氣。令該爐溫度為5 0 0 C以上8 0 0 C以下,被覆線之溫度 為200〜50CTC,且該被覆線之行進速度為5〜60 m/分鐘。實 施以上之擴散熱處理提高銅線(芯材)1與被覆層2之密接性 後,將其拉線至線徑為15〜50·8 μιη,再進行精煉熱處理以 使其拉伸伸長率爲8 %以上’獲得被覆層2之厚度t為 〇.〇〇1〜0.112卜111之接合導線?(實施例1〜45及比較例1〜13)。 表1中顯示2種貴金屬之例係以相同厚度雙重被覆該2種金 屬者。 其次,於表1顯示針對該各接合導線P進行下述評估之結 果0 146061.doc -10· 201037777 「被覆層(表面皮膜層)2之厚度」: 被覆層(表面皮膜層)2之厚度係以歐捷電子分光分析法 測定。以Ar從被覆層之表面濺鍍,且對每單位時間之濺鍍 進行光譜測定。令深度方向之單位為濺鍍時間,由之前預 先測定之標準試料Si〇2之濺鍍速率,以Si〇2換算算出對象 材料之深度方向之距離。關於被覆層,如圖3所示,在以 對象被覆元素之歐捷峰值強度為縱軸、深度為橫軸之曲線 圖中,係將歐捷峰值強度為84 %之位置至16 %之位置之距 離作為被覆層之厚度。 「芯材(銅)之純度」: 以GDMS(輝光放電質量)分析測定所有元素之濃度來決 定Cu純度。 「連續接合性」(1): 以接合機器進行10,000次連續接合,令不發生機器停止 為「A」,發生1次機器停止為「B」,發生2次以上機器停 止為「D」。此時,若台座溫度不降低,則難以進行該連續 接合,因此以200。(:(±5°C )、150。(3 (±5。(:)之2個水準進行。 「1st接合部之Si晶片損傷」(2): 接合後,為評估1 st球接合部正下方之si晶片損傷,以王 水溶解球接合部a及電極膜,以光學顯微鏡與SEM觀察以 晶片之龜裂。此時,觀察1 〇〇個接合部,其中令可觀察到i 個或完全觀察不到5 μιη以下之微小凹坑之情形為r a」,令 可觀察到2個以上5 μηι以下之微小凹坑之情形因實用上無 害而為「Β」,令可觀察到5 μπι以上之龜裂之情形為 146061.doc 201037777 「D」。 「綜合評估」: 將⑴,評估中2〇(TC.15(rc下皆為A,且⑺之評估中為A 者評為「A」;將⑴之評估中2〇〇t:_15(rc下皆為a,且⑺ 之砰估中為B者評為「B」;將(1)之評估中2〇〇t:下為a, 150C下為B者坪為「c」。並且’將即使有一個d者,因實 用上有問題而將其評其為「D」。 [表1]The combination of 'King Wang' has gained more stable bondage from time to time. In this case, when the coating layer J is formed of palladium, the copper purity of the core material is 146061.doc 201037777 99.999 mass% or more, and the thickness of the coating layer is 〇〇5 to 〇〇9^111. According to the invention, as described above, a bonding wire having a stable bonding strength and a pure copper-coated metal can be obtained. [Embodiment] Examples 1 to 45 and Comparative Examples i to 13 shown in Table 1 were produced and carried out. Test for the degree of damage and continuous bonding of the Si wafer (electrode a) of the 1st junction portion of the bonding wire P. That is, first, pure copper having a copper purity of 99.99% by mass (in Table 1: D) and a copper purity of 99.999 were prepared. 5% by mass of pure copper (in Table 1: 5 &gt; ^) 〇 2 ~ 〇. 8 mm diameter copper wire 'coated by the electrolytic plating method on the copper wire, Pd, Pt and Ag precious metals, in the rewind After passing through the annealing furnace and passing through the annealing furnace, the continuous diffusion heat treatment is performed by winding the reel for winding. The annealing furnace uses an electric furnace having a furnace tube having a furnace length of 1 m, and nitrogen gas flows through the furnace tube. The temperature of the furnace is below 500 ° C and below 80 ° C, the temperature of the covered wire 200 to 50 CTC, and the traveling speed of the covered wire is 5 to 60 m/min. After performing the above diffusion heat treatment to improve the adhesion between the copper wire (core material) 1 and the coating layer 2, the wire is drawn to a wire diameter of 15 〜50·8 μιη, and further subjected to a refining heat treatment to have a tensile elongation of 8 % or more. A thickness of the coating layer 2 is obtained as a bonding wire of 〇. 〇〇1 to 0.112 卜 111 (Examples 1 to 45 and Comparative Examples 1 to 13) Table 1 shows an example in which two kinds of precious metals are double-coated with the same thickness in the same thickness. Next, the results of the following evaluations for the respective bonding wires P are shown in Table 1 146061.doc -10· 201037777 "Thickness of coating layer (surface coating layer) 2": The thickness of coating layer (surface coating layer) 2 is measured by Auger electron spectrometry. Ar is sputtered from the surface of coating layer, and for each Spectral measurement was performed by sputtering per unit time, and the unit of the depth direction was the sputtering time, and the distance in the depth direction of the target material was calculated from Si〇2 in terms of the sputtering rate of the standard sample Si〇2 measured in advance. The layer, as shown in Figure 3, is The peak intensity of the element is the vertical axis and the horizontal axis is the horizontal axis. The distance from the position where the peak intensity of the Auger peak is 84% to 16% is the thickness of the coating layer. Purity: The purity of all elements is determined by GDMS (Glow Discharge Mass) analysis to determine the purity of Cu. "Continuous bondability" (1): 10,000 consecutive joints are carried out by the joining machine so that the machine stop does not occur as "A". The machine stop is "B" once, and the machine stop is "D" twice or more. At this time, if the pedestal temperature does not decrease, it is difficult to perform the continuous joining, so it is 200. (: (±5°C), 150. (3 (±5. (:) is performed at two levels. "Si wafer damage at 1st joint" (2): After bonding, the 1st ball joint is evaluated. In the lower Si wafer damage, the ball joint portion a and the electrode film were dissolved in aqua regia, and the wafer was cracked by optical microscopy and SEM observation. At this time, one joint was observed, and i or complete was observed. The case where the micro-pits of 5 μm or less are not observed is ra", so that it is possible to observe that two or more micro-pits of 5 μη or less are practically harmless, so that 5 μπι or more can be observed. The case of cracking is 146061.doc 201037777 "D". "Comprehensive evaluation": (1), 2评估 in the evaluation (TC.15 (A is the rc, and the A in the evaluation of (7) is rated as "A"; In the evaluation of (1), 2〇〇t:_15 (all are a in rc, and B in the evaluation of (7) is rated as “B”; in the evaluation of (1), 2〇〇t: a, 150C The lower one is B. The flat is "c". And 'even if there is one d, it will be evaluated as "D" because of practical problems. [Table 1]

Pd Au,Pd 皮膜層 材之 Cu純度 ①連續接合性 ②1st接合 部之Si晶 片損傷 綜合 評估 皮膜厚 一 (μηι) 200°C (士 5。〇 150°C (士 5〇C) 0.021 4N A B B ~~C~ 0.032 4N A B B c~ 0.022 5N A B A c 0.032 4N A B B c 0.041 5N A A A A— 0.075 4N A A B B 0.081 4N A A B B 0.022 4N A B B 0.042 4N A A B B 0.034 4N A B B C 0.043 4N A A B B 0.054 5N A A A A 0.088 5N A A A A— 0.031 4N A B B C— 0.042 4N A A B B 0.052 5N A A A A 0.065 4N A A B B— 0.079 4N A A B B 0.024 5N A B A C 0.046 5N A A A A 0.059 4N A A B B 0.026 5N A B A C 0.088 4N A A B B 0.021 4N A B B C 0.023 4N A B B C 0.057 4N A A B B~ 0.041 5N A A A APd Au, Pd film material Cu purity 1 continuous bonding 21st joint Si wafer damage comprehensive evaluation film thickness one (μηι) 200 ° C (士5. 〇150 ° C (士5〇C) 0.021 4N ABB ~ ~C~ 0.032 4N ABB c~ 0.022 5N ABA c 0.032 4N ABB c 0.041 5N AAAA— 0.075 4N AABB 0.081 4N AABB 0.022 4N ABB 0.042 4N AABB 0.034 4N ABBC 0.043 4N AABB 0.054 5N AAAA 0.088 5N AAAA — 0.031 4N ABBC — 0.042 4N AABB 0.052 5N AAAA 0.065 4N AABB— 0.079 4N AABB 0.024 5N ABAC 0.046 5N AAAA 0.059 4N AABB 0.026 5N ABAC 0.088 4N AABB 0.021 4N ABBC 0.023 4N ABBC 0.057 4N AABB~ 0.041 5N AAAA

No. 線徑 (μηι) 一 . 15 本 2 20 3 發 4 -________ 25 5 明 6 33 7 50 例 8 15 9 10 11 20 12 13 14 15 25 16 17 18 19 33 20 21 22 50 23 24 20 25 25— 26 —' 1 -33 27 __ 33 金屬 種類No. Wire diameter (μηι) I. 15 Ben 2 20 3 Hair 4 -________ 25 5 Ming 6 33 7 50 Example 8 15 9 10 11 20 12 13 14 15 25 16 17 18 19 33 20 21 22 50 23 24 20 25 25-26 —' 1 -33 27 __ 33 Metal Type

Au 146061.doc -12- 201037777 ΟAu 146061.doc -12- 201037777 Ο

28 15 Pt 0.023 4N ------ B B C 29 0.031 4N —A. B B C 30 20 0.038 4N -—A, B B C 31 0.042 4N _ A B B 32 0.078 5N A A A A 33 25 0.024 5N _____A B A c 34 0.043 5N ~ A A A A 35 0.058 T* — 4N A A B B 36 50 0.025 5N A__ B A C 37 0.054 CAT 5N A A A A 38 15 Ag 0.022 4N Δ B B C 39 20 0.031 4N 「 ~ A B B C 40 25 0.054 .4N A A B R 41 15 Au’Pt 0.029 4N A B B c 42 20 0.038 4N Λ B B c 43 20 Pd,Ag 0.036 4N r\ -----_I A B B c 44 20 0.069 5N --A_ A A A A 45 25 Au,Ag 0.078 ------ 5N A A Δ 比 較 例 1 15 Au 0.001 4N D D B D 2 20 0.014 L 4N ~B~~~ ----- D B D 3 20 0.095 5N A A D D 4 15 Pd 0.003 4N D D B D 5 25 0.002 ~~~ — 5N ~~~D~~~ .一·—— D A D 6 η 25 0.099 5N A A D n / 03 0.102 4N A D D 8 50 0.098 __5N . 4N A — A D D 9 1 Λ 15 〇 Λ Pt 0.002 D D B D 1 u Z U 0.001 5N --——. D A D 11 25 0.112 一 4N &quot; A A D D 12 t -7 20 〇 c Ag 0.001 4N D D B n 1 j 0.098 4N A A D D28 15 Pt 0.023 4N ------ BBC 29 0.031 4N —A. BBC 30 20 0.038 4N ——A, BBC 31 0.042 4N _ ABB 32 0.078 5N AAAA 33 25 0.024 5N _____A BA c 34 0.043 5N ~ AAAA 35 0.058 T* — 4N AABB 36 50 0.025 5N A__ BAC 37 0.054 CAT 5N AAAA 38 15 Ag 0.022 4N Δ BBC 39 20 0.031 4N ” ~ ABBC 40 25 0.054 .4N AABR 41 15 Au'Pt 0.029 4N ABB c 42 20 0.038 4N BB BB c 43 20 Pd, Ag 0.036 4N r\ -----_I ABB c 44 20 0.069 5N --A_ AAAA 45 25 Au,Ag 0.078 ------ 5N AA Δ Comparative Example 1 15 Au 0.001 4N DDBD 2 20 0.014 L 4N ~B~~~ ----- DBD 3 20 0.095 5N AADD 4 15 Pd 0.003 4N DDBD 5 25 0.002 ~~~ — 5N ~~~D~~~ .一———— DAD 6 η 25 0.099 5N AAD n / 03 0.102 4N ADD 8 50 0.098 __5N . 4N A — ADD 9 1 Λ 15 〇Λ Pt 0.002 DDBD 1 u ZU 0.001 5N --——. DAD 11 25 0.112 A 4N &quot; AADD 12 t -7 20 〇c Ag 0.001 4N DDB n 1 j 0.098 4N AADD

由該實驗結果可瞭解:當被覆層厚度1小於0.02 μπι時, 贿及⑽之兩個連續接合性將下降(比較例卜2、4、 5 9 10 12),备接近0.〇2_時’可滿足前者之連續接 合性(比較例2);當大於時,可滿足兩者之連續接 合性(實施例1〜45,比較例3、6〜8 11 、 13)° 另-方面’當被覆層厚度t大於0 09 _ 將會觀察到Si晶片(電極a)之損 ’將支硬, 13)。 h傷(比較例3、&quot;、u、 146061.doc -13· 201037777 又可知’使用純銅5N,且令被覆層厚度t為0.04 μιη以上 者(貫施例 5、12、13、ι6、20、27、32、34、37、44、 45) ’綜合評估為r Α」,即使台座溫度為15〇它左右之低 狐’其連續接合性仍為良好,且可有效保證其連續接合 性。尤其在被覆層厚度(為〇〇5 μιη以上時尤爲顯著(實施例 12 ' 13 、 16)。 【圖式簡單說明】 圖1係球形接合連接法之說明圖,係其進行中之 圖。 圖2係本發明之接合導線之剖面圖。 圖3係歐捷峰值強度與被覆層(鍍敷層)之深度之關係 圖。 【主要元件符號說明】 1 芯材 2 被覆層 a 積體電路元件之電極 b 接合球 c 電路配線基板之導體配線 p 接合導線 146061.docFrom the experimental results, it can be understood that when the thickness of the coating layer is less than 0.02 μπι, the two consecutive joints of bribe and (10) will decrease (Comparative examples 2, 4, 5 9 10 12), when the preparation is close to 0.〇2_ 'The continuous bondability of the former can be satisfied (Comparative Example 2); when it is larger than, the continuous bondability of the two can be satisfied (Examples 1 to 45, Comparative Example 3, 6 to 8 11 , 13) ° The thickness t of the coating layer is greater than 0 09 _ and it will be observed that the damage of the Si wafer (electrode a) will be hard, 13). h injury (Comparative Example 3, &quot;, u, 146061.doc -13· 201037777 It is also known that 'the pure copper 5N is used, and the thickness t of the coating layer is 0.04 μm or more (Examples 5, 12, 13, ι 6, 20) , 27, 32, 34, 37, 44, 45) 'Comprehensive evaluation is r Α", even if the pedestal temperature is 15 〇, the low fox's continuous joint is still good, and can effectively ensure its continuous jointability. In particular, the thickness of the coating layer (which is 〇〇5 μmη or more is particularly remarkable (Examples 12' 13 and 16). [Brief Description of the Drawings] Fig. 1 is an explanatory view of a spherical joint joining method, which is a middle view. Fig. 2 is a cross-sectional view of the bonding wire of the present invention. Fig. 3 is a diagram showing the relationship between the peak strength of the Oujie and the depth of the coating layer (plating layer). [Description of main components] 1 core material 2 coating layer a composite circuit component Electrode b bonding ball c circuit wiring substrate conductor wiring p bonding wire 146061.doc

Claims (1)

201037777 七、申請專利範圍: 1. 一種接合導線,其特徵在於: 其係用以藉由球形接合法連接積體電路元件之電極(a) , 與電路配線基板之導體配線(c)的線徑(L)為12 μιη以上 , 5〇.8 μΠ1以下者,且芯材(1)包含純度為99.99質量%以上 之銅’於該芯材⑴之外周全表面,形成有利用金、鉑、 鈀銀中之1種以上而成之厚度⑴為0 02〜〇·〇9 μπι之被覆 層(2)。 Ο 2.如明求項1之接合導線,其中上述被覆層(2)之厚度⑴為 〇·〇4〜G.Q9 μιη。 • 3.如吻求項1之接合導線,其中使上述被覆層(2)為其熔點 • · 局於上述鋼之熔點之鈀或鉑。 4. 如印求項2之接合導線,其中使上述被覆層(2)為其熔點 南於上述銅之熔點之鈀或鉑。 5. 如睛求項1之接合導線,其中使上述被覆層(2)為其熔點 ◎ 间於上述銅之熔點之鈀,且其厚度⑴為〇_〇5〜0.09 μηι。 6. 如凊求項丨至5中任一項之接合導線,其中使上述芯材 之銅純度為99.999質量%以上。 f 7· 一種接合導線之製造方法,其特徵在於: .其係請求項1至4中任一項之接合導線(P)之製造方法, °亥接合導線(p)係用以藉由球形接合法連接積體電路元件 之電極(a)與電路配線基板之導體配線(c)者;且,前述製 造方法係於包含純度為99.99質量%以上之銅之芯材〇)之 外周王表面,形成利用金、始、|巴、銀中之1種以上而 146061.doc 201037777 成之被覆層(2),且對其被覆線實施擴散熱處理而提高前 述芯材(1)與被覆層(2)之密接性後,將其拉線至線徑(L) 為12 μιη以上50.8 μιη以下,再進行精煉熱處理以使其拉 伸伸長率成為8%以上。 8.如請求項7之接合導線之製造方法,其中使上述芯材(1) 之銅純度為99.999質量%以上,且使上述被覆層(2)包含 把,並令其厚度t為0.05〜0.09 μιη。 146061.doc201037777 VII. Patent application scope: 1. A bonding wire characterized in that it is used for connecting an electrode (a) of an integrated circuit component by a ball bonding method and a wire diameter of a conductor wiring (c) of a circuit wiring substrate. (L) is 12 μm or more, and 5 〇.8 μΠ1 or less, and the core material (1) contains copper having a purity of 99.99% by mass or more, and is formed on the entire surface of the core material (1), and gold, platinum, and palladium are formed. The thickness (1) of one or more kinds of silver is a coating layer (2) of 0 02~〇·〇9 μπι. 2. The bonding wire according to claim 1, wherein the thickness (1) of the coating layer (2) is 〇·〇4 to G.Q9 μιη. 3. A bonding wire according to the item 1, wherein the coating layer (2) is a melting point of the palladium or platinum which is in the melting point of the steel. 4. The bonding wire of claim 2, wherein the coating layer (2) is palladium or platinum having a melting point of about the melting point of the copper. 5. The bonding wire according to item 1, wherein the coating layer (2) is palladium having a melting point of ◎ between the melting points of the copper, and the thickness (1) is 〇_〇5 to 0.09 μηι. 6. The bonding wire according to any one of item 5, wherein the copper material of the core material has a purity of 99.999 mass% or more. F7. A method of manufacturing a bonding wire, characterized by: a method for manufacturing a bonding wire (P) according to any one of claims 1 to 4, wherein the bonding wire (p) is used for ball bonding The electrode (a) of the integrated circuit component and the conductor wiring (c) of the circuit wiring board are legally connected; and the manufacturing method is based on the surface of the core material including the core material of copper having a purity of 99.99% by mass or more. The coating layer (2) is formed by using one or more of gold, ginseng, ba, and silver, and 146061.doc 201037777 is formed, and diffusion heat treatment is applied to the coated wire to increase the core material (1) and the coating layer (2). After the adhesion, the wire is pulled to a wire diameter (L) of 12 μm or more and 50.8 μm or less, and then subjected to a refining heat treatment to have a tensile elongation of 8% or more. 8. The method of producing a bonding wire according to claim 7, wherein the core material (1) has a copper purity of 99.999 mass% or more, and the coating layer (2) is provided with a thickness of 0.05 to 0.09. Ιιη. 146061.doc
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Cited By (3)

* Cited by examiner, † Cited by third party
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Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101053079A (en) 2004-11-03 2007-10-10 德塞拉股份有限公司 Stacked packaging improvements
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
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Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6278863A (en) * 1985-09-30 1987-04-11 Tanaka Denshi Kogyo Kk Copper wire for bonding of semiconductor element
JPS6297360A (en) * 1985-10-24 1987-05-06 Mitsubishi Metal Corp Minute high impurity copper wire, whose surface is coated, for bonding wire for semiconductor device
JPH0786325A (en) * 1993-09-14 1995-03-31 Hitachi Cable Ltd Copper wire for electronic device
US7969021B2 (en) * 2000-09-18 2011-06-28 Nippon Steel Corporation Bonding wire for semiconductor device and method for producing the same
JP2003133361A (en) * 2001-10-23 2003-05-09 Sumiden Magnet Wire Kk Bonding wire
JP2004064033A (en) * 2001-10-23 2004-02-26 Sumitomo Electric Wintec Inc Bonding wire

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