TW201032274A - Substrate structure and manufacturing method thereof - Google Patents

Substrate structure and manufacturing method thereof Download PDF

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Publication number
TW201032274A
TW201032274A TW98105510A TW98105510A TW201032274A TW 201032274 A TW201032274 A TW 201032274A TW 98105510 A TW98105510 A TW 98105510A TW 98105510 A TW98105510 A TW 98105510A TW 201032274 A TW201032274 A TW 201032274A
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Taiwan
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insulating layer
substrate
pattern
trench pattern
trench
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TW98105510A
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Chinese (zh)
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TWI394212B (en
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Chih-Cheng Lee
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Advanced Semiconductor Eng
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Abstract

A substrate structure and a manufacturing method thereof are provided. The substrate structure includes the follow steps. First, a substrate having an insulation layer is provided. Then, a mask is provided. Then, plasma is provided and a groove pattern whose the bottom surface is plane is formed through the plasma. Then, an embedded pattern is formed on the groove pattern. As a result, the substrate structure is formed. Furthermore, repeating the above steps is to form a multi-layer board.

Description

201032274 六、發明說明: 【發明所屬之技術領域】 本發明是有關於一種基板結構及其製造方法,且特 別是有關於一種具有埋入式線路(embedded pattern) 之基板結構及其製造方法。 【先前技術】 請參照第1圖,其繪示習知具有埋入式線路之基板 _ 結構示意圖。習知之基板結構100包括一基材102、一絕 緣層104及一埋入式線路層106,並具有一溝槽108。埋 入式線路層106形成於溝槽108。一般來講,製作溝槽 108之方式都是採用雷射加工方式。 然而,雷射光束之加工路徑只有沿著單軸向,即Z 軸方向來進行,而無法同時往Z軸之兩邊對絕緣層104 加工,因此導致溝槽108之槽寬會隨著其槽深縮小的現 象。如此,製作完成之溝槽108,其槽底面110自然呈一 ❿ 弧面。而呈弧面之槽底面110的表面積被受限,使後續 形成的埋入式線路層106的電性品質是不佳的。 此外,雷射加工一次只能於基材10 2的一面進行溝 槽加工,待此面的溝槽製作完成後,才能於另一面繼續 製作出溝槽,相當地費時及不便。 【發明内容】 本發明係有關於一種基板結構及其製造方法,以電 漿蝕刻製作埋入式線路之溝槽,使溝槽之槽底面形成平 201032274201032274 VI. Description of the Invention: [Technical Field] The present invention relates to a substrate structure and a method of fabricating the same, and in particular to a substrate structure having an embedded pattern and a method of fabricating the same. [Prior Art] Referring to Fig. 1, there is shown a schematic view of a substrate having a buried circuit. The conventional substrate structure 100 includes a substrate 102, an insulating layer 104, and a buried wiring layer 106, and has a trench 108. A buried wiring layer 106 is formed in the trench 108. In general, the way in which the grooves 108 are made is by laser processing. However, the processing path of the laser beam is only performed along the uniaxial direction, that is, the Z-axis direction, and the insulating layer 104 cannot be processed simultaneously on both sides of the Z-axis, thereby causing the groove width of the groove 108 to follow the groove depth. Shrinking phenomenon. Thus, the groove 108 of the groove is formed to have a substantially curved surface. The surface area of the grooved bottom surface 110 is limited, so that the electrical quality of the subsequently formed buried wiring layer 106 is not good. In addition, the laser processing can only perform groove processing on one side of the substrate 10 2 at a time. After the groove on the surface is completed, the groove can be continuously formed on the other side, which is quite time consuming and inconvenient. SUMMARY OF THE INVENTION The present invention relates to a substrate structure and a method of fabricating the same, in which a trench of a buried line is formed by plasma etching to form a groove bottom surface of the trench.

TW5145PA 面。如此,槽底面之面積係增加,使得後續形成之埋入 式線路層具有比較大的電性連接表面,增進了埋入式線 路層之電性。 根據本發明,提出一種基板結構,包括一基材及一 第一埋入式線路層。基材包括一第一絕緣層。第一絕緣 層具有一第一溝槽圖案,第一溝槽圖案之一槽底面為平 面。第一埋入式線路層形成於第一溝槽圖案。 根據本發明,提出一種基板結構之製造方法。製造 方法包括以下步驟。提供一基材,基材包括一第一絕緣 層。提供一第一光罩。提供一電漿,透過第一光罩於第 一絕緣層上蝕刻出一第一溝槽圖案,第一溝槽圖案之一 槽底面為平面。形成一第一埋入式線路層於第一溝槽圖 案上。 為讓本發明之上述内容能更明顯易懂,下文特舉一 較佳實施例,並配合所附圖式,作詳細說明如下: 【實施方式】 在本發明之基板結構及其製造方法中,係利用電漿蝕刻 製作出埋入式線路之溝槽,使溝槽之槽底面形成平面。 如此,槽底面之面積係增加,使得後續形成之埋入式線 路層具有比較大的電性連接表面,增進了埋入式線路層 之電性品質。以下以二個較佳實施例來作說明。 第一實施例 請參照第2圖,其繪示依照本發明第一實施例之基 4 板結構之示意圖。基板結構200包括一基材202及一第 一埋入式線路層206。基材202具有一第一表面208且包 括一第一絕緣層204及一金屬層214,例如是銅層。第一 絕緣層204,例如是介電層,形成於第一表面208上並與 金屬層214接觸。第一絕緣層204具有一第一溝槽圖案 210,第一埋入式線路層206形成於第一溝槽圖案210。 本實施例之第一溝槽圖案210係以電漿蝕刻方式製 作,請參照第3圖,其繪示第2圖中第一溝槽圖案之局 φ 部A之放大示意圖。為了清楚說明以電漿蝕刻製作第一 溝槽圖案之特色,於第3圖中省略第2圖之第一埋入式 線路層206。由於電漿加工方向不只有Z軸方向,也往Z 軸之兩邊方向D1及D2對第一絕緣層204進行蝕刻,所 以第一溝槽圖案210之槽側壁218的斜度會比較緩和。 並且,也可使第一溝槽圖案210之槽底面212形成平面, 如此,使得第一溝槽圖案210之戴面形狀可以是梯形, 甚至接近矩形。相較於第1圖之習知的溝槽108,本實施 φ 例之第一溝槽圖案210的溝槽表面積較大,有助於後續 形成的第一埋入式線路層206的電性品質。 此外,第一溝槽圖案210於第一絕緣層204之上表 面218露出一第一槽開口 220。在適當地控制電漿製程參 數下,第一溝槽圖案210之槽底面212之寬度W1小於或 實質上等於第一槽開口 220之寬度W2,本實施例之寬度 W1係以寬度W2的三分之一為例作說明。因此,相較於第 1圖習知之溝槽108,本實施例使用電漿製作出的第一溝 槽圖案210具有更大的溝槽表面積,且第一溝槽圖案210 5 201032274TW5145PA face. Thus, the area of the bottom surface of the trench is increased, so that the subsequently formed buried wiring layer has a relatively large electrical connection surface, which enhances the electrical properties of the buried wiring layer. According to the present invention, a substrate structure is proposed comprising a substrate and a first buried wiring layer. The substrate includes a first insulating layer. The first insulating layer has a first trench pattern, and a groove bottom surface of the first trench pattern is a flat surface. The first buried wiring layer is formed in the first trench pattern. According to the present invention, a method of fabricating a substrate structure is proposed. The manufacturing method includes the following steps. A substrate is provided, the substrate comprising a first insulating layer. A first photomask is provided. A plasma is provided, and a first trench pattern is etched through the first mask on the first insulating layer, and a bottom surface of the first trench pattern is planar. A first buried wiring layer is formed on the first trench pattern. In the following, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings, in which: FIG. The trench of the buried circuit is formed by plasma etching, so that the bottom surface of the groove is formed into a plane. Thus, the area of the bottom surface of the trench is increased, so that the subsequently formed buried wiring layer has a relatively large electrical connection surface, which improves the electrical quality of the buried wiring layer. The following description is made with two preferred embodiments. First Embodiment Referring to Figure 2, there is shown a schematic view of a base plate structure in accordance with a first embodiment of the present invention. The substrate structure 200 includes a substrate 202 and a first buried wiring layer 206. The substrate 202 has a first surface 208 and includes a first insulating layer 204 and a metal layer 214, such as a copper layer. A first insulating layer 204, such as a dielectric layer, is formed on the first surface 208 and in contact with the metal layer 214. The first insulating layer 204 has a first trench pattern 210, and the first buried wiring layer 206 is formed in the first trench pattern 210. The first trench pattern 210 of the present embodiment is formed by plasma etching. Referring to FIG. 3, an enlarged schematic view of the portion φ of the first trench pattern in FIG. 2 is shown. In order to clarify the feature of the first trench pattern by plasma etching, the first buried wiring layer 206 of Fig. 2 is omitted in Fig. 3. Since the plasma processing direction is not only the Z-axis direction, but also the first insulating layer 204 is etched in the two directions D1 and D2 of the Z-axis, the slope of the groove side wall 218 of the first trench pattern 210 is relatively moderate. Moreover, the groove bottom surface 212 of the first groove pattern 210 may be formed into a plane, such that the wearing shape of the first groove pattern 210 may be trapezoidal or even rectangular. Compared with the conventional trench 108 of FIG. 1, the first trench pattern 210 of the present embodiment has a larger trench surface area, which contributes to the electrical quality of the subsequently formed first buried wiring layer 206. . In addition, the first trench pattern 210 exposes a first trench opening 220 in the upper surface 218 of the first insulating layer 204. Under the proper control of the plasma process parameters, the width W1 of the groove bottom surface 212 of the first groove pattern 210 is less than or substantially equal to the width W2 of the first groove opening 220, and the width W1 of the embodiment is three points of the width W2. One is an example. Therefore, the first trench pattern 210 fabricated using the plasma in this embodiment has a larger trench surface area than the trench 108 conventionally illustrated in FIG. 1, and the first trench pattern 210 5 201032274

TW5145PA 之槽側壁218的斜度也較缓和。如此,第一溝槽圖案210 使後續形成的第一埋入式線路層206具有較佳的電性品 質。在實務上,寬度W1與寬度W2之尺寸比例可視對電 性品質之要求、製程成本及製程時間而定,本實施例並 非用以限定寬度W1與寬度W2的比例。 此外,雖然本實施例之第一溝槽圖案210未貫穿第 一絕緣層,然而另一實施例之第一溝槽圖案也可以貫穿 第一絕緣層204。請參照第4圖,其繪示另一實施態樣之 第一溝槽圖案的示意圖。第一絕緣層204之一第一溝槽 圖案224的一部分226貫穿第一絕緣層204並露出第一 表面208之一部份228,且於第一絕緣層204之上表面 216露出一第二槽開口 230。如此,金屬層214可以藉由 第一溝槽圖案224之此部分226與其它階層的電路進行 電性連接。 由於電漿蝕刻方向是多方向,雖然電漿在碰到金屬 層214時無法對金屬層214蝕刻,但還是會往Z轴兩邊 繼續蝕刻第一絕緣層204,使得第一表面208之一部份 228的寬度愈來愈寬。所以,第一表面208之一部份228 的寬度W3可接近或等於第二槽開口 230之寬度W4,此有 助提升後續形成的第一埋入式線路層的電性品質。 以下係以第5圖並搭配第6A至6C圖,詳細說明依 照本發明第一實施例之基板結構的製造方法。請參照第5 圖,其繪示依照本發明第一實施例之基板結構之製造方 法流程圖,製造方法包括以下步驟。 首先,請同時參照第6A圖,其繪示第一實施例之基 201032274 板結構之基材示意圖。於步驟S502中,提供基材202, 基材202具有第一表面208且包括第一絕緣層204及金 屬層214。 接著,請同時參照第6B圖,其繪示第6A圖中提供 有第一光罩之示意圖。於步驟S504中,提供一第一光罩 222,第一光罩222具有一摟空圖案234。 再來,請同時參照第6C圖,其繪示第6B圖中提供 有電漿之示意圖。於步驟S506中,提供一電漿P,透過 0 第一光罩222之摟空圖案234,而於第一絕緣層204上蝕 刻出第一溝槽圖案210。完成本步驟的作業環境係在一電 聚室(未緣示)内。 此外,於本步驟S506之後,尚須清除(desmear) 附著於第一溝槽圖案210上之雜質,以利接下來的步驟 S508中的形成第一埋入式線路層206。而清除方式例如 是採用電漿設備,以乾蝕刻方式完成。因此,可於本步 驟S506之後,移除第一光罩222,然後在相同的電漿設 ❿ 備内,使用電漿清除附著於第一溝槽圖案210上之雜質。 更進一步地說,在習知的雷射方式中,於溝槽製作完成 後,須費時、費力地移動基材至一可執行清除動作的電 漿設備或其它溼製程設備,此已經影響到整個製程的流 暢性。反觀本實施例,在不需變更設備且不需移動基材 202的情況下,可於移除第一光罩222後,直接以原電漿 設備執行清除動作,使整個製程在操作上變得相當流 暢、便利及省時。 此外,於步驟S506中,若蝕刻出的第一溝槽圖案 7 201032274The slope of the groove side wall 218 of the TW5145PA is also moderate. As such, the first trench pattern 210 allows the subsequently formed first buried wiring layer 206 to have a better electrical quality. In practice, the ratio of the width W1 to the width W2 may depend on the requirements of the electrical quality, the process cost, and the process time. This embodiment is not intended to limit the ratio of the width W1 to the width W2. In addition, although the first trench pattern 210 of the present embodiment does not penetrate the first insulating layer, the first trench pattern of another embodiment may penetrate the first insulating layer 204. Referring to Figure 4, a schematic diagram of a first trench pattern of another embodiment is shown. A portion 226 of the first trench pattern 224 of the first insulating layer 204 penetrates the first insulating layer 204 and exposes a portion 228 of the first surface 208, and a second trench is exposed on the upper surface 216 of the first insulating layer 204. Opening 230. As such, the metal layer 214 can be electrically connected to other levels of circuitry by the portion 226 of the first trench pattern 224. Since the plasma etching direction is multi-directional, although the plasma cannot etch the metal layer 214 when it hits the metal layer 214, the first insulating layer 204 is further etched on both sides of the Z-axis, so that one part of the first surface 208 The width of 228 is getting wider and wider. Therefore, the width W3 of a portion 228 of the first surface 208 can be close to or equal to the width W4 of the second slot opening 230, which helps to enhance the electrical quality of the subsequently formed first buried wiring layer. The manufacturing method of the substrate structure according to the first embodiment of the present invention will be described in detail below with reference to Fig. 5 and Figs. 6A to 6C. Referring to Figure 5, there is shown a flow chart of a method of fabricating a substrate structure in accordance with a first embodiment of the present invention, the method of manufacture comprising the following steps. First, please refer to FIG. 6A at the same time, which shows a schematic diagram of the substrate of the base structure of the first embodiment 201032274. In step S502, a substrate 202 is provided. The substrate 202 has a first surface 208 and includes a first insulating layer 204 and a metal layer 214. Next, please refer to FIG. 6B at the same time, which shows a schematic diagram of the first photomask provided in FIG. 6A. In step S504, a first mask 222 is provided, and the first mask 222 has a hollow pattern 234. Next, please refer to Fig. 6C at the same time, which shows a schematic diagram of the plasma provided in Fig. 6B. In step S506, a plasma P is provided to pass through the hollow pattern 234 of the first mask 222, and the first trench pattern 210 is etched on the first insulating layer 204. The working environment in which this step is completed is in a polymerization chamber (not shown). In addition, after the step S506, the impurities attached to the first trench pattern 210 must be removed (desmear) to facilitate the formation of the first buried wiring layer 206 in the next step S508. The cleaning method is, for example, a plasma device, which is completed by dry etching. Therefore, after the step S506, the first mask 222 can be removed, and then the plasma attached to the first trench pattern 210 can be removed by using plasma in the same plasma device. Furthermore, in the conventional laser mode, after the groove is completed, it takes time and labor to move the substrate to a plasma device or other wet process device capable of performing a cleaning action, which has affected the whole process. The fluency of the process. In contrast, in this embodiment, after the first mask 222 is removed, the cleaning operation can be directly performed by the original plasma device without changing the device and without moving the substrate 202, so that the entire process becomes equivalent in operation. Smooth, convenient and time saving. In addition, in step S506, if the first trench pattern is etched 7 201032274

1 WM4DFA 210包含了 一如第4圖之貫穿部位,即第一溝槽圖案224 之一部分226,則清除對象當然地也包含了此貫穿部位。 然後,於步驟S508中,形成第一埋入式線路層206 於第一溝槽圖案210上。形成第一埋入式線路層206的 方式例如是採用無電鍍(electroless plating)方式或 化學沉積方式。至此,完成如第2圖所示之基板結構200。 此外,另一實施例之製造方法也可以製造出如第4 圖之第一溝槽圖案224。舉例來說,請參照第7圖並同時 參照第8A圖,第7圖繪示另一實施例之製造方法流程 圖,第8A圖繪示第7圖之製造方法中第二光罩之示意 圖。步驟S502、S504、S506及S508於第5圖已說明過, 在此便不再贅述,此處從步驟S702開始說明。如第8A 圖所示,於步驟S702,提供一第二光罩232。第二光罩 232具有一摟空圖案238。 然後,請同時參照第8B圖,其繪示第8A圖中提供 有電漿之示意圖。於步驟S704,提供電漿P,透過第二 光罩232的之摟空圖案238,於第一絕緣層204上蝕刻出 一貫穿第一絕緣層204之貫穿部,貫穿部係成為第一溝 槽圖案224之一部分226。至此,完成如第4圖所示之第 一溝槽圖案224。 此外,一般來講,在製造過程中,基材202因受到 製程環境的作用力,例如是壓力、溫度或腐蝕對基材202 所產生的力量而產生變形。在另一實施態樣的製造方法 中,可使用多個第一光罩來配合基材202之變形後尺寸。 舉例來說,請參照第9圖,其繪示本實施例之基材的變 201032274 形示意圖。基材202’是基材202變形後之外觀,其上的 線路尺寸,例如是金屬層214上的線路圖案之尺寸(未 繪示)隨著基材202’之變形而被拉伸或縮短,而與原本 尺寸產生偏差。而本實施例可設計多個第一光罩,例如 是第一光罩236a、236b及236c分別對應至基材202,中 不同變形比例的多個部份’例如是分別對應至基材2〇2, 的第一部份202a’ 、第二部份202b,及第三部份 202c 。此些第一光罩236a、236b及236c的尺寸係配 _ 合基材202’的變形比例設計’以使後續形成的第一溝槽 圖案精確地對應至變形後的基材202’ 。 以下係以第一光罩236a與基材202’之第一部分 202a’的對應關係為例作說明。請同時參照第1〇圖,其 繪示第9圖之基材的第一部分變形示意圖。基材202’的 第一部份202a’在變形前是區域202a的部份。變形後之 基材202’的第一部份202a’的邊長L4在變形前是邊長 L2,所以變形比例是L4/L2 ;而邊長L3在變形前是邊長 ❹ L1,所以變形比例是L3/L1。而本實施態樣之第一光罩 236a可配合基材202’之第一部份202a’的變形比例設 計。也就是說,第一光罩236a上的摟空圖案(第一光罩 236a之摟空圖案未繪示)可配合上述變形比例L4/L2及 L3/L1作對應調整,使第一光罩236a上之摟空圖案的尺 寸與變形後之基材202’之第一部份202a’的尺寸實質 上相同,以確保後續形成之第一溝槽圖案能夠精確地對 應至變形後的基材202’ 。 9 2010322741 WM4DFA 210 includes a through portion of Fig. 4, i.e., a portion 226 of the first trench pattern 224, and the clearing object of course also includes the through portion. Then, in step S508, the first buried wiring layer 206 is formed on the first trench pattern 210. The manner in which the first buried wiring layer 206 is formed is, for example, an electroless plating method or a chemical deposition method. So far, the substrate structure 200 as shown in FIG. 2 is completed. Further, the manufacturing method of another embodiment can also produce the first trench pattern 224 as shown in FIG. For example, refer to FIG. 7 and refer to FIG. 8A. FIG. 7 is a flow chart showing a manufacturing method of another embodiment, and FIG. 8A is a schematic view showing a second photomask in the manufacturing method of FIG. 7. Steps S502, S504, S506, and S508 have been described in FIG. 5, and will not be described again here. Here, description will be made from step S702. As shown in FIG. 8A, in step S702, a second mask 232 is provided. The second mask 232 has a hollow pattern 238. Then, please refer to Fig. 8B at the same time, which shows a schematic diagram of the plasma provided in Fig. 8A. In step S704, the plasma P is supplied through the hollow pattern 238 of the second mask 232, and a through portion penetrating through the first insulating layer 204 is etched on the first insulating layer 204, and the through portion becomes the first trench. One portion 226 of pattern 224. Thus, the first groove pattern 224 as shown in Fig. 4 is completed. Moreover, in general, during the manufacturing process, the substrate 202 is deformed by the force of the process environment, such as pressure, temperature, or the forces generated by the substrate 202. In another embodiment of the fabrication method, a plurality of first reticles can be used to match the deformed dimensions of the substrate 202. For example, please refer to FIG. 9 , which shows a schematic diagram of the change of the substrate of the present embodiment 201032274. The substrate 202' is the appearance of the deformed substrate 202, and the line size thereon, for example, the size of the line pattern on the metal layer 214 (not shown) is stretched or shortened as the substrate 202' is deformed. There is a deviation from the original size. In this embodiment, a plurality of first masks can be designed. For example, the first masks 236a, 236b, and 236c respectively correspond to the substrate 202, and the plurality of portions of different deformation ratios are respectively corresponding to the substrate 2, respectively. 2, a first portion 202a', a second portion 202b, and a third portion 202c. The dimensions of the first reticles 236a, 236b, and 236c are designed to match the deformation ratio of the substrate 202' so that the subsequently formed first groove pattern accurately corresponds to the deformed substrate 202'. Hereinafter, the correspondence relationship between the first mask 236a and the first portion 202a' of the substrate 202' will be described as an example. Please also refer to the first drawing, which shows a schematic view of the deformation of the first part of the substrate of Fig. 9. The first portion 202a' of the substrate 202' is part of the region 202a prior to deformation. The side length L4 of the first portion 202a' of the deformed substrate 202' is the side length L2 before the deformation, so the deformation ratio is L4/L2; and the side length L3 is the side length ❹ L1 before the deformation, so the deformation ratio It is L3/L1. The first mask 236a of the present embodiment can be designed to match the deformation ratio of the first portion 202a' of the substrate 202'. That is, the hollow pattern on the first mask 236a (the hollow pattern of the first mask 236a is not shown) can be adjusted correspondingly to the deformation ratios L4/L2 and L3/L1, so that the first mask 236a The size of the upper hollow pattern is substantially the same as the size of the deformed first portion 202a' of the substrate 202' to ensure that the subsequently formed first groove pattern can accurately correspond to the deformed substrate 202'. . 9 201032274

i WM4^PA 第二實施例 請參照第i1圖’其繪示依照本發明第二實施例之基 板結構之示意圖。第二實施例與弟一實施例不同之處在 於,第二實施例之基板結構300之相對兩面皆具有溝槽 圖案。其它相同之處沿用相同標號’在此並不再贅述。 以下係詳細說明第二實施例之基板結構300之特徵。 基板結構300之基材302更包括一金屬層308,例 如是銅層及一第二絕緣層304。第二絕緣層304係形成於 基材302之第二表面306上且第二絕緣層304具有一第 二溝槽圖案322,而第二表面306係相對於第一表面2〇8。 相似於第一溝槽圖案224 ’第二溝槽圖案322具有 一貫穿第二絕緣層304之孔320。此外,第二溝槽圖案 322之槽底面310亦為平面。並且’第二溝槽圖案322於 第二絕緣廣304之上表面312露出一第三槽開口 314,第 二溝槽圖案322之槽底面310之寬度W6係小於或實質上 等於第三槽開口 314之寬度W5,本實施例之寬度W6係以 寬度W5的三分之一為例作說明。 此外,本實施例之基板結構300的兩面都具有電路 結構,而熟知此技術領域者應當了解,金屬層214與308 之間可透過一貫孔(via)(未繪示)進行電性導通。如 此,基板結構300兩面的電路結構可透過此貫孔、基板 結構300之第一溝槽圖案224之一部分226及第二溝槽 圖案322之孔320來電性連接。 此外,雖然本實施例之基板結構300之雙面上的結 構層數係以單層為例作說明,然熟知此技術領域者應當 了解,本實施例之基板結構300也可製作成雙面多層結 構。 當然,雖然第11圖之第二溝槽圖案322上未形成一 埋入式線路層。然而,此技術領域中具有通常知識者應 明暸,一第二埋入式線路層(未繪示)也可形成於第二 溝槽圖案322上。 以下係以第12圖並搭配第13A〜13B圖,詳細介紹 第11圖之基板結構300的製造方法。請參照第12圖, φ 其繪示依照本發明第二實施例之基板結構之製造方法流 程圖。步驟S502、S504及S508於第一實施例之製造方 法中皆已說明過,在此便不再贅述。以下係由步驟S802 開始說明。 請同時參照第13A圖,其繪示第12圖中之第三光罩 之示意圖。於步驟S802中,提供一第三光罩316,第三 光罩316具有一摟空圖案318。第一光罩222係鄰近第一 絕緣層204設置,而第二光罩232係鄰近第二絕緣層304 φ 設置。 然後,請同時參照第13B圖,其繪示第13A圖中提 供有電漿之示意圖。於步驟S802中,電漿P同時透過第 一光罩222的摟空圖案234及第三光罩314的摟空圖案 318,分別於第一絕緣層204及第二絕緣層304上蝕刻出 第一溝槽圖案210及第二溝槽圖案322。 至於孔320的形成方式係相似於第一溝槽圖案224 之一部分226的形成方式,此於上述第7圖中已說明, 在此便不再贅述。 11 201032274i WM4^PA Second Embodiment Referring to Figure i1, a schematic view of a substrate structure in accordance with a second embodiment of the present invention is shown. The second embodiment differs from the first embodiment in that the opposite sides of the substrate structure 300 of the second embodiment have a groove pattern. Other similarities are denoted by the same reference numerals and will not be described again. The features of the substrate structure 300 of the second embodiment will be described in detail below. The substrate 302 of the substrate structure 300 further includes a metal layer 308, such as a copper layer and a second insulating layer 304. The second insulating layer 304 is formed on the second surface 306 of the substrate 302 and the second insulating layer 304 has a second trench pattern 322, and the second surface 306 is opposite to the first surface 2〇8. The second trench pattern 322 is similar to the first trench pattern 224' having a hole 320 penetrating through the second insulating layer 304. In addition, the groove bottom surface 310 of the second groove pattern 322 is also planar. And the second trench pattern 322 exposes a third slot opening 314 on the upper surface 312 of the second insulating strip 304. The width W6 of the slot bottom surface 310 of the second trench pattern 322 is less than or substantially equal to the third slot opening 314. The width W5, the width W6 of the present embodiment is described by taking one third of the width W5 as an example. In addition, the substrate structure 300 of the present embodiment has a circuit structure on both sides, and those skilled in the art should understand that the metal layers 214 and 308 can be electrically connected through a common via (not shown). Thus, the circuit structure on both sides of the substrate structure 300 can be electrically connected through the through hole, the portion 226 of the first trench pattern 224 of the substrate structure 300, and the hole 320 of the second trench pattern 322. In addition, although the number of structural layers on both sides of the substrate structure 300 of the present embodiment is described by taking a single layer as an example, those skilled in the art should understand that the substrate structure 300 of the present embodiment can also be fabricated into a double-sided multilayer. structure. Of course, although a buried wiring layer is not formed on the second trench pattern 322 of Fig. 11. However, it will be apparent to those skilled in the art that a second buried wiring layer (not shown) may also be formed on the second trench pattern 322. Hereinafter, a method of manufacturing the substrate structure 300 of Fig. 11 will be described in detail with reference to Fig. 12 in conjunction with Figs. 13A to 13B. Referring to Fig. 12, φ is a flow chart showing a method of manufacturing a substrate structure in accordance with a second embodiment of the present invention. Steps S502, S504, and S508 have been described in the manufacturing method of the first embodiment, and will not be described again. The following is explained starting from step S802. Please also refer to Fig. 13A, which shows a schematic view of the third photomask in Fig. 12. In step S802, a third mask 316 is provided, and the third mask 316 has a hollow pattern 318. The first mask 222 is disposed adjacent to the first insulating layer 204, and the second mask 232 is disposed adjacent to the second insulating layer 304φ. Then, please refer to Fig. 13B at the same time, which shows a schematic diagram of providing plasma in Fig. 13A. In step S802, the plasma P is simultaneously etched through the hollow pattern 234 of the first mask 222 and the hollow pattern 318 of the third mask 314, and is first etched on the first insulating layer 204 and the second insulating layer 304, respectively. The groove pattern 210 and the second groove pattern 322. The manner in which the holes 320 are formed is similar to the manner in which the portion 226 of the first groove pattern 224 is formed, which has been described in the above-mentioned FIG. 7, and will not be described again. 11 201032274

1 W5145PA 然後,於步驟S508完成後,完成第11圖之基板結 構 300。 當然,此技術領域中具有通常知識者應明瞭,於步 驟S508後,也可以形成第二埋入式線路層(未繪示)於 第二溝槽圖案上322上。 由於電漿係分佈於整個電漿室内,應用此一特色, 本實施例之第一溝槽圖案210與第二溝槽圖案322可同 時形成,相當地省時。 本發明上述實施例所揭露之基板結構及其製造方 法,至少具有如下優點: (1) .採用電漿蝕刻所製作出的溝槽圖案,其槽底面 寬度可實質上等於其槽開口的寬度。如此,溝槽的表面 積增加,有助於後續形成的埋入式線路層之電性品質。 (2) .在不需變更設備且不需移動基材的情況下,可 於移除光罩後,直接以原電漿設備執行清除(desmear) 動作,相當便利且省時。 (3) .形成溝槽圖案的光罩可以設計成多個,分別對 應變形後的基材中不同變形比例的多個部份,以使後續 形成的溝槽圖案精確對應至變形後的基材。 綜上所述,雖然本發明已以較佳實施例揭露如上, 然其並非用以限定本發明。本發明所屬技術領域中具有 通常知識者,在不脫離本發明之精神和範圍内,當可作 各種之更動與潤飾。因此,本發明之保護範圍當視後附 之申請專利範圍所界定者為準。 12 201032274 L ΎΎ l ~r^/l i~%. 【圖式簡單說明】 第1圖繪示習知具有埋入式線路之基板結構示意 圖。 第2圖繪示依照本發明第一實施例之基板結構之示 意圖。 第3圖繪示第2圖中第一溝槽圖案之局部A之放大 示意圖。 . 第4圖繪示另一實施態樣之第一溝槽圖案的示意 φ 圖。 第5圖繪示依照本發明第一實施例之基板結構之製 造方法流程圖。 第6A圖繪示第一實施例之基板結構之基材示意圖。 第6B圖繪示第6A圖中提供有第一光罩之示意圖。 第6C圖繪示第6B圖中提供有電漿之示意圖。 第7圖繪示另一實施例之製造方法流程圖。 第8A圖繪示第7圖之製造方法中第二光罩之示意 圖。 第8B圖繪示第8A圖中提供有電漿之示意圖。 第9圖繪示本實施例之基材的變形示意圖。 第10圖繪示第9圖之基材的第一部分變形示意圖。 第11圖繪示依照本發明第二實施例之基板結構之 示意圖。 第12圖繪示依照本發明第二實施例之基板結構之 製造方法流程圖。 第13A圖繪示第12圖中之第三光罩之示意圖。 13 2010322741 W5145PA Then, after completion of step S508, the substrate structure 300 of Fig. 11 is completed. Of course, it should be understood by those skilled in the art that after the step S508, a second buried wiring layer (not shown) may be formed on the second trench pattern 322. Since the plasma system is distributed throughout the plasma chamber, the first trench pattern 210 and the second trench pattern 322 of the embodiment can be formed at the same time, which is quite time-saving. The substrate structure and the manufacturing method thereof disclosed in the above embodiments of the present invention have at least the following advantages: (1) A trench pattern formed by plasma etching has a groove bottom surface width substantially equal to a width of a groove opening thereof. Thus, the surface area of the trench is increased to contribute to the electrical quality of the subsequently formed buried wiring layer. (2) It is convenient and time-saving to perform the desmear operation directly on the original plasma equipment without removing the equipment and without moving the substrate. (3) The reticle forming the groove pattern may be designed in plurality to correspond to portions of different deformation ratios in the deformed substrate, so that the subsequently formed groove pattern accurately corresponds to the deformed substrate . In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. 12 201032274 L ΎΎ l ~r^/l i~%. [Simple description of the drawing] Fig. 1 is a schematic view showing the structure of a substrate having a buried line. Fig. 2 is a view showing the structure of a substrate in accordance with a first embodiment of the present invention. Fig. 3 is an enlarged schematic view showing a portion A of the first groove pattern in Fig. 2. Figure 4 is a schematic φ diagram of a first trench pattern of another embodiment. Fig. 5 is a flow chart showing a method of manufacturing a substrate structure in accordance with a first embodiment of the present invention. FIG. 6A is a schematic view showing the substrate of the substrate structure of the first embodiment. FIG. 6B is a schematic view showing the first photomask provided in FIG. 6A. Figure 6C is a schematic view showing the plasma provided in Figure 6B. FIG. 7 is a flow chart showing a manufacturing method of another embodiment. Fig. 8A is a schematic view showing a second photomask in the manufacturing method of Fig. 7. FIG. 8B is a schematic view showing the plasma provided in FIG. 8A. FIG. 9 is a schematic view showing the deformation of the substrate of the embodiment. Figure 10 is a schematic view showing the deformation of the first portion of the substrate of Figure 9. Figure 11 is a schematic view showing the structure of a substrate in accordance with a second embodiment of the present invention. Figure 12 is a flow chart showing a method of manufacturing a substrate structure in accordance with a second embodiment of the present invention. FIG. 13A is a schematic view showing the third photomask in FIG. 12. 13 201032274

TW5145PA 第13B圖繪示第13A圖中提供有電漿之示意圖。 【主要元件符號說明】 100、200、300 :基板結構 102、202 :基材 104 :絕緣層 106 :埋入式線路層 108 :溝槽 110、212、310 :槽底面 _ 202’ :變形後之基材 202a :區域 202a’ :第一部份 202b’ :第二部份 202c’ :第三部份 204 :第一絕緣層 206 :第一埋入式線路層 208 :第一表面 ⑩ 210、224 :第一溝槽圖案 214、308 :金屬層 216 :第一絕緣層之上表面 218 :第一溝槽圖案之槽側壁 220 :第一槽開口 222、236、236a、236b、236c :第一光罩 226 :第一溝槽圖案之一部分 228 :第一表面之一部份 14 201032274 230 :第二槽開口 232 :第二光罩 234、238、318 :摟空圖案 304 :第二絕緣層 306 :第二表面 322 :第二溝槽圖案 312 :第二絕緣層之上表面 314 :第三槽開口 •320 :孔TW5145PA Figure 13B shows a schematic diagram of the plasma provided in Figure 13A. [Description of main component symbols] 100, 200, 300: substrate structure 102, 202: substrate 104: insulating layer 106: buried wiring layer 108: trenches 110, 212, 310: groove bottom surface _ 202': after deformation Substrate 202a: region 202a': first portion 202b': second portion 202c': third portion 204: first insulating layer 206: first buried wiring layer 208: first surface 10 210, 224 : first trench pattern 214, 308: metal layer 216: first insulating layer upper surface 218: first trench pattern groove sidewall 220: first slot opening 222, 236, 236a, 236b, 236c: first light Cover 226: one portion of the first groove pattern 228: one portion of the first surface 14 201032274 230: second slot opening 232: second mask 234, 238, 318: hollow pattern 304: second insulating layer 306: Second surface 322: second trench pattern 312: second insulating layer upper surface 314: third slot opening • 320: hole

Dl、D2 :方向 LI、L2、L3、L4 :邊長 P :電漿 W卜 W2、W3、W4、W5、W6 :寬度 Z :轴向Dl, D2: direction LI, L2, L3, L4: side length P: plasma W b W2, W3, W4, W5, W6: width Z: axial

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Claims (1)

201032274 TW5145PA 七、申請專利範圍: I 一種基板結構之製造方法,包括: 提供—基材,該基材包括一第一絕緣層; 提供一第一光罩; 提供一電漿,透過該第一光罩於該第一絕緣層上蝕 刻出一第一溝槽圖案,該第一溝槽圖案之一槽底面為平 面;以及 形成一第一埋入式線路層於該第一溝槽圖案上。 2.如申請專利範圍第1項所述之製造方法,其中該 第一溝槽圖案於該第一絕緣層之上表面露出一第一槽開 口,該第一溝槽圖案之該槽底面之寬度係小於或實質上 等於該第一槽開口之寬度。 3·如申請專利範圍第丨項所述之製造方法,其中該 基材具有一第一表面,該第一絕緣層形成於該第一表面 上,於該蝕刻步驟中,該製造方法更包括: 提供一第二光罩;以及 提供該電漿,透過該第二光罩於該第一絕緣層上蝕 刻出一貫穿該第一絕緣層之貫穿部,該貫穿部為該第一 溝槽圖案之一部分,該貫穿部係露出該第一表面之—部 分且於該第一絕緣層之上表面露出一第二槽開口,該第 一表面之該部份的寬度係小於或實質上等於該第二槽開 口之寬度。 4.如申請專利範圍第1項所述之製造方法,其中於 蝕刻出該第一溝槽圖案之該步驟與形成該第一埋入式線 路層之該步驟之間,該製造方法更包括: 201032274 移除該第一光罩;以及 提供該電漿,清除(desmear)附著於該第一溝槽圖 案上之雜質。 5. 如申請專利範圍第1項所述之製造方法,其中該 基材具有相對之一第一表面與一第二表面,該第一絕緣 層形成於該第一表面上,而該第二絕緣層形成於該第二 表面上,該製造方法更包括: 提供一第三光罩; φ 於提供該電漿之該步驟中,該製造方法更包括: 該電漿同時透過該第三光罩於該第二絕緣層上蝕刻 出一第二溝槽圖案,該第二溝槽圖案之一槽底面為平 面;以及 該製造方法更包括·· 形成一第二埋入式線路層於該第二溝槽圖案上。 6. 如申請專利範圍第1項所述之製造方法,其中於 該提供該第一光罩之該步驟中,該製造方法包括: ❹ 提供複數個第一光罩,該些第一光罩之其中一者的 尺寸係對應於該基材之一部分變形後的尺寸。 7. —種基板結構,包括: 一基材,包括一第一絕緣層,該第一絕緣層具有一 第一溝槽圖案,該第一溝槽圖案之一槽底面為平面;以 及 一第一埋入式線路(embedded pattern)層,形成 於該第一溝槽圖案。 8. 如申請專利範圍第7項所述之基板結構,其中該 17 201032274 TW5145FA =圖=一絕緣層之上表面露出-第-槽開 等於該第一槽咖面之寬度係小於或實質上 基材1有項所j"之基板結構,其中該 上,該第一溝槽圖荦之'第一絕緣層形成於該第-表面 該第-表^ 貫⑽第―絕緣層並露出 參 第第i緣層之上表面露出一 ” σ ’該第-表面之該部份的寬度係 上等於該第二槽開口之寬度。 乂實質 1〇.如申請專利範圍第7項所述之基板結構,其中 =材具有相對之_第—表面與—第二表面及一第二絕 ,θ ’該第一絕緣層形成於該第一表面上,該第二絕緣 層形成於該第二表面上,該第二絕緣層具有一第二溝槽 ,該第一溝槽圖案之一槽底面為平面,該基板結構 更包括: 第一埋入式線路層,形成於該第二溝槽圖案。 響 =j1·如申請專利範圍第10項所述之基板結構,其中 該第二溝_案於該第二絕緣層之上表面露出—第三槽 開口’該第二溝槽圖案之該槽底面之寬度係小於或 上等於該第三槽開口之寬度。 、 18201032274 TW5145PA VII. Patent Application Range: I A method for manufacturing a substrate structure, comprising: providing a substrate, the substrate comprising a first insulating layer; providing a first mask; providing a plasma through the first light A first trench pattern is etched on the first insulating layer, a bottom surface of the first trench pattern is planar; and a first buried wiring layer is formed on the first trench pattern. 2. The manufacturing method of claim 1, wherein the first trench pattern exposes a first slot opening on a surface of the first insulating layer, and a width of the bottom surface of the first trench pattern It is less than or substantially equal to the width of the first slot opening. 3. The manufacturing method of claim 2, wherein the substrate has a first surface, the first insulating layer is formed on the first surface, and in the etching step, the manufacturing method further comprises: Providing a second reticle; and providing the plasma, through the second reticle, etching a through portion of the first insulating layer through the first insulating layer, the through portion being the first trench pattern a portion of the through portion exposing a portion of the first surface and exposing a second slot opening on a surface of the first insulating layer, the portion of the first surface having a width less than or substantially equal to the second portion The width of the slot opening. 4. The manufacturing method of claim 1, wherein the step of etching the first trench pattern and the step of forming the first buried wiring layer further comprises: 201032274 removing the first reticle; and providing the plasma to desmear impurities attached to the first trench pattern. 5. The manufacturing method of claim 1, wherein the substrate has a first surface and a second surface, the first insulating layer is formed on the first surface, and the second insulating layer a layer is formed on the second surface, the manufacturing method further includes: providing a third mask; φ in the step of providing the plasma, the manufacturing method further comprises: the plasma simultaneously passing through the third mask a second trench pattern is etched on the second insulating layer, and a bottom surface of the second trench pattern is planar; and the manufacturing method further comprises: forming a second buried wiring layer in the second trench On the groove pattern. 6. The manufacturing method of claim 1, wherein in the step of providing the first reticle, the manufacturing method comprises: ❹ providing a plurality of first reticle, the first reticle One of the dimensions corresponds to the deformed size of a portion of the substrate. 7. A substrate structure comprising: a substrate comprising a first insulating layer, the first insulating layer having a first trench pattern, a groove bottom surface of the first trench pattern being a flat surface; and a first An embedded pattern layer is formed in the first trench pattern. 8. The substrate structure of claim 7, wherein the 17 201032274 TW5145FA = map = an upper surface of the insulating layer is exposed - the first groove is equal to the width of the first groove surface is less than or substantially The material 1 has a substrate structure of the j", wherein the first trench layer is formed on the first surface, the first surface is (10) the first insulating layer and the first insulating layer is exposed The surface of the upper surface of the i-edge layer is exposed to a "σ". The width of the portion of the first surface is equal to the width of the opening of the second groove. 乂 Substantially 1. The substrate structure as described in claim 7 is Wherein the material has a first surface and a second surface and a second surface, θ 'the first insulating layer is formed on the first surface, and the second insulating layer is formed on the second surface, The second insulating layer has a second trench, and the bottom surface of the first trench pattern is a flat surface. The substrate structure further includes: a first buried wiring layer formed on the second trench pattern. The substrate structure as described in claim 10, wherein the _ Groove pattern over the second insulating layer exposed on the surface - a third groove opening 'of the width of the groove bottom surface of the second channel pattern of lines is less than or equal to the width of the third opening of the groove 18.
TW98105510A 2009-02-20 2009-02-20 Substrate structure and manufacturing method thereof TWI394212B (en)

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