TWI305673B - Method for manufacturing bit line - Google Patents

Description

1305673 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) <Scope of the Invention> The present invention relates to a method of manufacturing a semiconductor, which is a method for forming an easily formed method, more specifically, a bit line. The semiconductor package of the line in the line of the line is in the background of the invention. The width of the device is high, and the circuit wiring is gradually reduced. In particular, it belongs to the bit 绐 capacitor storage node (storage n〇de) electrode and the user U f ^ = edge: = between the layers: edge layer evaporation process and automatic pair "is: engineering ΐ; utility Uargin), pair 1 _View level system =, its bit line width, is required to remain below 〇 1. Once, in order to form such a fine line bit line, it is currently difficult to use #二:: body device. 〇"V:= It is not productive. % 忭 忭 唯 唯 现状 ( : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : The bit line is formed sequentially: (Γ) and the insulating layer (1°4). At this time, the hard mask role α, the person-person at the time of forming the insulating layer (off = ”) 'Applying a photosensitive film on the insulating layer (104) (PR: a photoresist twit diagram, the semiconductor substrate (1 〇〇) has a transistor composed of a source/drain guide and a field ^= pole) Structure

1305673

i ' % % g 兀 h / ^ j v 厶 y PhotoRes i st ), formed by overlaying and imaging to form a covered bit line field photopattern (108). The pattern of the photosensitive film (1〇8) is patterned with a minimum of 0.14 // m in the case of a general exposure. Next, as shown in Figure 1(b), the photosensitive film pattern (1〇8) is used as the etch mask, and the one-time anisotropic dry etching process (112) is used to remove the insulation (104) from being sensitized. A portion of the mask pattern (1〇8) is covered by a mask (105). After removing the photosensitive film pattern (1〇8), as shown in Fig. 1(c), the etching is not a hard mask (1〇5) by the secondary anisotropic dry etching process (114). A portion of the conductive layer (102) is covered to form a bit line (1〇3). ^ That is, the bit line (103) is a portion of the conductive layer (102) remaining after the secondary anisotropic dry etching process (114), and is patterned into the same pattern as the photosensitive film pattern (1〇8). 〇. 14 private m degree of line. Figures 2(a) to (c) and 3 are plan and cross-sectional views, respectively, of a half device formed by conventional techniques. 5 In the highly integrated components of the conventional 0. 1 4 " m line, the line = narrower and the space is also reduced, but the conductive problem of the conductive layer formed by the bit line is conductive. The height of the layer is relatively high.

Further, regarding the bit line, in order to form an automatic alignment contact with the capacitor in the subsequent process, the insulating layer is formed in the bit line forming opening, thereby increasing the position and height, in order to increase The separation of the L-shield insulating layer is performed by the vapor deposition method. Thus, the relative space is reduced and the high-element line and the storage node electrode are required to have a hard mask 1305673. The invention (3) causes difficulty. In the case where the conventional method is used to fabricate the bit line of the lower line, the second (a) to (c) and the third gap (gap fi 11) in the vapor deposition process of the desired interlayer insulating layer are defective and damage is generated, thereby generating a subsequent process. The bridge is formed, or the problems such as the contact point cannot be ensured. <Overview of the Invention> Therefore, in order to solve the above description. In order to achieve the above object, the half of the bit line of the fine line width is characterized in that: the method is characterized by the first step included in the base layer and the insulating layer. ^ The second step of the first light army pattern a fourth step of the third step of the mask pattern, the fourth step; and removing a portion of the conductive layer after the fourth step, and forming a bit < preferred embodiment Detailed example. In the following, with reference to the accompanying drawings, the G. 1 narrower G. 1 is used to carry out the bit line insulation on the subsequent process towel, and the automatic alignment contact process, as shown, will result from the interlayer insulating layer. Filling or cutting the bit line to form a hard mask, the storage node electrode and the like to create a bridge contact edge effect, and can not be turned on automatically to the conventional technology in providing the conductor to the invention board according to the absolute step; Removing the step; except for the detailed description of the line, the above-mentioned questions can be easily placed on the semiconductor device to form the bit line on the edge layer to form the first light. The second step of the second light residue is six steps. > The problem of the present invention is to form a 0. Forming a bit line forming an exposed mask pattern reticle pattern pattern part insulation having the present invention 1 # m method. The fifth layer mask formed by the formation of the conductive field is formed by the wire. The specific implementation is 1305673. 5. The invention (4) The figure #4 (a) to U) is the semiconductor device bit line in the embodiment of the present invention. / Method of sectioning the semiconductor device in each process. In the method for forming a bit line of a semiconductor device according to an embodiment of the present invention, first, as shown in the figure, a conductive layer (202) for forming a bit line is sequentially formed on a semiconductor substrate on which a transistor (not shown) is formed. An insulating layer (204) for forming a hard mask. The material of the % conductive layer (2〇2) is made of tungsten (w) or tungsten germanium (WSi), and the material and insulating layer (2〇4) are made of an oxide film or a nitride film. X > * It is applied to the insulating layer (204) for a long time, and the first photosensitive film pattern (2〇8) in a given field is exposed and developed. f A photosensitive film pattern, 08) If the current general exposure device is used, the pattern is formed to the minimum width. Next, as shown in Fig. 4(b), an isotropic dry etching process (21〇): one part of the first photosensitive film pattern (208) is formed to have a width larger than the first δ film pattern (208). The width of the second photosensitive film pattern is narrow (2〇9). At this time, the isotropic dry etching process (21 Å) is carried out by supplying oxygen (〇2) to the source of the electric poly dry etching apparatus. At this time, the oxygen flow is ',, and two '0 sccm, and the flow rate is preferably 350 to 45 0 sccm. In addition, the power of the microwave at this time is about 4 〇 〇 w, but it is preferable to supply it below 2 〇 〇 〜 3 〇 〇 w. The dry etching apparatus has a pressure inside the device of 8 〇. 〇 133 kPa (6 〇 () 〜 lOOOOmT), and the formation process of the second photosensitive film pattern (2 〇 9) is to form the first photosensitive film pattern (208) Etching 3 〇〇〇A per minute at a rate of speed. Due to the implementation of the isotropic dry etching process (210), the minimum can be private

1305673 V. INSTRUCTIONS (5) The width of the m degree maps the first photosensitive film pattern (209). Thereafter, as shown in FIG. 4(c), the second photosensitive film pattern (209) is used as the mask. The second photosensitive film pattern of the uninsulated layer (204) is removed by the one-time anisotropic dry etching process (212). Form (209) part of the mask to form hard light (205). The hard mask (205) is a part of the insulating layer (204) left after a single anisotropic dry etching process (21 2), which plays the role of the later patterning. Secondly, the second photosensitive film pattern (2〇9) is removed, as shown in Fig. 4(d), the etching is not covered by the hard light (20 5 ) by the secondary anisotropic dry etching process (214). A portion of the conductive layer (2〇2) forms a bit line (2〇3). At this time, the line 70 (203) belongs to a portion of the conductive layer (2〇2) remaining after the secondary anisotropic dry etching process (214), and is patterned in the same shape as the second photosensitive web. The same as the second photosensitive film pattern (2 0 9 ). 1 # ^ line width. In the above case, the first-applied isotropic dry remnant of the dry jingli.1...strand of the bit line electric installation according to the embodiment of the present invention forms ο.1"two (::) two round (209) 'The semiconductor Λ 之 之 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用The condition of the process (21〇) is to treat the cathode (not shown), and as in the above case, the gas is mainly etched by the 02 gas. Page 8 1305673 V. Inventive Note (6) '--Engraved gas. At this time, the A gas used is maintained at 8 〇〇sccm/guaranta as described above, and the c f gas may be added at a flow rate of about 5 〇 s c c m depending on the obstacle condition. In this case, the flow rate of the material should be 35 G to 45 Gsccm. And ^ should ^_ 丨 ^ 22,) dry (four) device pressure adjustment in the 8 " ~ j above the conditions of the engraving process, you can (four) squareness # and tune the bit line line to the smallest line to 〇.丨# m. Further, the modifications of the technical idea of the present invention are not detached. The pseudo-tank type, as described above, the bit line method of the semiconductor device of the present invention can form a bit line of fine lines of 〇. When, = talk about the gap between the gaps. X, can also be transferred to the automatic alignment: edge marginal utility, which can ensure the reliability of components. In addition, the semiconductor device bit according to the present invention utilizes a general dry-mode device using microwaves, which is a bit line of the lower line width. Therefore, it is possible to save a new dry etching ίν - additional production costs can be developed to achieve a high degree of integration = device required

1305673 BRIEF DESCRIPTION OF THE DRAWINGS The first (a) to (c) diagrams are sectional views of a semiconductor device showing a conventional technique for forming a bit line. The second (a) to (c) figure is a plan view of a bit line formed by a conventional technique. Figure 3 is a cross-sectional view of a bit line formed by conventional techniques. 4(a) to 4(d) are cross-sectional views showing the semiconductor device in each process of the bit line forming method in the embodiment of the present invention. Fig. 5 is a cross-sectional view showing a bit line formed by the bit line forming method of the present invention in the embodiment of the present invention. <Component Name and Symbol Comparison Table> 200 Semiconductor Substrate 202 Conductive Layer 203 Bit Line 204 Insulation Layer 205 Hard Photomask 208 209 Photosensitive Film Pattern 210 Isotropic Dry Silver Engraved 2 1 2, 2 1 4: anisotropic dry etching process

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Claims (1)

1305673 VI. Patent Application Range 1. A method for forming a bit line for manufacturing a semiconductor device. A scoop step for forming a bit line on a substrate; and a second insulating layer for using a conductive layer and an insulating layer Forming a first step of exposing the first reticle pattern of the field; the third step of forming the second reticle pattern to form the second reticle pattern is not covered by the second reticle pattern a fourth step of the cover; a fifth step of removing the second reticle pattern of the insulating layer; and removing the portion of the conductive layer remaining after the fourth step to form a bit line The sixth step. 2. The method of claim 2, as described in the scope of the patent application, refers to the formation of a point on the insulating layer, and the first v is formed into the first optical single pattern. The engraving process is in the form of a method of the first item, wherein the third step is to etch the first mask image to form the first mask pattern. The method of claim 3, wherein the isotropic dryness is performed by a plasma dry etching apparatus using microwaves. The method of claim 3, wherein the isotropic dry etching is performed by supplying oxygen. A method of item 5 of the patent scope, wherein the isotropic dry money engraving is carried out by adding the cf4 gas gift in addition to the oxygen. Page 11 1305673 VI. Scope of Application for Patent Application 7. For the method of applying for patent scope θβ0,n 固弟b or 6, wherein the oxygen is supplied at a flow rate of 3 50 to 45 0 seem. 8. The method of claiming the patent range 0.001 δ η η β, wherein the helium gas is supplied at a flow rate of 80 s c c m . Six Ί 9. If the scope of application for patents is 4, the force is below 400 watts. The method of the fourth aspect, wherein the microwave method, wherein the microwave power is 10. The unit of the fourth application patent range is 200 to 300 watts. 11. If the application for patent scope 3 is engraved, it is the force of the pressure of the item 〇~133Pa, which is the equivalent of the square. 12. For example, the application range i & ° oxide film or nitride film. The method of the present invention, wherein the insulating layer is a method, wherein the conductive layer is 13. The first crane layer or the dream crane layer as claimed in the patent application. In the method of the first step, wherein the third step is etched at an etch rate of less than 3,000 A per minute.