TW201031180A - Display device and television system - Google Patents

Abstract

To provide a display device which perform self-detection and self-repair, with an appropriate timing. The display part 90 of a liquid crystal television 400 includes a source driver 10a a display panel 80 for displaying video images, on the basis of video signals supplied from a DVD apparatus 402 and the source driver 10a for driving the display panel 80, which has a comparison and determination circuit 50 and a switching circuit 60 for detecting and repairing defects of the source driver 10a. The comparison and determination circuit 50 and the switching circuit 60 detect and repair the defects of the source driver 10a in a cleaning period as maintenance period for the DVD apparatus 402.

Description

201031180 VI. Description of the Invention: [Technical Fields of the Invention] The present invention relates to a display of a driving circuit using a self-detection and self-repair in a DA (Digital/Analog) converter output circuit Device. [Prior Art] In recent years, in the semiconductor integrated circuit for liquid crystal driving, the number of terminals of the liquid crystal driving output terminal is increasing, and the multi-value voltage output from the output terminal is increased in accordance with the increase in the size and the definition of the liquid crystal panel. Constantly more graying. For example, in the current mainstream semiconductor integrated circuit for liquid crystal driving, there are a number of about 500 output terminals including a voltage capable of outputting 256 gray scales. Further, the development of a semiconductor integrated circuit for liquid crystal driving including one or more output terminals has been carried out. Further, along with the multi-coloring of the liquid crystal panel, development of a liquid crystal driving semiconductor integrated circuit capable of outputting a gray scale output voltage of 1024 gray scales was also carried out. Here, the configuration of the conventional liquid crystal driving semiconductor integrated circuit will be described below with reference to Fig. 43. Fig. 43 is a block diagram showing the configuration of a conventional liquid crystal driving half-conductor body circuit. The liquid crystal driving semiconductor integrated circuit 1〇1 shown in the figure can output 111 gray-scale output voltages from n liquid crystal driving signal output terminals. First, the configuration of the liquid crystal driving semiconductor integrated circuit 101 will be described. The liquid crystal driving semiconductor integrated circuit 101 includes a clock input terminal 102, a gray scale data input terminal 1〇3 including a plurality of signal input terminals, a LOAD signal input terminal 1〇4, and a reference power supply terminal. 143485.doc 201031180 VO terminal 105, VI terminal 106, V2 terminal 107, V3 terminal 108, V4 terminal 109. Further, the semiconductor integrated circuit for liquid crystal driving includes a liquid crystal driving signal output terminal 111-1~ (hereinafter, the liquid crystal driving flash output terminal is referred to as a ## output terminal. Further, the liquid crystal driving signal output terminal is used. When 111-1 to 111-n are collectively referred to, it is referred to as a signal output terminal 111). Further, the liquid crystal driving semiconductor integrated circuit 1〇1 includes a reference power supply correction circuit 121, an index shift register circuit 123, a latch circuit unit 124, a hold circuit 125, and a D/A converter (Digital Analog Converter: It is called a DAC) circuit 126, and an output buffer 127. Further, the index shift register circuit 123 includes n stages of shift register circuits 123-1 to 123-n. Further, the latch circuit portion 124 includes n latch circuits 124-1 to 124-n, and the hold circuit 125 includes n holding circuits 125_1 to 125-n. Further, the DAC circuit 126 includes n DAC circuits 126-1 to 126-n. Further, the output buffer 127 includes n output buffers 1271 to 127_n' and each of the output buffers includes an operational amplifier. Next, the operation of the liquid crystal driving semiconductor integrated circuit 1〇1 will be described. The index shift register circuit 123 sequentially selects from the first latch circuit 124-1 to the nth latch circuit 124-11 based on the clock input signal input from the clock input terminal 1〇2. . The latch circuit 124 selected by the index shift register circuit U3 stores the gray scale wheel data from the gray scale data input terminal 1〇3. Further, the gray scale output data corresponds to each of the latch circuits 124, in other words, corresponding to each of the signal output terminals lu, synchronized with the clock input signal. Therefore, each latch circuit is called ~(2)·n to store the grayscale 143485.doc 201031180 output data corresponding to the respective values of each signal output terminal (1). The gray scale output data stored in the latch circuits 124-1 to l24_n* is transmitted to the corresponding n holding circuits 125-1 to 125-n based on the data LOAD signal. Further, the hold circuit outputs the gray scale output data input from the latch circuits 124-1 to 124-n as digital data to the DAC circuits 126-1 to 126-n. Here, the DAC circuits 126-1 to 126-n select one of the m kinds of gray scale voltages based on the gray scale output data from the hold circuit 125 and output them to the output buffers 127-1 to 127-n. Further, the DAC circuit 126 can output 111 kinds of gray scale voltages based on the voltage input from the reference power supply terminal V0 terminals 105 to V4 terminals 1 and 9. Then, the output buffer 127 buffers the gray scale voltage from the DAC circuit 126, and outputs it to the signal output terminals 111-1 to 11-n as signals for driving the liquid crystal panel. As described above, the number of the shift register circuit 123, the latch circuit 124, the holding circuit 125, the DAC circuit 126, and the output buffer 127 must be the same as the number of the liquid crystal driving signal output terminals 111, and the liquid crystal driving is used. The signal output terminal 111 is 1000 terminals, and each of the above circuits 124 to 127 also needs to be 1000. As described above, in recent years, display devices such as liquid crystal panels have been increasing in size and high definition, and in Fullspec's High Definition Television (HDTV), the number of data lines has reached 1920. Thereby, the display semiconductor integrated circuit must supply a signal of a gray scale voltage of R*GB (Red.Green.Blue) for each data line, and as a result, display the semiconductor integrated circuit for driving. 1920 x3 (RG*B)=5760 output numbers are required. In other words, 5760 liquid crystal drive signal output terminals must be included. 143485.doc 201031180 = 2:: The output of the semiconductor integrated circuit is several months from time to time. The semiconductor integrated circuit for driving is displayed. Normally, the semiconductor integrated circuit for driving the 7F is tested at the wafer stage. After the package is mounted on the liquid crystal panel, it is displayed. Further, 'the screening test using the burn-in or stress test' removes the semiconductor integrated circuit which may cause an initial failure. Therefore, a display device equipped with a semiconductor integrated circuit for display driving which may cause display failure is not shipped to the market. However, it is rare that a defect that is not judged to be defective at the time of leaving the factory or a screening test is extremely small, or a foreign matter is attached, and display failure occurs during use of the display device. For example, even if the ratio of one of the data lines of the semiconductor integrated circuit for display driving to the display is 0.01 ppm (100 million points), the display is defective in the HDTV of Full613 with a data line of 576 〇. The ratio is also 57 6 ppm (57.6 parts per million). That is, one of the approximately 17,361 units has a poor display, and the more it becomes larger and finer, the higher the proportion of poor display. In the case where the display is defective, it is necessary to quickly recover the display device and perform maintenance of the semiconductor integrated circuit for display driving. However, recovery and repair require a large amount of cost, and the image of the product is lowered. The technology discloses a preparatory circuit provided in a circuit for forming a defect in a semiconductor circuit for display driving, and switches a circuit having a defect to a preliminary circuit, thereby avoiding display semiconductor semiconductor products. Specifically, in Patent Document 1, there is disclosed a method in which a display semiconductor integrated circuit is mounted in a shift register. The segment includes a preparatory parallel circuit 'self-checking the shift register, and selecting one of the parallel circuits without defects according to the check result, thereby avoiding the defect caused by the defective shift register Further, Patent Document 2 discloses a method in which a selector is provided at an input end and an output end of a DAC circuit, and a RAM having a position of a defective DAC circuit is stored according to φ (Rand〇m Access

Memory, random access memory), switch selectors and choose to use a defect-free DAC circuit. [PRIOR ART DOCUMENT] [Patent Document 1] Japanese Laid-Open Patent Publication No. 208346 (published on July 26, 1994). [Patent Document 2] Japanese Laid-Open Patent Publication No. 278771 (October 1996) [Disclosed on the 22nd] "Summary of the Invention" Patent Application Laid-Open No. 6-曰 Patent-Opening No. 8-- [Problems to be Solved by the Invention] However, the display driving circuit having self-detection and self-healing functions has the following characteristics: In the case of performing the self-detection operation, it is necessary to separate the output circuit that supplies the video signal to the display device from the display device, and thus the image cannot be displayed during this period. Therefore, in the configuration of self-detection and self-repair disclosed in Patent Document 2 and Patent Document 2, for example, when the user is performing self-detection and self-repairing operations while viewing the display device, 143485.doc 201031180 will suddenly not display. image. Therefore, there is a problem that hinders the user's viewing or the user's misunderstanding of whether or not the display device is malfunctioning. Further, in Patent Document 1 and Patent Document 2, a method of self-detection for detecting a defect in an output circuit such as a DAC circuit is not disclosed at all. The present invention has been accomplished in view of the above problems, and an object thereof is to provide a display device having a drive circuit capable of self-detecting and self-repairing defects of an output block around an output circuit or an output circuit. Self-testing and self-healing at appropriate timings. [Means for Solving the Problems] In order to solve the above problems, the display device of the present invention is characterized in that the package 3_display panel is not imaged based on the image signal supplied from the image reproduction device; and the drive circuit is Driving the display panel, and having a self-checking and repairing the fault of the driving circuit, the self-detecting and self-repairing mechanism cannot supply the image signal to the image reproducing device (4), The failure of the above drive circuit is detected and repaired.

According to the above configuration, the display panel displays the image based on the image signal supplied from the image reproducing device. The image reproduction device can generate image signals 11 according to the data stored in various memory media, for example, a DVD _ (four) Ve fine ile Disc 'digital versatile disc) reproduction device or _ (Hard Disk Drive, broken boat private 3g, = · & hard drive) regenerative device, etc. Furthermore, the image reproduction device may be, for example, a notebook PC (per_ai c〇, a personal computer) or a portable printer having a liquid crystal display, or the like, or may be included in the display device as an independent device. It is configured by being connected to a display device via an electric environment or the like in a display device 143485.doc 201031180. Further, the display 2 does not have to have a television receiving function as in the case of the desktop type P c display. Further, the image reproducing device is a device having at least a reproducing function, and may be configured to have a function other than the reproducing function, such as a video recording function, and is not particularly limited. Further, according to the above configuration, the drive circuit drives the display panel. Moreover, the drive circuit has a self-detecting and self-healing mechanism that detects the failure of the drive itself and repairs the detected defects. Further, according to the above configuration, the self-detection and self-repair mechanism performs self-detection and self-repair while the image reproduction device is unable to supply the video signal. The period during which the video reproduction device cannot supply the video signal is a period in which the normal reproduction function cannot be used in the video reproduction device. During this period, the display device cannot display the video on the display panel based on the signal from the video reproduction device. As a result, in the display device of the present invention, the self-detection and self-repair of the media circuit are performed while the image cannot be reproduced by the image reproducing device, that is, while the user is not using the display device. Therefore, the user does not suddenly self-detect and self-repair when using the display device, and the user does not have a misunderstanding of the display device, thereby improving the convenience for the user. Further, in the display device of the present invention, the drive circuit preferably includes a plurality of output circuits for outputting an output signal for driving the display panel, and the self-detection and self-healing mechanism includes a determination mechanism for determining whether or not the output circuit is defective. When the determination result of the above-mentioned determination means is bad 143485.doc 201031180, the drive circuit is self-repaired by outputting the normal output signal to the display panel. The output circuit includes a plurality of output circuits for driving the display panel to output ==. The output circuit adds, for example, image data to a fire level and outputs it as an output signal for driving the display panel. The utual road, the self-detecting and self-repairing mechanism includes a judging mechanism for judging whether the output circuit is defective or not, and the judgment in the judging mechanism 2: when the condition is bad, 'to output the normal output signal to the display panel The way to self-repair the drive circuit. Thereby, in the display device of the present invention, the defect in the output circuit of the driving circuit can be detected, and self-repairing can be performed in the case where the wheel-out circuit is defective. Further, in the display device of the present invention, the driving circuit preferably includes a preliminary output circuit that can output the output signal to the display panel, and the detection and self-repair mechanism includes a switching mechanism, and the switching mechanism is connected to the upper determination mechanism. When the determination result is defective, the output signal from the defective output circuit is switched to the output signal from the preliminary output circuit as an output signal transmitted to the display panel. According to the above configuration, the drive circuit includes a preliminary output circuit that can output an output signal to the display panel. The preparatory output circuit is similar to the wheel-out circuit, for example, converting image data into gray-scale power and outputting it as an output signal for driving the display panel. Further, according to the above configuration, the self-detecting and self-repairing mechanism includes a switching mechanism that switches the output circuit that is judged to be defective to the preliminary output circuit by the 143485.doc 201031180. As a result, in the display device of the present invention, when the output circuit has a defect, the output circuit having the defect is switched to the preliminary output circuit, whereby the self-repair of the drive circuit can be easily performed. Further, in the display device of the present invention, the determining means preferably includes a comparing means for comparing an output signal from the output circuit with an output signal from the upper reference I preparatory output circuit' and the determining means is based on the comparison The comparison result of the mechanism determines whether the output circuit is defective or not. According to the above configuration, the judgment structure includes the comparison means. Further, the comparing means compares the output signal from the output circuit with the output signal from the preliminary output circuit. Moreover, the comparison result of the 敎 mechanism « _ constituting = determining whether the output circuit is defective or not. Therefore, in the display device of the present invention, by comparing the output of the output disk pre-output circuit of the output circuit, it is possible to determine the defective circuit of the wheel-out circuit. Therefore, it is possible to easily detect the output current by simple configuration. . The control unit has a control unit, and is widely input to the output circuit and the preparatory output circuit for control. The control unit inputs the input signals of different sizes to the upper 3 output circuit. And the comparison output circuit corresponding to the number is outputted from the comparison means = value, and the determination means determines that the output circuit is the same as the case where the comparison result is not the same as the expected value 143485.doc 201031180 bad. According to the above configuration, the control means controls the input signals input to the output circuit and the preliminary output circuit, and inputs input signals of different sizes. Further, the control unit outputs an expected value corresponding to the comparison result from the comparison means corresponding to the input signal of a different size. Further, the judging means judges that the output circuit is defective when the actual comparison result from the comparison means is different from the expected value from the control means. Specifically, for example, the input signal of the gray level „! is input to the output circuit, and the input signal of the gray level m+1 is input to the preliminary output circuit. Furthermore, the gray level voltage of the gray level m is grayscale m+1. The voltage of the gray scale voltage is lower. If the output circuit is normal, the comparison mechanism outputs a signal indicating a higher gray scale voltage input from the preliminary output circuit. On the other hand, there is a defect in the output circuit even if the input gray scale When the signal of m is output and the circuit can only output a higher gray-scale voltage, the 'comparison mechanism output indicates a signal with a higher gray-scale voltage input from the wheel-out circuit. As described above, the drive circuit of the present invention compares The mechanism compares the gray scale voltages outputted from the output circuit and the preliminary output circuit, and outputs a signal of the different value when the output is defective and when there is no defect. Second, the determining mechanism outputs the signal according to the self-comparing mechanism. Determining whether the output circuit is defective. Specifically, inputting the gray level plus the input signal to the output circuit as described above, the input signal of the gray scale m+1 When entering the preliminary output circuit, when the self-comparison mechanism inputs a signal indicating that the gray-scale voltage from the wheel-out circuit is high, it is determined that the output circuit is defective. 143485.doc -12- 201031180 Aspect, input from the comparison mechanism In the case where the signal of the step output voltage of the preliminary output circuit is high, the determination means determines that the output circuit is missing, whereby the display device of the present invention includes a specific mechanism for easily detecting the output trap. Self-repair can be performed if there is a defect in the output circuit.

In the display device of the present invention, the determining means preferably includes a comparing means for comparing output signals from at least two of the plurality of output circuits, and whether the output circuit is defective based on a comparison result of the comparing means Make a decision. According to the above configuration, the judgment structure includes a comparison institution. Further, the comparing means compares the output signals from at least two of the plurality of output circuits. Further, the judgment structure judges whether or not the output circuit is defective based on the comparison result of the comparison means. As a result, the display device t of the present invention can judge the defect of the output circuit by comparing the output of the output circuit. Therefore, it is possible to easily detect the defect of the output circuit with a simple configuration. In the display device of the present invention, it is preferable to further include a control mechanism for controlling input signals to at least two (four) out-of-circuit circuits of the plurality of output circuit pads, wherein the control mechanism converts the input signals of different sizes. And inputting to the at least two output circuits, and outputting an expected value of the comparison result from the comparing means corresponding to the input signal different in size, and determining, by the determining means, that the comparison result is different from the expected value, determining Any of the above at least two output circuits is defective. 143485.doc •13· 201031180 According to the above configuration, the control unit controls an input signal input to at least two of the plurality of output circuits, and inputs input signals of different sizes. Further, the control unit outputs an expected value of the comparison result from the comparison means corresponding to the input signal of a different size. Further, the judgment means determines that the output circuit is defective when the actual comparison result from the comparison means is different from the expected value from the control means. Specifically, for example, when a different input signal is input to the two output circuits of the ith output circuit and the second output circuit, the input signal of the gray-scale melon is input to the first output circuit, and the gray scale is m+1. The input signal is input to the second output circuit. Furthermore, the gray scale voltage of the gray scale m is lower than the gray scale voltage of the gray scale m+l. In this case, the 'the third output circuit is normal, and the comparison output unit 7F is higher than the gray output of the second output circuit', and there is a defect in the first output circuit, even if the input gray level is 4 The first output circuit can only turn out the higher gray-scale voltage, and the comparison mechanism output table does not have a higher gray-scale voltage input from the i-th output circuit. As described above, in the media smashing circuit of the present invention, the comparing means performs tt comparison on the gray scale voltage outputted from at least two of the output circuits of the self-complex 値 output circuit, and there is a defect in the output circuit. When the method is ~, clear, and there is no defect, the signal of the output is different. The judging mechanism judges whether the output is bad or not according to the signal output from the comparison mechanism. Specifically, when a different input f number is input to the two 1st solid output circuits of the 10,000th output circuit and the second round output circuit as described above, and the wheel input signal of the gray level* is input to In the first round, 143485.doc 201031180 When the input signal wheel of the gray scale m+1 is used, when the comparison mechanism inputs a signal indicating a higher condition from the 2 output circuit, the determining mechanism determines the gray scale of the first output circuit. At least one of the output circuits of the voltage path is defective. 1 output circuit and second output power The second output circuit is switched to the preliminary output power. At this time, the output of the 帛1 output circuit and the comparison mechanism are indicated by the second round.

In the case of the case, the judging means judges that the output circuit has a higher voltage signal, whereby the specific mechanism 2 for detecting the display defect of the present invention can easily perform self-repeating at the time of the circuit. The above-mentioned output circuit preferably includes an operational amplifier as an output buffer. The comparator is preferably a comparator including the above operational amplifier. According to the above configuration, the rounding circuit includes the operational amplifier n as an output buffer, and the comparator is a comparator including an operational amplifier. Usually, the output signal from the output circuit that drives the display panel is buffered and output to the output terminal. Here, the operational amplifier becomes an electric grinder follower circuit by negatively feeding back its own output to its own negative input terminal, and has a function as a buffer circuit. Therefore, as described above, by making the comparison means a comparator constituting an operational amplifier, the operational amplifier has both a buffer circuit for buffering an output signal from the output circuit and a comparison means. Therefore, the driving circuit of the present invention does not need to additionally include a buffer circuit for buffering the output signal from the output circuit, thereby exerting an effect of reducing the cost of 143485.doc 15 201031180. In the display device of the present invention, the operational amplifier preferably operates as a voltage follower when driving the display panel. Further, in the display device of the present invention, the image reproducing device is preferably a DVD reproducing device. Further, in the display device of the present invention, when the self-detecting and self-repairing mechanism is cleaning the DVD reproducing device during the period, it is preferable to detect and repair the defect of the driving circuit. According to the above configuration, the self-detection and self-repair mechanism detects the failure of the drive circuit and performs the repair operation when the DVD is being used for cleaning. Thereby, self-detection and self-repair can be performed during the cleaning of the DVD reproducing apparatus, that is, when the video cannot be reproduced by the DVD reproducing apparatus and the user does not use the display apparatus. Further, in the display device of the present invention, the image reproducing device is preferably an HDD reproducing device. Further, in the display device of the present invention, the self-detecting and self-repairing mechanism is preferably characterized in that the failure of the drive circuit is detected and repaired during the optimization of the memory region of the HDD playback device. According to the above configuration, when the self-detection and self-repair mechanism are optimized or recombined in the memory area of the hdd reproduction device, the failure of the drive circuit is detected and repaired. Thereby, recombination is performed in the HDD reproducing apparatus, that is, the image cannot be reproduced by the HDD reproducing apparatus and the user does not use the display apparatus 143485.doc -16 - 201031180, and self-detection and self-repair can be performed. Further, in the display device of the present invention, it is preferable that the HDD reproducing device starts maintenance at a set time, and the self-detecting and self-repairing mechanism is configured to perform a memory region of the HDD reproducing device that is started at the set time. During the optimization period, the defect of the above drive circuit is checked and repaired. According to the above configuration, the video reproduction device starts the protection at the set time. For example, the user sets the unused time of the video reproduction device and the display device, and starts maintenance at the set time. Further, the self-detection and self-repair mechanism can detect and repair the failure of the drive circuit during the maintenance of the image reproduction device at the time of collection. If the user can use the maintenance start time of the video reproduction device at the time when the display device is not manufactured, the convenience is improved. It is obvious that the television system of the present invention may be configured to include the display device described in any of the above items. φ [Effects of the Invention] In order to solve the above problems, the display device of the present invention includes a display panel, which displays an image according to the self-image reproducing device, and a driving circuit, such as "..." The above-mentioned display panel is driven... The detection circuit and the self-repair mechanism are inferior to the drive circuit, and the measurement and repair mechanism of the image reproduction device is described above and repaired. __ 'The above drive circuit Therefore, in the display device of the present invention, the display circuit is not reproduced by the user during the period in which the image reproduction device H3485.di 201031180 cannot be reproduced, that is, during the period in which the user does not use the display device. The self-detection and the self-repairing device can improve the convenience for the user. [Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. [Embodiment 1] Hereinafter, a description will be given below. 17, the first embodiment of the present invention (LCD TV 400)

Q As a representative of a display device using a display drive circuit, a thin type television represented by a liquid crystal television can be cited. A liquid crystal display (a liquid crystal display device is mounted on a display panel with a plurality of drive circuits fabricated by a semiconductor integrated circuit (LSKLa W Integmi), a large integrated circuit). In such a display device, when a failure occurs in the display drive circuit, it is directly recognized by the user as a display failure. In the event of such a bad situation, it is necessary to quickly repair the defective part. It is desirable to complete the repair in a short time as much as possible in the place where the manufacturer is smashed. If the control board is processed like a display signal, it is easy to replace by connecting the connector to the display panel. However, since the display drive power (4) is directly connected to the _ panel and is not connected by the wheel material, it is used. It is difficult to replace the place where the product is used. Therefore, the present applicant has proposed a display drive (four) circuit having a function of self-repairing self-repair of the display drive circuit itself (self-recovery self-repair function) (for example, Japanese Patent Patent No. 2, deletion, 48, 143,485) .doc -18. 201031180 曰 专利 特 -04 -04 -04 -04 -04 -04 -04 -04 -04 -04 -04 -04 -04 -04 -04 -04 -04 -04 -04 -04 -04 -04 -04 -04 -04 -04 -04 -04 -04 -04 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 1 is a block diagram showing the configuration of a liquid crystal television 400 of the present invention. As shown in FIG. 1, the LCD TV 400 includes a TFT-LCD (Thin Film Transistor-Liquid Crystal Display) module (display portion) 90, a switch button 401, a DVD device 402, an HDD device 403, and a DVD. And HDD control device 404. Further, the display unit 90 includes a source driver (drive circuit, integrated circuit) 10a, a preliminary source driver 1b, a TFT-LCD panel (display panel) 80, a gate driver 99, and a controller 100. Further, the source driver 10a, that is, the integrated circuit 10a, is the above-described display driving circuit having a self-detection and self-healing function. Further, the preparatory source driver 10b, that is, the preparatory integrated circuit 10b, may have a self-detection and self-repair function. Further, in the case where only the integrated circuit 1 〇 or the source driver 10 is referred to, the integrated circuits 1 〇 a and 1 〇 b are collectively referred to as the source drivers 10a and 10b. Hereinafter, after describing the basic operations of self-detection and self-repair in the display unit 90, the characteristic configuration of the self-detection and self-repair in the liquid crystal television 400, that is, the manner in which the user is not misunderstood. The self-testing and self-repairing components can be specifically described. (Display Unit 90) First, a schematic configuration of the display unit 90 of the present invention will be described with reference to Fig. 2 . FIG. 2 is a block diagram showing a schematic configuration of the display unit 90. As shown in FIG. 2, the display unit 90 includes a display panel 80 and a display driving semiconductor integrated circuit that drives the display panel 80 based on the grayscale 143485.doc -19-201031180 data input from the outside (hereinafter referred to as a product). Body circuit or source driver) 1 (). Further, the source driver, that is, the integrated circuit 10 (drive circuit) includes a switching circuit 6 (self-detection and self-repair mechanism, switching mechanism), a switching circuit 61 (self-detection and self-repair mechanism, switching mechanism), and an output circuit block. 30 (output circuit), preliminary output circuit block 40 (prepared output circuit), and comparison determination circuit 5 (comparison mechanism, determination mechanism, self-detection, and self-repair mechanism). Further, the display panel 80 includes pixels 7A to which the gray scale voltage from the integrated circuit 1 is applied. Next, the basic operation of the display unit 90 will be described. First, the display unit 90 is §, and two basic operations are included as basic operations. Specifically, the display unit 90 includes the following two basic operations: the integrated circuit 1 转换 converts the gray scale data input from the outside into a gray scale voltage (output signal), and displays the image on the display panel 80 according to the gray scale voltage. The general operation; and detecting whether the output circuit block 30 included in the integrated circuit 10 is defective, and when the output circuit block 30 is defective, the integrated circuit 1 自我 self-repairing self-repairing repair action. Hereinafter, the outline of the self-detection repair operation performed by the integrated circuit 10 will be described. First, when the self-detection repair operation is performed, gray scale data for operation confirmation is input from the outside to the output circuit block 30 and the preliminary output circuit block 4 via the switching circuit 61. Each of the output circuit block 30 and the preliminary output circuit block 4 converts the input gray scale data into a gray scale voltage and rotates to the comparison determination circuit. The comparison decision circuit 50 compares the gray scale voltage from the output circuit block with the gray scale voltage from the preliminary output circuit block. 'According to the comparison result, the output block is judged as to whether the circuit block is defective or not. 143485.doc -20- 201031180 . Further, the comparison determination circuit 5 输出 outputs a determination result (defect detection information) indicating whether or not the output circuit block is defective to the switching circuit 61 and the switching circuit 6A. The switching circuit 61 switches the output destination of the gray scale data from the outside based on the determination result from the comparison determination circuit 50. On the other hand, after switching the 'circuit 6 〇 from the output circuit block 3 〇 and the preliminary output circuit block 4 〇 to the respective input gray scale voltages, according to the determination result from the comparison decision circuit, φ from the input gray The gray scale voltage output to the display panel 80 is selected among the step voltages. More specifically, after the determination result indicating that the output circuit block 30 is defective is input to the switching circuit 61, the same gray scale data as the gray scale data outputted to the output circuit block 30 determined to be defective is also input. To the preliminary output circuit block 40. On the other hand, after the determination result indicating that the output circuit block 30 is defective is input to the switching circuit 6A, the gray scale voltage from the preliminary output 'circuit 40 is substituted for the gray scale from the output circuit block % 判定 determined to be defective. The voltage is output to the display panel 80. As a result, even if the output circuit block 30 becomes defective, the integrated output circuit block can be used instead of the integrated circuit block, and the normal gray scale voltage can be output to the display panel 8A. As described above, the integrated circuit 1A of the present embodiment includes the comparison determination circuit 50, the switching circuit 6A, and the switching circuit 61, whereby the defect of itself can be detected, and the defect of itself can be self-repaired. In other words, the integrated circuit 10 includes a self-repairing circuit (self-repairing mechanism) that detects the failure of itself and then repairs itself. Furthermore, the configuration of the source driver 10, that is, the integrated circuit 10 and self-detection, and the details of the repair operation of 143485.doc -21 · 201031180 will be described below. (Self-detection operation start switch) Fig. 3 is a view showing the appearance of the liquid crystal television. As shown in Fig. 3, the liquid crystal television 400 includes a switch button 4〇 (indicating mechanism) for starting a self-detecting operation. Hereinafter, the switch button 401 will be described in detail. Fig. 4 is a view showing an example of display when an abnormality occurs in the output circuit block 30 constituting the integrated circuit 1 included in the liquid crystal television 400. As shown in Fig. 4, when there is an abnormality in the output circuit block 30, there is a vertical line in the display. In general, when the source driver is shipped as an LSI, the function test is sufficiently performed, and the display is sufficiently confirmed in the display device, so that the possibility of display abnormality is extremely low. That is, the possibility of display failure is extremely low within the general use range of the display device. However, sometimes the damage caused in the path of the output signal due to sudden factors such as foreign matter mixing or damage when manufacturing the driver may be enlarged during use of the display device, causing an abnormality in the output circuit of the source driver. Causes poor display. Therefore, the source driver must perform a bad self-detection of the output circuit block. Here, it is also considered that, for example, the self-detection of the output circuit block is performed every time the power is turned on, but as described above, since the possibility of occurrence of a display defect is very low, the source driver does not need to be so high. The frequency performs self-detection of the output circuit block. Therefore, the liquid crystal television 400 includes a switch button 4〇1 for indicating the start of self-detection and self-repair. Thereby, the user can start self-detection and self-repair in the liquid crystal television 400 at any time. 143485.doc -22- 201031180 FIG. 5 is a diagram showing the self-detection and self-repairing actions in the liquid crystal television 400, and FIG. 5(a) is a diagram showing the LCD TV 400 before the self-detection and self-repairing operations are started. Fig. 5(b) is a diagram showing the liquid crystal television 400 in the process of self-detection and self-repair, and Fig. 5(c) is a diagram showing the liquid crystal television after the self-detection and self-repairing operations are completed. As shown in Fig. 5(a), when there is a display failure of the vertical line in the screen on which the liquid crystal television 4 is generated, the user presses the switch button 4〇1. Thereby, self-detection and self-repairing operations are started in the liquid φ crystal television 400. After the self-detection and self-repair actions are started, as shown in Fig. 5(b), the screen displayed from the liquid crystal television 400 temporarily disappears. During this period, the source driver 1 or the integrated circuit 10 performs self-detection, and after finding out the defective round-out circuit block from the output circuit block 3, the defective output circuit block and the preliminary output circuit block are replaced. 40. Then, after the self-detection and self-repairing operations are completed, as shown in Fig. 5(c), the liquid crystal television 4 is displayed again. At this time, the defective circuit block is replaced with the normal preliminary output circuit block, so that the display does not disappear. Further, as described above, when the switch button 401 is pressed, the start switch is turned on, and as shown in Fig. 5 (b), the display temporarily disappears. Therefore, when the user may misunderstand the situation as a failure, the phenomenon is clearly described in the instruction manual, and can be temporarily disappeared on the screen by the display panel 80 (notification mechanism) during the self-detection and self-repair operation. The content to be displayed may be a configuration in which the display is turned off by a notification by a speaker (notification means) by voice announcement or the like. Therefore, in the liquid crystal television 400, it is not necessary to perform self-detection and self-repair since the power is turned on, and it is not necessary to perform self-detection and self-repair each time the power is turned on. , shortens the time from power-on to display, and also saves power consumed by self-test. Further, the switch button 401 can also be used as a switch for maintenance of the liquid crystal television 4 itself. For example, when the switch button 401 is pressed, the controller 1 (the function table display control means) displays the maintenance function table of the liquid crystal television 400 (for example, an operation function table such as a clock setting, a screen color adjustment, and a screen adjustment). On the display panel 80. Fig. 6 is a view showing a display example of a maintenance function table in the liquid crystal television. The maintenance function table is provided with a function table for self-detecting ◎ and self-repair. When the display is bad, the user can select the user to display self-detection and self-repair from the maintenance function table displayed on the display panel 8〇. After the action function table ("3. Screen adjustment" in the example of the diagram), the self-detection and self-repair actions in the source driver are started. Furthermore, when the self-test and the self-repair are selected, the self-detection and self-repair actions are started after the notification display such as the screen display or the voice announcement disappears temporarily. Further, in the present embodiment, the switch button 4 is set on the liquid crystal panel 400. However, the switch button 4〇1 may be provided on the remote controller. # 'Press the switch button set on the remote control to send a signal to the LCD TV to self-detect and self-repair the signal. · In the LCD TV _, according to the received signal, the drive circuit self-test and Self-healing. (Preparation source driver) Fig. 7 is a diagram showing the self-detection and self-repairing action in the liquid crystal television 400. 143485.doc • 24· 201031180 Example diagram, FIG. 7(a) shows the liquid crystal before the self-detection and self-repairing operations are started. The diagram of the television 400, FIG. 7(b) shows a picture of the liquid crystal television 400 during the self-detection and self-repair operation, and FIG. 7(c) shows the LCD TV 400 after the self-detection and self-repair operation. As shown in Fig. 7(b), in the self-detection and self-repair process, the liquid crystal television 400 can display a screen for self-detection and self-repair, and notify the user of the current situation. Further, since the liquid crystal television 400 electrically disconnects the connection between the source driver, that is, the integrated circuit 10 and the liquid crystal panel, during the self-detection and self-repair operation, the integrated circuit 10 cannot be used in FIG. 7 (FIG. 7) b) A display of the meaning of the self-test and self-repair in progress as shown. Therefore, the liquid crystal television 400 includes a preliminary source driver for performing the facet display shown in FIG. 7(b), and performs self-detection and self-repair using the preparatory source driver during the self-detection and self-repairing operations. The meaning of the screen is displayed. Fig. 8 is a view showing an example in which a source driver 10a for driving the display panel 80 is mounted in a display portion 90? of a TFT-LCD module constituting the liquid crystal television 400. As shown in FIG. 8, the display unit 90 includes a source driver 10a, a gate driver 99, an FPC (Flexible Printed Circuit) (film cable "98, and a PWD (Printed Wiring Board) (printing). Substrate 97, glass substrate 96, source line 95, gate line 94, TFT (Thin Film Transistor) 93, pixel 92, and counter electrode 91. On the glass substrate 96, a source line 95, a gate line 94, a TFT 93, a pixel 92, and a counter electrode 91 are formed to constitute a liquid crystal panel 80. Further, the source driver 143485.doc • 25- 201031180 and the gate driver 99 are respectively mounted on one side of the glass substrate 96 of the liquid crystal panel 80. The source driver i〇a transmits a display voltage, that is, a grayscale voltage representing an image, to the pixel 92 via the source line 95. The gate driver 99 supplies a gate signal indicating the timing at which the on-time of the TFT 93 is transferred to the pixel by the on-time of the TFT 93 via the gate line 94. The input terminals of the source driver 1 〇a and the gate driver 99 are connected to the printed circuit board 97, and the control signal or the power supply voltage and the GND are supplied via the wiring of the printed substrate 97 (the ground p control signal, the power supply voltage, and the GND are self-transferred through the thin film. The control board (not shown) connected to the electric buffer 98 is supplied as a controller 00. As described above, the display unit 90 may be configured to include a preliminary source driver. Fig. 9 is a view showing a structure of a liquid crystal television. The tft_lcd module is a diagram showing an example of the source driver i〇a and the preliminary source driver 1 〇b for driving the display panel 8A in the display portion. In FIG. 9, the source driver 丨〇a ( The first driving circuit is mounted on one side of the glass substrate 96 constituting the display panel 8. The "prepared source driver 1" (second driving circuit) is mounted on the opposite side of the source driver 10a, and the source driver 1 Similarly, 控制a is connected to the printed circuit board 97 on the input side to supply a control signal or the like. Alternatively, the source driver, that is, the source driver 1〇3 and 1〇b may be mounted in the mounting form shown in FIGS. 10 to 12. Figure 1 A schematic diagram showing a state in which a source driver having a self-detection and self-healing function and a preliminary source driver 10b are mounted on a glass substrate % in parallel using a tape carrier 89. FIG. 10 has a configuration and FIG. The components of the display unit 90 shown in Fig. 9 having the same work a are attached with the same numbers. As shown in Fig. (10)*, the source drive 143485.doc 201031180 The actuator 10a and the preparatory source driver 1 〇b are connected to the input side. The printed circuit board 97' is connected to the glass substrate 96 constituting the display panel 8A on the output side. When the battery board 96 is mounted in a cylindrical shape as shown in FIG. 10, the source driver 10a and the source driver 10b may be connected to the printed circuit board 97. The input signal can be supplied from the shared substrate 97. Fig. 11 is a view showing a state in which the tape carrier 89 shown in Fig. 1 is opened. As shown in Fig. 11, the source driver 10a is removed from the tape type. The element hole portion 87 of the film substrate 83 of the carrier ❿ 89 is connected to the input side wiring 88 and the output side wiring 86. Further, the 'prepared source driver 1 〇b is connected to the thin film in the opposite direction to the source driver 1 〇a. Input of substrate 83 The side wiring 88 and the output side wiring 86. As shown in FIG. 11, the film substrate 83 is mounted on the tape carrier 89 by mounting the source driver 10a and the preliminary source driver 10b opposite to the front and back surfaces. The output terminals can be connected in common. Thereby, as shown in FIG. 1A, the source driver 10a and the source driver 1b can be mounted on the same side of the glass substrate 96 constituting the display panel 8A. In the direction A, a plan view of the tape carrier 89 in which the source drivers 10a and 10b are mounted as shown in Fig. 11 is observed. As shown in Fig. u, the both sides of the tape carrier 89 are formed to be connected to the input side wiring. The input terminal of 88 refers to the operation switching input terminal 82. Normally, the source driver 1A is operated after the signal of "L" is input to the operation switching input terminal 82, and the display unit 9A performs general display. At this time, the preparatory source driver 1〇b does not operate. On the other hand, in the case where the self-detection and self-healing operation is performed in the source driver 1A, the controller (control board) inputs a signal of "Η" to the operation switching input terminal 82. Thereby, the source driver 10a starts the detection and self-repair operation from 143485.doc •27· 201031180, and the preparatory source driver 1Gb starts to operate in the display unit 9〇 for self-detection and self-repair operation. The display. Further, since the preparatory source driver 1 〇b can be simply displayed, it can be composed of an inexpensive driving H having a small number of gray scales. For example, when the source driver 10a can display the gray level of i〇24, an 8-gray driver can also be used as the preliminary source driver 1 〇b. Further, the display control system of the preparatory driver 10b may be performed based on the control signal transmitted from the controller and the data k for display, similarly to the control of the source driver 1a, but in the case of the preparatory source driver If the display content is displayed in the internal display and the display content is memorized in advance, it is not necessary to continuously supply the display data to the preliminary source (4) (4) b. If the display memory is used to store the display data before the preparatory source driver 10b performs display, the display data can be displayed using the display data in the memory. When the display content is determined, the display memory is set to R〇M (Read Only Memory) or 〇TP (0ne Time Pr〇m, one-time programmable memory) to fix the display content. Thereafter, it is not necessary to transmit the display material to the preparatory source driver 10b from the outside, and the display control can be easily performed with a simple configuration. (Flag storage external memory) In the self-detection and self-repair, the comparison determination circuit 5 〇 performs the failure determination of the output circuit block 30, and the determination result is stored as a determination flag (bad detection information) and is stored in the source. In the memory inside the drive. The display unit % performs self-repair according to the determination flag, and it is necessary to memorize the determination flag in advance even when the source driver is not supplied with power supply 143485.doc -28 · 201031180. π, if the judgment flag is lost, it is impossible to specify π & Α ±Α ... the good wheel-out circuit, so it is necessary to enter the lamp self-detection again, so that each self-repair action takes a long time. If the memory of the source driver is non-volatile, there is no problem. The non-volatile memory is placed in the source driver, which causes an increase in cost. Therefore, the memory in the source driver is usually a volatile memory. • Μ ° Therefore, when the power is turned off, the judgment flag of the memory stored in the source driver disappears. Therefore, the liquid crystal television 400 includes a configuration in which, when the power is turned off, the content of the determination flag of the source driver is transmitted to the external memory clock as a memory device) when the power is turned on, otherwise the flag is determined to be self-determined. The external 5 memory 81 is read into the memory of the source driver Zhao Zhong. Fig. 13 is a view showing an example in which the display unit 90, which is a module of the liquid crystal television module (3), is mounted on the printed circuit board 97 to which the input of the source driver 1a is connected. The source driver 10a includes a serial I/〇 (Input/〇utput) for inputting and outputting the value of the volatile memory for storing the flag set in the internal output circuit block as the serial data. • Input/output) terminals '· terminals for setting data to the memory 81 ; and terminals for reading data from the memory 81 . The serial I/O terminal is connected to the memory 81, and data can be read and read between the volatile memory inside the source driver i〇a and the external memory 81. When the power of the liquid crystal is turned off by the operation of the user or the timer of the power supply, etc., the power supply of the liquid crystal is turned off (that is, when the power of the display unit 9 is turned off), the self-controller 1〇〇 (write control means), a signal for instructing writing of data to the memory 81 is supplied to a terminal for writing data to the memory 81, and the source driver 10a is set to write to the memory 81. The status of the data. Then, the data of the determination flag is written from the source driver 10a to the external memory 8i based on the finger #' from the controller 100, and the memory 8 stores the determination flag. This operation is performed for each of the source drivers 10a so that the decision flags of all the source drivers are memorized in the memory 81. On the other hand, when the power is turned on, the controller 1 〇〇 sets a signal for reading data from the memory 81, supplies a signal indicating that data is read from the memory 81, and sets the source driver 1 〇 a to be performed. The state of the memory 8 丨 read data. Thereby, the data of the judgment flag is read into the source driver 10a from the external memory 81, and the volatile memory inside the source driver 1A recalls the decision flag. This operation is performed for each of the source drivers 1a to cause the decision flag to be stored in the memory inside all of the source drivers. Then, the switching circuits 60 and 61 switch between the defective output circuit block 30 and the preliminary output circuit block 4A based on the read determination flag, and perform self-repair of the source driver 10a. Fig. 14 is a view showing another example of mounting the memory 81 on the printed circuit board 97 connected to the input end of the source driver in the display unit 90 which is a tft lcd module constituting the liquid crystal television. In the configuration of Fig. 14, the terminals of the source driver for inputting and outputting the flag of the determination flag of the source micro-aliasing device 10a are connected to each other, whereby the source driver of the mounted device can be written or read in series. Judging the entire flag. 143485.doc 201031180 Further, in the present embodiment, the memory 81 is a flash memory of a non-volatile memory, but may be a volatile RAM. At this time, as a circuit for always supplying electric dust to the power supply of the RAM, it is necessary to provide a capacitor or a battery that is prepared to be used after the sudden power supply is turned off. In the example of Fig. 13 and Fig. 14, the memory _ is placed on the printed circuit board 97, but may be provided on another substrate such as a control board and connected via the thin film electron microscope 98. • Next, the money 15 is described as a description of the configuration of the self-detection when the power of the display unit 9G is turned off. Fig. 15 is a flow chart showing the procedure of self-detection of the source driver 10a when the power of the display unit 9 is turned off. In this configuration, only self-repair is performed without self-detection when the power is turned on, and self-detection is performed when the power is turned off instead. After the display unit 90 is powered on (8) 5〇1), the memory 81 is stored from the determination flag, and the determination flag is transmitted to the internal memory of the source driver i〇a (S1502). Then, the source driver core performs self-repair based on the determination flag (S1503), and starts a general operation of displaying an image or the like on the display panel 80 (S1504). The display unit 9 determines whether or not the power-off command has been received at a fixed time interval in the normal operation (S1505). Further, the display unit 9 does not recognize the power-off command period (S1505.N.), and repeatedly determines whether or not the power-off command is received. Moreover, the S display portion 90 senses that the self-switch or the remote controller sends a power-off command to the liquid crystal television 400 (or the display unit 90) (si5〇5: Yes) is turned off on the display panel 8 Display of images (si5〇6). In the case of 143485.doc -31 - 201031180, the power supply of the entire system including the display unit 90 itself and the display unit 9A is not disconnected. Next, in the display unit 9A, the comparison determination circuit 5 determines whether or not each of the output circuits constituting the source driver 10a is defective. In other words, the display unit 90 performs self-detection of the source driver 1a, and stores the determination flag indicating the content of the determination result in the inside of the source driver 1A (S1507). Then, it is determined whether or not the self-detection is completed for all the source drivers 1 & (S1508). In the case where not all the source drivers 1〇a end self-detection (S15〇8: No), in the sl5〇7, the remaining source drivers 1〇a that are not self-detected are similarly The process of self-testing and storing the determination flag in the internal memory is repeated. When all the source drivers 10a end self-detection (s丨5〇8: Yes), the determination flags stored in the memory inside the source driver 10a are stored in the non-volatile outside the source driver 10a. In the memory 81 (sl5〇9), after the self-detection determination flag is stored in the memory outside the source driver j 〇a, the display unit 90 supplies the source driver 1A and the peripheral circuit power. When the above processing is performed, in the case where the output circuit block included in the source driver 1A generates an abnormality and the display is defective, the power is turned off and then connected again. The power is turned on to restore the display. (DVD device 402) FIG. 16 is a diagram showing an example of self-detection and self-repairing operations in the LCD TV, and FIG. 16(a) shows the self-detection and self-repair operations. Figure of LCD TV 400, Figure i6(b) shows the picture of LCD TV 400 in self-detection and self-repair operation, Figure 16 (Psychology shows self-test and self 143485.doc •32· 201031180 After the repair action is over The picture of the LCD TV 400. As shown in FIG, 400 is mounted in a liquid crystal television with a DVD (Digital

Versatile Disc or Digital Video Disc) device 402. The DVD device 402 has a function of reproducing, recording, and the like using a DVD. In the liquid crystal television 400, the DVD and HDD control unit 404 controls various operations of the DVD device 402 (video reproducing device) in accordance with an instruction from the user. The DVD needs to periodically clean the head of the read signal. Therefore, as shown in Fig. 16 (a), the cleaning disc is inserted to clean the head. After the DVD device 402 detects the insertion of the cleaning disc, the cleaning operation is started based on the control signal from the DVD and HDD control unit 404 corresponding to the user's instruction. Further, as shown in Fig. 16 (a), the liquid crystal television 400 has a defect that a vertical line exists on the display screen. Further, the liquid crystal television 400 is characterized in that the self-detection of the source driver 1a is performed while the cleaning of the DVD device 402 integrally included is performed. If it is explained in more detail, the DVD and HDD control unit 404 receives a signal indicating that the cleaning has started from the DVD device 402, and supplies the controller 100 with the self-detection and self-repair of the source driver 10a. Signal of indication. Then, in accordance with an instruction from the controller 100, the source driver 10a starts self-detection and self-repair operations. Further, the DVD device 402 may be configured separately from the liquid crystal television 400. As shown in Fig. 16 (b), the convenience of the user is improved when the notification of the meaning of the cleaning is being performed, but the general image display source driver 10a is cleaned at the same time. Self-detection is performed 143485.doc •33· 201031180, so it is necessary to have a preparatory source driver l〇b in advance as described above. Further, the determination flag indicating the determination result of the self-detection of the source driver 10a is held in the memory inside the source driver 10a, and the source driver 10a is judged according to the judgment flag held in the internal memory. Self-repairing action. Thereby, as shown in Fig. 16 (c), the defect of the vertical line on the display screen of Fig. 16 (&) is eliminated. When the power is turned off, the memory of the above-mentioned determination flag from the source driver 10a is stored in the external memory 81, and is read again into the source driver i〇a when the power is turned on. Self-repairing again in memory. (HDD device 403) FIG. 17 is a view showing an example of self-detection and self-repairing operation in the liquid crystal television, and FIG. 17(a) is a view showing the liquid crystal television 400 before the self-detection and self-repair operation, FIG. (b) is a diagram showing the LCD TV 400 in the self-test and self-repair operation, and Figure 17 (the figure shows the LCD TV after the self-test and self-repair operation. As shown in Figure 1, the LCD TV The HDD (Hard to Drive) device 403 is built in the 400. The HDD device 403 has a function of reproducing, recording, and the like by the HDD. In the liquid crystal television 400, the DVD and HDD control unit 404 pairs the HDD device 403 according to an instruction from the user. The various operations of the (image reproducing device) are controlled. The HDD needs to perform maintenance such as sorting of a memory area (for example, optimization of a memory area such as reorganization or error checking of a disc, etc.), and the HDD device 4〇3 is based on the user. The instruction corresponding to the control signal from the DVD and HDD control unit 4〇4 starts the maintenance operation. The video recording cannot be performed during the maintenance and the memory is restored. Therefore, the memory of the leg device 403 is recorded. The maintenance of the domain needs to be performed when the user does not use it. Therefore, as shown in Fig. 17 (4), the liquid crystal television 400 is configured to be used by the user for a reduced time (for example, late at night) and maintained at the designated time. That is to say, 'Fountain has a timer function that can be maintained at a preset time. Further, as shown in Fig. 17 (4), the LCD TV is completely defective in the vertical line on the display screen. Moreover, the LCD TV 400 It is characterized in that the φ is defined as follows, that is, the self-detection of the source driver is performed at the time of performing the maintenance of the unit 一体 integrally. As will be described in more detail, the _ and brain control unit 4 The 自4 self-surface device 403 receives a signal indicating that the optimization of the memory area has been started, and then the signal indicating that the controller has started the self-detection of the source driver ... self-repair is performed. Then, according to the controller (10) Indication 'Source Drive 1 阅a Reading> Start to self-test and self-repair. HDD device 4〇3 can also be built from LCD TV 4Q_t φ Self-testing is performed at the time when the user is not using it, so there is no need to do it: in the display of the meaning of maintaining the HDD, as shown in the figure, the display is closed, and the user is also forgotten that the user is forgetting to maintain the hdd. Therefore, it is possible to perform a simple display by mounting the above-described source driver 100b. The determination flag indicating the result of self-detection is held in the source driver (4). In the memory, 'self-repair is performed according to the judgment flag. Fig. 17 (4) shows the state of the screen when the display is performed again after the maintenance is completed, 143485.doc • 35· 201031180, and the user is informed that the maintenance has been completed. As shown in Fig. 17 (c), the defect of the vertical line on the display surface of Fig. 17(a) is eliminated. Moreover, when the power is turned off, it will be stored inside the source driver i 〇a. The decision flag in the hidden body is stored in the external memory, and is read again into the memory in the source driver 10a when the power is turned on, and the self-repair is performed again. (Configuration of Integrated Circuit 10) Next, the configuration of the source driver 1A of the present invention will be described with reference to Fig. 18. Further, as described above, the preliminary source driver 1b may be configured to be simpler than the source driver 1a, but may have the same configuration as the source driver 100a. Hereinafter, a circuit that can perform the same self-detection and self-repair operation as the source driver 1 〇 & is referred to as an integrated circuit 1 〇. Fig. 18 is an explanatory view showing the configuration of an integrated circuit 1 (drive circuit). As shown in the figure, the integrated circuit 10 includes: n sampling circuits 6_丨~6_n (hereinafter, referred to as a sampling circuit 6 in the case of a general term), and the data is input from a gray-scale data input terminal (not shown). The gray scale data corresponding to each of the n liquid crystal driving signal output terminals OUT1 to OUTn (hereinafter referred to as output terminals 〇 UT1 to OUTn) is input to the bus bar; n holding circuits 7-1 to 7-η (hereinafter, In the case of the general term, it is called a holding circuit 7); n DAC circuits 8-1 to 8-n (hereinafter, referred to as DAC circuit 8 in the case of a general term), which convert gray scale data into gray scale voltage signals; n operational amplifiers 1_1 to η (hereinafter, referred to as operational amplifier 1 in the case of a general term) 'which functions as a buffer circuit for the gray scale voltage signal from the DAC circuit 8; n determination circuits 3-1 to 3 - η (hereinafter, referred to as decision circuit 3 in the case of clearing of 143485.doc -36· 201031180); _determination flag 4]~'η (hereinafter, referred to as judgment flag 4 in the case of the general term); And n pull-up and pull-down circuits 5_ 1 5 η (hereinafter referred to as the pull-up and pull-down circuits in the case of the general term). As shown in the figure, the [integrated circuit 1〇 includes a plurality of switches 2a that switch between ON (open) and 〇FF (off) according to the addition (test) L number, and κ 根据 according to the test b signal. a plurality of switches 2b for switching between Ν and 〇ff; and a plurality of switches 2c (connection switching mechanism) for switching between (^ and 〇) according to an output signal from the determination flag 4, that is, ❹ Flag1 to Flagn And 2d (connection switching mechanism). Further, the switches h, 2b, and 2d become 〇n when the signal of "H" is input, and become 〇FF when the number of Lj is input. On the other hand, the switch & is 〇FF when the signal of "Η" is input, and becomes 〇N when the signal of "H" is input. Further, the integrated circuit 10 includes the following circuits each : a preliminary sampling circuit 26, a preliminary holding circuit 27, a preliminary DAC circuit 28 (pre-output φ output circuit), and a preliminary operational amplifier. Further, in Fig. 18, the sampling circuit 6, the holding circuit 7, and the dAC circuit 8 Corresponding to the output circuit block 3〇 shown in FIG. 2, the sampling circuit 26, and the hold The circuit 27 and the DAC circuit 28 correspond to the preliminary circuit block 4A shown in FIG. 2. The operational amplifier 1, the decision circuit 3, and the decision flag 4 correspond to the comparison decision circuit 50 shown in FIG. 2, and the output terminals ουτί~OUTn. The connected switch 2d and the switch 2c correspond to the switching circuit 6A shown in Fig. 2, and the switch 2d connected to the sampling circuit 6 corresponds to the switching circuit 61 shown in Fig. 2. Further, the integrated circuit 10 shown in Fig. 18 The display panel 8A is connected to the 143485.doc -37-201031180 shown in FIG. 2 via the output terminals OUT1 to OUTn. In FIG. 18, the illustration of the display panel 80 is omitted. (General operation of the integrated circuit 10) Next, the general operation of outputting the gray scale voltage to the display panel 80 (see Fig. 2) in the integrated circuit 10 will be described below with reference to Fig. 18. First, in the case of normal operation, the test signal is "l", and (4) the word is "H". When the test signal is "L", the switch becomes 〇ff; and the off 2b turns ON. Therefore, the signals from the shift register that are not shown, that is, the STR1 to STRn signals (referred to as the str signal in the case of the general name) are input to the corresponding sampling circuit sampling circuits 6 according to the input. The STR signal obtains the gray scale data corresponding to itself from the gray scale data input terminal via the data bus. The hold circuit 7 inputs the gray scale data obtained by the sampling circuit 6 based on the data [〇八〇 signal] from the sampling circuit. Then, the DAC circuit 8 (output circuit) inputs gray scale data from the holding circuit 7. The DAC circuit 8 converts the input gray scale data into a gray scale voltage signal and outputs it to the positive polarity input terminal of the operational amplifier 1 (comparison mechanism). Here, since the switch 2b is ON', the output of the operational amplifier 1 becomes a negative feedback to its own negative input terminal. Thereby, the operational amplifier 1 operates as a voltage follower. The operational amplifier 1 has a buffer circuit for the gray scale voltage from the DAC circuit 8, and outputs a gray scale voltage signal input to its own positive input terminal to the corresponding output terminals OUT1 to OUTn. Here, the switch 2c is turned on, and the switch 2d is turned off. The actions of switches 2c and 2d are described below. The block including the sampling circuit 6, the holding circuit 7, the DAC circuit 8, and the operational amplifier 1 connected in series to each of the output terminals is used as an output circuit block, and the output circuit block is 143485.doc -38 - 201031180 After the gray scale data input from the gray scale data input terminal is converted into the gray scale voltage for driving the display panel 80 , the converted gray scale voltage is output to the display panel 80 via the output terminal. (Switching to the operation confirmation test) Next, the test for confirming the operation of the operation of the DAC circuit 8 is switched, so that the test signal is "H" and the test B signal is "B". First, when the switch 2a is turned ON, the STR signal for the operation confirmation test, that is, the reference TSTR1彳5, is input to the preliminary sampling circuit 26, and the STR signal for the operation confirmation test, that is, the TSTR2 signal is input to the sampling circuit 6. Further, the gray scale voltage from the prepared DAC circuit 28 is input to the negative polarity wheel-in terminal of the operational amplifier i. Further, by turning off the switch 2b, the output of the operational amplifier 1 is blocked from being negatively fed back to its own negative input terminal. As a result, the operational amplifier 1 is a comparator that compares the output voltage from the DAC circuit 8 connected in series to its own positive input terminal to the output voltage from the standby DAC circuit 28. Φ Furthermore, the test signal and the test B signal are output from a control circuit (not shown) that switches the control operation confirmation test and the operation confirmation test operation. Further, the control circuit (control means) may be a circuit for controlling the gray scale data and the data LOAD signal input via the data "bus" in the operation confirmation test. Further, the control circuit can be the same as the control circuit for controlling the gray scale data, the data LOAD signal, and the shift clock input signal in the normal operation, or can be different control circuits. (Operation Confirmation Test 1 of the First Embodiment) Next, the first sequence of the operation confirmation test will be described below with reference to Fig. 19 143485.doc •39· 201031180. Fig. 19 is a flow chart showing the first procedure of the operation confirmation test of the first embodiment. In step S21 (hereinafter referred to as S21) shown in the figure, the test signal is "Η" and the test B signal is "L". As described above, the operational amplifier 1 of S21' has the function of a comparator. Then, in S22, the counter m included in the control circuit (not shown) is initialized to 0^ and then the 'control circuit makes the TSTR1 signal valid, and the gray scale data of the gray scale m corresponding to the value of the counter m is here. The gray scale data for the gray scale is stored in the preliminary sampling circuit 26 via the data bus. Further, the control circuit asserts the TSTR2 signal and adds the value of the counter m! The gray scale data of the gray scale m+1 and the gray scale data of the gray scale 1 are stored in the sampling circuit 6 via the data bus. Next, the preparatory holding circuit 27 obtains the gray scale data of the gray scale from the sampling circuit 26 based on the data LOAD signal. Further, the DAC circuit 28 inputs the gray scale data from the hold circuit 27, and outputs the gray scale voltage of the gray scale 输出 to the operational amplifier! Negative input terminal (S23). On the other hand, the holding circuit 7 obtains the gray scale data of the gray scale 1 from the sampling circuit 6 based on the data LOAD signal. Further, the DAC circuit 8 inputs gray scale data from the holding circuit 7. Each DAC circuit 8 outputs the gray scale voltage of the gray scale 1 to the positive polarity input terminal of each operational amplifier 串联 connected in series with itself (S23P and the 'integrated circuit 10 of the present invention outputs the gray scale voltage of η gray scale' The gray scale voltage of the order 0 is the lowest voltage value, and the gray scale voltage of the gray scale is η is the highest voltage value. Then the operational amplifier 1 inputs the gray scale voltage from the DAC circuit 8 to the positive polarity input terminal, and The gray scale voltage input from the DAC circuit 28 from the 143485.doc -40·201031180 is input to the negative polarity input terminal for comparison (S24). Specifically, the operational amplifier 1 inputs the gray scale voltage of the gray scale to 1 to its own positive polarity. The input terminal ' inputs the gray scale voltage of gray scale 0 to its own negative polarity input terminal. Here, if the DAC circuit 8 is normal, the gray scale voltage of the gray scale is 1 is higher than the gray scale voltage of the gray scale is 〇 Therefore, the operational amplifier 丨 outputs a signal of "H" level. However, when the output of the operational amplifier is a signal of "L" level, the DAC circuit 8 is defective. ❹ Then, the decision circuit 3 (determination mechanism) Input from the operation put The output signal of the device 1 compares the level of the input signal with the expected value stored by itself. Furthermore, the expected value memorized by the decision circuit 3 is from the control circuit provider. In the action confirmation test 1, the determination is made. The circuit 3 memorizes the expected value as the "H" level. Here, if the signal input from the operational amplifier i and the determination circuit 3 themselves have the same expected value as the "H" level, the determination circuit 3 determines that The DAC circuit 8 is normal. On the other hand, if the signal input from the operational amplifier 为 is "L" level, the decision circuit 3 determines that the DAC circuit 8 is defective, and outputs the H" flag to the decision flag 4. When the self-determination circuit 3 inputs the "H" flag, the determination flag 4 stores the input "H" flag in its own internal memory (S25). Further, the determination circuit 3 may be configured as follows. : Input the output signal from the operational amplifier factory. If the input signal is rH" level, then the flag will be taken out to the judgment flag 4. If the input signal is "1 level, then the port 4 will be _ ” flag—output to decision flag 4. At the time of the determination flag circuit 3, even if the "Η" flag is input once, the flag of 143485.doc -41 - 201031180 is input, and the "L" and "Η" flags are input from the decision circuit 3. When the standard 4 continues to maintain the rating circuit 3, it can become a flag of the person 4 and the rH is produced... When the judgment is judged to be bad, the judgment is not performed, and the subsequent determination operation is not performed, and the counter m is Whether the value is the determination (s26). When the value of the counter m is equal to or less than w, the counter 岐 value is incremented by 1 and the steps S23 to S25 are repeated until the value of m becomes ... 。. The η-series integrated circuit 10 can output the number of gray levels. (Operation Confirmation Test 2 of the First Embodiment) Next, a second procedure of the operation confirmation test will be described below with reference to Fig. 20 . Fig. 20 is a flow chart showing the second procedure of the operation confirmation test of the first embodiment. First, in the operation confirmation test 1, the gray scale voltage input to the positive polarity input terminal of the operational amplifier i is always higher than the gray scale voltage input to the negative polarity input terminal, so that only the lower voltage is output to the DAC in the presence of the signal. In the case of a defective circuit 28, or in the case where there is a defect that only a higher voltage is output to the circuit 8, the decision circuit 3 turns out to indicate a normal "L" flag. Therefore, in the operation check test 2, a lower gray scale voltage than the negative polarity input terminal is input to the positive polarity input terminal of the operational amplifier 而, and the operation is confirmed. First, after the operation confirmation test 1 is completed, the value of the counter m is initialized to 0 (S31). Then the 'control circuit makes the D81's 1 signal valid, and the value of the counter m is increased by 1 to obtain the grayscale data of m+1, which is grayscale 143485.doc •42· 201031180 is 1 The gray scale data is stored in the preliminary sampling circuit 26 via the data bus. Then, the control circuit makes the TSTR2 signal valid, and the gray scale data of the gray scale m corresponding to the counter m, and the gray scale data of the gray scale 于此 are stored in the sampling circuit 6 via the data bus. Here, similarly to S23 of the operation check test 1, the DAC circuit 28 inputs the gray scale data stored in the sampling circuit 26 via the hold circuit 27. Further, the DAC circuit 28 outputs the gray φ step voltage of the gray scale m+1 corresponding to the input gray scale data, and the gray scale voltage of the gray scale 1 to the negative polarity input terminal of the operational amplifier 1. On the other hand, the DAC circuit 8 inputs the gray scale data stored in the sampling circuit 6 via the holding circuit 7. Further, each of the dac circuits 8 outputs the gray scale voltage of the gray scale m corresponding to the input gray scale data, and the gray scale voltage of the gray scale 于此 to the respective operational amplification positive input terminals connected in series with the self (in this case) S32). Then, the operational amplifier 1 compares the gray scale voltage of the gray scale 0 from the DAC circuit 8 input to the positive polarity input terminal with the gray scale voltage of the gray scale 1 from the DAC circuit 28 input to the negative polarity input terminal ( ( S33). Therefore, if the DAC circuit 8 is normal, the gray scale voltage of the gray scale 较 is higher than the gray scale voltage of the gray scale ,, so the operational amplifier i outputs the signal of the "L" flag. Therefore, when the output of the operational amplifier is a signal of "H" level, the DAC circuit 8 is defective. Then, the decision circuit 3 inputs the output signal from the operational amplifier 1, and compares the level of the input signal with the expected value itself. In the operation confirmation test, the determination circuit 3 memorizes the expected value as the "l" level. Here, if the signal input from the operational amplifier 1 is from 143485.doc •43- 201031180

In the memory (S34). Repeat the above illusion 3~3 input the "H" flag flag in its own memory 33~S34 until the value of m becomes n-1 (S35, S36). (Operation Confirmation Test 3 of the First Embodiment) Next, a third sequence of the operation confirmation test will be described below with reference to Fig. 21 . Fig. 21 is a flow chart showing the third sequence of the operation confirmation test of the first embodiment. In the DAC circuit 8, there is a case where the operational amplifier i continues to maintain the gray-scale voltage input to the operational amplifier i by the acknowledgment test that has been performed when there is a problem that the output terminal is open, and the operation confirmation test In 1 and 2, the failure cannot be detected. In the 'operation confirmation test 3, the pull-down circuit is connected to the positive input terminal of the operational amplifier 1. Therefore, when the output of the DAC circuit 8 is open, it will be compared. The low voltage is input to the positive input terminal of the operational amplifier 1. As a result, the operation amplifier can be prevented from being maintained when the output of the DAC circuit 8 is open, in other words, when the DAC circuit 8 has no output. The grayscale voltage input to the operational amplifier 1 is performed by the confirmation test. The specific sequence of the operation confirmation test 3 is as shown in Fig. 21. First, the counter m is initialized to 〇 (S41). Then, the pull-up and pull-down circuit 5 will The positive input terminal of the operational amplifier 1 is pulled down (S42). The steps from S43 to S47 143485.doc -44- 201031180 and the above actions have been performed. Since the steps of tests S23 to S27 are the same, the description thereof is omitted here. As described above, 'the order of the test 1 is checked by pulling down the positive input terminal of the operational amplifier 1', and the output terminal of the DAC circuit 8 is opened. In the case, the operational amplifier 1 outputs a signal of the "L" level. The determination circuit 3 determines that there is a defect in the DAC circuit 8 based on the input "L" level signal, and determines that the flag 4 stores the "η" flag. ^ (Operation Confirmation Test 4 of the First Embodiment) Next, the fourth sequence of the operation confirmation test will be described below with reference to Fig. 22 . Fig. 22 is a flow chart showing the fourth procedure of the operation confirmation test of the first embodiment. Here, the operation check test 4 is used to correspond to the failure of the output end of the DAC circuit 8 in the same manner as the operation check test 3. As shown in the figure, first, the counter m is initialized to 〇 (S51). Then, the pull-up and pull-down circuit 5 pulls up the positive input terminal of the operational amplifier 1 (S52). The steps from S53 to S57 from the start of Φ are the same as the steps S32 to S36 of the above-described operation confirmation test 2, and thus the description thereof is omitted here. As described above, the operation check test 2 is performed by pulling up the positive input terminal of the operational amplifier ,, and when the output of the DAC circuit 8 is open, the operational amplifier 丨 outputs a signal of the rH" level. As a result, the determination circuit 3 determines that there is a defect in the DAC circuit 8 based on the input rH" level signal, and the determination flag 4 memorizes the "Η" flag. (Operation Confirmation Test 5 of the First Embodiment) Next, the fifth sequence of the operation confirmation test will be described below with reference to Fig. 23 143485.doc •45· 201031180. Fig. 23 is a flow chart showing the fifth sequence of the operation confirmation test of the first embodiment. In the DAC circuit 8, there is a case where the two gray-scale short circuits adjacent to each other are generated. As described above, in the case where two adjacent gray scales are short-circuited, the DAC circuit 8 outputs the intermediate voltage of the two gray scales of the short circuit. In this unfavorable situation, the gray scale voltage outputted by the DAC circuit 8 does not deviate from the voltage of 1 gray scale or more as compared with the normal case. Therefore, in the action confirmation test 4, the defect cannot be detected. Here, the purpose of the operation confirmation test 5 is to detect the failure of the two adjacent gray scales in the DAC circuit 8 as described above. The counter m is initialized to 〇 (S6l) as shown in the figure. Then, TSTR1 and TSTR2 are enabled, and further, the gray scale data of the gray scale m, the gray scale data of the gray scale, and the sampling circuit are input to the sampling circuit 26, and then the DAC circuits 28 and 8 are maintained via the data bus. Circuits 27 and 7' obtain self-sampling circuits 26 and 6 for gray scale data of gray scales. Further, the Dac circuits 28 and 8 output the gray scale voltage of the gray scale 输出 to the positive polarity input terminal and the negative polarity input terminal of the operational amplifier 1 (S62). Then, the positive input terminal of the operational amplifier 1 and the negative input terminal are short-circuited by a switch (not shown). Further, in the case of the operation panel identification tests 1 and 2, when it is determined that there is no defect in the DAC circuit 8, the difference between the gray scale voltages input to the positive polarity input terminal and the negative polarity input terminal does not become 1 gray scale or more. Voltage difference. Therefore, by short-circuiting the positive polarity input terminal and the negative polarity input terminal, there is no problem that a large current flows. Here, the same gray scale voltage is input to the two input terminals of the operational amplifier 1 by short-circuiting the positive input terminal of the operational amplifier 1 with the negative terminal 143485.doc -46-201031180 input terminal. Here, since the operation amplifier A has an input/output offset voltage, even if the same gray scale voltage is input to its own two input terminals, the output of the operational amplifier 1 outputs "H" or "L". One. The determination circuit 3 stores the level of the output of the operational amplifier 1 when the positive polarity input terminal and the negative polarity input terminal of the operational amplifier 短路 are short-circuited as an expected value (S63).继 Next, the switch (not shown) is turned 〇FF to cancel the short circuit between the positive input terminal and the negative input terminal of the operational amplifier 1. At this time, the gray scale voltage from the gray scale DAC of the DAC circuit 8 is input to the positive polarity input terminal ' of the operational amplifier ’, and the gray scale voltage from the gray scale DAC of the DAC circuit 28 is input to the negative polarity input terminal. Here, if there is no defect in the DAC circuits 28 and 8, the output of the operational amplifier 1 becomes the same output as the expected value stored in the decision circuit 3. Therefore, the decision circuit 3 compares the output from the operational amplifier 1 with the expected value stored by itself (S64). If the output value from the operational amplifier 1 is different from the expected value, the decision circuit 3 sets the "H" flag. Output to decision flag 4 (S65). Then, by switching a gray scale voltage from the DAC circuit 28 to the positive polarity input terminal of the operational amplifier 1 and inputting the gray scale voltage from the Dac circuit 8 to the negative polarity input terminal by a switch (not shown), switching is performed. The input terminal of the operational amplifier 1 (S66). Here, the same processing as that of S64 is performed (S67). In S67, if it comes from an operational amplifier! The output is different from the expected value stored by itself, and the decision circuit 3 outputs the "H" flag to the decision flag 4 (S68) ^ as described above, by the positive polarity input terminal and the negative polarity input 143485.doc -47 - 201031180 Switching between terminals' Even if the expected value memorized by the decision circuit 3 is "H" level or "L" level, the defect of the dac circuit 8 can be detected. By adding 1 to the value of the counter m, the above steps S62 to S68 are repeated until the value of the counter m becomes η (S69, S70). (Self-repair) Next, with reference to Fig. 24, in the case where the determination flag 4 has a "Η" flag, in other words, in the above-described operation confirmation test 5, the determination circuit 3 determines that the DAC circuits 8-1 to 8- Repair when any of η is defective © Explain. Fig. 24 is a flowchart showing the procedure of self-repairing by switching between the DAC circuit 8 determined to be defective and the standby DAC circuit 28. The determination circuit 3 sets the % flag when it is determined that the DAC circuit 8 is defective. Output to decision flag 4. Further, the "decision flag 4" is input from the "H" flag of the decision circuit 3 and is stored inside itself. Here, the control circuit detects whether or not the "H" is recorded in the determination flag 4 (S7i). When the control circuit detects that the determination flag 4 does not memorize "H", the process proceeds to π. On the other hand, when the control circuit detects that the determination flag 4 has % memory: the determination flag 4·1, The number of "H" flags remembered by each is complex: wide. Here, in the case where it is determined that the flag number of the "H" stored in the flag 4 is plural, the number of flags of the "H" memorized in the flag flag 4 is determined to be S73. On the other hand, in the case where the processing (S72) e and the number of S74 are -, the transition flag MM corresponds to the judgment flag 4 of the memory "H" flag. 143485.doc •48· 201031180 The DAC circuit 8 is switched to the processing of the preliminary DAC circuit 28 (S74). First, when the switching sequence between the defective DAC circuit 8 and the prepared DAC circuit 28 is described, the determination flag 4-1 corresponding to the liquid crystal driving signal output terminal ◦UT1 is stored as "Η". Flagkeeper. The determination flag 4-1 outputs the output signal of the Fiagl which becomes the "Η" level to the switches 2c and 2d. According to the output signal of Flagl, the "η" level has been entered.

The switch 2c of k is turned OFF, and the switch 2d is turned ON. Thereby, the switch 2C disconnects the output terminal of the operational amplifier 1_1 from the liquid crystal driving signal output terminal ουτι. On the other hand, the switch 2d outputs the STR1 signal input to the sampling circuit 6-1 to the sampling circuit 26. Thereby, the gray scale data corresponding to the liquid crystal driving signal output terminal OUT1 is also stored in the sampling circuit 26. Further, the switch 2d connects the output terminal of the operational amplifier 21 to the liquid crystal driving signal output terminal 〇UT1. As described above, the switches 24 and 24 are switched in accordance with the output signal of Flagl from the decision flag 4-1, whereby the defective DAC circuit 8-1 is switched to the standby DAC circuit 28. The person-to-person describes the processing of S73. When it is determined that the number of "H" flags stored in the flag 4 is plural, it is considered that the prepared DAC circuit 28 may be defective. Therefore, in the milk, the control circuit makes the flag of the judgment flag * the hidden flag; ^ all becomes the "L" flag, and then moves to the milk processing. When the person determines _ (No) in S71, after the processing of (7) or after the processing of S74, the control circuit switches the (10) signal to "[", and switches the (4)b signal to "Hj|, and moves to the general Action (Μ) As described above, the process of confirming the test and the self-repair is performed, and the integrated circuit 10 can switch the defective circuit to the prepared DAC 143485.doc -49 - 201031180. In the third embodiment, the preliminary sampling circuit 26 and the holding circuit 27 corresponding to the preparatory circuit u are included. Therefore, not only when the DAC circuit 8 is defective, but also when the sampling circuit 6 or the holding circuit 7 is defective. In this case, it is also possible to switch to the preparatory sampling circuit % and the holding circuit 28. Next, with reference to Fig. 25, the sequence from the power-on of the display device in which the integrated circuit (7) is mounted to the operation confirmation test is performed. Fig. 25 is a flow chart showing the processing procedure from the power supply 2 of the display device = moving to the normal operation after the operation confirmation test. As shown in the figure, first, the display device is powered on. The integrated circuit 10 is initialized, thereby judging flag 4 all become "L" flag (S8l). Then, the control circuit sets the test signal to "H", and switches the integrated circuit 10 to the state of the operation confirmation test after the B signal (S82), and then the control circuit and the integrated circuit 10 perform the above-described operation confirmation test ( S83) Further, the control circuit checks whether or not all the operation check tests 丨5 have been completed, and switches the circuit that has become defective to the standby circuit, and then moves to the normal operation (S84). (According to the operation of the operational amplifier 1) The verification test is based on the assumption that the operational amplifier is not defective. However, there is a possibility that the operational amplifier 1 is defective. Therefore, in the present embodiment, it is preferable to confirm the operation of the operational amplifier 1 before performing the above-described operation confirmation test. Therefore, the operation confirmation of the operational amplifier 1 will be described below with reference to Fig. 26. Fig. 26 is a view showing the configuration of the operational amplifier 143485.doc -50- 201031180 and the configuration of the peripheral circuit for confirming the operation of the operational amplifier 丨. As shown in the figure, switching between inputting the output from the DAC circuit 8 and inputting a specific voltage is shown. S5 is connected to the positive input terminal of the operational amplifier 1. Further, the switch S3 for switching between the two specific voltages Vref1 and Vref2 is connected to the B side of the switch S5 (on the input side of the specific voltage). A switch S6 for switching between an output of the operational amplifier 1 for negative feedback from the operational amplifier 1 and an input specific voltage is connected to the negative input terminal of the operational amplifier 1. Further, for two specific voltages The switch for switching between Vref1 and Vref2 is connected to the B side of the switch S4 (on the input side of the specific voltage). Next, the general operation of the operational amplifier 1 will be described. When the operational amplifier 1 is in general operation, the switch S5 is placed. The A side (the output side of the DAC circuit 8) 'Os the switch S6 is on the A side' is operated by the operational amplifier i as a circuit of the voltage follower. ❹ Next, the following is the procedure for confirming the operation of the operational amplifier 1. First, the switches 51 and 82 are switched to the b side. Thereby, there is no negative feedback of the operational amplifier 1, and the operational amplifier 1 is used as a comparator. Then, the switches S3 and S4 are switched to the A side. Thereby, the positive input terminal of the operational amplifier 1 is input with Vref1, and the negative input terminal is input with Vref2. Here, Vref1 and Vref2 are pre-generated voltages, and vrefl is made. The voltage value is greater than the voltage value of Vref 2. Further, the difference between the voltage values of Vref 1 and Vref2 is greater than the input wheel offset value of the operational amplifier 1. At this time, Vref2 I43485.doc -51- 201031180 of the negative input terminal is higher than the voltage of Vrefl2 input to the positive input terminal, so the amplifier amplifier 1 outputs a signal of "H" level. The determination circuit 3 detects the output from the operational amplifier 1 and compares it with the expected value rH" memorized by itself. Here, when the output of the operational amplifier 为 is "L" level, the determination circuit 3 can determine that the operational amplifier is defective. Furthermore, the expected value memorized by the decision circuit 3 is provided from the control circuit. Secondly, it is also considered that there is a fault in the operation of the comparator by the operational amplifier, and the operational amplifier! can only output the "H" level. Therefore, switches S3 and S4 are switched to the B side, Vref2 is input to the positive polarity input terminal of the operational amplifier ,, and Vref1 is input to the negative polarity input terminal. At this time, the voltage value input to the negative polarity input terminal is higher than the force button input to the positive polarity input terminal. Therefore, the operational amplifier i outputs the "L" level. The decision circuit 3 detects from the operational amplifier! After the output, it is compared with the expected value "L" memorized by itself. Here, when the output of the operational amplifier 为 is at the H" level, the determination circuit 3 can determine that the operational amplifier 1 is defective, and the switches S3 to S6 are cut by the control circuit.

change. Q

[Embodiment 2] Next, a second embodiment of the present invention will be described below with reference to Figs. 27 to 33. In the description of the second embodiment, only the differences from the embodiment will be described, and the description of the overlapping portions will be omitted. First, the differences between the first embodiment and the second embodiment will be briefly described. Implementation form! The output of the DAC circuit 8 is compared to the output of the ready circuit 28 in the arithmetic amplifier. On the other hand, the second embodiment is 143485.doc • 52- 201031180 The two DAC circuits 8 adjacent to each other are grouped and the outputs of the DAC circuits 8 from each other are compared in the operational amplifier 1. (Configuration of Display Driving Semiconductor Integrated Circuit 20) A configuration of the display driving semiconductor integrated circuit (hereinafter referred to as integrated circuit) 20 of the present invention will be described with reference to Fig. 27 . Fig. 27 is an explanatory view showing the configuration of an integrated circuit 2 (an integrated circuit for driving a display device).

The operational amplifier 1 inputs the output from the DAC circuit 8 connected in series to its own positive input terminal. Further, the operational amplifier is to be input from the output of the DAC circuit 8 connected in series to its own operational amplifier to its negative input terminal. Specifically, as shown in the figure, the operational amplifier 1-1 inputs the output from the DAC circuit 8-1 to its own positive input terminal, and inputs the output from the DAC circuit 8_2 to its own negative polarity via the switch 2a. Input terminal. Similarly, the operational amplifier 1-2 inputs the output from the DAC circuit 8_2 to its own positive input terminal, and the output from the DAC circuit 8-1 is input to its own negative input terminal via the switch 2&. Further, the integrated circuit 2A includes the preliminary sampling circuits 26A and 26B, the preliminary holding circuits 27A and 27B, the preparatory circuits 28A and 28B, the operational amplifiers 21 and 21B, and the pull-up and pull-down circuits 25A and 25B. In the reverse of the enemy, the output from the DAC circuit 28A is also input to itself;

The extremely steep input terminal is input from the output (four) switch 2a of the DAC circuit 28B to its own negative input terminal. In the operational amplifier 21B, the output from the DAC circuit 28B is also input to the positive input terminal from S, and the output from the dac circuit is input to its own negative input terminal via the switch 2a. 143485.doc -53- 201031180 (General operation of the integrated circuit 20) In the general operation of the integrated circuit 20, the control circuit sets the test signal to the "L" level and the test 8 signal becomes the same as in the embodiment i. The "H" level β is thereby used, and the DAC circuit 8 converts the gray scale data input from the holding circuit 7 into a gray scale voltage signal and outputs it as a gray scale voltage to the positive polarity input terminal of the operational amplifier 1. Here, since the switch 21? is 〇Ν, the output of the operational amplifier 1 becomes negative feedback to its own negative input terminal. Thereby, the operational amplifier 1 operates as a voltage follower. Thereby, the operational amplifier i buffers the gray scale voltage from the DAC circuit 8 and outputs it to the corresponding output terminals OUT1 to OUTn. (switching of action confirmation test)

In the switching of the operation check test of the integrated circuit 20, the control circuit sets the test signal to the "η" level, and makes the "3 signal" the "[" level. First, since the switch 2a is ON, the TSTR1 signal is input to the sampling circuit 26A and the odd-numbered sampling circuits 6 (sampling circuits 6_丨, 6-3.....6-0-1). Further, the TSTR2 signal is input to the sampling circuit 26B and the even-numbered sampling circuits 6 (sampling circuits 6_2, 6_3, ..., (4). Further, since the switch 2& turns ON, the negative input terminal of the odd-numbered operational amplifiers Input the output from the even-numbered DAC circuits 8 and input the output from the adjacent odd-numbered dac circuits 8 to the negative input terminals of the even-numbered operational amplifiers 1. Also, since the test B signal is at the "L" level Therefore, the switch (10) is turned off. Thereby, the negative output of the output of the operation A||1 is turned to the negative input terminal, and the operational amplifier i becomes the output from the DAC circuit 8 connected in series to itself. Comparator for comparing the outputs of the adjacent selling circuits 8 143485.doc -54 - 201031180 (Operation check test 1 of the second embodiment) The following describes the page sequence of the operation check test of the second embodiment with reference to Fig. 28 . Fig. 28 is a flow chart showing the first procedure of the operation confirmation test in the second embodiment.

. First, the control circuit sets the test signal to the "H" level so that the "Μ B letter Y becomes B" level (S101). Thereby, the operational amplifier 丨 acts as a comparator (S102). Then, the control circuit will an odd number of decision circuits 3 (determination circuits 3-1, 3_3. . . . . The expected value of 3-(n-l)) is set to rL" 〇 s > —.  In respect, the control circuit will have an even number of decision circuits 3 (decision circuit 3-2' 3-4. . . . . The expected value of 3-n) is set to the "H" level. Then, the control circuit initializes the counter claws included in itself to 〇(si〇3). Further, after the control circuit makes TSTR1 valid, the sampling circuit and the odd-numbered sampling circuits 6 input the gray scale data of the gray scale m via the data bus. Further, after the control circuit makes TSTR2 valid, the sampling circuit 26B and the even-numbered sampling circuits 6 input the gray scale data of the gray scale claw + 经由 via the data bus (S104). Here, considering the case where the value of the δ decimator m is 〇, the odd-numbered operational amplifier 1 inputs the gray scale voltage of the gray scale , from the odd-numbered DAC circuits 8 connected in series to the positive polarity of itself. Input terminal. Further, the odd-numbered operational amplifiers 1 input the gray scale voltage of the gray scale 1 from the adjacent even number of DAC circuits 8 to its own negative polarity input terminal. Here, if the DAC circuit 8 connected to the two input terminals of the operational amplifier 1 is normal, the output of the odd-numbered operational amplifier 1 is "L". On the other hand, the even number is 143485. Doc -55- 201031180 The operational amplifier 1 inputs the gray scale (four) of the gray scale 1 from the even number of DAC circuits 8 connected in series to its own positive input terminal. Further, the even-numbered operational amplifier 1 inputs the gray scale voltage of the gray scale , from the adjacent odd-numbered DAC circuits 8 to its own negative polarity input terminal. Here, if the DAC circuit 8 connected to the two input terminals of the operational amplifier 1 is normal, the even-numbered operational amplifier outputs "H". Then, the decision circuit 3 determines whether or not the level of the output signal from the operational amplifier i coincides with the expected value memorized by itself (s1 to 5). Here, when the output from the operational amplifier 不同 is different from the expected value, the determination circuit 3 outputs the "H" flag to the determination flag 4 (s1 〇 6). The above-described processing of S104 to S106 is repeated by incrementing the count value until the value of the counter m becomes 1 (s1〇7, s1〇g). (Operation check test 2 of the second embodiment) Next, a second procedure of the operation check test of the second embodiment will be described below with reference to Fig. 29 . Fig. 29 is a flow chart showing the second sequence of the operation confirmation test in the second embodiment. The operation confirmation test 2 in the second embodiment confirms the operation in which the voltage relationship between the odd-numbered and the even-numbered gray levels in the operation confirmation test 1 in the second embodiment is reversed, and the second and the second The action in the embodiment is the same as the test. First, the control circuit sets the expected value of the odd-numbered determination circuits 3 to H". On the other hand, the expected value of the even-numbered determination circuits 3 is set to L" and the control circuit initializes the counter melon contained therein to 〇 (Siii ) 〇143485. Doc 201031180 Next, after the control circuit makes TSTR1 valid, the sampling circuit 26A and the odd-numbered sampling circuits 6 input gray scale data of gray scale m+1 via the data bus. Further, after the control circuit makes TSTR2 valid, the sampling circuit 26B and the even-numbered sampling circuits 6 input the gray scale data * of the gray scale m via the data bus (S112). Here, if the value of the counter m is considered to be 〇, the odd-numbered operational amplifiers 1 input the gray scale voltage of the gray scale 1 from the DAC circuit 8 connected in series to its own symmetrical circuit DAC circuit 8 to its own positive input. Terminal. Further, the odd-numbered operational amplifiers 1 input the gray scale voltage of the gray scale , from the adjacent even number of DAC circuits 8 to their own negative polarity input terminals. Here, if the DAC circuit 8 connected to the two input terminals of the operational amplifier 1 is normal, the odd-numbered operational amplifiers! The output is at the rH" level. On the other hand, the even-numbered operational amplifier 1 inputs the gray scale voltage of the gray scale , from the even number of DAC circuits 8 connected in series to its own positive polarity input terminal. Further, the even-numbered operational amplifier 1 inputs the gray scale voltage of the gray scale 1 from the adjacent odd-numbered DAC circuits 8 to its own negative polarity input terminal. Thus, if the DAC circuit 8 connected to the two input terminals of the operational amplifier 1 is normal', the output of the even-numbered operational amplifier 1 is the rLj level. Next, the 'decision circuit 3 compares the level of the output from the operational amplifier 与 with the expected value stored by itself (S113). Here, when the output from the operational amplifier 1 is different from the expected value, the decision circuit 3 will "H". The flag is output to the decision flag 4. The value of the counter melon is incremented one by one, and the above processing of SU2 to SH4 is repeated until the value of the counter melon becomes the same (S115, S116). 143485. Doc 57-201031180 (Operation confirmation test 3 of the second embodiment) Next, the third procedure of the operation confirmation test of the second embodiment will be described below with reference to Fig. 3A. The operation confirmation test of the second embodiment is shown. Flow chart of the third sequence. As described in the operation check test 3 of the first embodiment, when the output terminal becomes an open circuit failure in the DAC circuit 8, the operational amplifier 1 continues to be input to the operation by the executed verification test. The gray scale voltage of the amplifier 1 was confirmed in the operation confirmation tests 1 and 2 of the second embodiment. First, similarly to the operation confirmation tests 1 to 2, the control circuit initializes the value of the counter m included in itself to 〇 (s21). Further, in the integrated circuit 2, the pull-up and pull-down circuit 5 is connected to the positive input terminal of the DAC circuit 8. Here, the control circuit controls the pull-up and pull-down circuit 5 so as to pull up the positive input terminal of the odd-numbered operational amplifier ( (S122). As a result, when the output of the odd-numbered DAC circuits 8 is open, a higher voltage is input to the positive input terminals of the odd-numbered operational amplifiers. On the other hand, the control circuit controls the pull-up and pull-down circuits 5 (s 122) by pulling down the positive polarity input terminals of the even-numbered operational amplifiers 丨. As a result, when the output terminals of the even-numbered DAC circuits 8 are opened, a lower voltage is input to the positive input terminals of the even-numbered operational amplifiers 1. The subsequent processing of S123-S127 is the same as that of the operation confirmation test 1 of the second embodiment. Therefore, the description thereof is omitted here. (Action Confirmation Test 4 of Embodiment 2) 143485. Doc - 58 - 201031180 Next, the fourth procedure of the operation confirmation test of the second embodiment will be described below with reference to Fig. 31. Fig. 31 is a flow chart showing the fourth sequence of the operation confirmation test in the second embodiment. The purpose here is to detect the same defect as the above-described action confirmation test 3. First, similarly to the operation confirmation test up to this point, the control circuit initializes the value of the counter m included in itself to 〇 (S13l). Then, the control circuit controls the pull-up and pull-down circuits 5 in such a manner that the positive input terminals of the odd-numbered operational amplifiers 1 are pulled down by Φ (S122). As a result, when the output terminals of the odd-numbered DAC circuits 8 are opened, a lower voltage is input to the positive input terminals of the odd-numbered operational amplifiers 1. On the other hand, the control circuit controls the pull-up and pull-down circuits 5 in such a manner as to pull up the positive input terminals of the even-numbered operational amplifiers (S122). As a result, when the output of the even-numbered DAC circuits 8 is open, a higher voltage is input to the positive input terminal of the even-numbered operational amplifier. The subsequent processing of S133 to S137 is the same as the operation confirmation test ❹ 2 of the second embodiment, and thus the description thereof will be omitted. (Operation check test 5 of the second embodiment) The fifth sequence of the operation check test of the second embodiment will be described below with reference to Fig. 32. Fig. 32 is a flow chart showing the fifth sequence of the operation confirmation test in the second embodiment. As described in the operation check test 5 of the first embodiment, the DAC circuit 8 has a defect in which two gray-scale short circuits adjacent to each other are generated. The purpose of the operation confirmation test 5 of the second embodiment is to detect such a defect. 143485. Doc -59- 201031180 As shown in the figure, first, the control circuit initializes the value of the counter m included in itself to 0 (S141). Next, TSTR1 and TSTR2 are made valid, and the gray scale data of the gray scale m is input to the sampling circuit 26A, the sampling circuit 26B, and the sampling circuit 6 via the data bus. Further, by making the data LOAD signal valid, the odd-numbered DAC circuits 8 and the even-numbered DAC circuits 8 output the gray scale voltage (s 142) of the same gray scale m. Then, the control circuit short-circuits the positive polarity input terminal of the operational amplifier 1 and the negative polarity input terminal via a switch (not shown). By short-circuiting the positive input terminal of the operational amplifier 1 and the negative input terminal, the same gray scale voltage is input to the positive input terminal and the negative input terminal of the operational amplifier 1. The second determination circuit 3 stores the level of the output of the operational amplifier when the positive polarity input terminal of the operational amplifier 1 is short-circuited with the negative polarity input terminal as an expected value (S143). Then, the switch (not shown) is turned OFF, and the short circuit between the positive input terminal and the negative input terminal of the operational amplifier i is released. At this time, the gray-scale voltage of the gray scale m from the odd-numbered DAC circuits 8 connected in series to the odd-numbered input terminals of the odd-numbered operational amplifiers 1 is input, and the input to the negative-polarity input terminal is adjacent to the first The gray scale voltage of the gray scale m of an even number of DAC circuits 8. On the other hand, for the positive input terminal of the even-numbered operational amplifier J, the gray-scale voltage 'from the gray-scale m of the even-numbered DAC circuits 8 connected in series is input', and the input to the negative-polarity input terminal is adjacent to itself. The gray scale voltage of the gray scale m of the odd number of DAC circuits 8. Here, the decision circuit 3 compares the expected value stored by itself with the round-out from the operational amplifier 1 (S144). Furthermore, from the operational amplifier 丄 143485. Doc -60· 201031180 Output, if the expected value of the 5th recall is different, the decision circuit 3 outputs the "H" flag to the decision flag 4. Further, the judgment flag (4) is stored in the "H" flag input from the decision circuit 3 in its own interior. .  , 'The rear control circuit uses a switch (not shown), which will be input from the DAC circuit 8 to the operational amplifier! The signal of the positive input terminal and the signal input to the negative input terminal are exchanged (S146). Thereafter, the same processing as that of S147 is performed (S147). Further, in the same manner as (4), when the output of the self-operated τ amplifier 1 is different from the expected value stored by itself, the determination circuit 3 outputs "H" to the determination flag 4 (S148). The above process of S142 S148 is repeated until the value of the counter claw is n (si49, S150) 〇 (self-repair of the second embodiment), so that the following is described with reference to FIG. 33. When it is determined that there is "H" in the flag 4, in other words, in the above-described operation confirmation test 丨5, the determination by the determination circuit 3 that the DAC circuit 8 is present is present. Fig. 33 is a flow chart showing the sequence in which the table tf is self-repaired by switching between the circuits 28A and 28B which are determined to be defective (the circuit (4) is prepared.  Figure. The f S ' control circuit detects whether or not the determination flag 4 is 彳 "H" (S15D. When the control circuit detects that the determination flag 4 does not memorize "H", it moves to S153. On the other hand, When the control circuit detects the determination flag 4 in which "H" is stored, the D AC circuit 8 corresponding to the judgment flag 4 in which "h" is stored is switched to the standby DAC circuit 2 8 A or 143485. . Doc -61· 201031180 28B. Here, in the second embodiment, since the two DAc circuits 8 are operated as a group, even if the flag "H" is stored in the flag 4, it is impossible to determine which of the DAC circuits in the group is defective. Therefore, in the second embodiment, the DAc circuit 8 corresponding to one of the determination flags 4 in which "H" is stored, in other words, the odd-numbered and even-numbered two DAc circuits 8 are switched to the preliminary DAC circuit 28A. And 28B (S152). Specifically, the following description will be made on the case where the DAC circuit 8-1 has a defect. Here, when there is a problem in the DAC circuit 8-1, by the operation confirmation tests 1 to 5, it is determined that the circuit 丨 and %] both output "Η" to the determination flags 4-1 and 4-2 ^ The determination flags 4_丨 and 4_2 output the "Η" flag input from the decision circuits 3_ and 3_2 to the switches 2c and 2d, and the switch 2c is turned OFF to turn the switch 2d ON. As a result, the sampling circuit 26A inputs the STR1 signal, and the sampling circuit 26B inputs the STR2 signal. Thereby, the sampling circuit μα obtains the gray scale data corresponding to the liquid crystal driving signal output terminal OUT 1 from the data bus and the sampling circuit 26B obtains the gray scale corresponding to the liquid crystal driving signal output terminal OUT2 from the data bus. data. Further, since the switch 2c is OFF', the output terminal of the operational amplifier 1_1 is disconnected from the liquid crystal driving signal output terminal OUT1, and the output terminal of the operational amplifier 1_2 is connected to the liquid crystal driving signal output terminal OUT2. open. Further, since the switch 2d is turned on, the output terminal of the operational amplifier 21A is connected to the liquid crystal driving signal output terminal OUT1, and the output terminal of the operational amplifier 21B is connected to the liquid crystal driving signal output terminal OUT2. As described above, the defective DAC circuit 8 and its paired DAC circuit 8 are switched into a set of DAC circuits 28A and 28B as a group, thereby 143485. Doc • 62· 201031180 It is possible to switch the defective DAC circuit 8 to the prepared DAC circuit 26A or 26B ° and then the 'control circuit makes the test signal "L", and the test B signal is "H", then move to the general action ( S153). [Embodiment 3] In the first embodiment and the second embodiment described above, the gray scale voltage from the output circuit block 30 (see Fig. 2) and the gray scale from the preliminary output circuit block φ 40 (refer to Fig. 2) The switching circuit 60 (see FIG. 2) for switching between voltages is included in the integrated circuits 10 and 20. However, the present invention is not limited thereto, and the switching circuit 60 may be configured to be included on the display panel side. Hereinafter, the display unit 9A of the switching circuit 60 will be included on the display panel side, and the configuration and operation will be described as a third embodiment of the present invention. In the present embodiment, differences from the embodiment will be described, and the description of the overlapping portions will be omitted. (Schematic configuration of display unit 90') First, the schematic configuration of display unit 90 of the present embodiment will be described with reference to Fig. 34. Fig. 34 is a block diagram showing a schematic configuration of the display unit 9A. As shown in Fig. 34, the display unit 9A includes a display panel 8A, and an integrated circuit 丨〇| (driver) that drives the display panel 8A according to grayscale data input from the outside. Circuit). Here, the integrated circuit 1A differs from the integrated circuit of the embodiment in that the switching circuit 6 is not included, and the other configuration is the same as the configuration X of the integrated circuit 10, and the panel 8 is displayed. The difference from the display panel 80 of the first embodiment is that the switching circuit (9) is included, and the other configuration is the same as that of the display panel 80. 143485. Doc • 63· 201031180 (Configuration of display unit 90) Next, a more detailed configuration of the display unit 90 of the present embodiment will be described with reference to Fig. 35 . Fig. 35 is a block diagram showing the configuration of the integrated circuit 1A. As shown in FIG. 35, the integrated circuit 1A includes: n sampling circuits 6 which are input from the gray-scale data input terminals (not shown) via the data bus and input to the respective n output terminals OUT 1 to OUTn. Corresponding gray scale data; n holding circuits 7; DAC circuit 8 for converting gray scale data into gray scale voltage signals; and operational amplifier 1' having a buffer circuit for gray scale voltage signals from DAC circuit 8; n determination circuit 3; and n pull-up and pull-down circuits 5 °, and as shown in FIG. 35, the integrated circuit 1 includes a plurality of switches 2a that switch between ON and OFF according to the test signal; The test B signal is a plurality of switches 2b that switch between ON and OFF; and a plurality of switches 2f that switch between ON and OFF according to the LF (Low Frequency 'low frequency) signal. Further, the switches 2a, 2b, and 2f are on when the "H" signal is input, and are OFF when the "L" signal is input. Further, the integrated circuit i〇 includes one of the following circuits: a prepared sampling circuit 26, a preliminary holding circuit 27, a preliminary DAC circuit 28, a preliminary operational amplifier 21, and a preliminary output terminal 〇uT〇. On the other hand, as shown in FIG. 35, the display panel 80' includes connection terminals (not shown) connected to the output terminals OUT1 to OUTn included in the integrated circuit 10'; the determination flag 9-^9 ^ (hereinafter, referred to as the judgment flag 9 in the case of the general term); the switch 2f that switches between ON and OFF according to the signal from the control circuit (not shown); the inverted signal 143485 according to the LIMt number . Doc -64- 201031180 is the switch 2e for switching the LFB (Low Frequency Band) signal between 〇N and off; and ON and OFF according to the output signal from the decision flag 9, that is, Flag 1 to Flagn Switches 2c and 2d are switched between. Further, the switches 2d, 2e, and 2f are ON when the Γ η signal is input, and 〇 FF when the "L" signal is input. Further, the switch 2c is turned ON when the "L" signal is input, and is turned OFF when the "H" signal is input. φ Further, the display panel 80' in the present embodiment is a liquid crystal display panel, and the data signal lines SL-1 to SL-n (hereinafter, referred to as the data signal line SL in the case of a general term) are switched via the switch as shown in FIG. 2e and 2c are connected to the respective output terminals out of the integrated circuit 1A. Further, the number of pixels P having the same number as the scanning signal line (31) is connected to each of the data signal lines SL. Further, in FIG. 35, the pixel P connected to the data signal line SL-1 is taken as the pixel P-1. The pixel P connected to the data signal line SL-n is used as the pixel pn. (Self-repair of the third embodiment) • Next, the result of the operation confirmation test in the display unit 9A of the present embodiment is the determination flag 4 The self-repairing operation in the case where the "H" flag is stored will be described. The method of the operation confirmation test in the present embodiment is the same as the operation confirmation test 丨5 described in the first embodiment, and therefore is omitted here. Description of the operation confirmation test First, at the time point when the operation confirmation test 5 ends, the signal is H"' test B signal becomes rL" e. Therefore, the operational amplifier 1 and the output terminal 〇UT are switched by the switch ^ The connection is disconnected. Here, after the operation confirmation tests 1 to 5 are completed, the control circuit outputs the "H" (10) signal, and: 143485. Doc •65- 201031180 The LFB signal of "L". By outputting the "h" signal, the switch ^ is turned ON. Each of the determination flags 4 is connected to each of the determination flags 9 via the respective output terminals (10) τ. Further, each of the determination flags 4 has its own "H" flag or L" flag as Flagl~Flagn, and is output to each of the judgment flags 9 via the respective output terminals 〇υτ @. Flag1~Flagn of the decision flag 4 output are memorized in its own internal memory and output to the switch 2 connected to itself. And 2廿. Furthermore, when the LF signal is "H", the LFB signal is "L", so each switch (4). Thereby, it is prevented that the Flag!~Flagn outputted by the determination flag 4 is output to the data signal lines ◎ 1 to SL-n, and as a result, it is determined that the correction outputted by the flag 4 does not affect the pixel P. Hereinafter, as a detailed description of the self-repairing operation in the display unit 9A, the case where the determination flag 4_丨 corresponding to the output terminal OUT1 is stored with the "H" flag will be described as an example. "First, when the judgment flag 4_丨 corresponding to the output terminal OUT1 stores the "H" flag, in other words, when the DAC circuit 81 is defective, the self-decision flag 4 in the flag 9] is judged. The output has the "H" flag and the flag "output" of © is recorded in the internal memory contained in itself. Furthermore, in this example, the determination flags 4_2 to 4_n are recorded with the "l" flag. Then, the decision flag 9] outputs the FUgl of the "H" flag to the connection; on its own switch 2. And 2 (1. By means of the switch connected to the judgment flag 9], the connection of the output terminal OUT1 and the data signal line sl] is cut off, and the switch of the determination flag W is connected to the output terminal 〇 Υτ〇 is connected to the data signal line SL-i. On the other hand, 'each judgment flag 9·2~ pair connection ^ from 143485. Doc -66- 201031180 The switches 2c and 2d of the body output Flag2~Flagn of the "L" flag, so the switch 2c connected to the judgment flags 9-2~9-n becomes ON' is connected to the judgment flag 9_ 2~9 The switch 2d of -n becomes 〇FF. As a result, the respective data signal lines SL_ 2 to SL-n are connected to the respective output terminals 〇υΤ2 to ουΤ via the switch 2e*. Each of the determination flags 9 outputs a LF signal of "L" after the switching of the switches 2c and 2d connected to itself based on Flag1 to Flagri from the determination flag 4, and outputs a 叩 signal of rH". Thereby, the respective output φ terminals OUT2 to OUTn are connected to the respective data signal lines SL-2 to SL-n. Next, after the control circuit outputs the "L" 2LF signal, the test signal of "L" and the test b signal of "H" are output, whereby the data signal line π" is connected to the output terminal of the operational amplifier 21 via the output terminal ουτο, and On the other hand, the respective data signal lines SL-2 to SL-n are connected to the operational amplifiers W to ^ via the output terminals 〇xjT2 to 〇UTn. Further, the switch 2d connected to the sampling circuit Η becomes (10) based on the judgment flag center (1) (10), and therefore the gray scale data input to the sampling circuit 6-1 (corresponding to the data signal line SL-1) Also input to the sampling circuit %. As a result, the gray scale data corresponding to the data signal line SL-丨 is output from the output terminal 〇υτ〇, and instead of the input terminal 〇im input to the data signal line SL_b, the input to the sampling circuit 6 and each preparation The switching of the gray scale data of the sampling circuit 26 is the same as that of the actual (four) state 1, and thus a detailed description thereof will be omitted herein. As described above, the display unit 90 performs a self-repairing operation, whereby the preliminary DAC circuit 28 can be used instead of the DAc circuit 8 which is detected as defective, and the normal gray scale voltage is output to the data 酴 green _ D 諕 line SL. Furthermore, in the same manner as the embodiment ’, the present embodiment also includes a circuit Μ opposite to the preparatory circuit 143485. Doc •67· 201031180 Prepared sampling circuit 26 and holding circuit 27. Therefore, not only the DAC circuit 8, but also the sampling circuit 6 or the holding circuit 7 may be switched to the preliminary sampling circuit 26 and the holding circuit 28. Next, the sequence of the display unit 90 from the power-on to the operation confirmation test and then to the normal operation will be described with reference to Fig. 36'. Fig. 36 is a flow chart showing the processing procedure from the time when the power is turned on from the display unit 90 to the normal operation after the operation check test is performed. As shown in FIG. 36, first, the display unit 90 detects that the integrated circuit 10 is initialized after the user turns on the power, so that all the flags memorized by the determination flag 4 become the "L" flag (S161). ). Then, the control circuit sets "the signal to "H" and sets the test B signal to "L", and then switches the integrated circuit 1 to the state of the operation confirmation test (S162). Next, the control circuit and the integrated circuit 1 perform the above-described operation check test (S163). Further, the control circuit confirms whether or not all the operation check tests 1 to 5 are completed (s i 64). When the control circuit detects that not all of the operation confirmation tests 1 to $ have been completed in the S1 64, the display unit 90 shifts the processing to S163' to perform an unfinished operation confirmation test based on an instruction from the control circuit. On the other hand, if the control circuit in si64 confirms that all the operation confirmation tests in the display unit 90' have been completed, the LF signal of "H" and the LFB signal of "L" are outputted to detect a defective circuit (sampling circuit) 6. In the case of the holding circuit 7, the DAC circuit 9, and the operational amplifier 1), the defective circuit is switched to the preparatory circuit (sampling circuit 26, holding circuit 27, DAC circuit 29, operational amplifier 21) and then moved to the general operation ( S165). Further, in the present embodiment, the display unit 9A is used as the memory determination unit 143485. Doc -68 - 201031180 The result of the determination of the path 3-1, that is, the circuit of the flag includes the configuration of the determination flag 4 and the determination flag 9. However, as a modification of the display unit 90', the determination flag 9 may not be included. The switch 2f and the switch 2e are arranged, and the flag 4 is controlled to control the switches 2c and 2d. At this time, it is not necessary to control the LF signal and the LFB signal of the switches 2f and 2e. On the other hand, wirings and connection terminals for connecting the determination flag 4 to the switches 2c and 2d are required. [Embodiment 4] In the first to third embodiments described above, the integrated circuit and the display panel are connected via the output terminal OUT, but the integrated circuit and the display panel are integrated without the output terminal OUT. Also included in the scope of the present invention. Hereinafter, a display unit 90" in which an integrated circuit and a display panel are integrated will be described as a fourth embodiment with reference to Fig. 37. Furthermore, the display unit 90" of this embodiment is an embodiment! In the modification of the display unit 90, the difference from the first embodiment will be described in the present embodiment, and the description of the overlapping portions will be omitted. (Configuration of Display Unit 90" First, the configuration of the display unit 9A of the present embodiment will be described with reference to Fig. 37. Fig. 37 is a block diagram showing the configuration of the display unit 90" As shown in Fig. 37, the display unit 90 is shown. The integrated circuit 10 and the display panel 80 shown in the first embodiment are not different, and the output terminals of the operational amplifiers 1 and 21 are directly connected to the data signal line sl via the switches 2b, 2c, and 2d. That is, the difference between the display unit 90" in the present embodiment and the display unit 9 in the first embodiment is whether or not the output terminal OUT is included, and other configurations and implementations are 143,485. Doc •69- 201031180 The display unit 90 of the form 1 is the same. In the present embodiment, a modification of the first embodiment will be described. However, in the same manner as in the second and third embodiments, the integrated circuit and the display panel are integrated without the output terminal OUT. It is included in the scope of the present invention. (Television System) Next, a television system 300 including the display unit 90 of the first embodiment will be described with reference to Fig. 38. Further, Fig. 38 is a block diagram showing the configuration of the television system 300. In the following description, the television system 300 will be described as the display unit 90 according to the first embodiment. However, the television system of the present invention is not limited thereto, and the display device according to the second to fourth embodiments may be used instead of the display unit 90. Composition. (Configuration of Television System 300) As shown in FIG. 38, the television system 300 includes an antenna 301 that receives a broadcast wave, and a tuner section 302' that demodulates the received broadcast wave into a video sound signal; the signal separation section 303, The image and audio signal is demultiplexed into a video signal and a sound signal; the video signal processing unit 304 decodes the separated video signal into a digital video signal; and the display unit 90 obtains the digital video signal of the solution Gray scale data, and displaying an image on the display panel 80 (refer to FIG. 2) according to the obtained gray scale data; the sound signal processing unit 3〇5' decodes the separated sound signal into a digital sound signal; and the sound signal output The part 306 converts the decoded digital sound signal into an analog sound signal, and converts the analog sound signal as a sound from the speaker wheel 0 143485. Doc •70- 201031180 (Operation of TV system 300) Next, explain the action processing in the TV system. First, the antenna 301 receives the broadcast from the broadcast station and sends the received broadcast wave to the tuner section 302. Tune ||shirt,. , must be adjusted to the part 3G2 to demodulate the output broadcast wave into a shirt image sound signal and output it to the letter • knife away from 0P 303 Ms 唬 separation unit 303 The image sound signal outputted by the long-term is separated into image signal and sound signal and The wide number is output to the video signal processing unit 3G4 and the audio signal processing unit φ K like the signal processing unit 3. The decoded video signal is decoded into a digital video signal, and the decoded digital video signal is output as gray scale data to the display. Not part 90. The display unit 90 displays the output gray scale data using the display panel (10) included in itself. On the other hand, the sound signal processing unit 3〇5 interprets the sound signal separated by the signal separating unit 303 into a digital sound signal and outputs it to the sound output unit 3〇6. The audio signal output unit 306 converts the digital sound signal into an analog sound signal, and outputs the analog sound signal as a sound using the speaker included in the sound signal. Further, the television system 30 of the present invention has a configuration in which the video signal is obtained from the broadcasting station using the antenna 3〇1 and the tuner unit 302 as a mechanism for acquiring video and audio signals, but the present invention is not limited thereto. For self-recording media.  Reading out a content such as a DVD player recorded on the content of the recording medium.  A reading device or a component that acquires data from the Internet or the like via a PC (personal computer). The operation confirmation test and the self-repair processing operation described in the first embodiment and the fourth embodiment are configured to perform the operation immediately after the liquid crystal driving semiconductor integrated circuit 1 is turned on, but the present invention is not limited thereto. This is also 143485. Doc-71 - 201031180 The configuration is performed by inputting a control signal to the liquid crystal driving semiconductor integrated circuit ίο, and the above operation can be performed at an arbitrary timing. For example, it is also possible to perform an operation confirmation test and self-repair by inputting a signal indicating a return period of the display to the liquid crystal driving semiconductor integrated circuit "0" from the controller of the display device. In addition, the operation of the operation confirmation test and the self-repair process may be performed at the following point in time, that is, the circuit for detecting the abnormality of the liquid crystal driving semiconductor integrated circuit 10 is formed in the liquid crystal driving semiconductor integrated circuit 1A. This operation is performed when an abnormality occurs in the semiconductor integrated circuit 10 for driving. For example, the current of the signal output from the liquid crystal driving semiconductor integrated circuit 10 can be measured and the operation confirmation test and the self-repair processing operation can be performed when the detected current exceeds the set current. Further, the action confirmation test and the self-repair process can be performed periodically. For example, the operation may be performed during each vertical flyback period in which display is not performed, or may be performed at each accumulated display time set in advance. Further, the operation confirmation test and the self-repair processing operation can also be performed in one of the periods during which the display is performed. For example, since the pixel is recorded as the display voltage in the liquid crystal display device, even after the charging of the display voltage is completed, even if the output of the liquid crystal driving semiconductor integrated circuit 10 is made high impedance, there is no problem in display. In the portion of the display period, the output of the semiconductor integrated circuit 10 for liquid crystal turbulence is made high impedance, and the operation confirmation test and the self-repair processing operation are performed. At this time, 'If you do not perform all the operation confirmation test mode: time', you can also perform the judgment of, for example, the mode in the part of the display period of the W line', and also during the display period of the one face or several displays U3485. Doc -72- 201031180 During the period of the face. Further, in the integrated circuit of the present invention (see Fig. 18), in order to perform self-detection (operation check test) on its own defect, it is necessary to stop the output signal for driving the display panel 8G (see Fig. 2). That is, the integrated circuit 1 cannot drive the display panel 80 during the self-detection. Therefore, the time during which the integrated circuit 10 performs the self-detection must be performed during a period in which the display of the image of the display device is not affected. In the embodiment of the present invention, as an example in which the integrated circuit 10 performs self-detection, the integrated circuit 10 performs self-detection and self-repair in the startup process when the power of the display device is turned on. The reason is that, during the startup of the display device, since the display device does not display the display of the image, the integrated circuit 10 can perform self-detection without affecting the display of the image of the display device. Self-healing. As described above, the integrated circuit 10 of the present embodiment performs self-detection for detecting self-defects during startup of the display device when the power is turned on. However, the invention is not limited thereto, and may be performed during the startup of the display device. Self-test and self-repair in other periods. Hereinafter, a period in which self-detection and self-repair can be performed other than during the startup of the display device will be described as an embodiment. [Embodiment 1] (Self-detection and self-repair during vertical return to her) First, as a first embodiment, in the vertical flyback period of the display device, the integrated circuit 10 can display the image of the display device without Self-detection and self-healing in the state of influence. The reason is explained below. 143485. Doc -73- 201031180 The next step 3, Fig. 39(a) to Fig. 39(f), is the date and time of the input to the display device. 39(a) to 39(f) are timing charts showing the timings of signals input to the liquid crystal display device. 39(4) shows the output from the scanning side driving circuit of the scanning line of the driving display device; the scanning signal SCN1 '(4)(b) supplied to the first scanning signal line of the display device indicates the output from the scanning side driving circuit The scanning signal SCN2 of the second scanning signal line of the display device is not provided, and the figure (e) represents the jth of the self-integrated circuit 1〇 (refer to FIG. 18) provided to the image signal inversion circuit and the display device The image signal DSj corresponding to the root data signal line, the image (D) of the image signal DRVj corresponding to the jth data signal line of the display device is not supplied from the image signal inversion circuit to the data side driving circuit, The figure (e) shows the image signal DATAj ' supplied to the jth data signal line of the display device. The figure (f) shows the pixel connected to the first scanning signal line and the jth data signal line connected to the display device. The applied driving voltage VDlj°, the period τν of the time t1 to t5 shown in FIG. 39 is the vertical scanning period of the display device 'the period during which the TV1 is the vertical return period, and the period TH of the time t1 to t3 is the horizontal scanning period, the time Period t2~t3 TH1 horizontal flyback interval. Furthermore, the image inversion circuit is a circuit that inverts the polarity of the image signal DSj from the integrated circuit 10 during each horizontal scanning period TH and the vertical scanning period so that the display is performed in each pixel of the display device. The polarity of the electrodes is reversed. As shown in FIGS. 39(a) and (b), the scanning side driving circuit sequentially delays the horizontal scanning period ΊΉ from the first scanning signal line, and outputs the scanning signal SCN1 to each scanning signal line of the display device. Scanning signal I43485. Doc • 74· 201031180 SCN2. . . . . Scan signal SCNm. Further, the scanning side driving circuit is for each vertical scanning period TV, and the scanning signals SCN1 to SCNm are repeatedly output to the respective scanning signal lines of the display device. Furthermore, here, the display device includes m scanning signal lines. The image signal DSj from the integrated circuit 1A shown in Fig. 39 (c) is input to the image signal inverting circuit. Then, the image signal inversion circuit inverts the polarity of the image signal DSj during each horizontal scanning period TH, and inverts the polarity of the image signal DSj during each vertical scanning period to generate FIG. 39(d). The image shown is #DRVj. Further, the video signal inverting circuit inputs the generated shirt image 彳s number DRVj to the data side drive circuit. Then, the negative-side driving circuit samples the image signal DRVj from the image signal inverting circuit during each horizontal scanning period TH, and delays the sampled signal value by one horizontal scanning period, as shown in FIG. 39(e). The image signal DATAj is output to the first data signal line of the display device. Then, in a pixel connected to the display device of the first scanning signal line and the jth data signal (hereinafter referred to as pixel (1), the pixel 〖j is obtained by the scanning signal SCN1 during the horizontal scanning of the time center 2 The result is that the TFT is turned on. The result is applied to the display electrode in the pixel 1j as the driving voltage v by the image signal voltage of the image L number DATAj at the time t1 to t2 via the jth data signal line. That is, it is convenient for the time port 〜c to turn off the turn-on of the TFT in the pixel". The driving voltage vmj applied to the display electrode of the pixel lj continues to maintain the voltage level during the time (four). Similarly, it is connected to the first root. The scanning signal line and the jth data signal line are displayed 143485. Doc -75.  In the pixel of the display device (hereinafter referred to as pixel 2j), the TFT in the pixel 2j is turned on by the scanning signal SCN2 in the horizontal scanning period TH at time t3 to t4, and the result is via the jth data signal line. The video signal voltage of the image k number DATAj at time t3 to t4 is applied as a driving voltage to the display electrodes in the pixels. Here, even if the TFT in the pixel hook is turned off, the driving voltage applied to the display electrode of the pixel 2j is maintained at the voltage level during the period from time t3 to time t4. As described above, even if the TFTs in the respective pixels are turned on, the driving voltage in each pixel of the display device is maintained at the voltage level of the driving voltage applied when the TFT is turned on. Thereby, the scanning side driving circuit does not output the scanning parameters scni to SCNm for turning on the TFTs of the respective pixels to the scanning signal line, in other words, during the period in which the TFTs of the respective pixels are turned off, that is, the vertical return period TV1, The display device does not need to apply a voltage to the display electrodes of the respective pixels. In other words, the integrated circuit 10 does not need to output the video signal DSj, which is the source of the driving voltage, and does not affect the image display of the display device even if the integrated circuit 1 is electrically disconnected from the display device. Therefore, in the vertical flyback period of the display device, the integrated circuit 1 can perform self-detection and self-repair without affecting the image display of the display device. (Detection of malfunction of the entire integrated circuit 10) The self-detection processing of the defective output circuit block included in the integrated circuit 10 of the present embodiment is performed for each data signal line. The output circuit block is processed for the entire output circuit block. Thereby, the self-detection process takes time. 143485. Doc •76- 201031180 II's inviting circuit. In the case of the possibility of each of the included circuit blocks, the integrated circuit ig does not need to perform the self-detection operation: the two-integrated circuit 10 has only the reference in each output circuit block. In the case of <, self-detection processing may be performed. The full =: body circuit 10 includes an operation determining circuit, and it is possible for the integrated circuit 10 to have a malfunction, and it is only necessary to determine by which the integrated circuit 10 has an action. Bad feelings

Self-detection processing at the time of the shape prevents the self-detection process in vain. The operation determination circuit 200 for determining whether or not there is a possibility of malfunction in the entire path included in the integrated circuit 1A will be described below with reference to Figs. 40 to 42. First, when a malfunction occurs in the integrated circuit 10, the power supply current supplied to the integrated circuit 1G is higher than that in the normal operation, in other words, compared with the initial stage when it is judged to be a good product when it is shipped as a product. Therefore, when the value of the power supply current supplied to the integrated circuit 1 is larger than the fixed value, the integrated circuit 10 may cause malfunction. Therefore, the operation determination circuit 200 detects the value of the power supply current supplied to the integrated circuit 10, and determines whether or not a malfunction has occurred in the integrated circuit 10 based on the value of the detected power supply current. (Configuration of Operation Determination Circuit 200) Hereinafter, the configuration of the operation determination circuit 200 will be described with reference to Fig. 40. Fig. 40 is a block diagram showing the configuration of the operation judging circuit 2A. As shown in FIG. 40, the 'action determination circuit 2' is between the VA 201 and the integrated circuit 1A for supplying power to the integrated circuit 1A, and includes a resistor 2〇2 (detection mechanism) 143485.doc -77- 201031180 and Switch 203. Further, the resistor 202 and the switch 203 are connected in parallel to each other. Further, the operation determination circuit 200 includes an A/D converter 204 (detection mechanism) connected to one end of the resistor 202 and the switch 203 on the side of the integrated circuit 10, and a switch 205 whose input is from the A/D converter 204. Output signal; EEPROM (Electrically Erasable and Programmable Read Only Memory) 206 (normal current value memory mechanism), which is a non-volatile memory connected to an output terminal of one of the switches 205; A data latch circuit 207 connected to the other output terminal of the switch 205; and a comparison circuit 208 (current value comparing means, drive circuit determining means) for outputting the output value of the EEPROM 206 and the output from the data latch circuit 207 Values are compared. Further, the output terminal of the comparison circuit 208 is connected to a control circuit included in the integrated circuit 10, and outputs the comparison result in the comparison circuit 208 to the control circuit. Furthermore, the switching of the switches 203 and 205 is controlled by the control circuit included in the integrated circuit 10. (Schematic Operation of Operation Determination Circuit 200) The operation determination circuit 200 stores the value corresponding to the power source current value when the integrated circuit 10 operates normally as the reference data in the EEPROM 206. Here, the operation determination circuit 200 detects a value corresponding to the power supply current value supplied to the integrated circuit 1 when determining whether or not the integrated circuit 10 has a malfunction, and detects the detected value with the EEPROM. 206 The value of the reference data stored in advance is compared. When the detected value is equal to or greater than the fixed value, it is determined that the integrated circuit 10 has a malfunction. Further, the operation determination circuit 200 outputs, to the control circuit 143485.doc •78-201031180 included in the integrated circuit 10, a signal indicating that a malfunction has occurred in the integrated circuit ί, whereby the control circuit starts self-detection of the integrated circuit 10. Processing and self-healing processing. (Generation and Memory Processing of Reference Data) As described above, the operation determination circuit 200 needs to store the reference data in advance in the EEPROM 206 included in itself. Therefore, a process for the operation determination circuit 200 to store the reference data in the EEPROM 206 will be described below with reference to FIG. Fig. 41 is a flow chart showing the operation of the operation determination circuit 200 for storing the reference data in the EEPROM 206. As shown in Fig. 41, when the reference data is generated, the control circuit turns on the switch 203 to cause the power source current from the VA 201 to flow in the resistor 202 (S301). Here, the resistance value of the resistor 202 is such that the voltage of the resistor 202 when the integrated circuit 10 operates normally becomes a resistance value of about 0.1 V. Furthermore, the resistance value of the resistor 202 should be determined in consideration of the current consumption of the integrated circuit. Then, the A/D converter 204 converts the voltage value at one end of the integrated circuit 10 side of the resistor 202 into a digital value (S302). The A/D converter 204 inputs the converted digital value to the EEPROM 206 via the switch 205. The EEPROM 206 memorizes the input digital value from the A/D converter as a base material (S303). Furthermore, the switch 205 in S303 is switched by the control circuit to connect the A/D converter 204 to the EEPROM 206. Then, after the EEPROM 206 memorizes the basic data, the control circuit short-circuits the switch 203 to return the integrated circuit 1 to the normal operation state (S3〇4). Furthermore, the generation and memory processing of the reference data from S301 to S304 is performed at the factory stage of the display device including the integrated circuit 10, in other words, 143485.doc -79· 201031180 in the integrated circuit ι by various It is judged to be normal at the factory inspection. (Operation failure detection processing of the operation determination circuit 200) Next, a process of detecting the malfunction of the integrated circuit 10 by the operation determination circuit 200 will be described below with reference to Fig. 42. Fig. 42 is a flowchart showing the processing of the malfunction of the detected integrated circuit 10 in the operation determining circuit 200. As shown in Fig. 42, first, the control circuit opens the switch 203 to cause the power source current from the VA 201 to flow in the resistor 202 (S305). Then, the A/D converter 204 converts the voltage value of the resistor 202 to one end of the integrated circuit 10 side into a digital value (S306). The A/D converter 204 inputs the converted digital value to the data latch circuit 207 via the switch 205. The data latch circuit 207 memorizes the input digital value from the A/D converter as detection data (S307). Further, the switch 205 in S306 is switched by the control circuit to connect the A/D converter 204 and the data latch circuit 207. Then, the comparison circuit 208 reads the reference data stored in the EEPROM 206 and the detection data memorized by the data latch circuit 207, and compares the value of the read reference data with the value of the detected data (S308). Further, the comparison circuit 208 detects whether or not the difference between the value of the reference data and the value of the detection data is equal to or greater than a specific value (for example, three or more digits) (S309). In the case where the difference between the value of the reference data and the value of the detection data is a specific value or more (for example, when the digital value is 3 or more), a signal indicating that the malfunction of the integrated circuit 10 is generated is output to the integrated circuit. 10 control circuits included. Here, the control circuit inputs a signal indicating that the 143485.doc -80·201031180 in the integrated circuit 10 has caused a malfunction, and starts the self-check of the integrated circuit 10 (), and further, in the integrated circuit. When the self-detection integrated circuit 1 detects a defect in its own output circuit block, the integrated power _ switches the output of the defective output circuit block to the output of the positive output circuit block. Self-healing. Further, when the failure of the output circuit block cannot be detected in the self-detection of the integrated circuit 10 of S3u, the fluctuation of the power supply current value due to other factors is considered. Therefore, at this time, since the power supply current value fluctuates, the operation determination circuit 200 generates the reference data shown in S301 to S304 and performs the memory processing, and stores the generated power supply current value as the new reference data in the EEpR〇M. 2(10) (S312). Further, after S312, the control circuit short-circuits the switch 2〇3 to cause the operation determination circuit 2〇〇 and the integrated circuit 丨〇 to be in a normal operation state (S310). On the other hand, in S309, when the comparison circuit 2〇8 detects When the difference between the value of the reference data and the value of the detected data is less than a specific value (for example, φ is represented by a digital value but less than 3), the process proceeds to S3 10. [Embodiment 2] (Self-detection of the integrated integrated circuit 10) Further, self-detection (operation confirmation test) and self-repair of the integrated circuit 10 may be performed periodically. Specifically, the self-detection (action confirmation test) and self-repair of the integrated circuit 10 can be performed during each vertical flyback period of the display device as described in the above embodiment i. At this time, the vertical sync signal is counted, and the above self-detection and self-repair are performed in each fixed number of displays. At this time, the counter is composed of non-volatile memory, and counting 143485.doc -81 - 201031180 counts the number of vertical sync signals, thereby achieving this. Further, the integrated circuit 10 may include a timer for measuring time, and the operating time is counted by the timer, and the self-detection of the integrated circuit 1G is performed for each predetermined accumulated operation time. And self-healing. [Embodiment 3] Further, the self-detection (operation confirmation test) and the self-repair processing operation of the integrated circuit 10 may be performed in a part of the period during which the display device performs video display. For example, each of the display devices f memory the voltage of the display electrode. Therefore, after the charging of the voltage of the display electrode is completed, the display of the image in the display device is displayed even if the output terminals OUT1 to QUTn of the integrated circuit 1 are made high impedance. There are still no problems. Therefore, in one of the display periods during which the display device performs video display, the outputs #子〇UT1 to 〇UTn of the integrated circuit 10 are made high impedance, and self-detection (operation confirmation test) and self-repair processing operations are performed. As an example of the method of making the output terminal bribe 1 to X η high impedance, the switch is opened in series with respect to each signal transmission path for connecting the output terminals 〇 UT1 to (5) 与 to the display device, thereby opening the switch. The output terminals OUT1 OUTn and the display device can be made high impedance, in other words, the two can be electrically disconnected. In the self-test (operation confirmation test), as in the present embodiment, there is a right-dry mode in the month of the sentence. Therefore, if the time of all modes of self-detection (action is determined) is not performed, "The part of the self-test (action confirmation test) in the file during the display of the line (for example, only the mode). Thereby, all modes of the self-test (action confirmation test) can be performed during the display period of the display device 143485.doc 201031180 or during the display of several frames. Further, if the above method is performed in which the modes are performed separately without performing the self-detection (operation confirmation test) mode at one time, the self-detection (operation confirmation test) can be performed during the horizontal flyback period shown in Fig. 39. Further, in the above-described first to third embodiments, the integrated circuit of the embodiment has been described as a subject. However, the present invention is not limited thereto, and the present invention is also applicable to the integrated circuit 10 of the second and third embodiments. 20 and the display unit 90" in the fourth embodiment. Further, in the first to fourth embodiments, the liquid crystal display device that displays an image by the liquid crystal display panel has been described. However, the present invention is not limited thereto, and may be applied to a display device other than the liquid crystal display device such as a plasma television. Wait. The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the claims. The embodiments obtained by appropriately combining the technical mechanisms disclosed in the different embodiments are also included in the technology of the present invention. In the range of the characteristics, the integrated circuit for driving the display device of the present invention and the display device may be configured as follows. [First configuration] A drive circuit that drives a display panel and includes a self-healing mechanism that self-repairs the drive circuit that is defective. [Second Configuration] The driving circuit of the first configuration includes an output circuit for outputting an output signal for driving the display panel, 143485.doc - 83 - 201031180 The self-healing mechanism includes whether the output circuit is defective or not. In the case where the judgment result of the above-mentioned judging means is a bad condition, the drive circuit is self-repaired by outputting a normal output to the display panel. [Third configuration] The drive circuit of the second configuration includes a preliminary output circuit that can output the output signal to the display panel, and the self-healing mechanism includes a switching mechanism, and the determination result of the determination means is Unsatisfactory situation: At the time of 'switching the output signal from the above-mentioned defective turn-out circuit to the output of the above-mentioned preliminary output circuit 15 虓 as the output signal to the display panel. [Fourth configuration] The driving circuit according to the third aspect, wherein the determining means includes a comparing means for comparing an output signal from the output circuit with an output signal from the preliminary output circuit, and comparing the comparison means according to the comparison means As a result, it is determined whether or not the above output circuit is defective. [Fifth Configuration] A display device is characterized in that it includes a drive circuit having any one of the i-th configuration and the first embodiment, and the display panel. [6th configuration] A display device is characterized in that it includes a display panel and a circuit for driving 143485.doc -84 - 201031180, the drive circuit includes an output circuit for driving output, and the κ output signal is driven by the above The circuit comprises: a judging mechanism 'whether or not the output circuit is ready for the output circuit, which can select m from the m, and the display panel outputs the output signal; the display panel includes a switching mechanism, and the The result of the determination by the above-mentioned judging means is that the output signal from the pre-output circuit output circuit is switched to the input signal of the (four) circuit as the output signal of the board. JX is not visible [7th configuration] A display device comprising: · a display panel; an output circuit, the output of which is used to drive a reference preparatory output circuit, which can be paired with the upper two; Whether or not the output circuit is defective in the switching mechanism, and in the determination of the above-mentioned determining mechanism, the condition that the 'will be from the upper and the lower and the lower limit will be from the above-mentioned bad output circuit. The output signal of the above-mentioned preparatory output circuit is output signal of &·", and the above display panel [Eighth configuration] A television system characterized by including any one of the items 5 to 7 143485.doc -85 - 201031180 Display device. [9th configuration] A driving circuit, comprising: an output terminal connected to a display panel; an output circuit block 'which includes a wheel connection; a second output circuit block comprising: an output circuit connectable to the output terminal; and driving the display panel,

The driving circuit includes: j; a switching mechanism 3, which compares an output signal from the output power to an output signal from the preparatory wheel and the output signal of the preparatory output circuit;

a determination unit that determines whether the circuit is defective according to a comparison result of the comparison means; J. a connection switching mechanism that causes the preliminary output circuit to replace the output circuit when the determination result of the determination means is defective And connected to the above output terminal.

[10th configuration] The drive circuit of the ninth aspect, wherein the comparison means is an operational amplifier. [11th configuration] The drive circuit of the ninth aspect, wherein the output circuit block and the preliminary output circuit block further include an output buffer of an operational amplifier, and the use of the operational amplifier as the comparison means In the case of a bad situation, connect the above-mentioned preliminary output circuit block instead of the above output circuit block of 143485.doc -86 - 201031180. [12th configuration] The driving circuit of the ninth aspect, wherein the output circuit block and the preliminary output circuit block further include: an output buffer using an operational amplifier, and a signal for supplying an input terminal to the output circuit In the case where the operational amplifier is used as the comparison means and the determination result is defective, the preparatory output circuit block is connected instead of the input/output circuit block. [13th configuration] The driving circuit according to any one of the ninth to twelfth aspects, comprising: a control unit that controls an input signal input to the output circuit and the preliminary output circuit, wherein the control unit is connected to the output circuit An input signal having a different input size from the preliminary output circuit, and outputting an expected value of the comparison result from the comparison means corresponding to the input signal different in size, the above-mentioned judging means is different from the expected value In the case of the case, the above output circuit is judged to be defective. [Fourth configuration] The drive circuit of any one of the ninth to thirteenth configurations further includes a flag storage unit that stores a flag indicating a determination result of the determination unit, wherein the value of the flag indicates the output circuit In the case of a failure, the connection switching mechanism connects the preliminary output circuit to the output terminal instead of the output circuit. [Fourteenth configuration] The driving circuit according to any one of the ninth to fourteenth aspects, wherein the comparing means does not affect the image displayed on the display panel The output signal from the output circuit is compared with an output signal from the preliminary output circuit, and the determining means determines whether the round circuit is defective based on a comparison result of the comparing means, and the connection switching means is for the output terminal Connecting, the output end of the output circuit determined to be defective by the determining means is switched to the output end of the preliminary output circuit, and the preliminary output is connected after the connection switching means connects the output terminal to the output end of the preliminary output circuit The circuit outputs an output signal to the output terminal. [16th configuration] The drive circuit according to any one of the ninth to fifteenth configurations, further comprising: a detection mechanism that detects a value of a power supply current supplied to the drive circuit; a normal power/"L value S a memory mechanism that pre-memorizes the value of the power source current when the driving circuit is normally operated; and a current value comparing mechanism that performs a value of a power source current from the detecting mechanism and a value of a power source current from the normal current value memory mechanism And a driving circuit determining unit that determines whether the driving circuit is defective according to a result of the comparison of the current value comparing means J43485.doc -88 - 201031180; and when the determination result of the driving t path determining means is bad The comparison means compares an output signal from the output circuit with an output signal from the preliminary output circuit, and the service mechanism determines whether the round circuit is defective based on a comparison result of the comparison means, and the connection switching mechanism For the connection of the above output terminals, it is judged by φ 1 The output terminal of the output circuit that is determined to be defective by the mechanism is switched to the output terminal of the preparatory output circuit. [Parallel configuration] The drive circuit of any one of the ninth to sixteenth configurations, wherein the power supply of the display panel is just connected After the pass, the comparing means compares an output signal from the output circuit with an output signal from the preliminary output circuit, and the determining means determines whether the output φ circuit is defective based on a comparison result of the comparing means, and the connecting The switching mechanism switches the output terminal of the output circuit determined to be defective by the determination means to the output terminal of the preliminary output circuit for the connection of the output terminal. [18th configuration] In the ninth to sixteenth configurations In any one of the driving circuits, wherein the comparing means compares an output signal from the output circuit with an output signal from the preliminary output circuit during a vertical flyback of the display panel, 143485.doc -89 - 201031180 According to the comparison results of the above comparison institutions, the above It is determined whether or not the circuit is defective, and the connection switching means switches the output end of the output circuit determined to be defective by the determining means to the output end of the preliminary output circuit by the connection to the output terminal. [19th structure] The drive circuit of any one of the ninth to eighteenth aspects, further comprising: a cutting mechanism that cuts a signal transmission path from the output terminal to the display panel, wherein the cutting mechanism is from the output terminal to the After the signal transmission path of the display panel is cut off, the comparison means compares an output signal from the output circuit with an output signal from the preliminary output circuit, and the determination means performs a defect on the output circuit based on a comparison result of the comparison means. It is determined that the connection switching means switches the output of the output terminal to the output end of the preliminary output circuit from the output of the output circuit determined by the judgment. [Industrial Applicability] The present invention provides a display device including a specific mechanism for detecting and self-repairing defects of an output circuit, and including a display drive integrated circuit which can more easily handle an output circuit. In particular, the present invention is preferably adapted to a liquid crystal display device that can self-detect and self-repair at an appropriate timing. 1 is a block diagram showing a configuration of a liquid crystal television according to an embodiment of the present invention; and FIG. 2 is a block diagram showing a configuration of a display device according to an embodiment of the present invention. Fig. 3 is a fSI diagram showing the appearance of a liquid crystal television according to an embodiment of the present invention, and Fig. 4 is a diagram showing an abnormality of an output circuit block of an integrated circuit included in a liquid crystal television according to an embodiment of the present invention. FIG. 5 is a diagram showing an example of self-detection and self-repairing operations in a liquid crystal television according to an embodiment of the present invention, and FIG. 5(a) shows the start of self-detection and self-repairing operations. The picture of the former LCD TV, Figure 5 (b) shows the picture of the LCD TV in the process of self-detection and self-repair, Figure 5 (the picture of the LCD TV after the self-test and self-repair of the illusion table; Φ 6 is a view showing a display example of a maintenance function table in a liquid crystal television according to an embodiment of the present invention; and FIG. 7 is a view showing self-checking in a liquid crystal television according to an embodiment of the present invention. Figure 7 (a) shows the LCD TV before self-test and ' self-repair action, and Figure 7 (b) shows the LCD TV in self-test and self-repair action. FIG. 7(c) is a view showing a liquid crystal television after the end of the self-detection and self-repairing operation; FIG. 8 is a view showing the display unit of the display unit in which the liquid crystal LCD module is constructed according to the embodiment of the present invention. Driving source drive 143485.doc -91 · 201031180 FIG. 9 is a diagram showing an example of the actuator; FIG. 9 is a tfT-LCD module constituting a liquid crystal television according to an embodiment of the present invention, that is, a display unit is mounted on the display unit. FIG. 10 is a diagram showing an example of a source driver and a preparatory source driver having a self-detection and self-repair function according to an embodiment of the present invention using a tape carrier. FIG. 11 is a view showing a state in which the tape carrier shown in FIG. 10 is opened; FIG. 12 is a view showing the direction shown in FIG. FIG. 13 is a top view showing a tape carrier of a pole driver and a preparatory source driver; FIG. 13 is a view showing a tFT_LCD module constituting a liquid crystal television according to an embodiment of the present invention, in which a memory is mounted on a source driver; FIG. 14 is a view showing a display unit of a tft_LCD module constituting a liquid crystal television according to an embodiment of the present invention, wherein a memory is mounted on an input terminal to which a source driver is connected. FIG. 15 is a flow chart showing the sequence of performing self-detection of the source driver when the power of the display portion of the embodiment of the present invention is turned off; FIG. 16 is a diagram showing one of the present inventions. FIG. 16(a) is a diagram showing a liquid crystal television before self-detection and self-repair operation, and FIG. 16(1) shows self-detection and self. FIG. 16(a) is a diagram showing an example of self-detection and self-repairing operations in a liquid crystal television according to an embodiment. Figure 17 ((;) shows the picture of the LCD TV after the end of the self-test and self-repair operation; Figure 17 shows the actual picture of the present invention. Self-checking in the form of LCD TV 143485.doc • 92- 201031180 2 Self-repairing action - example of the figure, Figure 17 (4) shows the picture of the LCD TV before the self-checking and repairing action, Figure 17 (b) shows the self FIG. 17(c) is a view showing a liquid crystal television after completion of self-detection and self-repairing operations; FIG. 18 is a view showing a display driving semiconductor body according to an embodiment of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 19 is a flow chart showing the first sequence of the operation confirmation test according to an embodiment of the present invention; and FIG. 20 is a flow chart showing the second sequence of the operation confirmation test according to an embodiment of the present invention. Figure 21 is a flow chart showing the third sequence of the operation confirmation test according to an embodiment of the present invention; Figure 22 is a flow chart showing the fourth sequence of the operation confirmation test according to an embodiment of the present invention; A flowchart of the fifth sequence of the operation confirmation test according to an embodiment of the present invention; and FIG. 24 is a diagram showing the switching of the defective output circuit to one embodiment of the present invention. Flowchart of the sequence of the output circuits; FIG. 25 is a flow chart showing the sequence of the power supply from the display device to the normal operation until the operation confirmation test is performed according to an embodiment of the present invention; FIG. 27 is a view showing a circuit configuration for confirming the operation of an operational amplifier according to an embodiment of the present invention; and FIG. 27 is a display driving semiconductor according to another embodiment of the present invention. 143485.doc -93 - 201031180 Integrated circuit FIG. 2 is a flowchart showing a first procedure of the operation confirmation test according to another embodiment of the present invention; and FIG. 29 is a second sequence of the operation confirmation test according to another embodiment of the present invention. Figure 3 is a flow chart showing a third sequence of the operation confirmation test according to another embodiment of the present invention; and Figure 3 is a flow chart showing the fourth sequence of the operation confirmation test according to another embodiment of the present invention. Figure 32 is a flow chart showing the fifth sequence of the operation confirmation test according to another embodiment of the present invention; and Figure 33 is a view showing another embodiment of the present invention. FIG. 34 is a block diagram showing a schematic configuration of a display device according to still another embodiment of the present invention; FIG. 35 is a block diagram showing still another embodiment of the present invention. FIG. 3 is a block diagram showing the sequence of the display device to the normal operation from the power-on of the display device to the normal operation after the operation confirmation test according to still another embodiment of the present invention; 37 is a block diagram showing a configuration of a display device according to still another embodiment of the present invention; and FIG. 38 is a block diagram showing a configuration of a television system according to an embodiment of the present invention; 143485.doc 201031180 FIG. 39(a) to FIG. 3(f) shows a timing of a voltage value of a scanning signal, a video signal, and a pixel electrode which are wheeled into a display device according to an embodiment of the present invention. FIG. 40 is a view showing an operation of an embodiment of the present invention. FIG. 41 is a block diagram showing the power supply current value of the integrated circuit during normal operation according to an embodiment of the present invention; Fig. 42 is a flowchart showing a process of detecting a malfunction of the integrated circuit based on a power source current value supplied to the integrated circuit according to an embodiment of the present invention; and Fig. 43 is a view showing Description of the configuration of the semiconductor integrated circuit for display driving in the prior art. [Explanation of main component symbols] 1-1 Operational amplifier (comparison mechanism) 1-2 Operational amplifier (comparison mechanism) 1 -η Operational amplifier (comparison mechanism) 2c Switch (connection switching mechanism) 2d switch (connection switching mechanism) 3-1 Judgment circuit (determination mechanism) 3-2 Judgment circuit (judgment mechanism) 3-n Judgment circuit (judgment mechanism) 4-1 Judgment flag (flag storage mechanism) 4-2 Judgment flag (flag storage mechanism) 4- n Judgment flag (flag storage mechanism) 143485.doc •95· 201031180 8-1 DAC circuit (output circuit) 8-2 DAC circuit (output circuit) 8-n DAC circuit (output circuit) 10 Semiconductor product for liquid crystal drive Body circuit (drive circuit) 10, semiconductor integrated circuit for driving liquid crystal drive (drive circuit) 10a Semiconductor integrated circuit for liquid crystal drive (drive circuit, first drive circuit, and source driver) l〇b Semiconductor integrated circuit for liquid crystal drive (Drive circuit, second drive circuit, and preparatory source driver) 20 Semiconductor integrated circuit for driving liquid crystal drive (drive circuit) 21 Operational amplifier (comparison mechanism) 21A Operational Amplifier (Comparison Mechanism) 21B Operational Amplifier (Comparative Mechanism) 28 DAC Circuit (Prepared Output Circuit) 28A DAC Circuit (Prepared Output Circuit) 28B DAC Circuit (Prepared Output Circuit) 50 Comparison Judging Mechanism (Self-Detection and Self-Repair Mechanism, Mechanism ) Judging 60 switching circuit (self-detecting and self-healing mechanism, cutting) Switching 61 switching circuit (self-detecting and self-repairing mechanism) 80 Display panel 80' Display panel 81 Recording body (memory device) 143485.doc ·% · 201031180 82 Operation switching input terminal 83 Film substrate 84 Input terminal 85 Solder resist • 86 Output side wiring • 87 Component hole 88 Input side wiring 89 Tape carrier A w 90 Display unit (display unit) 92 Pixels 93 TFT 94 Gate Polar Line 95 Source Line 96 Glass Substrate 97 Printed Substrate (PWD) Win 98 Membrane Cable (FPC) 99 Gate Driver 100 Controller (Write Control Mechanism) - 202 Resistance (Detection Mechanism) 204 A/D Converter (Detection Organization) 206 EEPROM (normal current value memory mechanism) 208 comparison circuit Current value comparison mechanism, drive circuit determination mechanism) 300 TV system 143485.doc -97- 201031180 400 LCD TV 401 switch button DVD reproduction device) HDD reproduction device 402 DVD device (image reproduction device 403 HDD device (image reproduction device 404 DVD) And HDD Control Department 143485.doc -98-

Claims (1)

201031180 VII. Patent application scope: 1. A display device characterized by comprising: a display panel that displays an image according to an image signal supplied from the image reproduction device; and a driving circuit that drives the display panel and includes The self-detecting and self-repairing mechanism for detecting and repairing the defect of the driving circuit; the self-detecting and self-healing mechanism detecting and repairing the defect of the driving circuit while the image reproducing device is unable to supply the image signal. 2. The display device of claim 1, wherein the driving circuit comprises a plurality of output circuits for outputting an output signal of the display panel, wherein the self-detecting and self-repairing mechanism comprises determining whether the output circuit is defective. When the determination result of the determination means is defective, the determination means self-repairs the drive circuit so as to output a normal output signal to the display panel. 3. The display device of claim 2, wherein. The driving circuit includes a preliminary output circuit capable of outputting the output signal to the display panel, wherein the self-detecting and self-repairing mechanism includes a switching mechanism, and when the result of the determination is abnormal, the The output signal of the above-mentioned defective output circuit is switched to the output signal from the upper circuit as the output signal to the display panel. 143485.d〇c 201031180. The display device of claim 3, wherein the determining means includes A comparison means for comparing an output signal from the output circuit with an output signal from the preliminary output circuit, and determining whether the output circuit is defective based on a comparison result of the comparison means. 5. The display device of claim 4, further comprising a control mechanism for controlling an input signal to the output circuit and the preliminary output circuit, wherein the control mechanism inputs the size of the output circuit and the preliminary output circuit a different input signal, and outputting an expected value of the comparison result from the comparison means corresponding to the input signal different in size, wherein the determining means sets the output circuit when the comparison result is different from the expected value It was judged to be bad. 6. The display device of claim 3, wherein the determining means comprises comparing means for comparing output signals from at least two of the plurality of output circuits, and comparing the output according to a comparison result of the comparing means Whether the circuit is bad or not. 7. The display device of claim 6, further comprising a control mechanism for controlling an input signal input to at least two of the plurality of output circuits, wherein the control mechanism inputs the at least two output circuits Input signals of different sizes, and outputting the input signal phase different from the above size 143485.doc 201031180 8. 9. ❹ 10. 11. 12. 13. 14. Corresponding to the expected value of the comparison result from the above comparison mechanism, The determining means determines that any of the at least two output circuits is defective when the comparison result is different from the expected value. A display device according to claim 4, wherein said output circuit includes an operational amplifier as an output buffer, and said comparison means includes a comparator including said operational amplifier. A display device according to claim 8, wherein said operational amplifier operates as a voltage follower when driving the display panel. The display device of claim 1, wherein the video reproduction device is a DVD reproduction device. The display device of claim 10, wherein the self-detecting and self-healing means detects and repairs a defect of the drive circuit when cleaning the DVD reproducing device as the period. The display device of claim 1, wherein the image reproducing device is an HDD reproducing device. The display device of claim 12, wherein the self-detecting and self-healing means detects and repairs a defect of the driving circuit when optimizing the memory area of the HDD reproducing device during the period. The display device of claim 13, wherein the HDD reproducing device can optimize the 143485.doc 201031180 of the memory region at the set time, wherein the self-detecting and self-repairing mechanism performs the HDD regeneration starting at the set time. During the optimization of the memory area of the device, the failure of the above drive circuit is detected and repaired. A television system characterized by comprising the display device of claim 1. 143485.doc