TW201025501A - Method of manufacturing through-silicon-via and through-silicon-via structure - Google Patents

Method of manufacturing through-silicon-via and through-silicon-via structure Download PDF

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Publication number
TW201025501A
TW201025501A TW097151896A TW97151896A TW201025501A TW 201025501 A TW201025501 A TW 201025501A TW 097151896 A TW097151896 A TW 097151896A TW 97151896 A TW97151896 A TW 97151896A TW 201025501 A TW201025501 A TW 201025501A
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Taiwan
Prior art keywords
layer
conductive
conductive layer
manufacturing
bump
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TW097151896A
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English (en)
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TWI366890B (en
Inventor
Ching-Chiun Wang
Tai-Yuan Wu
Yu-Sheng Chen
Cha-Hsin Lin
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Ind Tech Res Inst
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Priority to TW097151896A priority Critical patent/TWI366890B/zh
Priority to US12/480,694 priority patent/US20100164062A1/en
Publication of TW201025501A publication Critical patent/TW201025501A/zh
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Publication of TWI366890B publication Critical patent/TWI366890B/zh

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    • H—ELECTRICITY
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    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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  • Engineering & Computer Science (AREA)
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  • Computer Hardware Design (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

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201025501 P51970125TW 29595twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種石夕導通孔（Through-Silicon-Via，TSV)結構及其製造方法。 【先前技術】 矽導通孔(TSV)技術是通過在晶片和晶片之間、晶圓 φ 和晶圓之間製作垂直導通，是目前三維積體電路製程整合 技術中’能實現晶片之間互連的勒新技術，如A. W. Topol 等人於西元2006年發表於IBM J. RES. & DEV. Vol. 50 No. 4/5第491〜506頁的技術。與以往的ic封裝鍵合和使用凸 點的疊加技術不同’ TSV能夠使晶片在三維方向堆疊的密 度最大’外形尺寸最小，並且提升元件速度、減少信號延 遲和功專消耗’因此TSV可被視為應用於3D 1C技術之新 一代的連接導線(Interconnect)。 近來’也有提出環狀(annular) TSV結構的研究，如P. • S. Andry 等人於西元 2006 年發表於 Electronic Components and Technology Conference 會議中的“A CMOS-compatible Process for Fabricating Electrical Through-vias in Silicon”。 這種環狀TSV結構相對於傳統的圓柱狀（Cyiin(jricai) TSV，可減少導電層截面積、降低製程成本，同時可減少 熱應力。但是此處的環狀TSV結構仍只具傳遞訊號的功 201025501 ^iy/ui/5TW 29595twf.doc/n 【發明内容】 本發明提出一種矽導通孔的製造方法，包括先於一矽 形成—第—環狀溝渠’再於第—環狀溝渠内形成— 第：導電層、一電容介電層與一第二導電層。然後，於第 一裱狀溝渠所圍繞的矽基底中形成一個開口，再於開口的 ^表面形成一絕緣層，並於開口内填入一導電材料。之後， 從1基底的背面進行一平坦化製程，以去除部份石夕基底， ❹ f時t除開Μ部的絕緣層而構成-個導電通孔，並去除 第一環狀溝渠底部的第一導電層及電容介電層。接著，去 ^絕緣層與第二導電層之_絲底與第_導電層及電容 门電層，以形成一第二環狀溝渠，然後於第二環狀溝渠内 填入=低介電常數(l〇w_k)材料。隨後，形成與上述開口底 部的導電材料接觸的凸塊(bUmp)。 m本發明另提出一種矽導通孔結構，包括一矽基底、— 狀電谷、一導電通孔、一低介電常數(1〇W_k)材料層以及 f塊。上述裱狀電容位於矽基底内，且環狀電容從内到外 鲁是由-第-導電層、—電容介電層與—第二導電層所構 成。，導電通孔是位於環狀電容所圍繞的石夕基底中，而低介 電常數(l〇W-k)材料層則位於環狀電容與導電通孔之間。至 於凸塊是與導電通孔相接觸，以利於與其他晶片做接合。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉貫施例，並配合所附圖式作詳細說明如下。 201025501 FMy /〇l25TW 29595twf.doc/n 【實施方式】 圖1A至圖1J是依照本發明之一實施例之一種矽導通 孔的製造流程剖面示意圖。 請參照圖1A，本實施例之製程可與目前汇製程做整 合，因此在製作矽導通孔之前可先進行前段電晶體製程； 也就是先在矽基底100上形成由閘極1〇2以及源極與汲極 104構成的電晶體1〇6,再於矽基底1〇〇上覆蓋一層内層介 電層(ILD)l〇8。在本圖中的電晶體1〇6位置與數量均^ 照設計需求作變更，而不限於此。 然後，請參照圖1Β，可利用乾蝕刻方式，於矽美 酬中形成—第一環狀溝渠11〇,其中所用的餘刻氣^ 如Cl2、CF4脑。由於第-環狀溝帛11〇的位置後續合 形成電容器，所以可設置在電晶體1〇6旁。此外，因為: 圖只顯示結構的剖面，所以圖中所顯示 … 狀溝渠110。 似弟一％
第-請參關心於第—環狀溝渠⑽内形成一 上的内層介電 電ί i ^本五^内表面共形地(C〇nf_a_積第一導 介i戶114 :弟一導電層U2表面共形地沉積上述電容 i 後於電容介電層114所構成的空間内填滿 第-導電層116,最後可利用化學機械 一環狀溝渠m以外之第-導電芦112 fCMP)去除第 與第二導電層H6。另外，第^ —12·電容介電層114 ^义弟―·導電層112、116的 201025501 j^My/uiz5TW 29595twf.doc/n 材料例如氮化鈦(TiN)、氮化鈕(TaN)、釕(ru)或鉑(Pt)。而 電容介電層114的材料可選用高介電常數材料，如氧化钽 (Ta2〇5)、氧化鋁(Al2〇3)、氧化铪(Hf〇2)或氧化鈦(Ti〇2)。 接著，請參照圖1D，可在内層介電層中製作與 源極與汲極104接觸的製程接觸層（pr〇cess⑶泔加 layer)118，再於内層介電層108上形成m (Metal l)120a〜c，其中Ml 120a只與製程接觸層118相連、M1 12〇b 和第一導電層112及製程接觸層ία相連、mi i20c則與 第一與第二導電層U2和116相連。以上製程接觸層118 與Ml 120a〜c的位置均可依設計需求作變更。之後，在矽 基底100上形成覆蓋Ml 120a〜c的一層内層金屬介電層 (IMD)122。 然後，請參照圖1E，可利用乾蝕刻方式，於第一環狀 溝渠11〇所圍繞的矽基底100、内層介電層1〇8與内層金 屬介電層122中形成-個開口 124,其中所用的乾侧氣 體=如α2、CF4或臟。開D 124的位置可如圖所示與第 • 一糸狀溝渠110相隔一段距離，或者也可緊貼第一環狀溝 渠110，以縮減元件面積。 接著，凊參照圖1F’於開口 124的内表面形成一絕緣 層126 ’其材料可為Si〇2等氧化物與SiN等氮化物。隨後， 於開口 124内填入-導電材料128,其例如銅(Cu)、鶴(w)、 銅(Cu)或鎢(W)之合金或多晶矽(p〇ly_Si)。接著可在内層 介電層㈣與内層金屬介電層122中製作與閑極1〇2接^ 的接觸窗m ’再於内層金屬介電層m上形成和接觸窗 6 132還可依設計需
201025501 rj ! yfui^5TW 29595twf.doc/n 130 相連的 M2(Metal 2) 132，其中 M2 妻與導電材料128相連。 、，然後，請參照圖1G，從矽基底100的背面1〇〇a進行 平坦化裝程，以去除部份石夕基底，同時去除開口 124 底部的絕緣層126而構成一個導電通孔134，並去除第一 環狀溝渠11〇底部的第一導電層112及電容介電層114。 其中，平坦化製程例如化學機械研磨製程。 之後，請參照圖1H，去除絕緣層126與第二導電層 116之間的矽基底100與第一導電層112及電容介電層 114，以形成一第一每狀溝渠136。此時，保留下來的第一 導電層112、電容介電層1H與第二導電層Π6即為 電容(Metal-Insulator-Metal)。 接著，請參照圖II，於第二環狀溝渠136内填入—低 w電常數(low-k)材料138，其例如氟倍半石夕氧烧(FSq)、氫 倍半矽氧烷(hydrogen silsesquioxane，HSQ)或甲基倍半矽 氧烧(methyl silsesquioxane ’ MSQ)。隨後，於矽基底 1〇〇 的背面100a形成一層絕緣薄膜HO’覆蓋低介電常數材料 138、第一導電層112、電容介電層114與第二導電層116。 其中，上述絕緣薄膜140可為Si〇2等氧化物與SiN等氮化 物。 最後，請參照圖1J，形成與開口 124底部的導電通孔 134接觸的凸塊(bump)l42，以利於與其他晶片做接合。凸 塊142譬如金凸塊、pbSn凸塊、CuSn凸塊或CoSn凸塊。 圖2是依照本發明之另一實施例之一種可具有電容功 201025501 i-My /Ul25TW 29595twf.doc/n 能之矽導通孔結構的俯視圖；圖3是圖2之m_In線段之 剖面示意圖。 請參照圖2與圖3，本實施例之可具有電容功能之石夕 導通孔結構包括一矽基底2〇〇、一環狀電容2〇2、一導電通 孔204、一低介電常數(i〇w-k)材料層206以及凸塊208。 上述環狀電容202位於矽基底2〇〇内，上述環狀電容2〇2 的外徑大小例如在1 μιη以上與1〇〇μπι以下。而且，環狀 電谷202從内到外是由一第一導電層210、一電容介電層 212與一第二導電層214所構成。第一或第二導電層210、 214的材料例如氮化鈦(TiN)、氮化钽(丁咖）、釕供口)或鉑 (pt^。至於電容介電層212的材料可為高介電常數材料， 如氧化鈕(Ta2〇5)、氧化鋁(a12〇3)、氧化铪(Hf〇2)或氧化鈦 (Τι〇2)。上述導電通孔204則是位於環狀電容2〇2所圍繞 的石夕基底2〇0中’而導電通孔2〇4之材料例如銅(Cu)、鹤 (W)、銅(Cu)或鶴(W)之合金或多晶石夕_y Si)。而低介電 常數材料層2〇6則位於環狀電容逝與導電通孔綱之 ❹ Μ ’其中低介電常數材料層206例如氟倍半石夕氧烧(FSq)、 氫倍半碎纽(HSQ)S f基倍特纽(MSQ)。至於凸塊 208是與導電通孔綱相接觸，以利於與其他晶片做接合， 其中凸塊208可以是金凸塊、pbSn凸塊、CuSn凸塊或c〇Sn 凸塊。在本實施例中，於低介電常數材料層施與導電通 孔204之間還可包括一絕緣層216，其材料可為
Si02等氧 化物與SW等氮化物。另外，在本實施例令，於石夕基底· 的背面200a還可加上—絕緣薄膜218，覆蓋上述環狀電容 8 iTW 29595twf.doc/n 201025501 202的底部，並可進一步介於凸塊2〇8與低介電常數材料 層206之間。其中，絕緣薄膜218可為以〇2等氧化 SiN等氮化物。 ^ ❹ 綜上所述，本發明利用半導體製程來製作矽導通孔結 構並搭配環狀電容的製作，可得到一種周圍可兼具電容功 能的矽導通孔(TSV)結構，使得TSV不再是只能傳遞訊 號，而是能利用製程技術製作一種結合被動元件功能的 TSV’因此本發明可大幅提高TSv在3D 1C製程整合中的 功能性與價值性。 σ 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明，任何所屬技術領域中具有通常知識者，在不脫離 本發明之精神和範圍内，當可作些許之更動與潤飾，故本 發明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1Α至圖ij是依照本發明之一實施例之一 孔的製造流程剖面示意圖。 逋 a圖2疋依照本發明之另一實施例之一種可具有電容功 能之矽導通孔結構的俯視圖。 圖3是圖2之ΙΙΙ-ΙΠ線段之剖面示意圖。 【主要元件符號說明】 100、200 :矽基底 102 :閘極 5TW 29595twf.doc/n 201025501 104 :源極與汲極 106 :電晶體 108 :内層介電層 110 :第一環狀溝渠 112 :第一導電層 114 :電容介電層 116 :第二導電層 118 :製程接觸層 〇 120a〜c : Ml 122 :内層金屬介電層 124 :開口 126 :絕緣層 128 :導電材料 130 :接觸窗 132 ： M2 134 :導電通孔 . 136:第二環狀溝渠 138 :低介電常數(low-k)材料 140 :絕緣薄膜 142 :凸塊 202 :環狀電容 204 :導電通孔 206 :低介電常數材料層 208 :凸塊 201025501 oTW 29595twf.doc/n 210 ： 第一導電層 212 : 電容介電層 214 ： 第二導電層 216 : 絕緣層 218 : '絕緣薄膜

Claims (1)

  1. 2010255015TW29595twfdoc/n 七、申請專利範面： 1·一種矽導通孔的製造方法，至少包括： 於一矽基底中形成一第一環狀溝渠； 電 於該第一環狀溝渠内形成一第一導電層、— 層與一第二導電層，· 电奋；丨 於該第-環狀溝渠所圍繞的該石夕基底中形成 . 於該開口的内表面形成一絕緣層； ， 於该開口内填入一導電材料· 從該絲底时面進行—平坦化製程，財除部份該 孔，二絕緣層而構成-導電以 介電層；、° /冓水底部的該第一導電層及該電容 -導該第二導電層之間的該矽基底與該第 電層，以形成—第二環狀溝渠； 料；= 渠内填入一低介電常數(1〇叫材 ^成與，開π底部的該導電通孔接觸#凸塊㈣叫）。 甘如申凊專利範圍第i項所述之通孔的製造方 法\其中形賴第—環崎渠之方法包括乾餘刻。 •如申Μ專利範圍第2項所述之料通孔的製造方 C =中形成該第-環狀清渠所用的乾氣體包括cl2、 % 或 HBr。 法，4·如申請專利範圍第1項所述切導通孔的製造方 ’其中於該第—環狀溝渠内形成該第—導電層、該電容 12 -5TW 29595twf.doc/n 201025501 介電層與該第二導電層之步驟包括： 該第:底上與遠第-環狀溝渠的内表面共形地沉積 於5亥第—導電層表面共形地沉積該電容介電層； 以及於該電〜丨電層所構成的空助填滿該第二導電層； J用機械研磨(CMP)，去除該第-環狀溝渠以外 的該第-導電層、該電容介電層與該第二導電層。 、土 專利圍第1項所述之石夕導通孔的製造方 :τ.Μ、、广第—導電層或該第二導電層的材料包括氮化欽 (™)、氮化钽(TaN)、釕(Ru)或鉑⑽。 如申％專利範圍第1項所述之石夕導通孔的製造方 法’其中該電容介電層的材料為高介電常數材料。 、如，明專利範圍第6項所述之石夕導通孔的製造方 法’其中，電容介電層的材料包括氧化组(Ta205)、氧化銘 (Ai2〇3)、氧化铪(Hf〇2)或氧化鈦(了丨〇2)。 、8.如申印專利範圍第1項所述之矽導通孔的製造方 法’其中形成該開口之方法包括乾钱刻。 9.如申凊專利範圍第8項所述之矽導通孔的製造方 法其中形成該開口所用的乾蝕刻氣體包括Cl2、CF4或 HBr。 ι〇.如申凊專利範圍第1項所述之矽導通孔的製造方 法’其中該絕緣層的材料包括氧化物或氮化物。 u.如申晴專利範圍第1項所述之矽導通孔的製造方 .25TW 29595twf.doc/n 201025501 法’其中該導電材料包括銅(Cu)、鎮(W)、銅(Cu)或鶴(w) 之合金或多晶矽(Poly-Si)。 .12.如申請專利範圍第1項所述之矽導通孔的製造方 法，其中該平坦化製程包括化學機械研磨製程。 13·如申請專利範圍第1項所述之矽導通孔的製造方 法’其中該低介電常數材料包括氟倍半矽氧烷(FSq)'氫倍 半矽氧烷(hydrogen silsesquioxane，HSQ)或曱基倍半石夕氧 烧(methyl silsesquioxane，MSQ)。
    14.如申請專利範圍第i項所述之矽導通孔的製造方 法，其中於s亥弟二環狀溝渠内填入該低介電常數材料之後 以及形成該凸塊之前更包括：於該矽基底的背面形成一絕 緣薄膜，覆盍該低介電常數材料、該第一導電層、該 介電層與該第二導電層。 ~ 15·如申請專利範圍第14項所述之矽導通孔的製造方 法，其中該絕緣薄膜包括氧化物或氮化物。 16.如f μ專利乾圍第丨項所述之♦導通孔的製造方 法，其中該凸塊包括金凸塊、PbSn凸塊、CuSn凸塊或c〇Sn Λ换。 17. —種矽導通孔結構，至少包括·· 一矽基底； β由二狀位於抑基底内’該環狀電容從内到外 ίΐΐΓΓ電容介電層與1二導電層所構成； -==於該環狀電容所圍繞的該石夕基底中； 低，丨電咖㈣材料層，位於該環狀電容與該導 201025501 ：^TW 29595twf.doc/n 電通孔之間；以及 一凸塊，與該導電通孔的底部接觸。 18.如中請專利範圍第17項所述切導通孔 中該環狀電容的外徑大小為1μιη以上與1〇〇叫2 /、 ㈣1二如t料利範㈣17項所述切導通孔結構，豆 ΓΓ二氣^電層或該第二導電層的材料包括氮化鈦 (lN)、氮化纽(TaN)、釕(Ru)或鉑(pt)。 2丄如申請專利範圍第項所述之石夕導通孔結構，盆 中μ電谷介電層的材料為高介電常數材料。 ’、 2L如申請專利範圍第2〇項所述之石夕導通孔結構，直 厂電谷介電層的材料包括氧化鈕（Ta2〇5)、氧化在呂 2〇3)、氧化铪(Hf〇2)或氧化欽(Ή〇2)。 ^如申請專利範圍第17項所述之石夕導通孔結構，更 ^。—絕緣層’位於該低介電常數材料層與該導電通孔之 23.如申請專利範圍第22項所述之矽導通孔結構，1 亥絕緣層的材料包括氧化物鎮化物。 '、 中，24’如申請專利範圍第17項所述之矽導通孔結構，其 」導電通孔之材料包括銅(Cu)、鎢(W)、銅(Οι)或鶴(w) 金或多晶矽(p〇ly_Si)。 25.如申請專利範圍第以項所述之矽導通孔結構，其 =低，電常數材料層的材料包括氟倍半矽氧烷(FSQ)、氫 ^半矽氧烷(HSQ)或曱基倍半矽氧烷(MSQ)。 * 6.如申凊專利範圍第17項所述之砍導通孔結構，更 15 201025501^TW29595tw,doc/n 包括-絕緣薄膜，位於财基底的背面並覆蓋該環狀電容 的底部。 27·如申請專利範圍第26項所述之矽導通孔結構，其 中該絕緣薄膜包括氧化物或氮化物。 28·如申請專利範圍第17項所述之矽導通孔結構，其 中該凸塊包括金凸塊、PbSn凸塊、CuSn凸塊或CoSn凸 塊。
    16
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