TW201017878A - Self-aligned planar double-gate process by self-aligned oxidation - Google Patents

Self-aligned planar double-gate process by self-aligned oxidation Download PDF

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TW201017878A
TW201017878A TW098143184A TW98143184A TW201017878A TW 201017878 A TW201017878 A TW 201017878A TW 098143184 A TW098143184 A TW 098143184A TW 98143184 A TW98143184 A TW 98143184A TW 201017878 A TW201017878 A TW 201017878A
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gate
transistor
layer
electrode
gate electrode
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TWI402984B (zh
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Omer H Dokumaci
Bruce B Doris
Kathryn W Guarini
Suryanarayan G Hegde
Meikei Ieong
Erin Catherine Jones
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface

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  • Engineering & Computer Science (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

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201017878 六、發明說明： 【發明所屬之技術領域】 本發明之技術領域係關於在積體電路程序中形成雙重閘 極電晶體，詳言之係自我對齊雙重閘極電晶體。 【先前技術】 積體電路領域中之工人堅持不懈地努力減小裝置之尺 寸，詳言之係電晶體之尺寸。 隨著FET尺寸之縮小，其變得日益難以藉由習知方法來控 制短通道效應（Short-channel effect)。熟習此項技術者所熟 知的短通道效應係短通道裝置中極限電壓Vt之減小，意 即，0.1微米以下，其係歸因於閘極與源極/汲極區域之間的 二維靜電荷共享。 一種超越標準單閘極金屬氧化物半導體場效應電晶體 (MOSFET)之發展為雙閘極MOSFET，其中裝置通道係被限 制在頂部與底部閘極介電層之間。 與習知單閘極MOSFET結構相比，具有對稱閘極結構之 此結構，可縮小至約通道長度的一半。吾人熟知：雙重閘 極或雙閘極MOSFET裝置相比於習知單閘極MOSFET裝置 具有若干優點。具艎言之，相比於習知單閘極對應物之優 點包含更高轉導及經改良之短通道效應。 舉例而言，已在30nm通道之雙重閘極MOSFET裝置上進 行Monte Carlo模擬且其表明：雙重閘極裝置具有非常高之 轉導（23 00 mS/nm)及快速轉換速度（對於nMOSFET而言為 1 · 1 ps) 〇 145242.doc 201017878 此外，可獲得減至20 „„1通道長度的經改良之短通道特 性，而無需在通道區域中需要攙雜。此避免了通常存在於 單閘極MOSFET裝置中與通道攙雜相關聯之穿遂擊穿 (tunneling breakdown)、攙雜劑量子化及攙雜劑耗盡問題。 备前，该領域中之許多工人積極地推行垂直及水平閘極 結構。水平閘極結構相比於垂直閘極結構具有若干優點， 其係歸因於該技術中之CM0S裝置之電流狀態的相似性。然 而，製造雙閘極的一主要及棘手之挑戰係使底部閘極與頂 部閘極對齊。 【發明内容】 本發明係關於一種具有雙重閘極電晶體之積體電路。 本發明之一態樣係關於藉由將前閘極用作氧化罩氧化後 閘電極層之一部分來形成自動對齊後閘極。 本發明之另一態樣係關於在該結構之外邊緣處植入一種 促進氧化之物質。 本發明之另一態樣係關於經歷足以減少電晶體本體中之 應力之時間及溫度的氧化。 本發明之另一態樣係關於氧化之橫向範圍，其用以在電 晶體本體之邊緣下方延伸後閘極之邊界。 本發明之另一態樣係關於在由界定電晶體本體之寬度的 分隔物所留下之空間内形成突起源極及汲極結構。 【實施方式】 圖1A展示一具有表體基板105之初始SOI晶圓，埋藏氧化 物（BOX) 107將該表體基板自將成為電晶體本體之單晶梦 U5242.doc 201017878 S〇1層4分離開。層4具有2 nm至50 nm範圍内之標稱厚度。 將成為後閘極介電質之熱氧化層3在矽層4上成長到丨nm 至3 nm之厚度且將成為後閘極之多晶石夕（p〇iy)層2係藉由 (：¥.〇而沈積到10()11111至400 11111之範圍内。層3可包括氮氧化 物或作為一種設計選擇’其可被氮化，只要其適合作為閘 極介電質即可。 圖1B展示將第二表體晶圓結合至第一表體晶圓及移除基 板1〇5(譬如藉由研磨）及B0X層1〇7(譬如藉由在稀釋之氫氟 酸中蝕刻）之結果。該新基板在圖⑺中係由數字1來指示。 以將成為前閘極介電質之熱氧化物5再次氧化層4。層5 亦可為氮氧化物或被氮化。其視情況亦可為諸如Zr〇2、 Hf〇2、Al〇2之高介電材料或其他習知高介電常數（highk) 材料。另一多晶矽層6係藉由CVD來沈積，較佳厚度在7〇 nm 至250 nm之範圍内。 圖2展示將一對第一及第二圖案轉移層沈積至多晶矽層石 上之結果’圖解情況為1〇 nm至70 nm之氧化物（si〇2)之層7a 及10 nm至70 nm之氮化物（SisN4)之層7b。沈積並圖案化一 層光阻以界定前閘極。姓刻圖案轉移層以界定一硬式遮罩 並剝離該光阻。將該硬式遮罩用作一圖案來蝕刻多晶石夕層6 以形成第一（前）閘極8。 圖3展示沈積及界定將於第二或後閘極之形成期間保護 第一閘極8之層的結果。沈積一等形（conformal)氧化層9， 圖解情況為厚度為2 nm至10 nm之CVD TE0S。其次，、、尤積 一厚度為10 nm至100 nm之CVD氮化物薄膜。在習知定向触 145242.doc 201017878 射_職化物薄膜來移除水平方向上之薄膜以形成氮 化物分隔物10，從而終止氧化物薄膜9上之蝕刻。 圖4展不以下操作之結果：譬如以化學（HBj> -mistry)執行對層9及閘極層5之另—定向姓刻及一選擇 纟地移除石夕至氧化物（譬如化學邮）以餘刻通過層4、終止 於層3之定向㈣。前述定向㈣為習知的且―般被描述為 反應式離子蝕刻。 結果為將電晶體本體界定成在圖中左側及右側延伸越過 籲 帛閘電極分隔物9及10之厚度。分隔物9及10將被認為接 近閘極及電晶體本體之垂直邊緣，其意味著該等分隔物靠 近所參考之結構但不必直接與其接觸。可沈積額外概塾作 為姓刻終止物或作為絕緣體以保留在最終結構令。此圖中 電晶體本體之垂直邊緣係由數字11來指示且將被在後-階 段中所添加之額外矽接觸。正如與習知情況一樣，將根據 所》又·》十之電a曰體電流容量來設定垂直於紙平面之電晶體本 體厚度。 視情況而定，在紙平面之前方或後方可容許存在額外空 間以與將自層2所形成之低閘電極相接觸。 圖5展示沈積CVD氮化物之等形層並定向地將其蝕刻以 形成分隔物12之結果，該分隔物12保護電晶體本體之垂直 邊緣且亦界定將在以下步驟中被氧化之層2中之區域的邊 界。 圖解情況為，如圖6t所示，設定分隔物1〇及〗2之厚度以 有助於以下氧化步驟，其中層2係通過氧化層3而被氧化， 145242.doc 201017878 使得僅中心未氧化部分充當後閘電極，而符號〗3指示該後 閘電極之氧化部分。 熟習此項技術者不會考慮利用氧化物之橫向成長來穿透 於電晶體本體下方，因為吾人已認為，與矽相比，氧化物 體積之擴張會分層或在電晶體本體上施加不當之應力。 有利情況係，已發現橫向氧化物成長在多晶矽層2中係足 夠快的，從而使得所得之應力為可接受的。此外，已發現 若在約1000C或更高溫度下執行氧化約2〇分鐘或更長時 間，則由於Si〇2在此等條件下更具黏性，因此由氧化所產 生之應力將被緩和。 基於經驗對氧化步驟之參數進行調整以提供正確的側面 成長量。視情況而定，可在氧化之前使用磷或其它氧化促 進材料之傾斜離子植入（在圖5中由箭頭123或由陰影區域 125來示意性地表示）以有助於及控制橫向氧化範圍。關於 晶圓法線之角度將依鄰近結構之高度及間隔而定。基於經 驗來設定劑量及電壓。可藉由增加電壓來達成更多橫向穿 透。 其它或另外，可以正入射角執行氮（或其他氧化延遲材料） 植入，圖5中由箭頭127及陰影區域128來示意性地表示。含 有足夠量之氮的後閘極將延遲垂直方向上之氧化，從而能 夠給予垂直至橫向的氧化範圍更多控制及可撓性。可設定 電壓以在層2之頂部附近留下較少劑量’且在較低部分中留 下延遲劑量。 氧化朝向中心部分橫向穿透標稱30細至70細，且向下 穿透標稱30 nm至70 nm。 145242.doc 201017878 · 圖7展示沈積一 CVD氧化物薄膜14至標稱大於閘極堆（加 上層7a及7b)高度之厚度的結果，接著（譬如）在化學機械研 磨程序（CMP)中將該氧化物薄膜平面化。 在平面化之後，氧化物凹陷至小於閘極堆高度之高度（且 大於閘極8之高度）。
圖8展示（譬如）在熱磷酸中剝離分隔物丨0及12及帽7b以為 突起源極/汲極結構敞開一孔25之結果。具有10nm至7〇nm 之標稱厚度的另一氣化物分隔物15形成於該孔之垂直表面 • 上，以將S/D觸點自閘極隔離開。此時可在孔25中執行S/D 之習知幅度植入。無論此時或在圖9中所示之突起s/D步驟 之後，完成S/D即完成了該電晶體。 一習知清洗步驟（較佳為濕式清洗）移除來自電晶體本體 之垂直表面11的任何殘餘物以在該本體與突起S/D結構之 間形成良好接觸。 圖9展示藉由選擇性磊晶法或藉由非晶矽或多晶矽（p〇ly) 之沈積（具有或不具有S/D植入）用石夕16填充孔25之結果。平 ❿ 面化（譬如CMP)繼而乾式姓刻以使石夕凹陷導致了所示之結 構’其中孔27係用於習知互連之沈積以連接電晶體來形成 電路。 執行習知中段及後段步驟以完成該電路，為方便起見稱 作完成該電路。 使形成閘電極2及8之層具有足以為閘極提供合適傳導性 的習知攙雜劑濃度（或稍後植入）。類似地，突起S/D結構具 有在沈積期間所添加之適量攙雜劑。 145242.doc 201017878 形成電晶體本體之層4可具有習知攙雜劑濃度。熟習此項 技術者瞭解用以形成NFET及PFET之攙雜劑的類型及濃度。 程序流程 初始晶圓製備 以矽SOI層開始SOI晶圓 用於後閘極介電質之熱氧化物 用於後閘電極之多晶矽（poly) 結合載體晶圓 移除初始基板 移除初始BOX 前閘極介電質 前閘電極 閘極圖案化 圖案化轉移層1(氧化物） 圖案化轉移層2(氮化物） 圖案化前閘極 第一分隔物形成 沈積姓刻終止層 沈積分隔物層 定向蝕刻以形成分隔物 通道圖案化 蝕刻圖案化轉移層1 蚀刻通道，終止於後氧化物上 第二分隔物形成 145242.doc -10- 201017878 沈積分隔物材料 界定分隔物 界定自我對齊後閘極 氧化後閘極層’水平地延伸氧化以界 卜疋目我對齊閘極 沈積厚介電質，平面化 移除第一及第二分隔物 閘極隔離分隔物 S/D接觸沈積 儘管根據單一較佳實施例描述了本發明，但熟習此項技 術者將認識到：可在以下申請專利範圍之精神及範鳴内以 各種形式實施本發明。 【圖式簡單說明】 圖1A及1B展示原始未成型結構之形成中的步驟。 圖2展示一前閘電極。 圖3展示界定電晶體本體之第一對分隔物的形成。 圖4展示蝕刻SOI層以界定電晶體本體之結果。 圖5展示在氧化期間保護電晶體本體之第二對分隔物的 形成。 圖ό展示界定後閘電極寬度之氧化的結果。 圖7展示圍繞電晶體結構沈積介電質之結果。 圖8展示剝離分隔物以形成一固持突起S/D結構之孔的結 果。 圖9展示具有隔離介電質以絕緣S/D觸點之突起S/D觸點。 【主要元件符號說明】 145242.doc 201017878 1 轉移層 2 多晶石夕層 3 熱氧化層 4 單晶矽SOI層 5 熱氧化物/層 6 多晶矽層 7a, 7b 層 8 第一閘極 9 等形氧化層/氧化物薄膜/分隔物 10 分隔物 11 垂直邊緣/垂直表面 12 分隔物 14 氧化物薄膜 15 分隔物 16 矽 25, 27 孔 105 表體基板 107 埋藏氧化物（BOX) 123, 127 箭頭 125, 128 陰影區域 145242.doc -12-

Claims (1)

  1. 201017878 七、申請專利範圍： 1. -種形成於-具有一基板及—裝置層之半導體晶圓中之 雙閘極電晶體，該電晶體包括： 一位於該裝置層下方之後閘極介電層； 一位於該後閘極介電層下方之後閘電極； 位於該裝置層上方的前閘極介電層； 一位於該前開極介電層上方且與該後閘電極垂直對齊 之前閘電極； • 一安置於與該前閘電極對稱之該後閘極介電層上方之 電阳體本體，該後閘電極具有—形成於該電晶體本體下 方及於該後閘電極之一_心部分之任一侧邊上的一層氧 化物，從而定位與該前閘電極自我對齊之該後閘電極；及 位於該電晶體本體之相對側邊上的源電極及汲電極。 2. 如請求項1之電晶體，其中若干傳導性S/D接觸部件係安 置於該源電極及該汲電極上方，其在該前閘極介電上方 延伸至一位於一小於該前閘電極之高度的高度處之接觸 鲁 表面。 3. 如請求項1之電晶體，其中該裝置層包含一單晶矽矽上絕 緣體（SOI)層。 4. 如凊求項1之電晶體，其中該裝置層具有一從約2nm至 50nm之厚度。 5·如請求項1之電晶體，其中後閘極介電包括一熱氧化物、 一氮氧化物（oxynitride)、一氮化氧化物（nitridized 〇xide) 或其組合物β 145242.doc 201017878 6. 如請求項1之電晶體，其中該後閘極介電係為 物。 —熱氧化 7. 如請求項1之電晶體，其中該後閘極介 方—從約lnm 至3nm之厚度。 8. 如請求項1之電晶體，其中該後閘電極包括多晶石夕。 9. 如請求項丨之電晶體’其中該後閘電極具有一從約i〇〇nm 至40〇nm之厚度。 10. 如請求項丨之電晶體，其中該前閘極介電包括一熱氧化 物、一氮氧化物、一氮化氧化物、一高1^值極介電或其組 合物。 11·如請求項丨之電晶體，其中該前閘極介電包括一熱氧化 物0 12.如叫求項1之電晶體，其中該後閘極介電與該前閘極介電 都由一熱氧化物所組成。 13·如請求項1之電晶體，其中該前閘電極包括多晶矽。 14. 如請求項！之電晶體，其中該前閘電極具有一約4〇nm至 250nm之厚度。 15. —種形成於一具有一基板及一裝置層之半導體晶圓中之 雙閘極電晶體，該電晶體包括： 一位於該裝置層下方之後閘極熱氧化物層； 一位於該後閘極熱氧化物層下方之後閘電極； 一位於該裝置層上方的前閘極熱氧化物； 一位於該前閘極熱氧化物上方且與該後閘電極垂直對 齊之前閘電極； 145242.doc -2 - 201017878 一安置於與該前閘電極對稱之該後閘極熱氧化物層上 方之電晶體本體’職閘電極具有—形成於該電晶體本 體下方及於該後閘電極之_中心部分之任-側邊上的一 層氧化物，從而定位與該前閘電極自我對齊之該後閘電 極；及 位於該電晶體本體之相對侧邊上的源電極及汲電極。 16.如請求項15之電晶體，其中其中若干傳導性s/d接觸部件 係安置於該源電極及該汲電極上方，其在該前閘極熱氧 化物層上方延伸至一位於一小於該前閘電極之高度的高 度處之接觸表面。 17·如請求項15之電晶體，其中該前閘電極與該後閘電極都 包括多晶石夕。 18· —半導體結構，包含： 位於一包括一基板及一具有從約2ηηι至5〇11111厚度的單 晶矽矽上絕緣體（SOI)裝置層之半導體晶圓内之一雙閘極 電晶體，該電晶體包括： 一具有約從lnm至3nm厚度之後閘極熱氧化物層，其位 於該單晶矽矽上絕緣體（SOI)裝置層之下方； 一具有約從lOOnm至400nm厚度之後閘極多晶碎電 極’其位於該後閘極熱氧化物層之下方； 一前閘極熱氧化物’其位於該單晶矽矽上絕緣體（s〇I) 裝置層之上方； 一具有約從70nm至250nm厚度之前閘極多晶石夕電極 層，其位於該前閘極熱氧化物之上方且垂直地對準該後 145242.doc 201017878 閘極多晶石夕電極； 一安置於該後閘極熱氧化層上方之電晶體本體，對稱 於該前閘極多晶矽電極層，該後閘極多晶矽電極具有一 氧化層，其位於該電晶體本體之下方，並在該後閘極多 晶矽電極之中央部分兩側之其中一側上’藉此安置該後 閘極多晶矽電極自身對齊於該前閘極多晶矽電極層；源 電極與汲電極在該電晶體本體之相對側；且 若干傳導性S/D接觸部件係安置於該等源電極與汲電 極上方’該等傳導性S/D接觸部件在該前閘極熱氧化層上 延伸至-位於-小於該前閘極多晶石夕電極高度的高度處 之接觸表面。 145242.doc -4-
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