FR3059150B1 - Procede de realisation d'un transistor fet a grille debordante - Google Patents
Procede de realisation d'un transistor fet a grille debordante Download PDFInfo
- Publication number
- FR3059150B1 FR3059150B1 FR1661228A FR1661228A FR3059150B1 FR 3059150 B1 FR3059150 B1 FR 3059150B1 FR 1661228 A FR1661228 A FR 1661228A FR 1661228 A FR1661228 A FR 1661228A FR 3059150 B1 FR3059150 B1 FR 3059150B1
- Authority
- FR
- France
- Prior art keywords
- layer
- semiconductor
- producing
- gate
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 abstract 6
- 238000005530 etching Methods 0.000 abstract 3
- 239000004020 conductor Substances 0.000 abstract 1
- 239000002019 doping agent Substances 0.000 abstract 1
- 238000002513 implantation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Procédé de réalisation d'un transistor FET (103), comportant les étapes suivantes : - réalisation, sur une couche semi-conductrice cristalline, d'une couche diélectrique de grille sur laquelle est disposée une couche conductrice de grille, - gravure de la couche conductrice telle qu'une portion restante de cette couche recouvre entièrement une première portion (120) semi-conductrice formant une zone active et une deuxième portion semi-conductrice adjacente à la zone active, - implantation d'atomes et/ou de dopants dans la couche semiconductrice , amorphisant le semi-conducteur autour de la première portion et celui de la deuxième portion, - gravure de la portion restante de la couche conductrice et de la couche diélectrique selon un motif de grille recouvrant partiellement la première portion et la deuxième portion, formant la grille (122) et un débordement de grille, - gravure du semi-conducteur amorphe.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1661228A FR3059150B1 (fr) | 2016-11-18 | 2016-11-18 | Procede de realisation d'un transistor fet a grille debordante |
US15/816,328 US10121707B2 (en) | 2016-11-18 | 2017-11-17 | Method of fabrication of a FET transistor having an overlapped gate |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1661228 | 2016-11-18 | ||
FR1661228A FR3059150B1 (fr) | 2016-11-18 | 2016-11-18 | Procede de realisation d'un transistor fet a grille debordante |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3059150A1 FR3059150A1 (fr) | 2018-05-25 |
FR3059150B1 true FR3059150B1 (fr) | 2019-05-10 |
Family
ID=57590702
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1661228A Active FR3059150B1 (fr) | 2016-11-18 | 2016-11-18 | Procede de realisation d'un transistor fet a grille debordante |
Country Status (2)
Country | Link |
---|---|
US (1) | US10121707B2 (fr) |
FR (1) | FR3059150B1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112133706A (zh) * | 2019-06-25 | 2020-12-25 | 上海箩箕技术有限公司 | 半导体结构及其形成方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7078298B2 (en) * | 2003-05-20 | 2006-07-18 | Sharp Laboratories Of America, Inc. | Silicon-on-nothing fabrication process |
US7153753B2 (en) * | 2003-08-05 | 2006-12-26 | Micron Technology, Inc. | Strained Si/SiGe/SOI islands and processes of making same |
US7205185B2 (en) * | 2003-09-15 | 2007-04-17 | International Busniess Machines Corporation | Self-aligned planar double-gate process by self-aligned oxidation |
FR2961016B1 (fr) | 2010-06-07 | 2013-06-07 | Commissariat Energie Atomique | Circuit integre a dispositif de type fet sans jonction et a depletion |
US8507989B2 (en) * | 2011-05-16 | 2013-08-13 | International Business Machine Corporation | Extremely thin semiconductor-on-insulator (ETSOI) FET with a back gate and reduced parasitic capacitance |
FR3035265B1 (fr) * | 2015-04-16 | 2018-02-16 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de fabrication de transistors soi pour une densite d'integration accrue |
-
2016
- 2016-11-18 FR FR1661228A patent/FR3059150B1/fr active Active
-
2017
- 2017-11-17 US US15/816,328 patent/US10121707B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US10121707B2 (en) | 2018-11-06 |
US20180144992A1 (en) | 2018-05-24 |
FR3059150A1 (fr) | 2018-05-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8878300B1 (en) | Semiconductor device including outwardly extending source and drain silicide contact regions and related methods | |
CN103311299B (zh) | 具有漏斗形沟槽的屏蔽栅极mosfet装置 | |
US8729634B2 (en) | FinFET with high mobility and strain channel | |
WO2007021701A3 (fr) | Structure et procede permettant de former un dielectrique interpoly dans un transistor a effet de champ a grille blindee | |
WO2013002902A3 (fr) | Procédé et structure pour régions de source et de drain de faible résistivité dans un déroulement de processus à grille métallique de remplacement | |
TW200515596A (en) | Epitaxially deposited source/drain | |
JP2016532296A5 (fr) | ||
DE102015104597A1 (de) | Dislocation Stress Memorization-Technik (DSMT) an Epitaxialkanal-Bauelementen | |
EP2428986A3 (fr) | Réduction de la capacité de jonction de transistor par le renfoncement des régions de drainage et source | |
DE102006019937A1 (de) | SOI-Transistor mit eingebetteter Verformungsschicht und einem reduzierten Effekt des potentialfreien Körpers und ein Verfahren zur Herstellung des Transistors | |
TW200725890A (en) | Excessive round-hole shielded gate trench (SGT) MOSFET devices and manufacturing processes | |
WO2006079964A3 (fr) | Procédé pour produire un transistor à effet de champ à deux grilles | |
DE102015117320A1 (de) | Halbleitervorrichtung und deren herstellungsverfahren | |
GB2577197A (en) | Embedded bottom metal contact formed by a self-aligned contact process for vertical transistors | |
TW200608610A (en) | Process for fabricating a strained channel MOSFET device | |
US9502558B2 (en) | Local strain generation in an SOI substrate | |
US9929182B2 (en) | Semiconductor structure and fabrication method thereof | |
KR20090044799A (ko) | 액티브 핀의 제조 방법 및 이를 포함하는 트랜지스터 | |
DE102014115798A1 (de) | In einem Halbleitersubstrat ausgebildete Isolationsstruktur und Verfahren zum Ausbilden einer Isolationsstruktur | |
WO2012054144A3 (fr) | Structure semi-conductrice et ses procédés de fabrication | |
US20160172436A1 (en) | Semiconductor device, termination structure and method of forming the same | |
GB2577417A (en) | Super long channel device within VFET architecture | |
JP2018537858A5 (fr) | ||
FR3059150B1 (fr) | Procede de realisation d'un transistor fet a grille debordante | |
JP2019021871A5 (fr) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PLFP | Fee payment |
Year of fee payment: 2 |
|
PLSC | Publication of the preliminary search report |
Effective date: 20180525 |
|
PLFP | Fee payment |
Year of fee payment: 4 |
|
PLFP | Fee payment |
Year of fee payment: 5 |
|
PLFP | Fee payment |
Year of fee payment: 6 |
|
PLFP | Fee payment |
Year of fee payment: 7 |
|
PLFP | Fee payment |
Year of fee payment: 8 |