TW201010074A - A chipset with bundle magnetic capacitors and a method for manufacturing the said chipset - Google Patents

A chipset with bundle magnetic capacitors and a method for manufacturing the said chipset Download PDF

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Publication number
TW201010074A
TW201010074A TW97132333A TW97132333A TW201010074A TW 201010074 A TW201010074 A TW 201010074A TW 97132333 A TW97132333 A TW 97132333A TW 97132333 A TW97132333 A TW 97132333A TW 201010074 A TW201010074 A TW 201010074A
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TW
Taiwan
Prior art keywords
magnetic
integrated circuit
electrode
capacitor
substrate
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TW97132333A
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Chinese (zh)
Inventor
Shu-Ming Tsao
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Lite On Technology Corp
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Priority to TW97132333A priority Critical patent/TW201010074A/en
Publication of TW201010074A publication Critical patent/TW201010074A/en

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Abstract

A chipset with bundle magnetic capacitors and a method for manufacturing the said chipset are disclosed. The chipset comprises a substrate, a plurality of IC units, and a magnetic capacitor unit, wherein the magnetic capacitor unit connects to the IC units. The IC units and the magnetic capacitor unit collectively can be set in the said chipset by semiconductor manufacturing method. The magnetic capacitor unit offers the electricity to the said chipset. Therefore the size of the said chipset can be smaller and lighter.

Description

201010074 九、發明說明: 【發明所屬之技術領域】 本發明係有關於積體電路晶片及其製作方法,尤指一 種内建磁性電容之積體電路晶片及其製作方法。 【先前技術】201010074 IX. Description of the Invention: [Technical Field] The present invention relates to an integrated circuit chip and a method of fabricating the same, and more particularly to an integrated circuit chip having a built-in magnetic capacitor and a method of fabricating the same. [Prior Art]

拜科技之進步,許多電子產品(例如:個人電腦、手 機、或其他電子設備)提供各種功能使人們的日常生活更 為便利,更具體說明,電子產品之所以能提供特定功能, 其係藉由設置於電子產品内部的晶片運作達成的,亦即該 等晶片進行運算或控制,藉此使電子產品產生功能來提供 服,。然,未來的電子產品之設計概念趨向於重量輕、外 觀薄等特點’為了設計出更輕薄的電子產品, 減電子產品内部的空間實為考驗,而縮減電子肉 部的空間最直接的解決方式即是縮減晶片的體積,主^ 隨著晶片體積縮小,電子產品的外觀也可進一步縮=未者 而達到重量輕、外觀薄等目的。 、、’、,進 比較目前電子產品内之晶片的設計,可發現具有以下 缺點· 1、 目前電子產品内之晶片所需的電力皆是以外接 源的方式來提供晶片所需的電力,而以外接電力源 方式即表示增加電子產品的内部空間,因為除了/需要 設置晶片的空間外,還必須另外規劃出電力源 間’因此不容易縮小電子產品内的空間。 、二 2、 關於晶片外接的電力源,其係為目前常見的電池,而 5 201010074 雖然標榜著可重複使用,作 多次充放電或長時間不使用=辱命之限制。在 下降,且容易損壞,原因在=容量會 暂,買要保其活性,才不至於失效變 =合物活性都作用完或將近用完時,便 ^再進仃新的化學反應,進而導致電池老化而宣告 3、若是利用多顆電容來儲存電能 構複雜、空間過於龐大、成本“gj:電電路的結 緣是,本發明人有感上述缺失之可改善 理且有效改善上述缺失之本發明。 δ 【發明内容】 體積目的係在提供一種内建能量儲存密度高、 電容之積體電路晶片。 。命等優點的磁性 本發明之另一目的係提出以一 Capaeit:r)!^t^^ ; Β曰片内,以知:供晶片運作時所需之電力。 、 路曰供—種内建磁性電容之積體電 任何特疋功能之晶片内,使晶片無 來維持運作’藉此達到晶片整體輕薄短小的電力源 為了達成上述之目的,本發明係提供一種 容之積體電路⑼,其包括有:―形成有導電線路m電 6 201010074 複數個積體電路(ic)林,所述之積體電路 於該基板巾赠此紐連接4及—雖電 性電容單元設置於縣Μ,且該雜電容單元電性連接 所述之積體電路元件’以供應電力維持所述之積體電路元 件運作。 較佳地,該磁性電容單元包括由複數個磁性電容單元 以串聯或並聯等方式組成。 ❹ 較佳地,該磁性電容單元包含有一第一磁性電極、一 第二磁性電極以及設於其間之—介電層,其中該第一磁性 電極與第二磁性電極内具有磁偶極以抑制該磁 之漏電流。 平 較佳地,該第一磁性電極包含有:一第一磁性層,具 有排列成第-方向之磁偶極;一第二磁性層,具有排列成 第二方向之磁偶極;以及一隔離層,包含有非磁性材料, 設於該第-磁性層與該第二磁性層之間;其中該第一方向 與該第二方向互為反向,以抑制該磁性電容單元之漏電流。 • 本發明另提供一種積體電路晶片,其包括有:-基板; 複數個積體電路元件設於該基板上,各該積體電路元件相 互電連接;-磁性電容單元,設置於該基板上,可選擇性 的電連接至一外部電源,該磁性電容單元包含有至少一磁 性電谷,用來儲存電位能並提供一電力輸出至該些積體電 路元件;以及一放電單元,電連接於該磁性電容與該複數 個積體電路元件之間,該放電單元包含有一直流/直流轉換 器,用以控制該磁性電容單元至該些積體電路元件之電力 7 201010074 n 中當該外部電源未供應電力至該積體電路晶片 B’ ’ ’ t容會持續提供電力輸出至該 元件,以維持該複數個積體電路元件的運作。積體電路 -本=::====作 成複數個彼此電性連接的積體電路元件;形成-i性電^ 單兀於祕板中並^電性連接所述之積體電路元件。 “ Τ佳地ρ4 ,提供複數個基板’並以系統封裝 )方式《科並魏連接= 作二建磁性電容之積想電路晶片蝴 達到晶片整體輕薄短小的目的。、 ^進-步 可作為-極佳之能晋极升月b量館存密度,故 性電容單元輕^^置/電力供齡源,且由於磁 存,相較於主要以化學 以電位能的方式進行储 存密度外,更-分財衫 8 201010074 放電次數)、無記憶效應、可進行高功率輸出、快速充放電 等特點。 為使能更進一步瞭解本發明之特徵及技術内容,請參 閱以下有關本發明之詳細說明與附圖,然而所附圖式僅提 供參考與說明用,並非用來對本發明加以限制者。 【實施方式】Thanks to the advancement of technology, many electronic products (such as personal computers, mobile phones, or other electronic devices) provide various functions to make people's daily lives more convenient. More specifically, electronic products can provide specific functions. The operation of the wafers disposed inside the electronic product, that is, the wafers are operated or controlled, thereby enabling the electronic product to function to provide services. However, the design concept of future electronic products tends to be light in weight and thin in appearance. In order to design thinner and lighter electronic products, the space inside the electronic products is tested, and the most direct solution to reduce the space of the electronic meat department. That is, the volume of the wafer is reduced, and as the size of the wafer is reduced, the appearance of the electronic product can be further reduced to a lower weight and a thinner appearance. Comparing with the current design of the wafers in the electronic products, the following disadvantages can be found. 1. The power required for the wafers in the electronic products is the source of the external source to provide the power required by the wafer. The external power source mode means that the internal space of the electronic product is increased, because in addition to the space where the wafer needs to be set, the power source must be separately planned. Therefore, it is not easy to reduce the space in the electronic product. 2, 2, about the external power source of the chip, which is the current common battery, and 5 201010074 although it is advertised as reusable, for multiple charge and discharge or long time no use = insult limit. It is falling, and it is easy to be damaged. The reason is that if the capacity is temporary, it is necessary to protect its activity, so that it will not fail. If the compound activity is used or nearly used up, it will enter a new chemical reaction, which will lead to If the battery is aged, it is declared that if the capacitor is used to store the electric energy, the structure is complicated, the space is too large, and the cost is “gj: the connection of the electric circuit is, the present inventors are aware of the above-mentioned invention which can improve the rationality and effectively improve the above-mentioned deficiency. δ [Invention] The purpose of volume is to provide a built-in energy storage density, capacitance of the integrated circuit chip. The advantages of the magnetic properties of the invention Another object of the present invention is to present a Capaeit: r)! ^t^ ^ ; Inside the , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , To achieve the above-mentioned purpose, the present invention provides a capacitive integrated circuit (9) comprising: "formed with conductive lines m electricity 6 201010074 a plurality of integrated circuits (ic) Lin, the integrated circuit provides the button connection 4 to the substrate, and the electrical capacitor unit is disposed in the county, and the capacitor unit is electrically connected to the integrated circuit component Preferably, the magnetic capacitor unit comprises a plurality of magnetic capacitor units connected in series or in parallel, etc. Preferably, the magnetic capacitor unit comprises a first magnetic electrode, a second magnetic electrode and a dielectric layer disposed therebetween, wherein the first magnetic electrode and the second magnetic electrode have magnetic dipoles therein to suppress leakage current of the magnetic. Preferably, the first magnetic electrode comprises a first magnetic layer having a magnetic dipole arranged in a first direction; a second magnetic layer having a magnetic dipole arranged in a second direction; and an isolation layer comprising a non-magnetic material disposed on the Between the first magnetic layer and the second magnetic layer; wherein the first direction and the second direction are opposite to each other to suppress leakage current of the magnetic capacitor unit. The present invention further provides an integrated circuit chip. package a substrate is disposed on the substrate, and each of the integrated circuit components is electrically connected to each other; and a magnetic capacitor unit is disposed on the substrate and selectively electrically connected to an external power source. The magnetic capacitor unit includes at least one magnetic electric valley for storing potential energy and providing a power output to the integrated circuit components, and a discharge unit electrically connected between the magnetic capacitor and the plurality of integrated circuit components The discharge unit includes a DC/DC converter for controlling the power of the magnetic capacitor unit to the integrated circuit components 7 201010074 n when the external power source does not supply power to the integrated circuit chip B'' The device continuously supplies power to the component to maintain the operation of the plurality of integrated circuit components. The integrated circuit - this =::==== creates a plurality of integrated circuit components electrically connected to each other; forming -i The electrical circuit is electrically connected to the integrated circuit component. " Τ佳地ρ4, providing a plurality of substrates 'and system packaging) way "Ke Wei Wei connection = two built magnetic capacitors to think about the circuit chip to achieve the overall thin and short wafer. The ^ step - can be - Excellent energy can increase the density of the library, so the capacity of the capacitor unit is lighter than the power source, and because of the magnetic storage, compared with the storage density mainly by means of potential energy, -Finance shirt 8 201010074 discharge times), no memory effect, high power output, fast charge and discharge, etc. To enable a better understanding of the features and technical contents of the present invention, please refer to the following detailed description of the present invention. The drawings are to be construed as illustrative and not restrictive.

。青參閱第一 A圖所示,本發明係提出一種内建磁性電 谷之積體電路晶片1〇 〇,該積體電路晶片丄〇 〇包括 有· 一基板1、複數個積體電路(丨C)元件2以及一磁 性電容單元3 ’其巾該基板1形成有導·路1 1,而該 =數個频電路元件2設置於該基板!中,且該複數個積 神ί路元件2藉由該基板1的導電線路11使彼此互相電 、接,另外,該基板1、該複數個積體電路元件2與 成於基板1之導電線路11係以半導體製程製作。、 性電容單元3 πμ丁守菔眾程製作於基板丄中, =^板1之導電線路:L U電性連接該複數個積體電路 牛2。磁性電容單S3 ’可選擇性的電連接至一外 :(未顯示)’以作為充電之用。其中’磁性電容 = 3收的電力’係以電位能的形式進行儲存,並可二夕3斤 提^連接或未供應電力至積體電路晶片1⑽時 =輪出至積體電路元件2 ’以維持該積體電路元: 值得注_是,賴在習知_體電路晶片(圖 中,亦會有-些電容的設計’但由於其所能儲存的電力上 9 201010074 當小,因此其設計目白j多是作為-緩衝裝置(例如用於穩壓 或滤波)或是〆記憶單几(例如用於〇或1的訊號判別),因 此,都必鎮在有外部電力持續供應的狀況下,方能持續運 作。換言之,二旦,部電源停止供應電力,習知的積體電 路晶片(β未示)就會失去電力來源,而無法繼續運作。 而本發明中的磁性電容單元3則具有-㈣能量儲存能 力,因此,即使當積體電路晶片1 0 〇未連接至外部電源 時’亦能藉由磁性電容單元3内部所儲存的電力,來維持 癱· 積體電路晶片1 〇 〇 一段時間(例如數小時)的運作。 在本發明之一實施例中,積體電路晶片丄〇 〇另包含 有一放電單元4 (如第一 Β圖所示)’電連接於磁性電容單 元3與積體電路元件2之間,放電單元4包含有一直流/ 直流轉換器,用以根據積體電路元件2的電力需求來控"制 磁性電容單元3之電力輸出,舉例來說,可提供一定電壓 或定電流之電力輸出。 此外,亦可進一步設置複數個基板1 (圖未示),各基 • 板1皆設有所述之積體電路元件2與所述之磁性電容單二 3 ’且所述之積體電路元件2與所述之磁性電容單元3彼 此藉由導電線路11電性連接’其中各基板丄彼此垂直堆 疊且電性連接,進而形成三維積體電路晶片。 清參閱第一Α圖與第二圖所示’該磁性電容單元3包 含有至少一磁性電容(Magnetic Capacitor)3 0,磁性^ 容3 0的結構包括有:一第一磁性電極3 1、一第二磁性 電極3 2與一介電層3 3,該介電層3 3位於該第;:磁性 201010074 電極3 1與該第二磁性電極3 2之間,其中該介電層3 3 係用以分隔該第一磁性電極31與該第二磁性電極3 2, 藉此讓該第一磁性電極31與該第二磁性電極3 2能累積 電荷,儲存電位能。 在本發明之一實施例中,磁性電容單元3係包含有複 數個磁性電容3 0,且各磁性電容3 0係以串聯或並聯的 方式電連接,以調整磁性電容單元3之等效電壓值或電容 值,而符合產品之需求。 • 在此’進一步說明磁性電容3 0之結構與運作原理如 下’第—磁性電極31與第二磁性電極3 2係由磁性導電 材料構成,其中該第一磁性電極3 1與該第二磁性電極3 2接受適當的外加電場進行磁化,使得其内部形成二磁偶 極(Magnetic Dipole) 3 1 1、3 2 1,而該兩磁偶極 3 1 1、3 2 1之方向可為同向或反向(如第二圖與第三圖 所示)’該一磁偶極3 1 1、3 2 1於該磁性電容單元3内 部構成一磁場,對帶電粒子的移動造成影響,從而抑制該 φ 磁性電容單元3之漏電流。 所需要特別強調的是,第二圖與第三圖中磁偶極31 1、3 21的箭頭方向僅為一示意圖。對熟習該項技藝者 而言,應可瞭解到磁偶極3 1 1、3 2 1實際上係由多個 整齊排列的微小磁偶極所疊加而成,且在本發明中,磁偶 1 1、3 21最後形成的方向並無限定,可依磁性電 谷單70 3之形狀進行調整,例如可指向同一方向或不同方 向0 11 201010074 另外,該第一磁性電極31與該第二磁性電極3 2係 包含有磁性導電材質,例如稀土元素,而該介電層3 3係 由氧化鈦⑽3)、氧化鋇鈦(隨〇3)或一半導體層,例如.、 氧化石夕(Silicon Oxide)所構成;然而必須強調的是 明之磁性電容單元3並不限於此材料,該第一磁性電極3 1、該第二磁㈣極3 2與該介電層3 3均可視產 求而選用適當之其他材料。 進一步說明磁性電容單元3之操作原理:物質在一定 ❼磁場下電阻改變的現象,稱為「磁阻效應」,磁性金屬和合 金材料一般都有這種磁電阻現象,通常情況下,物質的電 阻率在磁場中僅產生輕微的減小;在某種條件下,電阻率 減小的幅度相當大,比通常磁性金屬與合金材料的磁電阻 值高出1 0倍以上,稱為「巨磁阻效應」(GMR)。進一步結 合Maxwell-Wagner電路模型,磁性顆粒複合介質中也可能 產生所謂的龐磁電容(Colossal magneto capacitance, CMC) 效應或巨磁電容(Giant magneto capacitance,GMC)效應。 % 由於習知電容中’電容值C係由電容之面積A、介電 層之介質常數心心及厚度d決定,如下公式所示: C — 111 d 然而在本發明中,磁性電容單元3主要利用第一磁性 電極3 1與第二磁性電極3 2中整齊排列的磁偶極3 1 1、3 21來形成磁場來,使内部儲存的電子朝同一自旋 方向轉動,進行整齊的排列,故可在同樣條件下,容納更 12 201010074 多的電荷,進而增加能量 本發明之磁性電容單元3之、子密度。類比於習知電容, 用來改變介電層3 3之介雷::原理相當於藉由磁場之作 提升。 數,故而造成電容值之大幅 此外’該第-磁性電極3 面3 4以及該第二磁性電極血層3 3之間的介 面35均為_=3 2與齡電層3 3之間的介 U丰坦 的表面’以藉由增加表面積A的方 式’進一步提升磁性電容單元3之電容值c。縣的方 -構=參2四圖,第四圖為該第-磁性電極3 !之 :構不意圖,該第—磁性電極3 i係為—多層 勺$ :-第-磁性層31 2、一隔離層313以及一第二二: 而該第-磁性層3 ! 2與該第二磁性層3 i j 磁性的導電材料’並在磁化時,藉由不同的外加電ς有你 得第-磁性層3 ;L 2與第二磁性層3丄4中的磁偶極3丄吏 21、3 141分別具有不同的方向,其中磁偶極312 1 3141的方向係為反向,藉此能進—步抑制本發 之磁性電容單元3的漏電流。 此外’需要強調的是,該第一磁性電極3 i之結構並 不限於前述之三層結構’而可以類似之方式,以複數個^ 性層與非磁性層不斷交錯堆疊,再藉由各磁性層内磁偶極 方向的調整來進一步抑制漏電流,甚至達到幾乎無漏電流 的效果。 & 由於習知儲能元件多半以化學能的方式進行彳諸存因 13 201010074 此都需要有一定的尺寸,否則往往會造成效率的大幅下 降。相較於此,本發明之磁性電容單元3係以電位能的方 式進行儲存,且因所使用之材料可適用於半導體製程,故 可藉由適當的半導體製程來形成該磁性電容單元3與該複 數個積體電路元件2,進而縮小磁性電容單元3之體積盥 重量。 〃 ❹. Referring to FIG. 1A, the present invention provides a built-in magnetic electric valley integrated circuit chip 1A, which includes a substrate 1, a plurality of integrated circuits (丨C) Element 2 and a magnetic capacitor unit 3' The substrate 1 is formed with a channel 1 and the number of frequency circuit elements 2 is disposed on the substrate! The plurality of integrated circuit elements 2 are electrically connected to each other by the conductive line 11 of the substrate 1. Further, the substrate 1, the plurality of integrated circuit elements 2 and the conductive lines formed on the substrate 1 The 11 series is manufactured in a semiconductor process. The capacitive capacitor unit 3 πμ丁守菔 is made in the substrate ,, =^ the conductive line of the board 1: L U is electrically connected to the plurality of integrated circuits. The magnetic capacitor single S3' can be selectively electrically connected to an external: (not shown) for charging. Wherein 'magnetic capacitance = 3 received power' is stored in the form of potential energy, and can be connected or not supplied to the integrated circuit chip 1 (10) when it is connected to the integrated circuit chip 1 (10) = rounded to the integrated circuit component 2 ' Maintaining the integrated circuit element: It is worth noting _ Yes, depending on the conventional _ body circuit chip (in the figure, there will also be some capacitor design 'but because of the power it can store on the 9 201010074 when it is small, so its design Many of them are used as buffers (for example, for voltage regulation or filtering) or for memory (for example, signal discrimination for 〇 or 1). Therefore, in the case of continuous supply of external power, In order to continue operation, in other words, the power supply of the part stops supplying power, and the conventional integrated circuit chip (β not shown) loses the power source and cannot continue to operate. The magnetic capacitor unit 3 of the present invention has - (4) Energy storage capacity, therefore, even when the integrated circuit chip 10 〇 is not connected to the external power source, the power stored in the magnetic capacitor unit 3 can be maintained to maintain the integrated circuit chip 1 period of time( In an embodiment of the invention, the integrated circuit chip further includes a discharge unit 4 (as shown in the first figure) electrically connected to the magnetic capacitor unit 3 and the integrated circuit component. Between the two, the discharge unit 4 includes a DC/DC converter for controlling the power output of the magnetic capacitor unit 3 according to the power demand of the integrated circuit component 2, for example, providing a certain voltage or a constant current. Further, a plurality of substrates 1 (not shown) may be further disposed, and each of the base plates 1 is provided with the integrated circuit component 2 and the magnetic capacitors 2 and 3' The integrated circuit component 2 and the magnetic capacitor unit 3 are electrically connected to each other by a conductive line 11 in which each substrate stack is vertically stacked and electrically connected to each other to form a three-dimensional integrated circuit wafer. In the second figure, the magnetic capacitor unit 3 includes at least one magnetic capacitor 30, and the magnetic capacitor 30 includes a first magnetic electrode 31 and a second magnetic electrode 32. One dielectric a layer 3 3 , the dielectric layer 33 is located between the first magnetic electrode 31 and the second magnetic electrode 3 2 , wherein the dielectric layer 33 is used to separate the first magnetic electrode 31 from the The second magnetic electrode 3 2 is configured to allow the first magnetic electrode 31 and the second magnetic electrode 3 2 to accumulate charge and store potential energy. In one embodiment of the invention, the magnetic capacitor unit 3 includes a plurality of The magnetic capacitors 30 and the magnetic capacitors 30 are electrically connected in series or in parallel to adjust the equivalent voltage value or capacitance value of the magnetic capacitor unit 3 to meet the requirements of the product. The structure and operation principle of the structure is as follows: 'The first magnetic electrode 31 and the second magnetic electrode 32 are made of a magnetic conductive material, wherein the first magnetic electrode 31 and the second magnetic electrode 32 receive an appropriate applied electric field. Magnetization such that a magnetic dipole 3 1 1 , 3 2 1 is formed inside thereof, and the directions of the two magnetic dipoles 3 1 1 , 3 2 1 may be in the same direction or in the opposite direction (as shown in the second figure) The third figure shows that 'the magnetic dipole 3 1 1 , 3 2 1 is in the magnetic The inside of the capacitor unit 3 constitutes a magnetic field, which affects the movement of the charged particles, thereby suppressing the leakage current of the φ magnetic capacitor unit 3. It is particularly emphasized that the directions of the arrows of the magnetic dipoles 31 1 and 3 21 in the second and third figures are only a schematic view. For those skilled in the art, it should be understood that the magnetic dipoles 3 1 1 , 3 2 1 are actually superposed by a plurality of neatly arranged micro magnetic dipoles, and in the present invention, the magnetic couple 1 The direction of the final formation of the first and third magnetic electrodes 31 and The 3 2 series includes a magnetic conductive material such as a rare earth element, and the dielectric layer 3 3 is composed of titanium oxide (10) 3), titanium ruthenium oxide (with 3) or a semiconductor layer, for example, Silicon Oxide. However, it must be emphasized that the magnetic capacitor unit 3 is not limited to this material, and the first magnetic electrode 31, the second magnetic (four) pole 3 2 and the dielectric layer 33 can be selected and used appropriately. other materials. Further explaining the operation principle of the magnetic capacitor unit 3: the phenomenon that the resistance of the substance changes under a certain ❼ magnetic field is called “magnetoresistive effect”, and magnetic metal and alloy materials generally have such a magnetoresistance phenomenon. Usually, the resistance of the substance The rate only produces a slight decrease in the magnetic field; under certain conditions, the resistivity decreases by a considerable amount, which is more than 10 times higher than the magnetic resistance of the magnetic metal and alloy materials, which is called "giant magnetoresistance". Effect" (GMR). Further in combination with the Maxwell-Wagner circuit model, so-called Colossal magneto capacitance (CMC) effects or Giant magneto capacitance (GMC) effects may also occur in magnetic particle composite media. % Since the capacitance value C in the conventional capacitor is determined by the area A of the capacitor, the dielectric constant core of the dielectric layer, and the thickness d, as shown in the following formula: C - 111 d However, in the present invention, the magnetic capacitor unit 3 is mainly utilized. The magnetic poles 3 1 1 and 3 21 arranged in the first magnetic electrode 31 and the second magnetic electrode 3 2 form a magnetic field, so that the internally stored electrons are rotated in the same spin direction and arranged neatly. Under the same conditions, more than 12,100,070,74 more charges are charged, thereby increasing the energy density of the magnetic capacitor unit 3 of the present invention. Analogous to conventional capacitors, used to change the dielectric layer of the dielectric layer 3: The principle is equivalent to the magnetic field. Therefore, the capacitance value is large, and the interface 35 between the first magnetic electrode 3 surface 34 and the second magnetic electrode blood layer 3 3 is both between _=3 2 and the age layer 3 3 . The surface of U Fontan 'furrows the capacitance value c of the magnetic capacitor unit 3 by increasing the surface area A. The square-construction of the county=the second figure of FIG. 2, and the fourth figure shows the first-magnetic electrode 3: the first magnetic electrode 3i is a multi-layer spoon $:-the first magnetic layer 31. An isolation layer 313 and a second two: and the first magnetic layer 3! 2 and the second magnetic layer 3 ij magnetic conductive material 'when magnetized, by different external power, you have the first magnetic The magnetic dipoles 3丄吏21, 3141 in the layer 3; L2 and the second magnetic layer 3丄4 respectively have different directions, wherein the directions of the magnetic dipoles 312 1 3141 are reversed, thereby enabling The step suppresses the leakage current of the magnetic capacitor unit 3 of the present invention. In addition, it should be emphasized that the structure of the first magnetic electrode 3 i is not limited to the foregoing three-layer structure, and in a similar manner, a plurality of layers and non-magnetic layers are continuously staggered and stacked, and then magnetically The adjustment of the magnetic dipole direction in the layer further suppresses the leakage current and even achieves an effect of almost no leakage current. & Because most of the conventional energy storage components are chemically energized. 13 201010074 This requires a certain size, otherwise it will often cause a significant drop in efficiency. In contrast, the magnetic capacitor unit 3 of the present invention is stored in a potential energy manner, and since the material used can be applied to a semiconductor process, the magnetic capacitor unit 3 can be formed by a suitable semiconductor process. The plurality of integrated circuit elements 2 further reduce the volume and weight of the magnetic capacitor unit 3. 〃 ❹

睛參閱$五圖所示’該磁性電容單元3可依據使用者 需求’利用半導體製程於該基板1上製作複數個小尺寸的 232元;,並藉由適當的金屬化製程,於該複數個 ,生電…3之間形成電性連接,從而構成一個包含有 容單元3的磁性電容組4 ’再以該磁性電容組 4作為電力供應的來源。 陣列内的複數個磁性電容單元3係以類似 同的電壓ίίίϊ:而t發明;不限於此:而可根據不 各種不同裝置的電力供應聯或並聯’以滿足 電池或超級電。容)主: 置’仁在此同時’其所能產 〜裝 :;=而無法快速的充於 且充放電次數有限,渦谇 刀午褥出, 過度充放時易滋生各種問題。相較於 201010074 =;性因電:3:了中=量全部係以電位能的方 次數)、無記憶效應、可進行高功率輸出、 問題。等特點,故可有效解決當前電池所遇到的各種Referring to the figure shown in FIG. 5, 'the magnetic capacitor unit 3 can make a plurality of small-sized 232 yuan on the substrate 1 by using a semiconductor process according to the user's requirements; and by a suitable metallization process, the plurality of An electrical connection is formed between the generators 3 to form a magnetic capacitor group 4' containing the capacitor unit 3, and the magnetic capacitor group 4 is used as a source of power supply. The plurality of magnetic capacitor units 3 in the array are similar in voltage ίίίϊ: and are not limited thereto: they can be connected or paralleled according to the power supply of various devices to satisfy the battery or the super power. Rong) Lord: Set the 'ren at the same time' and its ability to produce ~ installed :; = can not be quickly filled and the number of charge and discharge is limited, the vortex knives smashed out, easy to breed problems when overcharged. Compared with 201010074 =; sexual power: 3: the medium = the amount of all the potential energy), no memory effect, high power output, problems. And so on, it can effectively solve the various problems encountered by current batteries.

圖,圖所示,並配合參考第-A圖與第-B 提供—基板1 ’其中該基板1為砍基材,且 月以"導體製程來製作導電線路工工於基板工。 曰曰 =利用半導體製程於基板工甲形成複數個彼此電性 Ϊ接的積體電路元件2,而複數個積體電路元件2使得 製程完成後的麵電路晶片i⑽可提供特定功能,例 如:該積體電路晶片i 〇 ◦為處理器(Pr〇cesser) 一 B曰 片、控制器(Controller)晶片或是其他特定功能之 片。 (C)進一步以半導體製程製作該磁性電容單元3於該 基板1中並且電性連接所述之積體電路元件2,俾藉^ 磁性電容單元3來儲存電能,以提供積體電路晶片ϋ 0所需的電力,使積體電路晶片i 0 〇無需外接任 力源來維持運作。 € 值得注意的是,為說明方便起見,在前述之步驟說明 中,係將積體電路元件2、磁性電容單元3以及其他電連 15 201010074 接製程分開描述,然而前沭牛酿+ & 序要求,對熟習該項技在,時’並無特定之順 對各項半導體製程進行製程磐^。應可根據產品之設计, 另外必須提及的是,兮·其心、 板1設置有所述之積體電亦可設置複數個,各基 該複數個基板磁性電容單元3,且 來形成三維積體電路晶片。(Systeralnpackaging’slp) ❹作方ί:有磁性電容之積體電路晶片及其製 1、建電路晶片’是_ 源:止供應電力時,仍可維持晶片繼續運作。 、而==容:元可以半導體製程來製作,進 的目的。、里丈可輕易達到晶片整體輕薄短小 3、製==7編_侧的以半導體 4 能:理電器容=::)^ M 、〇CeSSer)或控制器(Control ler)。 來係藉由於上、下電極處形成之磁場, 極佳之能量儲存裝置或電力供故可作為一 式ί ίίΐ \\中 =存的能量全部係以電位能的方 儲存’且具有可匹配的能量儲存密度,更因充 201010074 分保有電容的特性,而具有壽命長、無記憶效應、可 進行高功率輸出、快速充放電等特點。 惟以上所述僅為本發明之較佳實施例,非意欲侷限本 發明之專利保護範圍,故舉凡運用本發明說明書及圖式内 容所為之等效變化,均同理皆包含於本發明之權利保護範 圍内,合予陳明。 【圖式簡單說明】 第一 A圖係本發明之内建磁性電容之積體電路晶片之 ❿ 架構示意圖。 第一 B圖係本發明之内建磁性電容之積體電路晶片之 另·一架構不意圖。 第二圖係本發明之磁性電容單元之結構示意圖。 第三圖係本發明之磁性電容單元之另一結構示意圖。 第四圖係本發明之磁性電容單元之第一磁性電極之結 構示意圖。 第五圖係本發明之磁性電容組之架構示意圖。 • 第六圖係本發明之磁性電容單元與其他習知能量儲存 媒介之比較示意圖。 第七圖係本發明之内建磁性電容之積體電路晶片之製 作方法流程圖。 【主要元件符號說明】 100 積體電路晶片 1 基板 17 201010074 11 導電線路 2 積體電路元件 3 磁性電容單元 30 磁性電容 31 第一磁性電極 3 1 1 磁偶極 3 1 2 第 一磁性層 3 1 2 1 3 1 3 隔 離層 3 1 4 第 二磁性層 磁偶極 磁偶極 3 14 1 32 第二磁性電極 321 磁偶極 3 3 介電層 3 4 介面 3 5 介面 4 磁性電容組 18As shown in the figure, with reference to the drawings -A and -B, the substrate 1 ' is used as the substrate to be cut, and the conductive circuit is fabricated on the substrate by the conductor process.曰曰=Using a semiconductor process to form a plurality of integrated circuit elements 2 electrically connected to each other on the substrate, and the plurality of integrated circuit elements 2 enable the surface circuit chip i (10) after the process is completed to provide a specific function, for example: The integrated circuit chip i is a processor (Pr〇cesser), a B chip, a controller chip or other specific function chip. (C) further manufacturing the magnetic capacitor unit 3 in the substrate 1 by a semiconductor process and electrically connecting the integrated circuit component 2, and storing the electrical energy by the magnetic capacitor unit 3 to provide an integrated circuit chip ϋ 0 The required power is such that the integrated circuit chip i 0 〇 does not require an external source of power to maintain operation. It is worth noting that for the convenience of explanation, in the above description of the steps, the integrated circuit component 2, the magnetic capacitor unit 3 and the other electrical connections 15 201010074 are separately described, but the former 沭 牛 牛 + & The order requires that there is no specific process for the semiconductor process to be familiar with the skill. According to the design of the product, it must be mentioned that the core and the board 1 are provided with the integrated body, and a plurality of the plurality of substrate magnetic capacitor units 3 are formed. Three-dimensional integrated circuit chip. (Systeralnpackaging'slp) ί : : 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积 积And ==容: Yuan can be made by semiconductor process, the purpose of entering. Lizhang can easily reach the overall thinness and shortness of the wafer. 3. System==7 _ side of the semiconductor 4 can: electrical equipment capacity =::) ^ M, 〇CeSSer) or controller (Control ler). Thanks to the magnetic field formed at the upper and lower electrodes, an excellent energy storage device or power supply can be used as a type of energy stored in the potential energy and has a matching energy. The storage density, as well as the charge of 201010074, has the characteristics of long life, no memory effect, high power output, fast charge and discharge. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Therefore, the equivalents of the present invention and the equivalents of the drawings are all included in the present invention. Within the scope of protection, it is given to Chen Ming. BRIEF DESCRIPTION OF THE DRAWINGS The first A diagram is a schematic diagram of the 架构 architecture of the integrated circuit chip of the built-in magnetic capacitor of the present invention. The first B diagram is not intended to be another architecture of the integrated circuit chip of the built-in magnetic capacitor of the present invention. The second figure is a schematic structural view of the magnetic capacitor unit of the present invention. The third figure is another schematic structural view of the magnetic capacitor unit of the present invention. The fourth figure is a schematic view showing the structure of the first magnetic electrode of the magnetic capacitor unit of the present invention. The fifth figure is a schematic diagram of the structure of the magnetic capacitor group of the present invention. • Figure 6 is a schematic diagram comparing the magnetic capacitor unit of the present invention with other conventional energy storage media. Fig. 7 is a flow chart showing the method of manufacturing the integrated circuit chip of the built-in magnetic capacitor of the present invention. [Description of main component symbols] 100 Integrated circuit chip 1 Substrate 17 201010074 11 Conductive line 2 Integrated circuit component 3 Magnetic capacitor unit 30 Magnetic capacitor 31 First magnetic electrode 3 1 1 Magnetic dipole 3 1 2 First magnetic layer 3 1 2 1 3 1 3 Isolation layer 3 1 4 Second magnetic layer Magnetic dipole magnetic dipole 3 14 1 32 Second magnetic electrode 321 Magnetic dipole 3 3 Dielectric layer 3 4 Interface 3 5 Interface 4 Magnetic capacitor group 18

Claims (1)

201010074 f·、申請專利範園: 1二=Γ電容之積體電路晶片,其包括有: 一形成有導電線路之基板; 複數個積體電路(I c)元件,所 ^ ^A . 所述之積體電路元件 g 又置於该基板中且彼此電性連接;以及 一磁性電料元,設置於縣板巾,且雜連接 之積體電路元件’該磁性電容單元係用來儲存電位能,並 供應電力維持所述之積體電路元件運作。 2、 如申請專利第1項所述之内建磁性電容 ,電路晶片’其中該磁性電容單元包含有至少—個磁 容,該磁性電容包含有: 电 一第一磁性電極; 一第二磁性電極;以及 一介電層,該介電廣炎設於該第一谢生電極與 磁性電極之間,其中該第-磁性電極與該第二磁性電: 具有一磁偶極(Magnetic Dip〇es)以抑制該磁性 之漏電流。 电奋早7〇 3、 如申請專利範圍第2項所述之内建磁 體電路晶片,其中該第〆磁性電極之磁偶極之積 電極之磁偶極指向同一方向。 、/弗一磁性 4、 如申請專利範圍第2項觀之内建磁 體電路晶片’其中該第,磁性電極之磁偶 奋之積 電極之磁偶極互為反向。 、以第二磁性 201010074 體電路晶t申ΐ專利範圍第2項所述之内建磁性電容之積 其中該第一磁性電極包含有: 一第〜礤性層; 一第二礤性層;以及 該第二之^含有非磁性材料’設於該第-磁性層與 6、士 體電路晶片申2利範圍第5項所述之内建磁性電容之積 偶極,而該第」該第一磁性層具有排列成第一方向之磁 該第一方向〜磁性層具有排列成第二方向之磁偶極,且 抑制該磁性電方向之磁偶極互為反向,以 體電:晶:申之積 其二=性電容之積想電路晶㈣作方法, (A)提供一基板; 1中形成複數倾此電性連接的_電路元件於該基 ⑹利用半導體製程,於該基板上形成 ::該磁性電容單元係電性連接至所述之積= 201010074 9、如申請專利範圍第8項所述之内建磁性電容之積 體電路晶片之製作方法,其進一步提供複數個基板,並以 系統封裝(System in Packaging, SIP)方式以堆疊並電性 連接各基板。 1 0、一種積體電路晶片,其包括有: 一基板; 複數個積體電路元件設於該基板上,各該積體電路元 件相互電連接; ⑩ 一磁性電容單元,設置於該基板上,可選擇性的電連 接至一外部電源,該磁性電容單元包含有至少一磁性電 容,用來儲存電位能並提供一電力輸出至該些積體電路元 件;以及 一放電單元,電連接於該磁性電容與該複數個積體電 路元件之間,該放電單元包含有一直流/直流轉換器,用以 控制該磁性電容單元至該些積體電路元件之電力輸出; 其中當該外部電源未供應電力至該積體電路晶片時, φ 該磁性電容會持續提供電力輸出至該複數個積體電路元 件,以維持該複數個積體電路元件的運作。 21201010074 f·, application for patent garden: 1 2 = tantalum capacitor integrated circuit chip, comprising: a substrate formed with a conductive line; a plurality of integrated circuit (I c) components, ^ ^ A. The integrated circuit component g is further disposed in the substrate and electrically connected to each other; and a magnetic electric element is disposed on the county plate, and the integrated circuit component of the miscellaneous connection is used to store potential energy And supplying power to maintain the operation of the integrated circuit components. 2. The built-in magnetic capacitor according to claim 1, wherein the magnetic capacitor unit comprises at least one magnetic volume, the magnetic capacitor comprising: an electric first magnetic electrode; a second magnetic electrode And a dielectric layer disposed between the first X-ray electrode and the magnetic electrode, wherein the first magnetic electrode and the second magnetic electrode: having a magnetic dipole (Magnetic Dip〇es) In order to suppress the leakage current of the magnetic. The electric magnetic circuit chip described in claim 2, wherein the magnetic dipoles of the magnetic dipoles of the magnetic electrodes of the second magnetic electrode point in the same direction. / / 弗-magnetic 4, as in the scope of the patent application of the second item of the built-in magnetic circuit chip 'where the magnetic electrode of the magnetic electrode of the magnetic pole of the electrode is opposite to each other. The first magnetic electrode includes: a first erbium layer; a second erbium layer; and the second magnetic layer 20101074 The second non-magnetic material is disposed on the first magnetic layer and the dipole of the built-in magnetic capacitor described in item 5 of the second circuit of the circuit of the circuit board, and the first The magnetic layer has a magnetic field arranged in a first direction, the first direction, the magnetic layer, and the magnetic dipoles arranged in the second direction, and the magnetic dipoles in the magnetic direction are opposite to each other, and the body is electrically: The product of the two = capacitive capacitors (4) is used as a method, (A) provides a substrate; 1 is formed in a plurality of electrically connected _ circuit components on the substrate (6) using a semiconductor process, formed on the substrate: The magnetic capacitor unit is electrically connected to the product of the product = 201010074. The manufacturing method of the integrated circuit capacitor of the built-in magnetic capacitor according to claim 8 of the patent application further provides a plurality of substrates, and System in Packaging (SIP) The substrates are stacked and electrically connected. 10, an integrated circuit chip, comprising: a substrate; a plurality of integrated circuit components are disposed on the substrate, each of the integrated circuit components are electrically connected to each other; 10 a magnetic capacitor unit disposed on the substrate Optionally electrically connected to an external power source, the magnetic capacitor unit includes at least one magnetic capacitor for storing potential energy and providing a power output to the integrated circuit components; and a discharge unit electrically connected to the magnetic Between the capacitor and the plurality of integrated circuit components, the discharge unit includes a DC/DC converter for controlling the power output of the magnetic capacitor unit to the integrated circuit components; wherein when the external power source is not supplied with power In the integrated circuit chip, φ the magnetic capacitor continuously supplies power to the plurality of integrated circuit components to maintain operation of the plurality of integrated circuit components. twenty one
TW97132333A 2008-08-25 2008-08-25 A chipset with bundle magnetic capacitors and a method for manufacturing the said chipset TW201010074A (en)

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