TW200943384A - Spacer double patterning for lithography operations - Google Patents

Spacer double patterning for lithography operations

Info

Publication number
TW200943384A
TW200943384A TW098101692A TW98101692A TW200943384A TW 200943384 A TW200943384 A TW 200943384A TW 098101692 A TW098101692 A TW 098101692A TW 98101692 A TW98101692 A TW 98101692A TW 200943384 A TW200943384 A TW 200943384A
Authority
TW
Taiwan
Prior art keywords
pattern
spacer
substrate
spacer material
initial
Prior art date
Application number
TW098101692A
Other languages
English (en)
Other versions
TWI452607B (zh
Inventor
Christophe Pierrat
Original Assignee
Cadence Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cadence Design Systems Inc filed Critical Cadence Design Systems Inc
Publication of TW200943384A publication Critical patent/TW200943384A/zh
Application granted granted Critical
Publication of TWI452607B publication Critical patent/TWI452607B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
TW098101692A 2008-01-16 2009-01-16 微影操作之隔離層雙重圖案化 TWI452607B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/014,985 US7927928B2 (en) 2008-01-16 2008-01-16 Spacer double patterning for lithography operations

Publications (2)

Publication Number Publication Date
TW200943384A true TW200943384A (en) 2009-10-16
TWI452607B TWI452607B (zh) 2014-09-11

Family

ID=40885618

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098101692A TWI452607B (zh) 2008-01-16 2009-01-16 微影操作之隔離層雙重圖案化

Country Status (5)

Country Link
US (2) US7927928B2 (zh)
JP (1) JP5356410B2 (zh)
CN (2) CN102543688B (zh)
TW (1) TWI452607B (zh)
WO (1) WO2009091665A1 (zh)

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Publication number Priority date Publication date Assignee Title
US8255837B2 (en) * 2009-02-03 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for cell boundary isolation in double patterning design
US8692310B2 (en) 2009-02-09 2014-04-08 Spansion Llc Gate fringing effect based channel formation for semiconductor device
CN101963755B (zh) 2009-06-26 2012-12-19 罗门哈斯电子材料有限公司 自对准间隔物多重图形化方法
US8584052B2 (en) * 2010-12-22 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cell layout for multiple patterning technology
US8726215B2 (en) 2011-08-02 2014-05-13 Synopsys, Inc. Standard cell placement technique for double patterning technology
US8309462B1 (en) 2011-09-29 2012-11-13 Sandisk Technologies Inc. Double spacer quadruple patterning with self-connected hook-up
US8802574B2 (en) 2012-03-13 2014-08-12 Globalfoundries Inc. Methods of making jogged layout routings double patterning compliant
US8997026B1 (en) * 2012-05-11 2015-03-31 Cadence Design Systems, Inc. System and method for self alignment of pad mask
US8799834B1 (en) * 2013-01-30 2014-08-05 Taiwan Semiconductor Manufacturing Company Limited Self-aligned multiple patterning layout design
US8806393B1 (en) 2013-03-25 2014-08-12 International Business Machines Corporation Generation of design shapes for confining stitch-induced via structures
US9601367B2 (en) 2013-03-25 2017-03-21 International Business Machines Corporation Interconnect level structures for confining stitch-induced via structures
US9141744B2 (en) 2013-08-15 2015-09-22 United Microelectronics Corp. Method for generating layout pattern
US9274413B2 (en) * 2013-09-11 2016-03-01 United Microelectronics Corp. Method for forming layout pattern
US8966412B1 (en) * 2013-09-24 2015-02-24 Globalfoundries Inc. Methods of generating circuit layouts that are to be manufactured using SADP techniques
KR102185281B1 (ko) 2014-01-09 2020-12-01 삼성전자 주식회사 자기 정렬 더블 패터닝 공정을 이용하여 반도체 소자의 패턴을 형성하는 방법
US9454631B2 (en) 2014-05-23 2016-09-27 International Business Machines Corporation Stitch-derived via structures and methods of generating the same
US9710592B2 (en) 2014-05-23 2017-07-18 International Business Machines Corporation Multiple-depth trench interconnect technology at advanced semiconductor nodes
US10290528B2 (en) 2014-06-13 2019-05-14 Intel Corporation Ebeam align on the fly
TWI559487B (zh) * 2014-10-02 2016-11-21 旺宏電子股份有限公司 線路佈局及其間隙壁自對準四重圖案化的方法
US11107658B2 (en) 2016-09-30 2021-08-31 Intel Corporation Fill pattern to enhance e-beam process margin
CN114830294A (zh) * 2019-11-01 2022-07-29 应用材料公司 抗结晶的基于非晶硅的膜

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JPH03257825A (ja) * 1990-03-07 1991-11-18 Toshiba Corp 半導体装置の製造方法
JPH03261126A (ja) * 1990-03-12 1991-11-21 Nikko Kyodo Co Ltd パターン形成方法
US5140388A (en) 1991-03-22 1992-08-18 Hewlett-Packard Company Vertical metal-oxide semiconductor devices
JP3087364B2 (ja) * 1991-08-27 2000-09-11 株式会社日立製作所 マスクの製造方法
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JPH06216084A (ja) * 1992-12-17 1994-08-05 Samsung Electron Co Ltd 半導体装置のパターン分離方法および微細パターン形成方法
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JP3581628B2 (ja) * 2000-03-13 2004-10-27 沖電気工業株式会社 半導体装置の製造方法
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JP4580656B2 (ja) * 2004-01-28 2010-11-17 ルネサスエレクトロニクス株式会社 二重露光フォトマスクおよび露光方法
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Also Published As

Publication number Publication date
CN101910940A (zh) 2010-12-08
CN101910940B (zh) 2013-06-05
US20110018146A1 (en) 2011-01-27
US8278156B2 (en) 2012-10-02
TWI452607B (zh) 2014-09-11
US20110012237A1 (en) 2011-01-20
CN102543688B (zh) 2015-05-20
WO2009091665A1 (en) 2009-07-23
CN102543688A (zh) 2012-07-04
JP2011514655A (ja) 2011-05-06
JP5356410B2 (ja) 2013-12-04
US7927928B2 (en) 2011-04-19

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