200942105 几、贫明說明： 【發明所屬之技術領域】 ,本發明係有關於一種嵌埋有半導體元件之封装基板 衣法，其係可裸露半導體元件之非主動面以達散熱效果。 "【先前技術】 由於電子產品日趨輕薄短小，故對於用於承載半導體 元件或電子元件之封裝基板亦需隨之縮減，而半導體封裝 技術的演進已開發出不同的封裝型態，其中如球栅陣列^ ❾（Ball gr 1(i array’ BGA),係為一種先進的半導體封裝技 術，其特點在於採用一基板來安置半導體晶片。 惟’傳統上該球栅陣列式之半導體封裝結構係將半導 體晶片以覆晶接合（Flip chip)方式與基板電性連接，雖 可達到高腳數的目的，然在更高頻使用時或高速操作時， 因導線連接路徑過長而產生電氣特性無法提昇，因而效能 有所限制；另外，因傳統封裝需要多次的連接介面，相對 地增加生產製造成本。 為能有效地提昇電性品質而符合下世代產品之應 用，業界紛紛研究採用將半導體晶片埋入封裝基板中以直 接電性連接，而可縮短電性傳導路控，並減少訊號損失及 讯號失真，以提昇在高速運作之能力。 請參閱第1A1 10;圖，係為習知將半導體晶片嵌埋在 封裝基板中之製法剖視圖。 如第1A圖所示’首先’提供一第一基板1〇&及第二 基板10b，其中該第-基板1〇a係具有至少一貫穿之開口 110593 5 200942105 ιυυ ° 如弟1B圖所示’將該第一基板i 〇 a結合於該第二基 板10b上，且於該第一基板i〇a之開口 1〇〇中容置有一半 導體晶片11 ’並以結合材料11 〇將該半導體晶片j丨固定 於該開口 100中，該半導體晶片丨丨係具有一主動面！丄a 及與該主動面11a相對之非主動面llb，且該主動面 係具有複數電極墊111，以供線路層電性連接至該半導體 晶片11。 ❹ 如第1C圖所示，於該第一基板l〇a及半導體晶片u 之主動面11a上形成有一增層結構12，以將該半導體晶 片11嵌埋於第一及第二基板l〇a，l〇b中，該增層結構Γ2 係包括至少-介電層12〇、疊置於該介電層ΐ2〇上之線路 層121，以及複數形成於該介電層120中之導電盲孔122, 且4伤之導電盲孔122電性連接該半導體晶片u之電極 墊111，又於該增層結構12上具有複數電性接觸墊， ❹生m123電性連接該線路層121;另於該增層 、，構12上形成有防焊層13,且該防焊層13中 開孔13Q以對應露出該電性接㈣123。 ^ 然：前述製法中’該半導體晶片u 板1 0a中，且該篦-1 4c , m ^ 在· 1〇η , 基板1013封住該第一基板10a之開口 1 0 0的一;^ ’故該半導體曰 县4屮.日陣—導日日片11運作時所產生之熱量不 易政出，且酼者半導體晶片效 的熱量亦明顯增加，如盖法 ’、θ，*而伴隨產生 導體晶片之性能及壽命，。、冑效進仃散熱’將嚴重影響半 ]10593 6 200942105 因此，如何提出一種半導體晶片嵌埋式封裝結構，以 克服習知半導體封裝結構製程中結構不易散熱等問題银 已成為目前業界亟待解決之課題。 只 【發明内容】 • #於以上所述習知技術之缺失，本發明之—目 提供一種叙埋有半導體元# ; 件之封裝基板製法，係裸露半導 體讀之非主動面以達散熱效果。 备牛導 為達上揭目的’本發明提供一種嵌埋 ❹，基板製法，係包括:提供一嵌埋有半導體晶片= ，主=1?片具有一主動面及相對應之非主動 " 具有複數電極墊，該介電層之二表面分別且有望 增及弟一金屬層’且该介電層接觸於該第一 侧為第一表面，接觸於― w 、Μ第一金屬層侧為相對應之第二表 ，〜弟一及第二金屬層經圖案j ^ ^ 第一矣；π 〇、& Μ杀亿I釭以於该介電層之 第一 “第一線路層’而於該介電層之第二表面形成 ❹以及移除形成於該半導體晶片之非主動面 層以露出該半導體晶片之非主動面。 依上述之製法，該嵌埋有半導 表面具有之第一月m 守歷Β曰月之"電層及於其 一入 第一金屬層之製法，係包括：提供一第 穿之門口「 層’其中該第二介電層中形成有-貫 曰曰片，於該第-介電層之外側置設有一第一…: 該筮—人布院 且叹有弟一金屬層’並於 屬：…I電層及該半導體晶片之非主動面設 屬層，以及愿合該第一金屬層、第一介電層、第二介電層 110593 7 200942105 及弟二金屬層’使該第—介電層及第 層以固定該半導體„日H甘丄 曰。成一介電 a ^ 片，其中，該介電層接觸於嗲m ， 屬層側成為第一表面，％a 苐一金 二表面。 衣面二金屬層側成為相對應之第 .之製法，該嵌埋有半導體晶片之介電層及於 ιίΓ 金屬層之製法，係包括：提供由第 金屬：及第一介電層組成之第一背膠銅羯，及由第 屬層及第二介電層組成之第二背膠銅绪，且該第n 成有-貫穿之開口區；於該第二介電層之：口“ 奋叹該半導體晶片；以及壓合該第—背 膠銅箔，使該第一介雷思白汉弟一月 —/ 電層及第二介電層合成一介電層以固 疋該半導體晶片，其中，該介電層接觸於該第一金屬層側 成為第一表面，於該第二金屬層側成為相對應之第二表 面。 或依上述之製法，該嵌埋有半導體晶片之介電層及於 ❹其表面具有之第一及第二金屬層之製法，係包括：提供由 5二金屬層及第二介電層組成之第二背膠銅箔、具有核心 介電層開口之核心介電層、及係由第一金屬層及第一介電 層組成之第一背膠銅箔；於該第二背膠銅箔之第二介電 層上接置该半導體晶片之非主動面，且該核心介電層開口 對應該半導體晶片；壓合該第一背膠銅箱、核心介電層、 及第二背膠銅箔，使該第一介電層、核心介電層及第二介 電層合成一介電層’並將該半導體晶片固定於該介電層， 其中該介電層於該第一金屬層侧係為第一表面，而於該第 8 110593 200942105 -金屬層側係為相對應之第二表面。 又依上述之製法，該嵌 其表面具有之第-及第二金屬/之¥^晶片么之介電層及於 承載板’於該承載板上設有由第'包# :提供-_成之第二背膠銅_， 一、蜀自及第二介電層組 ，置於該承載板㈣以其第二金屬層接 以露出該承载板之部二銅落中形成有-開口區， 接置該半導體晶片之非主：面於：開口區中之承載板上 ❹開口之核心介電層、以及由動第面，】：供具有核心介電層 之第-背膠銅箔，”，’枋〃屬層與第一介電層組成 晶片，· Μ合該第介電層開口對應該半導體 羯，使該第—介電層、椤：八)1電層、及第二背膠銅 電層，以將該半導體曰二電層及第二介電層合成-介 等篮日日片固夂於該介電 於該第-金屬層側係為第 =曰/、中该介電層 為相對應之第_表面...^ ;該第二金屬層側係 體晶片之非以及移除該承載板，以露出該半導 依前述之製法，該第一介雷 性材料，並以雷射或電第-”電層係為熱固 的介電層。 水移除该半導體晶片之非主動面上 或依前述之製法，該第— :性材料，並以曝光顯影之製程感 動面上的介電層。 亍等體B日片之非主 依以上之製法，該半導體晶 於該非主動面上，而該具有點著屏…：心層形成 、頁黏者層之+導體晶片製法，係 110593 9 200942105 包枯.提供一承载平板·於兮 於。亥承载平板上形成一黏著層，· 將一包3有複數半導體晶片半 合於該黏著層上，·切料半^曰（ er)背面貼 你队斗、 ”亥+導體晶圓及該黏著層，·以及 方夕除该承载平板，以形成複數 -u. 取歿数月面具有黏著層之半導體晶 片’该具有黏著層之半導體曰山 • ¥體日日月敗埋於該介電層中，並露 出该黏者層’之後以加埶哎丨丨 之黏著層。 …次υν先肤射移除該半導體晶片 魏展及第二金屬層係為該第一及第二線路 ❽層之製法，係包括：於該介電 # 电巧义第一表面及第一金屬層 上形成有位於該半導體晶月 报占古普咖 日日片之電極墊上的介電層開孔，並 " 〃一貝牙該第一金屬層、介電層及第二金屬層之 通孔；於該第一金屬層'第二金屬層、通孔、介電層開孔 及電極塾之部份表面上形成一導電層 面形成-第三金屬層，並於兮、Sw 守电續之表 , 、°亥通孔内部形成導電通孔，該 導電通孔復填充導電或不導雷 、s^ A 飞不導電之填充材料，以填滿該導電 通孔内部之空間，或該導電通 © ^ . M „ . L係為貫心導電通孔；於該 二.屬層之表面形成—第一阻層，該第一阻層經圖案化 衣程而形成有對應該半導體晶片之電極塾二 口與對應該半導體晶片之非士勒_二α 闹 日曰片之非主動面的阻層第二開口；移 除該阻層第-開口中之第三金屬層、導電層、第一金屬 層’並移除該阻層第二開口中之第三金屬層、導電層及第 二金屬層；以及移除該第-阻層，以於該介電層1= =成該第-線路層’並於該介電層之第一開孔中形成第 -導電盲孔以電性連接該半導體晶片之電極塾，且於該介 110593 10 200942105 單層之弟二表面形成該第二線路層 形成有複數第一電性接觸墊，而該第：：弟-線路層並 數第二電性接觸墊，且1 、在路層亚形成有複 及第二線路層。 …电、孔電性連接該第-線路層 復包括於該介電層之第一 •形成有一第一防嫜厣#炫 亥第—線路層表面 孔以針廂ΐ山 ㈣一防痒層並形成有複數第-門 孔以對應露出該第—電性接觸塾之二開 電層上之筮_ ^ 弟—介電層、疊置於該第三介 電盲孔，該三介電層中之第二導 層，且該第一1 並電性連接該第一及第三線路 數繁λ s層結構上具有電性連接該第三線路層之複 =\電:生接觸塾，並於該第-增層結構上形成有= 〇 “三=—防焊層中形成有複數第-開孔，以對應露出 表面與該第=塾之部分表面。復包括於該介電層之第二 烊声升面形成有一第二防焊層，該第二防 且^楚成有弟一開口，以露出該半導體晶片之非主動面， 一:防焊層並形成有複數第二開孔以對應露出該第 表书陡，觸墊之部分表面；或復包括於該介電層之第二 -=及第二線路層上形成至少一第二增層結構，並於該第 ^ θ構上形成第二防焊層，且該第二增層結構並形成 體=二開口對應該第二防焊層之第一開口，以露出該半導 曰曰片之非主動面’該第二增層結構係包括有至少一第四 11 110593 200942105 介冤層、疊置於該第四介電層上 於第四介電層中之第：導帝亡$ 線路層、及複數設 ，玄弟一及弟四線路層’且該第二增層結構上具有電性 連接該第四線路層之複數第四電性接觸墊 層結構上形成有第二防焊層，<第一心 •笼_ ρ^, 贗弟一防知層中形成有複數 苐開孔，以對應露出該第四電性接觸墊之部分表面，且 防焊層並形成有第一開口，以露出該半導體晶片之 非主動面。 © s依上述之製法，復包括於該第—介電層及第二介電 層之間夾設有-核心板，其中該核心板並形成有—貫穿之 核心板開口以供容置該半導體晶片，該核心板係為具有線 路之線路板或絕緣板，且該核心板復包括形成有一位於咳 核心板開口周緣之阻膠框（Dam)，而該具有阻膠框之核二 =裝法’係包括·提供一核心板，該核心板具有相對應之 弟，及第四表面，經圖案化製程以於該核心板之第三表面 ❾上形成有第五線路層，而於該第四表面上則形成有第六線 路層以及-阻膠框；於該第四表面上形成第二阻層，且該 第二阻層形成有開口區域以露出該第四表面之第六線路 層；薄化未為該第二阻層所覆蓋之第五線路層與第六線 路層以成為第五薄化線路層與第六薄化線路層，使該阻 膠框，銅落厚度高於該第五及第六薄化線路層；以=移 除該第二阻層，並於該阻膠框所圍構之空間中形成貫穿該 核心板之核心板開口。 本發明係將半導體晶片般埋於第一介電層及第二介 110593 12 200942105 :層中’且於”亥第一及第二介電層上分別形成有第一及第 二線路層，使該第-線路層電性連接該半㈣晶片，並裸 露該半導體晶片之非主動面，使該半導體晶片所產生之熱 量可有效逸散，俾達散熱效果。 ^【實施方式】 • 訂請配合圖式說明本發明之具體實施例，以使所屬 技術中具有通常知識者可輕易地瞭解本發明之技術特徵 與達成功效。 ❹[第一實施例] 請參第2A至2L圖，係為本發明嵌埋有半導體元件之 封裝基板製法之剖面示意圖。 二 w 丁业取风有一頁穿 之開口區210’’’且該第二介電層21”兵為 該第-介電層21，。丨電層21文熱後之流動性低於 G中容:ί 示’於該第二介電層21，，之開口區21°” 中谷，又有一 +導體晶片22，該半導體晶片Μ ==其相對應之非主動面22b，且該主動面仏具 複數電極塾221。 -有如及2C，圖所示，於該第一介電層21，之外側置 二於該第二介電層21，，及該半導 體=片22之外側置設有一第二金屬層23b，其中該第一 及第二金屬層23a,23b係為㈣；或可結合該第 圖所示之步驟，直接於該半導體晶片22之主動面他上 人=2A圖所示’首先，提供—第—介電層21，及第 "电層21”，其中該第二介電層21”中並形成有一貫穿 110593 13 200942105 歷合由第一金屬層23a及第一介電層21，組成之 銅冶（Resm coated copper f0il)，而於該半導體晶片 22之非主動面22b上壓合由第二金屬層23b及第二介 層21”組成之第二背膠銅箔，且該第二介電層2丨，，中形成 有—貫穿之開口區210”，又該開口區21〇”係為該第二 .屬層23b所封閉，以供容置該半導體晶片22於該開口區 21〇”中’如第2C，圖所示；之後以第2C圖所示之結構作 明。 °疋 ❿ 如第2D圖所*，塵合該第一金屬層23a、第一介電 層21’、第二介電層21”及第二金屬層撕，使該第一介恭 層21，及第二介電層21 ”合成一介電層21，且該介電層= 係填充於該開口區210”與半導體晶月22之間的間隙a中， 並溢流至該半導體晶片22之非主動面22b上，以將該半 導體晶片22固定於該介電層21中，其中該介電層^於 該第-金屬層23a侧係為第一表面2U，而於該第二 層咖侧係為相對應之第二表面⑽；《壓合前述之第一 及第二背膠銅箔，俾以構成相同之結構。 如第2E圖所示，薄化該第一及第二金屬層取咖， 再以雷射開孔於該介電層21之第一表面仏及第一金屬 層23a上形成有位於該半導體晶片22之電㈣221上的 )ι電層開孔211a，並以雷射開孔或機械鑽孔形成有至少 -貫穿該第-金屬層23a'介電層21以及第二金屬層挪 之通孔211 b。 ϋ 2F 81 ~示’接著’利用物理沈積之滅鍍 110593 14 200942105200942105 A few, poor description: [Technical field to which the invention pertains] The present invention relates to a package substrate method in which a semiconductor element is embedded, which is capable of exposing an inactive surface of a semiconductor element to achieve a heat dissipation effect. "[Prior Art] As electronic products become thinner and lighter, the package substrate used to carry semiconductor components or electronic components needs to be reduced, and the evolution of semiconductor packaging technology has developed different package types, such as balls. Grid array (Ball gr 1 (i array' BGA), an advanced semiconductor packaging technology, is characterized by the use of a substrate to house a semiconductor wafer. However, the ball grid array type semiconductor package structure will be conventionally The semiconductor wafer is electrically connected to the substrate by a flip chip method, and although the number of high pins can be achieved, when the high frequency is used or the high speed operation is performed, the electrical characteristics cannot be improved due to the long connection path of the wires. Therefore, the performance is limited; in addition, because the traditional packaging requires multiple connection interfaces, the manufacturing cost is relatively increased. In order to effectively improve the electrical quality and meet the application of the next generation of products, the industry has studied using semiconductor wafers. Directly electrical connection into the package substrate, which can shorten the electrical conduction path and reduce signal loss and signal No. Distortion to improve the ability to operate at high speed. Please refer to FIG. 1A1 10; FIG. 1 is a cross-sectional view of a conventional method of embedding a semiconductor wafer in a package substrate. As shown in FIG. 1A, a first substrate is provided. 1〇& and a second substrate 10b, wherein the first substrate 1A has at least one through opening 110593 5 200942105 ιυυ ° as shown in FIG. 1B', the first substrate i 〇a is bonded to the second On the substrate 10b, a semiconductor wafer 11' is received in the opening 1 of the first substrate i?a, and the semiconductor wafer j is fixed in the opening 100 by a bonding material 11? The active surface 丄a and the non-active surface 11b opposite to the active surface 11a, and the active surface has a plurality of electrode pads 111 for electrically connecting the circuit layer to the semiconductor wafer 11. ❹ Figure 1C As shown, a build-up structure 12 is formed on the first substrate 10a and the active surface 11a of the semiconductor wafer u to embed the semiconductor wafer 11 in the first and second substrates 10a, 10b. The build-up structure Γ 2 includes at least a dielectric layer 12 〇, a circuit layer 121 stacked on the dielectric layer 2, and a plurality of conductive vias 122 formed in the dielectric layer 120, and 4 conductive vias 122 electrically connected to the electrode pads 111 of the semiconductor wafer u And having a plurality of electrical contact pads on the build-up structure 12, the m123 is electrically connected to the circuit layer 121; and the build-up layer 12 is formed with a solder resist layer 13, and the solder resist layer 13 The middle opening 13Q is correspondingly exposed to the electrical connection (four) 123. ^ 然: In the above method, the semiconductor wafer u board 10a, and the 篦-1 4c , m ^ is · 1〇η, the substrate 1013 seals the first The opening of a substrate 10a is 1 0 0. Therefore, the heat generated by the semiconductor 曰 屮 日 日 导 导 导 导 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 运作 11 11 11 11 , such as the cover method ', θ, * with the performance and life of the conductor chip. Therefore, the heat sink 'will seriously affect the half' 10593 6 200942105 Therefore, how to propose a semiconductor chip embedded package structure to overcome the problem that the structure of the semiconductor package structure is not easy to dissipate heat has become an urgent problem in the industry. Question. [Invention] The present invention provides a method for manufacturing a package substrate in which a semiconductor element is embedded, which is an inactive surface of a bare semiconductor read to achieve a heat dissipation effect. The present invention provides an embedded crucible, a substrate manufacturing method, which comprises: providing a semiconductor wafer embedded with embedded =, the main = 1 sheet having an active surface and corresponding non-active " a plurality of electrode pads, the two surfaces of the dielectric layer are respectively expected to be added to the first metal layer and the dielectric layer is in contact with the first side as a first surface, and the first metal layer side is in contact with the "w" Corresponding to the second table, the first one and the second metal layer are patterned by the first j ^ ^ π &, & Μ 亿 亿 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 釭 第一Forming a second surface of the dielectric layer and removing an inactive surface layer formed on the semiconductor wafer to expose an inactive surface of the semiconductor wafer. According to the above method, the embedded semi-conductive surface has a first month The method of manufacturing the first layer of the metal layer and the method of providing the first layer of the metal layer a first one is placed on the side of the first dielectric layer: the 筮 人 人 人 且 且 且 且 且The genus layer 'and belongs to: ...I electrical layer and the non-active surface layer of the semiconductor wafer, and is willing to combine the first metal layer, the first dielectric layer, the second dielectric layer 110593 7 200942105 and the second metal The layer 'make the first dielectric layer and the first layer to fix the semiconductor. Forming a dielectric a ^ sheet, wherein the dielectric layer is in contact with 嗲m, and the side of the genus layer becomes the first surface, and the surface of the %a 苐-gold two surface. The method of fabricating the dielectric layer of the semiconductor wafer and the method for forming the metal layer of the semiconductor layer comprises: providing a first metal layer and a first dielectric layer a backing copper beryllium, and a second backing copper consisting of a first layer and a second dielectric layer, and the nth layer has an open area through the opening; in the second dielectric layer: Squeezing the semiconductor wafer; and pressing the first-back adhesive copper foil to cause the first dielectric layer and the second dielectric layer to form a dielectric layer to fix the semiconductor wafer, wherein The dielectric layer is in contact with the first metal layer side to form a first surface, and the second metal layer side is a corresponding second surface. Or according to the above method, the dielectric layer embedded with the semiconductor wafer and The method for manufacturing the first and second metal layers on the surface thereof comprises: providing a second adhesive copper foil composed of a 5 metal layer and a second dielectric layer, and a core dielectric layer having a core dielectric opening And a first adhesive copper foil composed of a first metal layer and a first dielectric layer; a second dielectric layer of the second adhesive copper foil is connected to the inactive surface of the semiconductor wafer, and the core dielectric layer opening corresponds to the semiconductor wafer; pressing the first adhesive copper box, the core dielectric layer, and a second adhesive copper foil, wherein the first dielectric layer, the core dielectric layer and the second dielectric layer are combined with a dielectric layer ′ and the semiconductor wafer is fixed to the dielectric layer, wherein the dielectric layer is The first metal layer side is a first surface, and the 8th 110593 200942105 - the metal layer side is a corresponding second surface. According to the above method, the embedded surface has the first and second metal / The dielectric layer of the chip and the carrier plate are provided on the carrier plate by the first package #: providing - the second adhesive copper _, one, the 蜀 and the second dielectric layer And the carrier plate (4) is formed with a second metal layer connected to expose the portion of the carrier plate to form an opening region, and the non-main surface of the semiconductor wafer is mounted on the carrier plate in the open region The core dielectric layer of the opening, and the moving surface,]: for the first-backing copper foil with a core dielectric layer,", '枋The dynasty layer and the first dielectric layer constitute a wafer, and the dielectric layer opening corresponds to the semiconductor 羯, the first dielectric layer, the 椤: 八)1 electrical layer, and the second adhesive copper electrical layer, The semiconductor germanium second electrical layer and the second dielectric layer are synthesized and the same is applied to the first metal layer side, and the dielectric layer is corresponding to the dielectric layer. a surface of the second metal layer side of the body wafer and removing the carrier plate to expose the semiconductor device according to the foregoing method, the first dielectric material, and the laser or The electric-"electric layer is a thermosetting dielectric layer. Water removes the non-active surface of the semiconductor wafer or according to the foregoing method, the first: material, and the exposure surface of the exposure process The electric layer. The semiconductor B is not the main method according to the above method, the semiconductor crystal is on the inactive surface, and the dot-screen is formed...: the formation of the core layer, the layer of the adhesive layer + conductor wafer method, is 110593 9 200942105 Bundle. Provide a carrying tablet. An adhesive layer is formed on the carrier plate, and a package of three semiconductor wafers is semi-bonded to the adhesive layer, and the back of the material is affixed to your team, "Hai + conductor wafer and the adhesive Layer, · and Fang Xi in addition to the carrying plate to form a complex -u. Take the semiconductor wafer with an adhesive layer on the moon surface. The semiconductor with the adhesive layer is buried in the dielectric layer. And exposing the adhesive layer' followed by the adhesive layer of the twisted layer. The second film is removed to remove the semiconductor wafer and the second metal layer is the first and second circuit layers. The method includes: forming a dielectric layer opening on the first surface of the dielectric and the first metal layer on the electrode pad of the semiconductor crystal moon, and " a through hole of the first metal layer, the dielectric layer and the second metal layer; on a surface of the first metal layer 'the second metal layer, the via hole, the dielectric layer opening and the electrode layer Forming a conductive layer to form a third metal layer, and in the 兮, Sw, the continuation of the watch, in the Haitong hole Forming a conductive via, the conductive via is filled with a conductive or non-leading, s ^ A fly non-conductive filling material to fill the space inside the conductive via, or the conductive flux © ^ M „ L a through-hole conductive via; a first resist layer formed on the surface of the second layer, the first resist layer being patterned to form an electrode corresponding to the semiconductor wafer and corresponding to the semiconductor wafer a second opening of the resistive layer of the non-active surface of the non-Sile _ _ α ; ;; removing the third metal layer, the conductive layer, the first metal layer of the first opening of the resist layer and removing the resistance a third metal layer, a conductive layer and a second metal layer in the second opening of the layer; and removing the first resist layer such that the dielectric layer 1 = = the first wiring layer and the dielectric layer Forming a first conductive via in the first opening to electrically connect the electrode of the semiconductor wafer, and forming a second circuit layer on the surface of the second layer of the dielectric layer 110593 10 200942105 to form a plurality of first electrical contacts Pad, and the first:: brother-line layer and the number of second electrical contact pads, and 1, in the road layer sub-form And a second circuit layer. Electrically and electrically connecting the first circuit layer to the first of the dielectric layer, forming a first anti-smashing layer, the surface of the circuit layer, and the anti-itch layer of the pinch mountain (four) Forming a plurality of gate-holes corresponding to the dielectric layer on the second power-on layer exposing the first electrical contact, stacked in the third dielectric via, in the three dielectric layers a second guiding layer, and the first 1 is electrically connected to the first and third lines, and the plurality of layers are electrically connected to the third circuit layer, and the electrical contact is The first build-up structure is formed with = 〇 "three = - a plurality of first openings are formed in the solder resist layer to correspond to the exposed surface and a portion of the surface of the first 塾. The second layer is included in the dielectric layer The second rising layer is formed with a second solder mask, and the second surface is formed with an opening to expose the inactive surface of the semiconductor wafer, and a solder resist layer is formed with a plurality of second openings to correspond to Exposing the surface of the table to a steep portion of the surface of the touch pad; or forming a second layer on the second-= and second circuit layers of the dielectric layer to form at least one second build-up structure, And forming a second solder resist layer on the θθ structure, and the second build-up structure forms a body=two openings corresponding to the first opening of the second solder resist layer to expose the non-conductive film The active layer 'the second build-up structure includes at least one fourth 11 110593 200942105 dielectric layer stacked on the fourth dielectric layer in the fourth dielectric layer: And a plurality of sets, a second layer of the fourth layer of the mysterious brother and the fourth layer, and the second layer of the fourth electrical contact layer having the second layer of the second layer is electrically connected to the fourth layer of the second contact layer, and a second solder resist layer is formed, < a first core, a cage _ ρ^, a plurality of 苐 openings are formed in the 防 一 防 防 , , , , , , , , , , , , 露出 露出 露出 露出 露出 露出 露出 部分 一 一 一 一 一 一 一 一 一 一 一 一 一 一Exposing the inactive surface of the semiconductor wafer. The method according to the above method comprises: sandwiching a core plate between the first dielectric layer and the second dielectric layer, wherein the core plate is formed with a through-going The core board is open for receiving the semiconductor wafer, and the core board is a circuit board or an insulating board having a line. The core plate comprises a barrier frame (Dam) formed on the periphery of the opening of the cough core plate, and the core 2 of the barrier frame includes a core plate, and the core plate has a corresponding brother And a fourth surface, through the patterning process, a fifth circuit layer is formed on the third surface of the core plate, and a sixth circuit layer and a resistive frame are formed on the fourth surface; Forming a second resist layer on the fourth surface, and the second resist layer is formed with an opening region to expose the sixth circuit layer of the fourth surface; thinning the fifth circuit layer not covered by the second resist layer a sixth circuit layer to be a fifth thinned circuit layer and a sixth thinned circuit layer, such that the resistive frame has a copper drop thickness higher than the fifth and sixth thinned circuit layers; and the second resistive layer is removed by = And forming a core plate opening through the core plate in a space surrounded by the resistive frame. The present invention is formed by embedding a semiconductor wafer in a first dielectric layer and a second dielectric layer 110593 12 200942105: and forming first and second circuit layers on the first and second dielectric layers, respectively. The first circuit layer is electrically connected to the half (four) wafer, and the inactive surface of the semiconductor wafer is exposed, so that the heat generated by the semiconductor wafer can be effectively dissipated, and the heat dissipation effect is achieved. [Embodiment] • The drawings illustrate the specific embodiments of the present invention so that those skilled in the art can easily understand the technical features and achieve the functions of the present invention. 第一 [First Embodiment] Please refer to Figures 2A to 2L for A schematic cross-sectional view of a method for fabricating a package substrate in which a semiconductor element is embedded is provided. The second dielectric layer 21" is an opening region 210"" and the second dielectric layer 21" is the first dielectric layer 21. The fluidity of the tantalum layer 21 after the heat is lower than that of the G medium: λ indicates that in the second dielectric layer 21, the open region 21°, there is a + conductor wafer 22, and the semiconductor wafer Μ == Corresponding to the non-active surface 22b, and the active surface is configured with a plurality of electrodes 221. - as shown in FIG. 2C, the second dielectric layer 21 is disposed on the outer side of the first dielectric layer 21, And a second metal layer 23b disposed on the outer side of the semiconductor=sheet 22, wherein the first and second metal layers 23a, 23b are (4); or may be combined with the step shown in the figure, directly on the semiconductor wafer The active face of 22 is the one shown in Fig. 2A. First, the first dielectric layer 21 and the second electrical layer 21 are provided. The second dielectric layer 21 is formed with a through hole 110593 13 200942105. The second metal layer 23b and the second metal layer 23b are laminated on the inactive surface 22b of the semiconductor wafer 22, and the second metal layer 23b and the second metal layer 23b are laminated on the non-active surface 22b of the semiconductor wafer 22. a second adhesive copper foil composed of a dielectric layer 21", and the second dielectric layer 2 is formed with a through-opening region 210" The opening area 21〇 is closed by the second layer 23b for accommodating the semiconductor wafer 22 in the opening area 21′′ as shown in FIG. 2C, as shown in FIG. 2C. The structure is as shown in Fig. 2D, dusting the first metal layer 23a, the first dielectric layer 21', the second dielectric layer 21" and the second metal layer to tear the first The dielectric layer 21 and the second dielectric layer 21 "synthesize a dielectric layer 21, and the dielectric layer = is filled in the gap a between the opening region 210" and the semiconductor crystal moon 22, and overflows to The semiconductor wafer 22 is fixed to the dielectric layer 21 on the inactive surface 22b of the semiconductor wafer 22, wherein the dielectric layer is a first surface 2U on the side of the first metal layer 23a. The second layer of coffee is a corresponding second surface (10); "the first and second backing copper foils are pressed together to form the same structure." As shown in FIG. 2E, the first and second metal layers are thinned, and the semiconductor wafer is formed on the first surface of the dielectric layer 21 and the first metal layer 23a by laser openings. The electric layer opening 211a of the electric (four) 221 of the 22, and the through hole 211 formed by at least the dielectric layer 21 and the second metal layer passing through the first metal layer 23a' is formed by laser opening or mechanical drilling. b. ϋ 2F 81 ~ shows 'then' using physical deposition of the plated 110593 14 200942105
Csputtering)或化學沈積之益 層他、第二金屬層23b、通孔電:、式」^該第一金屬 及電極墊221之部份表面上形成—導電層'4開丄a、 2/主要作為後述電鍍金屬材料所需之電流傳導路徑 可由金屬、合金或沉積數層金屬層所構成，如選自銅、錫: •鎳、鉻、鈦及銅-鉻合金等所組群組之其中一者，或 電層24係為聚乙块、聚苯胺或有機硫聚合物等導電°高分 子材料。 ❹ =%及犯圖所示，於該導電層24表面電錢形成 有弟二金屬層23c，並於該通孔2nb中形成有導電通 孔26,如第2G圖所示，其中該第三金屬層23。之材料係 如鉛、錫、銀、銅、金、鉍、銻、鋅、鎳、锆、鎂、銦、 碲以及鎵等金屬之其中一者；惟，依實際操作之經驗，由 於銅為成熟之電鑛材料且成本較低，因此，該第三金屬層 23c以由電鑛銅所構成者為較佳，但非以此為限；之後: =真充一導電或不導電之填充材請(如銅或環氧樹月旨 專）以―填滿該導電通孔26内部；或於該通孔2Ub中電鍍 形成實心導電通孔26，，如第2G，圖所示；之後以第2G圏又 所示之結構作說明。 如第2H圖所示，於該第三金屬層23c之表面利用印 刷、、旋塗或貼合等方式形成第一阻層27，該第一阻層π 係為乾膜或液態光阻等光阻層，且該第一阻層27再經由 曝光、顯影等之圖案化製程而形成有複數阻層第一開口 270a及一阻層第二開口 27〇b，其中該阻層第一開口打h Π0593 15 200942105 你鉻出該第三金屬層23c之部份表面，而該阻層第二開口 270b係對應該半導體晶片22之非主動面22b。 如第21圖所示，藉由蝕刻以移除該阻層第—開口 27〇\中之第三金屬層&、導電層24及第一金屬層 二及第三金屬層23c、導電層24及第二金屬層23b，以於 忒介電層21之第-及第二表面21a，21b分別形成有第一 及第二線路層28a, 28b，並於該介電層開孔2Ua中形成 第導電目孔280a’以電性連接該半導體晶片22之電極 ❹墊22卜且該導電通孔26電性連接該第一線路層心及 2二線路層28b，又該第一線路層28a係形成有複數第一 性接觸墊281a ’而該第二線路層28b係形成有複數第 二电性接觸墊281b;其中，該第一線路層28a係由該 金屬層23a、導電層24及第三金屬層23c所構成，而 ^第二線路層28b係由該第二金屬層挪、導電層^及 :金屬層23c所構成；並移除該阻層第二開口” <弟三金屬層23c、導雷廢94 «楚 X Η Λ ©讀丰…屬層咖，以露出 +導體阳片22之非主動面22b上的介電層2ι。 如第2J圖所示，移除續篦—阳思 移除以阻層27,以露出該介電 層 Γί 第一線路層28a，及露出該介電 1之第一表面21b的第二線路層28b。 如第2K圖所示’移除位於該半導體晶片2 面22b上的介電層21 ,以®:屮今主道触 非動 ^ n 以路出s玄丰導體晶片22之非主動 =2b;其中該介電層21為熱固性材料材料，係以J 或電聚(―移除該第二表面21b之部分介電層a 110593 16 200942105 向忒=電層21為感光性材料，則以曝光及顯影之製程移 除該第二表面21b之部分介電層21，俾以露出該半導體 晶片22之非主動面22b。 清麥閱第2L圖’復於該介電層21之第一表面2ia 與忒第一線路層28a表面形成有一第一防焊層29a，該第 •一防焊層29a中並形成有複數第一開孔29〇a以對應露出 該第一電性接觸墊281a之部分表面，而於該介電層21 之第二表面211}與該第二線路層28b表面形成有一第二防 Ά -n 不 一 ryj 焊層29b，該第二防焊層29b形成有第一開口 29ib，以露 出該半導體晶片22之非主動面22b，且該第二防焊層29b 形成有複數第二開孔292b以對應露出該第二電性 281b之部分表面。 凊另芩閱第2L’圖，上述結構復可各於該介電層2ι 之第一表面21a及第-線路層28a上形成一第一增層結構 29’ ’其中，該第一增層結構29，係包括有至少一第三介電 層·，、疊置於該第三介電層，上之第三線路層291，、 及複數形成於該第三介電層29〇，中之第二 292 ’其中部份之第二導電盲孔292，並電性連接該第一線 路層28a及第三線路層291，，且該第一增層結構^，上呈 有複數第三電性接觸墊293，，復於該第—增層結構心 面形成有弟-防谭層29a，該第-防焊層咖表面且有複 數個第-開孔290a以對應露出該第三電 部分表面；另於該介電層21之第二 t 293之 « oou , y , 矛面21b及第二線路 層28b上形成-第二增層結構29”，該第二增層結構μ， 110593 17 200942105Csputtering) or the chemical deposition layer, the second metal layer 23b, the via hole: a portion of the first metal and the electrode pad 221 is formed on the surface - the conductive layer '4 opening a, 2 / main The current conduction path required as a plating metal material to be described later may be composed of a metal, an alloy or a plurality of metal layers deposited, such as one selected from the group consisting of copper, tin: nickel, chromium, titanium, and copper-chromium alloy. The electric layer 24 is a conductive polymer material such as a polystyrene block, a polyaniline or an organic sulfur polymer. ❹ =% and the diagram shows that the surface of the conductive layer 24 is formed with a second metal layer 23c, and a conductive via 26 is formed in the via 2nb, as shown in FIG. 2G, wherein the third Metal layer 23. The materials are one of metals such as lead, tin, silver, copper, gold, antimony, bismuth, zinc, nickel, zirconium, magnesium, indium, antimony and gallium; however, due to practical experience, copper is mature The electric ore material is low in cost. Therefore, the third metal layer 23c is preferably made of electro-mineral copper, but is not limited thereto; after: = true charge or non-conductive filler material (such as copper or epoxy tree) to fill the inside of the conductive via 26; or to form a solid conductive via 26 in the via 2Ub, as shown in Fig. 2G, shown in Fig. 2; The structure shown in 圏 is explained. As shown in FIG. 2H, the first resist layer 27 is formed on the surface of the third metal layer 23c by printing, spin coating or lamination, and the first resist layer π is a dry film or a liquid photoresist. a first resist layer, and the first resist layer 27 is formed with a plurality of resistive first openings 270a and a resistive second opening 27〇b through a patterning process such as exposure, development, etc., wherein the first opening of the resist layer is h Π0593 15 200942105 You chrome out part of the surface of the third metal layer 23c, and the second opening 270b of the resist layer corresponds to the inactive surface 22b of the semiconductor wafer 22. As shown in FIG. 21, the third metal layer & the conductive layer 24 and the first metal layer 2 and the third metal layer 23c, the conductive layer 24 are removed by etching to remove the resist layer first opening 27? And the second metal layer 23b, the first and second circuit layers 28a, 28b are formed on the first and second surfaces 21a, 21b of the germanium dielectric layer 21, respectively, and the first and second circuit layers 28a, 28b are formed in the dielectric layer opening 2Ua. The conductive mesh 280a' is electrically connected to the electrode pad 22 of the semiconductor wafer 22, and the conductive via 26 is electrically connected to the first circuit layer core and the second circuit layer 28b, and the first circuit layer 28a is formed. The plurality of first contact pads 281a' and the second circuit layer 28b are formed with a plurality of second electrical contact pads 281b; wherein the first circuit layer 28a is composed of the metal layer 23a, the conductive layer 24 and the third metal The layer 23c is formed, and the second circuit layer 28b is composed of the second metal layer, the conductive layer and the metal layer 23c; and the second opening of the resist layer is removed. <The third metal layer 23c, Guide Thunder Waste 94 «Chu X Η Λ ©Read Feng... is a layer of coffee to expose the dielectric layer 2ι on the inactive surface 22b of the +conductor positive film 22. As shown in Figure 2J The first circuit layer 28a is exposed, and the second circuit layer 28b exposing the first surface 21b of the dielectric 1 is exposed. As shown in the figure, 'the dielectric layer 21 on the surface 22b of the semiconductor wafer 2 is removed, and the non-active = 2b of the Xuanfeng conductor wafer 22 is removed from the main channel. The electric layer 21 is a thermosetting material material, and is formed by J or electropolymerization (the partial dielectric layer a 110593 16 200942105 of the second surface 21b is removed to the 忒=electric layer 21 as a photosensitive material, and the process of exposure and development is performed. Removing a portion of the dielectric layer 21 of the second surface 21b to expose the inactive surface 22b of the semiconductor wafer 22. The second surface of the dielectric layer 21 is formed on the first surface 2ia and the first surface of the dielectric layer 21. A first solder resist layer 29a is formed on the surface of the circuit layer 28a, and a plurality of first openings 29a are formed in the first solder resist layer 29a to correspondingly expose a portion of the surface of the first electrical contact pad 281a. The second surface 211} of the dielectric layer 21 and the surface of the second circuit layer 28b are formed with a second anti-n-yry ryj solder layer 29b. The layer 29b is formed with a first opening 29ib to expose the inactive surface 22b of the semiconductor wafer 22, and the second solder resist layer 29b is formed with a plurality of second openings 292b to correspondingly expose a portion of the surface of the second electrical portion 281b. Further, referring to FIG. 2L', the above structure may form a first build-up structure 29'' on the first surface 21a and the first-line layer 28a of the dielectric layer 2i, wherein the first build-up structure 29, comprising at least a third dielectric layer, a third circuit layer 291 stacked on the third dielectric layer, and a plurality of third dielectric layers 29, The second conductive blind hole 292 of the second portion 292 is electrically connected to the first circuit layer 28a and the third circuit layer 291, and the first build-up structure has a plurality of third electrical contacts thereon. a pad 293, formed in the core surface of the first layer-increasing structure, has a ridge-proof layer 29a, the surface of the first solder mask layer has a plurality of first opening-opening holes 290a to correspondingly expose the surface of the third electrical portion; Further, a second build-up structure 29 is formed on the "oou, y, the spear surface 21b and the second circuit layer 28b of the second t 293 of the dielectric layer 21" The second layer structure by μ, 110593 17 200942105
形成有第二開口 9CM 開口 294 ,以露出該半導體晶片22 面22b，該第二捭> & 非主動 矛~層結構29”係包括有至少一第四八+ a 290”、疊置於兮坌而人 弟四）丨電層 置於β亥第四介電層29〇，，上之第四線路 及複數設於第四介恭^ai -,^ ;丨电層29〇”中之第三導電盲孔292，，，J： * IT；?"1"" 及第四線路層9q a 層291 ，且该第二增層結構29”上且右適 數第四電性接觸墊2cn，，作 八有復 伐蜩蝥“3，後於該第二增層結構29”上形成 有第二防焊層2()h，s & , m Λ 口 第二防焊層2此並形成有第一開 ❹露出1丰應該第二增層結構29,之第二開口 294，並 22之非主動面22b，又該第二防焊層 中形成有複數個第二開孔292b以對應 性接觸墊293”之部分表面。 /弟四电 [第二實施例] 請參閱第3A至3D圖及第〇至41圖，係為本發明嵌 埋有半導體元件之封裝基板製法的第三實施例剖視圖。A second opening 9CM opening 294 is formed to expose the semiconductor wafer 22 face 22b, the second 捭>&inactive spear-layer structure 29" includes at least one fourth eight + a 290", stacked兮坌 人 人 人 人 丨 丨 人 人 人 人 人 人 人 人 丨 人 人 丨 丨 人 人 人 人 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四The third conductive blind via 292,,, J: *IT;?"1"" and the fourth circuit layer 9q a layer 291, and the second build-up structure 29" and the right fourth electrical contact Pad 2cn, for the eight-resection 蜩蝥 "3, after the second build-up structure 29" is formed with a second solder mask 2 () h, s & m Λ second solder mask 2 The first opening is exposed to form a second build-up structure 29, the second opening 294, and the non-active surface 22b of the 22, and the second solder mask is formed with a plurality of second openings 292b. Part of the surface of the corresponding contact pad 293". /Second embodiment, please refer to Figures 3A to 3D and Figures 41 to 41, which are the first method for manufacturing a package substrate in which a semiconductor element is embedded. Three embodiments Cutaway view.
首先，請參閱第3A至3D圖，係使半導體晶片之非主 動面上形成有黏著層之製法。 如第3A圖所示，首先，提供一承載平板3〇，並於該 承載平板3G上形成有-黏著層3卜該黏著層31係由一 加熱後易去除或利用UV光照後易去除之材料所組成。 如第3B圖所示，將該具有複數半導體晶片22之半導 體晶圓2的背面貼合於該黏著層31上。 如第3C圖所示，切割該半導體晶圓2及黏著層31， 以將該半導體晶圓2分割成複數半導體晶片22 ^ Π0593 18 200942105 如第3D圖所示，移除該承載平板3〇，以形成複數非 主動面具有黏著層31之半導體晶月。 接著’請參閱第4A至4J圖，係盔士々 姊_ 矛' 為本發明嵌埋有半導 體兀件之封裝基板製法的第二 卞守 -一每例剖面示意圖，與該第 一只施例之不同處在該半導體晶 .^ ^ 守組日日月之非主動面上復包括 ^成有一黏著層。 入如第4A圖所示，首先，提供—第_介電層？!，及第 一二電層2Γ，，該第二介電層21，，中並形成有一貫穿之開 ©口區210” ’於該第二介電層21，，之開口區2ι〇，，中容設該 非主動面22b具有黏著層31之半導體晶片22，並於該第 一 ’丨電層21’之外侧置設有一第一金屬層23&，而於該第 :’丨電層21”及該半導體晶片22之黏著層31上設有一第 二金屬層23b。First, referring to Figs. 3A to 3D, a method of forming an adhesive layer on a non-main surface of a semiconductor wafer is described. As shown in FIG. 3A, firstly, a carrying plate 3 is provided, and an adhesive layer 3 is formed on the carrying plate 3G. The adhesive layer 31 is made of a material which is easily removed after heating or is easily removed by using UV light. Composed of. As shown in Fig. 3B, the back surface of the semiconductor wafer 2 having the plurality of semiconductor wafers 22 is bonded to the adhesive layer 31. As shown in FIG. 3C, the semiconductor wafer 2 and the adhesive layer 31 are diced to divide the semiconductor wafer 2 into a plurality of semiconductor wafers 22 ^ Π 0593 18 200942105 as shown in FIG. 3D, the carrier plate 3 is removed, To form a semiconductor crystal moon having a plurality of inactive surfaces having an adhesive layer 31. Then, please refer to Figures 4A to 4J, the helmet 々姊 _ spear is the second 卞 - 一 一 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 嵌 卞 嵌 卞 嵌 卞 卞 卞The difference is that the semiconductor layer includes an adhesive layer on the non-active surface of the day. As shown in Figure 4A, first, provide the -th dielectric layer? And the first dielectric layer 2, the second dielectric layer 21, is formed with a through opening region 210"' in the second dielectric layer 21, the opening region 2ι〇, The semiconductor wafer 22 having the adhesive layer 31 is disposed on the non-active surface 22b, and a first metal layer 23& is disposed on the outer side of the first 'electrical layer 21', and the first: 'the electric layer 21' A second metal layer 23b is disposed on the adhesive layer 31 of the semiconductor wafer 22.
如第4B圖所示，壓合該第一介電層21，與該第二介 電層21”形成介電層21以固定該半導體晶片22，此處該 半導體晶片22之非主動面22b貼合有黏著層31，其係與 介電層21不具親和性’故溢膠僅形成於該半導體晶片22 之非主動面22b的周緣，而不致於全面性地形成於半導體 日曰片22之非主動面22b，故有利於後續清除半導體晶片 22之非主動面22b之介電層。 製法之第4C至4H圖的製程係與第一實施例中之第 2E至2J圖相同，故不再贅述。 如第41圖所示，移除形成於該半導體晶片22之非主 動面22b上之部份介電層21以露出該半導體晶片22之非 19 110593 200942105 主動面22b上之勸著層。 如第4J圖所示，以加熱後或利用uv光照射之方式， 移除該半導體晶片22 非幸叙 为“之非主動面22b上之黏著層&，以 露出該半導體晶片22之非主動面22b。 最後’如同第—實施例’復可於該介電層之表面及線 .路層上形成防焊層與增層結構。 [第三實施例] 月ί閱第5A至5D圖，係為本發明嵌埋有半導體元件 ❹之封裝基板製法第三實施例的剖面示意圖。 如第5Α圖所示’首先，提供由第二金屬層聊及第 21,二：層21組成之第二背膠銅箔’且於該第二介電層 1上接置-半導體晶片22，該半導體晶片22具有一主 且=2a及與其相對應之非主動® 22b’於該主動面22a =數電極，且該半導體晶片22以其非主動面聊 接置於該第二介電層21”上。 ❹#帛5B圖所示’再提供核心介電層4G及第-背膠銅 :白’其中該第一背膠銅箱係由第-金屬層23a及第一介電 =、且成玄核心介電層40具有-對應該半導體晶 月22之核心介電層開口 4〇〇。 入如第5C圖所示’接著，壓合該第一背膠銅镇、核心 二層40、及第二背膠銅箔，使該第一介電層21，、核心 =層40及第二介電層21 ”合成—介電層2卜並將該半 體晶片22固定於該介電層2卜其中該介電層^於該 乐 金屬層23a側係為筮 主a οι 馮弟一表面21 a，而於該第二金屬層 110593 20 200942105 —側係為相對應之第二表面21b。 之第弟至：圖’之後製程如同與本發明第-實施例 =至2K圏，以於該介電層21之第一表面&上形 -於該介/並電性連接該第一線路層_，而 ，，且形:有4二::面'上形成有第二線路層 〇〇a ... “導电通孔26以電性連接該第一線路層 動面22br層28b，並且露出該半導體晶片22之非主 ❹[第四實施例] 月多閱第6A至6D圖，係為本發明欲埋有半導體元件 之封裝基板製法第四實施例的剖面示意圖。 如第6A圖所示，首先，提供一承載板2〇〇，於該承 載板200上設有由第二金屬層饥及第二介電層？！，，組成 之第二背膠銅箔，該第二背膠銅箔以其第二金屬層2扑 接置於該承載板200上，且於該第二背膠銅箔中形成有一 開口區210”，以露出該承載板2〇〇之部份表面。 ❹ 如第6B圖所示，於該開口區210”中之承載板200上 接置一半‘體晶片22’該半導體晶片22具有一主動面22a 及與其相對應之非主動面22b，於該主動面22a具複數電 極墊221 ’且該半導體晶片22以其非主動面22b接置於 該承載板200上；再提供具有核心介電層開口 4〇〇之核心 介電層40、以及由第一金屬層23a與第一介電層21，組成 之第一背膠鋼箔，其中’該核心介電層開口 4〇〇對應該半 導體晶片22。 21 110593 200942105 如第6C圖所示，接著，壓合兮坌 σ °衷弟一背膠銅箔、核心 介電層40、及第二背膠銅箔，使哕笛人_ 從弟一介電層21，、核心As shown in FIG. 4B, the first dielectric layer 21 is pressed, and a dielectric layer 21 is formed with the second dielectric layer 21" to fix the semiconductor wafer 22, where the inactive surface 22b of the semiconductor wafer 22 is pasted. The adhesive layer 31 is combined with the dielectric layer 21 so that the adhesive layer is formed only on the periphery of the inactive surface 22b of the semiconductor wafer 22, and is not formed comprehensively on the semiconductor wafer 22 The active surface 22b is advantageous for subsequently removing the dielectric layer of the inactive surface 22b of the semiconductor wafer 22. The process of the fourth embodiment of the method of the fourth embodiment is the same as that of the second embodiment of the first embodiment, and therefore will not be described again. As shown in FIG. 41, a portion of the dielectric layer 21 formed on the inactive surface 22b of the semiconductor wafer 22 is removed to expose the persecution layer on the non-19 110593 200942105 active surface 22b of the semiconductor wafer 22. As shown in FIG. 4J, the semiconductor wafer 22 is unfortunately removed as "adhesive layer on the inactive surface 22b" after heating or by irradiation with uv light to expose the inactive surface of the semiconductor wafer 22. 22b. Finally, as in the first embodiment, a solder resist layer and a build-up structure are formed on the surface of the dielectric layer and the line layer. [THIRD EMBODIMENT] Figs. 5A to 5D are cross-sectional views showing a third embodiment of a method of manufacturing a package substrate in which a semiconductor device is embedded. As shown in FIG. 5, 'first, a second backing copper foil composed of a second metal layer and a 21st, 2nd layer 21 is provided, and a semiconductor wafer 22 is attached to the second dielectric layer 1, The semiconductor wafer 22 has a main and = 2a and an inactive ® 22b' corresponding to the active surface 22a = a plurality of electrodes, and the semiconductor wafer 22 is placed on the second dielectric layer 21 by its inactive surface. "上. ❹#帛5B shows the 're providing core dielectric layer 4G and the first-back adhesive copper: white', wherein the first adhesive copper case is made of the first metal layer 23a and the first dielectric =, and The sinusoidal core dielectric layer 40 has a core dielectric opening 4 corresponding to the semiconductor crystal moon 22. As shown in FIG. 5C, 'Next, the first backing copper town, the core second layer 40, and The second adhesive copper foil is such that the first dielectric layer 21, the core layer 40 and the second dielectric layer 21 are "synthesized-dielectric layer 2" and the half wafer 22 is fixed to the dielectric layer 2 In the dielectric layer 23a, the side of the metal layer 23a is a surface 21a of the main body a οι Fengdi, and the second metal layer 110593 20 200942105 is a corresponding second table. Face 21b. The second brother to: the process of the subsequent process is as in the first embodiment to the second embodiment of the present invention, so that the first surface of the dielectric layer 21 is superposed on the first line. Layer _, and, and shape: there are 4 2:: surface is formed with a second circuit layer 〇〇 a ... "conductive via 26 to electrically connect the first circuit layer moving surface 22br layer 28b, And exposing the non-mains of the semiconductor wafer 22 [Fourth Embodiment] FIG. 6A to 6D are a schematic cross-sectional view showing a fourth embodiment of the method for manufacturing a package substrate in which a semiconductor element is buried in the present invention. As shown, first, a carrier board 2 is provided, and a second backing copper foil composed of a second metal layer hunger and a second dielectric layer is provided on the carrier board 200, and the second back is provided. The copper foil is placed on the carrier 200 with its second metal layer 2, and an opening region 210" is formed in the second adhesive copper foil to expose a part of the surface of the carrier. As shown in FIG. 6B, a half-body wafer 22 is attached to the carrier 200 in the open area 210". The semiconductor wafer 22 has an active surface 22a and a corresponding non-active surface 22b. The surface 22a has a plurality of electrode pads 221 ' and the semiconductor wafer 22 is attached to the carrier 200 with its inactive surface 22b; a core dielectric layer 40 having a core dielectric opening 4, and a first The metal layer 23a and the first dielectric layer 21 constitute a first adhesive steel foil, wherein 'the core dielectric layer opening 4 〇〇 corresponds to the semiconductor wafer 22. 21 110593 200942105 as shown in FIG. 6C, then, press兮坌 ° ° ° 衷 brother a backing copper foil, core dielectric layer 40, and the second adhesive copper foil, so that the whistle _ brother a dielectric layer 21, the core
介電層40及第二介電層21，，合成一介命M 〇i L 取；丨電層21，以將該半 ‘體晶片22固定於該介電層21中，缺仏必人 -οηΛ 1〒’然後移除該承載板 200’以露出該半導體晶片22之非主叙而4丄人 , 井王動面22b;其中該介 電層21於該第一金屬層23a側传為笼主二 ^ 』1示馬第一表面21a，而於 該第二金屬層23b侧係為相對應之第二表面21匕 如第6D圖所示，之後製程如同與本發明第一實施例 ❹之第2E至2K圖，以於該介電層21之第一表面2ia上形 成有第一線路層28a，而於該介電層21之第二表面2lb 上形成有第二線路層28b，且形成有一導電通孔26以電 性連接該第一線路層28a及第二線路層28b，並且露出該 半導體晶片22之非主動面22b。 [第五實施例] 請參閱第7A至7C圖，係為本發明嵌埋有半導體元件 之封裝基板製法第五實施例的剖面示意圖，與該第一實施 例之不同處在本貫施例係具有一核心板。 如第7A圖所示’首先，提供第一介電層21，、核心 板50以及第二介電層21” ’其中’該核心板5〇係為具有 線路之線路板或絕緣板，且該核心板50具有第三表面5〇a 及相對應之第四表面5Ob，該核心板5 0之第三表面5〇a 上形成有第五線路層51a，而於該第四表面50b上形成有 弟六線路層51 b，該核心板5 0並形成有一貫穿該第三表 面50a及第四表面5〇b之核心板開口 500，而於該第二介 22 110593 200942105 電層21”中亦形成有—貫 ： σ ,ηπ . .. a 貝牙之開口區210”，於該核心板 y及弟二介電層21，，之開口區 半 片22,且於該第一介電； 丫直认千V肢日日 兒層21之外側置設有一第一金屬層 面mi望二 該半導體晶片22之非主動 面』2b 5又有弟二金屬層23b。 如第7B圖所示’壓人 層2卜核心板50、第八;弟一金屬層他、第-介電 #兮笛入^ 電層21”及第二金屬層2北， 使该第一介電層21，及篦-八 ; ❹並填充於該核心板層21”合成—介，層21 ’ 之門的門隙由 板開口 500與半導體晶片& <間的間隙中，且該公命 电曰21溢流至該半導體晶片22 乂中:Γ上，以將該半導體晶片22固定於該介電 二类JV/ 介電層21於該第一金屬層23以則係為第 矣而a’而於該第二金屬層咖侧係為相對應之第二 表面Z1 b。 :第7C圖所示’之後製程如同與本發明第一實施例 ❹^右筮E一至2K圖以於該介電層21之第-表面21a上形 ^ 線路層28a，並電性連接該第五線路層51a，而 =亥介电層21之第二表面仙上形成有第二線路層 並電陡連接該第六線路層51b，且形成有一導電通 孔26以電性連接該第一線路層28a及第二線路層28b， 並且露出該半導體晶片22之非主動面22b。 [第六實施例] 請參閱第8A至8D圖及第^至卯圖，係為太發明嵌 埋有半導體元件之封裝基板製法第六實施例的剖面示意 110593 23 200942105 圖，興前-實施例之不同處在於該核心板復具有一阻膠框 (Dam)以阻隔溢膠，藉由該阻膠框之形成以防止介電 壓合後溢流至半導體元件之非主動面上。 • /如第8A圖所示，首先’提供-核心板50，該核心板 50係具有第三表面5Gaa及與該第三表面咖相對之第 ，四表面50b，且經圖案化製程以於該核心板㈤之第三表 面咖上形成有第五線路㉟…，❿於該核心板5〇之第 四表面50b上形成有第六線路層讯及一阻膠框…。 ❹如第8B圖所示，於該第四表面抓上以印刷、旋塗 :貼合專方式形成第二阻層6〇，該第二阻層6〇係 或液態光阻等光阻層（Ph〇t〇resist)，且該第二阻声 藉由曝光、顯影等圖案化製程形成有開口區域600以露出 该第四表面50b之第六線路層51b。 所覆圖所示，刻方式薄化未被該第二阻層 之第五線路層51a與第六線路層51b，使該第五線 a la與第六線路層51b分別成為第五薄化 ❾及第六薄化線路層51b，，使該阻膠框…f = 第五薄化線路層51a，及第六薄化線路層训，厚度间於该 如第8D圖所示，移除該第二阻層6〇，並以雷射 或機械鑽孔於該阻膠框51c所圍構之空間中形 ; 穿該核心板50之第二表面5〇a月筮 主 開口 500。弟一表面5〇a及第四表面5〇b之核心板 復請參閱第8U8D圖，係為本發明嵌埋有 彳之封裝基板製法之第六實施例的製法剖面示意圖，與該 110593 24 200942105 第五貫施例之不同處在於核心板具有一阻膠框，且該半導 體晶片之非主動面上形成有黏著層。 如第9A圖所示，提供一第一介電層21，、核心板5〇 以及第二介電層21，，，其中該核心板5〇具有第三表面5〇a 及相對應之第四表面50b，於該核心板5〇之第三表面5〇a •上形成有第五線路層51a，而於該第四表面50b上形成有 第六線路層51b及阻膠框51c，該核心板5〇並形成有一 貝牙該第二表面50a及第四表面50b之核心板開口 500， ❹而於該第二介電層21”中亦形成有一貫穿之開口區 210 ，於s亥核心板開口 5 〇〇及第二介電層2丨，，之開口區 210中置设半導體晶片22，其中，該開口區21 〇，，較佳應 大於該阻膠框51 c的外緣，以避免後續壓合製程中，該第 一"電層21溢流至該半導體晶片22之非主動面22b，該 半導體晶片22具有黏著層31，且於該第一介電層21，之 外側置設有一第一金屬層23a，而於該第二介電層21，，及 該半導體晶片22之非主動面22b設有第二金屬層23b。 如第9B圖所示，壓合該第一金屬層23a、第一介電 層21’、核心板50、第二介電層21”及第二金屬層2扑， 使該第一介電層21，及第二介電層21”合成一介電層21並 填充於該核心板50之核心板開口 500與半導體晶片22 之間的間隙中，以將該半導體晶片22固定於該^電層 21，且該核心板50之阻膠框51c接觸於該第二金屬層 23b。 如第9C圖所示’後續之製程如與第二實施例中之第 110593 25 200942105 4H圖之圖案化線路製程，以露出該半導體晶片22 之非主動面22b上之黏著層31。 ^如第9D圖所示，藉由加熱或uv光照射之方式，移除 該半導體晶片22之非主動面22b上之黏著層31，以露出 该半導體晶片22之非主動面22b。 敢後，如同第一實施例，復可於該介電層之表面及線 路層上形成防焊層與增層結構。 本發明係將半導體晶片嵌埋於第一介電層及第二介 φ電層中’且於該第一及第二介電層上分別形成有第一及第 ^線路層，使該第一線路層電性連接該半導體晶片，故可 鈿紐電性連接路徑，且為防止介電材料壓合後溢流至半導 體晶片之非主動面上，並藉由該核心板之阻膠框以阻隔溢 膠，並藉由裸露出該半導體晶片之非主動面，俾使半導體 晶片所產生之熱量可有效逸散，以達散熱效杲。 惟以上所述之具體實施例，僅係用以例釋本發明之特 ❹點及功效，而非用以限定本發明之可實施範疇，在未脫離 本發明上揭之精神與技術範疇下，任何運用本發明所揭示 内容而完成之等效改變及修飾，均仍應為下述之申請專利 庫έ*圍所涵蓋。 【圖式簡單說明】 第1Α至ic圖係顯示習用底穴:置晶型球栅陣型式封裝 結構製法之剖面示意圖； 、 第2A至2L圖係顯示本發明嵌埋有半導體元件之封装 基板製法之剖面示意圖； 、 110593 26 200942105 至2C圖合併之另一實施例之剖面 第2C’圖係為第2a 示意圖； 弟2G圖係為第2G圖之另一實施例； 第2L圖係為第2L圖之另一實施結構； 第3A至3D圖係顯示本發明嵌埋有半導體元件之 ^板製法中具有黏著層之半導體晶片之製法剖面示意 元件之封裝 元件之封裝 元件之封裝 元件之封裝 元件之封裝 示意圖；以 第4A至4 J圖係顯示本發明嵌埋有半導體 ❹基板製法之第二實施例剖面示意圖； 第5A至5D圖係顯示本發明嵌埋有半導體 基板製法之第三實施例剖面示意圖； 第6A至6D圖係顯示本發明嵌埋有半導體 基板製法之第四實施例剖面示意圖； 第7A至7C圖係顯示本發明嵌埋有半導體 基板製法之第五實施例剖面示意圖； 植 ❹ 第8A至8D圖係顯示本發明嵌埋有半導 基板製法中具有阻膠框之核心、板的製法剖 及 元件之封敦基 第9A至9D係顯示本發明嵌埋有半導體 板製法之第六實施例剖面示意圖。 【主要元件符號說明】 10a 10b 100 第一基板 第二基板 開口 H0593 27 200942105 II、 22 半導體晶片 110 結合材料 III、 221電極墊 11a、22a主動面 lib、22b非主動面 * 12 增層結構 120 ' 21 介電層 121 線路層 〇 122 導電盲孔 123 電性接觸墊 13 防焊層 130 開孔 2 半導體晶圓 200 承載板 21 介電層 21， 第一介電層 ❹ 21，， 第二介電層 210 開口 210” 開口區 211a 介電層開孔 211b 通孔 21a 第一表面 21b 第二表面 23a 第一金屬層 200942105 ΔόΌ 第二金屬層 23c 第三金屬層 24 導電層 26 導電通孔 26， 實心導電通孔 * 260 填充材料 27 第一阻層 270a 阻層第一開口 ❹ 270b 阻層第二開口 280a， 第一導電盲孔 281a 第一電性接觸墊 281b 第二電性接觸墊 28a 第一線路層 28b 第二線路層 29， 第一增層結構 29，， 第二增層結構 ❿ 290， 第三介電層 290” 第四介電層 290a 第一開孔 291’ 第三線路層 291” 第四線路層 291b 第一開口 292’ 第二導電盲孔 292” 第三導電盲孔 29 110593 200942105 z y z d 第二開孔 293’ 第三電性接觸墊 293” 第四電性接觸墊 294 第二開口 ' 29a 第一防焊層 ’ 29b 第二防焊層 30 承載平板 31 黏著層 ❹40 核心介電層 400 核心介電層開口 50 核心板 500 核心板開口 50a 第三表面 50b 第四表面 51a 第五線路層 51a’ 第五薄化線路層 〇 51b 第六線路層 51b’ 第六薄化線路層 51c 阻膠框 60 第二阻層 600 開口區域 30 110593The dielectric layer 40 and the second dielectric layer 21 are combined to form a dielectric layer M 〇i L; the germanium layer 21 is used to fix the semiconductor wafer 22 in the dielectric layer 21, and the defect is indispensable. Then, the carrier board 200' is removed to expose the semiconductor wafer 22, and the dielectric layer 22 is transferred to the side of the first metal layer 23a. The first surface 21a of the horse is shown in FIG. 1 and the second surface 21 is formed on the side of the second metal layer 23b, as shown in FIG. 6D, and the process is the same as that of the first embodiment of the present invention. 2E to 2K, a first wiring layer 28a is formed on the first surface 2ia of the dielectric layer 21, and a second wiring layer 28b is formed on the second surface 2lb of the dielectric layer 21, and a The conductive vias 26 are electrically connected to the first wiring layer 28a and the second wiring layer 28b, and expose the inactive surface 22b of the semiconductor wafer 22. [Fifth Embodiment] Please refer to FIGS. 7A to 7C, which are cross-sectional views showing a fifth embodiment of a method for manufacturing a package substrate in which a semiconductor element is embedded in the present invention, and the difference from the first embodiment is in the present embodiment. Has a core board. As shown in FIG. 7A, 'first, a first dielectric layer 21, a core board 50, and a second dielectric layer 21 are provided. ' 'While the core board 5 is a circuit board or an insulating board having a line, and The core plate 50 has a third surface 5〇a and a corresponding fourth surface 5Ob. The third surface 5〇a of the core plate 50 has a fifth circuit layer 51a formed thereon, and the fourth surface 50b is formed on the fourth surface 50b. a sixth circuit layer 51b, the core plate 50 is formed with a core plate opening 500 extending through the third surface 50a and the fourth surface 5〇b, and is formed in the second dielectric layer 22 110593 200942105 There is: σ, ηπ . . . a open area 210" of the teeth, in the core plate y and the second dielectric layer 21, the open area half 22, and the first dielectric; On the outer side of the day-to-day layer 21 of the thousand-V limb, a first metal layer is formed, and the inactive surface of the semiconductor wafer 22 is 2b 5 and the second metal layer 23b is formed. As shown in Fig. 7B, the layer 2 is pressed. Core board 50, eighth; brother-metal layer, first-dielectric #兮笛 into ^ electric layer 21" and second metal layer 2 north, the first dielectric layer 21, and -8; ❹ and filled in the core layer 21" composite - the gate gap of the gate 21' is in the gap between the board opening 500 and the semiconductor wafer &< In the semiconductor wafer 22, the semiconductor wafer 22 is fixed to the dielectric second-type JV/dielectric layer 21 on the first metal layer 23, and The second metal layer is the corresponding second surface Z1 b. The following process is the same as the first embodiment of the present invention, as shown in Fig. 7C, and the first layer of the present invention. - a surface layer 28a is formed on the surface 21a and electrically connected to the fifth wiring layer 51a, and a second wiring layer is formed on the second surface of the dielectric layer 21 and electrically connected to the sixth wiring layer 51b And a conductive via 26 is formed to electrically connect the first wiring layer 28a and the second wiring layer 28b, and expose the inactive surface 22b of the semiconductor wafer 22. [Sixth embodiment] Please refer to Figures 8A to 8D And a cross-sectional view of a sixth embodiment of a method for fabricating a package substrate in which a semiconductor element is embedded, 110593 23 20094210 The difference between the embodiment and the embodiment is that the core plate has a resist frame (Dam) to block the overflow, and the resistive frame is formed to prevent the dielectric from overflowing to the semiconductor device. Active surface. • / As shown in Fig. 8A, firstly, a 'core-core plate 50 having a third surface 5Gaa and a fourth surface 50b opposite to the third surface is patterned and patterned. The process is such that a fifth line 35 is formed on the third surface of the core board (5), and a sixth line layer and a resistive frame are formed on the fourth surface 50b of the core board 5'. For example, as shown in FIG. 8B, a second resist layer 6 is formed on the fourth surface by a printing, spin coating: bonding method, and the second resist layer 6 is a photoresist layer such as a liquid resist or a liquid photoresist. And the second damper is formed with an opening region 600 by a patterning process such as exposure, development, etc. to expose the sixth wiring layer 51b of the fourth surface 50b. As shown in the figure, the fifth line layer 51a and the sixth line layer 51b which are not the second resist layer are thinned, and the fifth line a la and the sixth line layer 51b are respectively made thinner. And the sixth thinned circuit layer 51b, the resistive frame ... f = the fifth thinned circuit layer 51a, and the sixth thinned circuit layer training, the thickness is removed as shown in FIG. 8D The second resist layer is 6 〇 and is formed in a space surrounded by the resistive frame 51c by laser or mechanical drilling; the second surface 5 〇a of the core plate 50 is inserted through the main opening 500. The core plate of the surface 5〇a and the fourth surface 5〇b is referred to the 8U8D drawing, which is a schematic cross-sectional view of the manufacturing method of the sixth embodiment of the method for manufacturing a package substrate with embedded germanium according to the present invention, and the 110593 24 200942105 The fifth embodiment differs in that the core board has a resistive plastic frame, and an adhesive layer is formed on the inactive surface of the semiconductor wafer. As shown in FIG. 9A, a first dielectric layer 21, a core board 5〇, and a second dielectric layer 21 are provided, wherein the core board 5 has a third surface 5〇a and a corresponding fourth The surface 50b is formed with a fifth circuit layer 51a on the third surface 5〇a of the core plate 5, and a sixth circuit layer 51b and a resistive frame 51c are formed on the fourth surface 50b. 5〇 and forming a core plate opening 500 of the second surface 50a and the fourth surface 50b of the shell tooth, and an opening region 210 is formed in the second dielectric layer 21", and the core plate opening is formed 5 〇〇 and the second dielectric layer 2 丨, the semiconductor wafer 22 is disposed in the opening region 210, wherein the opening region 21 〇, preferably should be larger than the outer edge of the resistive plastic frame 51 c to avoid subsequent In the embossing process, the first "electric layer 21 overflows to the inactive surface 22b of the semiconductor wafer 22, the semiconductor wafer 22 has an adhesive layer 31, and a first dielectric layer 21 is disposed on the outer side of the first dielectric layer 21. a first metal layer 23a, and a second metal layer 23 on the second dielectric layer 21, and the inactive surface 22b of the semiconductor wafer 22 b. As shown in FIG. 9B, the first metal layer 23a, the first dielectric layer 21', the core board 50, the second dielectric layer 21", and the second metal layer 2 are pressed together to make the first medium The electric layer 21 and the second dielectric layer 21" are combined with a dielectric layer 21 and filled in a gap between the core board opening 500 of the core board 50 and the semiconductor wafer 22 to fix the semiconductor wafer 22 to the ^ The electrical layer 21, and the resistive plastic frame 51c of the core plate 50 is in contact with the second metal layer 23b. As shown in Fig. 9C, the subsequent process is patterned as shown in Fig. 10593 25 200942105 4H in the second embodiment. The wiring process is performed to expose the adhesive layer 31 on the inactive surface 22b of the semiconductor wafer 22. As shown in Fig. 9D, the inactive surface 22b of the semiconductor wafer 22 is removed by heating or uv light irradiation. The adhesive layer 31 is adhered to expose the inactive surface 22b of the semiconductor wafer 22. After the dare, as in the first embodiment, a solder resist layer and a build-up structure are formed on the surface of the dielectric layer and the wiring layer. And embedding a semiconductor wafer in the first dielectric layer and the second dielectric layer, and in the first and second The first and the second circuit layers are respectively formed on the electrical layer, so that the first circuit layer is electrically connected to the semiconductor wafer, so that the electrical connection path can be connected, and the dielectric material is prevented from overflowing to the semiconductor wafer after being pressed. On the non-active surface, and through the resistive plastic frame of the core board to block the overflow, and by exposing the inactive surface of the semiconductor wafer, the heat generated by the semiconductor wafer can be effectively dissipated to achieve heat dissipation. The specific embodiments described above are merely used to exemplify the features and functions of the present invention, and are not intended to limit the scope of the present invention, without departing from the spirit and technology of the present invention. Any equivalent changes and modifications made by the disclosure of the present invention should still be covered by the following patent library. BRIEF DESCRIPTION OF THE DRAWINGS The first to the ic diagrams show a conventional bottom hole: a schematic cross-sectional view of a method of forming a crystal ball grid type package structure; and the second embodiment of the present invention show a method of manufacturing a package substrate in which a semiconductor element is embedded in the present invention. A cross-sectional view of a cross section 2C' of another embodiment in which the combination of 110593 26 200942105 to 2C is a 2a schematic view; a 2G diagram is another embodiment of the 2G diagram; and a 2L diagram is a 2L Another embodiment of the present invention; FIG. 3A to FIG. 3D are diagrams showing a package component of a package component of a package component of a packaged component of a semiconductor chip having an adhesive layer in a method of embedding a semiconductor device in the present invention; FIG. 4A to FIG. 6 are schematic cross-sectional views showing a second embodiment of the method for fabricating a semiconductor germanium substrate embedding the present invention; and FIGS. 5A to 5D are cross-sectional views showing a third embodiment of the method for fabricating a semiconductor substrate embedding the present invention. 6A to 6D are cross-sectional views showing a fourth embodiment of the method for fabricating a semiconductor substrate in the present invention; and FIGS. 7A to 7C are diagrams showing the semiconductor substrate embedded in the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 8A to FIG. 8D are diagrams showing the core of a resistive plastic frame embedded in a method for manufacturing a semi-conductive substrate according to the present invention, and the method and the components of the board are shown in Figures 9A to 9D. The present invention embeds a cross-sectional view of a sixth embodiment of a method for fabricating a semiconductor wafer. [Main component symbol description] 10a 10b 100 First substrate Second substrate opening H0593 27 200942105 II, 22 Semiconductor wafer 110 Bonding material III, 221 Electrode pads 11a, 22a Active surface lib, 22b Inactive surface * 12 Additive structure 120 ' 21 dielectric layer 121 circuit layer 〇 122 conductive blind hole 123 electrical contact pad 13 solder mask 130 opening 2 semiconductor wafer 200 carrier plate 21 dielectric layer 21, first dielectric layer , 21,, second dielectric Layer 210 opening 210" opening region 211a dielectric layer opening 211b through hole 21a first surface 21b second surface 23a first metal layer 200942105 ΔόΌ second metal layer 23c third metal layer 24 conductive layer 26 conductive via 26, solid Conductive via hole* 260 filling material 27 first resistive layer 270a resistive layer first opening 270 270b resistive layer second opening 280a, first conductive blind via 281a first electrical contact pad 281b second electrical contact pad 28a first line Layer 28b second circuit layer 29, first build-up structure 29, second build-up structure 290, third dielectric layer 290" fourth dielectric layer 290a first opening 2 91' third circuit layer 291" fourth circuit layer 291b first opening 292' second conductive blind hole 292" third conductive blind hole 29 110593 200942105 zyzd second opening 293' third electrical contact pad 293" fourth Electrical contact pad 294 second opening '29a first solder mask' 29b second solder mask 30 carrier plate 31 adhesive layer 40 core dielectric layer 400 core dielectric opening 50 core plate 500 core plate opening 50a third surface 50b fourth surface 51a fifth wiring layer 51a' fifth thinned wiring layer b51b sixth wiring layer 51b' sixth thinned wiring layer 51c plastic resistive frame 60 second resistive layer 600 open region 30 110593