TWI626863B - Circuit board structure - Google Patents
Circuit board structure Download PDFInfo
- Publication number
- TWI626863B TWI626863B TW104113950A TW104113950A TWI626863B TW I626863 B TWI626863 B TW I626863B TW 104113950 A TW104113950 A TW 104113950A TW 104113950 A TW104113950 A TW 104113950A TW I626863 B TWI626863 B TW I626863B
- Authority
- TW
- Taiwan
- Prior art keywords
- metal layer
- layer
- resin
- circuit board
- board structure
- Prior art date
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 197
- 239000002184 metal Substances 0.000 claims abstract description 197
- 229920005989 resin Polymers 0.000 claims abstract description 76
- 239000011347 resin Substances 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 238000005530 etching Methods 0.000 claims abstract description 39
- 238000007747 plating Methods 0.000 claims abstract description 17
- 239000000126 substance Substances 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims abstract description 10
- 238000004544 sputter deposition Methods 0.000 claims abstract description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 41
- 239000011889 copper foil Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 21
- 239000010949 copper Substances 0.000 claims description 20
- 229910052802 copper Inorganic materials 0.000 claims description 16
- 230000008569 process Effects 0.000 claims description 16
- 239000011651 chromium Substances 0.000 claims description 9
- 239000012779 reinforcing material Substances 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 9
- 230000000903 blocking effect Effects 0.000 claims description 8
- 229920000049 Carbon (fiber) Polymers 0.000 claims description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 5
- 239000004917 carbon fiber Substances 0.000 claims description 5
- 229910052804 chromium Inorganic materials 0.000 claims description 5
- 239000003365 glass fiber Substances 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 239000004743 Polypropylene Substances 0.000 claims description 4
- 239000003989 dielectric material Substances 0.000 claims description 4
- 239000012777 electrically insulating material Substances 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 4
- 229920000647 polyepoxide Polymers 0.000 claims description 4
- 229920001955 polyphenylene ether Polymers 0.000 claims description 4
- -1 polypropylene Polymers 0.000 claims description 4
- 229920001155 polypropylene Polymers 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- 238000007772 electroless plating Methods 0.000 claims description 3
- 229920001296 polysiloxane Polymers 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 abstract description 5
- 238000009713 electroplating Methods 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000000654 additive Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 239000004945 silicone rubber Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
本發明係一種線路板結構，包含在基板的樹脂層上由下而上堆疊的第一、第二、第三金屬層，分別經濺鍍、化學膚鍍、電鍍而形成。基板包含由下而上堆疊的阻止層及樹脂層，且阻止層具有圖案，並包含至少一接觸區，未被樹脂層覆蓋。第一、第二、第三金屬層具蝕刻圖案，位於接觸區以外的區域且相互對齊而曝露出部分的樹脂層。第三金屬層的蝕刻圖案可當作電氣線路的線路圖案。因第一金屬層具較佳表面特性，使得第二、第三金屬層更加穩固，而第三金屬層的蝕刻圖案的線寬/線距小於10um，可滿足電子元件封裝及電子應用產品對線路板細線寬/線距的要求。 The invention is a circuit board structure comprising first, second and third metal layers stacked on the resin layer of the substrate from bottom to top, respectively formed by sputtering, chemical plating and electroplating. The substrate includes a barrier layer and a resin layer stacked from bottom to top, and the barrier layer has a pattern and includes at least one contact region which is not covered by the resin layer. The first, second, and third metal layers have an etched pattern located in regions other than the contact regions and aligned with each other to expose a portion of the resin layer. The etching pattern of the third metal layer can be regarded as a wiring pattern of the electric wiring. Because the first metal layer has better surface characteristics, the second and third metal layers are more stable, and the etching width of the third metal layer has a line width/line spacing of less than 10 um, which can satisfy the circuit of electronic component packaging and electronic application products. Board thin line width / line spacing requirements.
Description
本發明係有關於一種線路板結構，尤其是將濺鍍形成的第一金屬層、化學膚鍍形成的第二金屬層、電鍍形成的第三金屬層依序堆疊在基板的樹脂層上，並藉第一金屬層提供較佳的表面特性，使得第二金屬層、第三金屬層更加穩固，可使得線路圖案具有線寬/線距小於10um的線路，滿足電子元件封裝及電子應用產品對線路板的細線寬/線距的要求。 The present invention relates to a circuit board structure, in particular, a first metal layer formed by sputtering, a second metal layer formed by chemical plating, and a third metal layer formed by plating are sequentially stacked on a resin layer of the substrate, and The first metal layer provides better surface characteristics, so that the second metal layer and the third metal layer are more stable, so that the line pattern has a line width/line spacing of less than 10 um, which satisfies the line of electronic component packaging and electronic application products. The thin line width/line spacing requirements of the board.
近年來，隨著大型積體電路(VLSI)的快速發展，連接線路也越來越細。例如，在半導體22nm技術中，單位面積上的晶片密度和信號處理能力已不斷提高，而迫使連接線路進一步細微化，結果導致現有的生產、製造設備及製程面臨到前所未有的艱鉅挑戰。再者，為進一步提高封裝密度，將晶片進行堆疊以形成三維封裝，此時，線路基板的線寬/線距需從100um縮小到30-50um。對於業界不斷縮小線寬/線距的要求，線路的銅表面結構要求也不斷嚴格。通常，一般的印刷電路板(Printed Circuit Board，PCB)中的銅粗糙度Rz為5-7um，其中載板的粗糙度須低於5um，但是對於線寬/線距10-20um，線路的銅線表面粗糙度Rz一般要在2um，否則很容易會發生線路變形而導致整體的電氣功能失效，或者，線間會因殘留的銅而導致短路，因而無法實現高精度、高可靠度的互連。 In recent years, with the rapid development of large integrated circuits (VLSI), the connection lines have become more and more fine. For example, in semiconductor 22nm technology, wafer density and signal processing capacity per unit area have been continuously increased, forcing the connection lines to be further miniaturized, resulting in unprecedented challenges in existing production, manufacturing equipment and processes. Furthermore, in order to further increase the package density, the wafers are stacked to form a three-dimensional package, and at this time, the line width/line distance of the circuit substrate needs to be reduced from 100 um to 30-50 um. As the industry continues to reduce the line width / line spacing requirements, the copper surface structure requirements of the line are also increasingly strict. Generally, the copper roughness Rz in a general printed circuit board (PCB) is 5-7um, wherein the roughness of the carrier must be less than 5um, but for the line width/line spacing 10-20um, the copper of the line The line surface roughness Rz is generally 2 um, otherwise it is easy to cause line deformation and the overall electrical function failure, or the line will be short-circuited due to residual copper, thus failing to achieve high-precision, high-reliability interconnection. .
在習用技術中，一般是利用半加成法(Semi Additive Process，SAP)以製作細線寬/線距50um以下的線路，而線寬小於25um的半加成SAP技術是使用素之味的ABF樹脂當絕緣層材料，或採用三菱瓦斯所生產的包覆樹脂銅箔(Primer Coated Copper Foil，PCF)及半固化片(或稱膠片，Prepreg)，藉壓合方式而實現。對於包覆樹脂銅箔(PCF)，主要是先在單面粗化好的銅箔面上塗覆一層2-3微米厚度的樹脂，經固化後再與半固化片一同壓合而形 成，而壓合後，可將銅箔去除以形成表面有一定粗超度的樹脂表面，因而可在樹脂表面藉化學鍍銅法(或化學膚鍍方式)而得到結合力良好的化學鍍銅層，藉以製作要求更為精細的線路。 In the conventional technology, a semi-additive process (SAP) is generally used to make a line with a fine line width/line spacing of 50 μm or less, and a semi-additive SAP technique with a line width of less than 25 μm is a plain ABF resin. When the insulating layer material, or the use of Mitsubishi Gas, the production of Copper Coated Copper Foil (PCF) and prepreg (or film, Prepreg), by pressing. For the coated resin copper foil (PCF), the surface of the copper foil which is roughened on one side is first coated with a layer of resin of 2-3 micrometers, and after curing, it is pressed together with the prepreg. After pressing, the copper foil can be removed to form a surface of the resin having a certain rough excess. Therefore, an electroless copper plating layer having good bonding force can be obtained by electroless copper plating (or chemical plating) on the surface of the resin. In order to make more demanding lines.
以利用包覆樹脂銅箔(PCF)的SAP法為例，其具體作法是先將PCF壓合於內層線路上，再去除PCF上的銅箔，留下具有高度表面特性的樹脂，用以藉化學膚鍍方式，在樹脂的表面上形成具細線寬/線距的線路圖案層。 Taking the SAP method using coated resin copper foil (PCF) as an example, the specific method is to press PCF onto the inner layer line, and then remove the copper foil on the PCF, leaving a resin with high surface characteristics for A wiring pattern layer having a fine line width/line pitch is formed on the surface of the resin by a chemical plating method.
然而，上述習用技術的缺點在於去除PCF的銅箔後所留下的樹脂不夠穩固，使得利用化學膚鍍方式所形成的線路圖案層很容易因附著力不足而發生斷裂、剝離、脫落，而且很難保持線路圖案層在填滿盲孔以當作連接柱的直立形狀不發生偏移，影響線路的電氣品質及操作的可靠度。 However, the above-mentioned conventional technique has a disadvantage in that the resin remaining after removing the copper foil of the PCF is not sufficiently stable, so that the wiring pattern layer formed by the chemical skin plating method is liable to be broken, peeled, and peeled off due to insufficient adhesion, and is very It is difficult to keep the line pattern layer filling the blind hole to be used as the upright shape of the connecting post without offset, affecting the electrical quality of the line and the reliability of operation.
因此，非常需要一種線路板結構，包含在基板的樹脂層上依序堆疊的第一金屬層、第二金屬層、第三金屬層，使得化學膚鍍形成的第二金屬層、電鍍形成的第三金屬層更加穩固，且第三金屬層的線路圖案的線寬/線距可小於10um，滿足電子元件封裝及電子應用產品對線路板的細線寬/線距的要求，因而解決上述習用技術的所有問題。 Therefore, there is a great need for a circuit board structure comprising a first metal layer, a second metal layer, and a third metal layer which are sequentially stacked on a resin layer of a substrate, such that a second metal layer formed by chemical skin plating is formed by electroplating. The three metal layers are more stable, and the line width/line distance of the circuit pattern of the third metal layer can be less than 10 um, which satisfies the requirements of the thin line width/line spacing of the circuit board for electronic component packaging and electronic application products, thereby solving the above-mentioned conventional technology. All questions.
本發明之主要目的在於提供一種線路板結構，具有細線寬/線距線路的特性及較高的線路精確度，主要包括基板、第一金屬層、第二金屬層以及第三金屬層。基板是由電氣絕緣材料所構成，並包含的阻止層及樹脂層，是位於基板上由下而上堆疊。阻止層具有特定的圖案，包含至少一接觸區，且部分的基板未被阻止層覆蓋，而是由樹脂層覆蓋，並由樹脂層進一步覆蓋接觸區以外的阻止層。 The main object of the present invention is to provide a circuit board structure having the characteristics of a thin line width/line line and a high line accuracy, and mainly includes a substrate, a first metal layer, a second metal layer, and a third metal layer. The substrate is made of an electrically insulating material and includes a barrier layer and a resin layer which are stacked on the substrate from bottom to top. The blocking layer has a specific pattern including at least one contact region, and a portion of the substrate is not covered by the blocking layer, but is covered by the resin layer, and the resist layer outside the contact region is further covered by the resin layer.
具體而言，第一、第二、第三金屬層是依序由下而上堆疊在樹脂層上以及在阻止層的接觸區上，其中第一金屬層、第二金屬層、第三金屬層是分別由濺鍍、化學膚鍍、電鍍而形成，且第一金屬層覆蓋接觸區的部分為凹陷區，是低於第一金屬層的其餘部分。第一金屬層具有蝕刻圖案，是在凹陷區以外的部分，而第二、第三金屬層也分別具有蝕刻圖案， 其中第一、第二、第三金屬層的蝕刻圖案是利用線路蝕刻而形成並且相互對齊而曝露出部分的樹脂層，且第三金屬層的蝕刻圖案可當作電氣線路的線路圖案。 Specifically, the first, second, and third metal layers are sequentially stacked from bottom to top on the resin layer and on the contact region of the blocking layer, wherein the first metal layer, the second metal layer, and the third metal layer It is formed by sputtering, chemical plating, and electroplating, respectively, and the portion of the first metal layer covering the contact region is a recessed region, which is lower than the rest of the first metal layer. The first metal layer has an etching pattern, which is a portion outside the recessed region, and the second and third metal layers also have an etching pattern, respectively. The etching patterns of the first, second, and third metal layers are formed by line etching and are aligned with each other to expose a portion of the resin layer, and the etching pattern of the third metal layer can be regarded as a line pattern of the electric circuit.
再者，樹脂層可覆蓋經預先處理的銅箔層，而預先處理可包含對銅箔層進行黑化處理或棕化處理，藉以氧化銅箔層的表面。樹脂層的表面具有適當的粗糙度，Ra=0~1um及Rz=0~10um，且可包含樹脂基材，而樹脂基材包含環氧樹脂、FR4、FR5、改質(Modified)FR4、矽膠、BT樹脂、聚苯醚樹脂(PPO)、聚醯亞胺(PI)、Ajinomoto內建膜(ABF)、聚丙烯或光可成像介電材料(PIDM)。 Furthermore, the resin layer may cover the pretreated copper foil layer, and the pretreatment may include blackening or browning the copper foil layer to thereby oxidize the surface of the copper foil layer. The surface of the resin layer has appropriate roughness, Ra=0~1um and Rz=0~10um, and may include a resin substrate, and the resin substrate includes epoxy resin, FR4, FR5, modified FR4, silicone rubber , BT resin, polyphenylene ether resin (PPO), polyimine (PI), Ajinomoto built-in film (ABF), polypropylene or photoimageable dielectric material (PIDM).
基板可具有內層線路層，而第一金屬層可包含上部金屬層及下部金屬層，且上部金屬層是堆疊於下部金屬層上，因而下部金屬層是堆疊於內層線路層的裸露部分上。上部金屬層包含銅(Cu)，而下部金屬層包含鈦(Ti)、鉻(Cr)或鉭(Ta)，且第二金屬層50及第三金屬層60是包含銅。 The substrate may have an inner wiring layer, and the first metal layer may include an upper metal layer and a lower metal layer, and the upper metal layer is stacked on the lower metal layer, so that the lower metal layer is stacked on the exposed portion of the inner wiring layer . The upper metal layer contains copper (Cu), and the lower metal layer contains titanium (Ti), chromium (Cr) or tantalum (Ta), and the second metal layer 50 and the third metal layer 60 contain copper.
上述的第一金屬層可進一步包含底部金屬層，位於下部金屬層之下並接觸到內層線路層的裸露部分，而底部金屬層包含氮化鈦(TiN)。樹脂層可包含均勻分佈的強化材料，比如玻璃纖維或碳纖維。 The first metal layer described above may further comprise a bottom metal layer underlying the lower metal layer and contacting the exposed portion of the inner wiring layer, and the bottom metal layer comprising titanium nitride (TiN). The resin layer may comprise a uniformly distributed reinforcing material such as glass fiber or carbon fiber.
由於第一金屬層、第二金屬層、第三金屬層之間具有較強的貼附強度，因而不易剝離，且濺鍍處理形成的第一金屬層能與接觸區、樹脂層形成較佳的貼附作用，使得本發明的線路板結構相當穩固，不易翹曲或變形，具有較佳的可靠度及耐用性。 Since the first metal layer, the second metal layer, and the third metal layer have strong adhesion strength, the metal layer is not easily peeled off, and the first metal layer formed by the sputtering process can be formed better with the contact region and the resin layer. The attaching action makes the circuit board structure of the invention quite stable, is not easy to warp or deform, and has better reliability and durability.
具體而言，本發明的線路板具有小於10um的線寬/線距，可大幅改善線路板的品質，尤其是易於利用習用製作工具而具體實施，不僅降低整體材料成本，具有價格優勢，還能確實滿足電子元件封裝及電子應用產品對線路板的細線寬/線距的要求，有利於市場競爭。 Specifically, the circuit board of the present invention has a line width/line spacing of less than 10 um, which can greatly improve the quality of the circuit board, and is particularly easy to implement by using a conventional manufacturing tool, which not only reduces the overall material cost, but also has a price advantage. It does meet the requirements of the thin line width/line spacing of the circuit board for electronic component packaging and electronic application products, which is conducive to market competition.
10‧‧‧基板 10‧‧‧Substrate
12‧‧‧阻止層 12‧‧‧blocking layer
14‧‧‧接觸區 14‧‧‧Contact area
20‧‧‧樹脂層 20‧‧‧ resin layer
40‧‧‧第一金屬層 40‧‧‧First metal layer
41‧‧‧凹陷區 41‧‧‧ recessed area
50‧‧‧第二金屬層 50‧‧‧Second metal layer
60‧‧‧第三金屬層 60‧‧‧ third metal layer
H‧‧‧導通孔 H‧‧‧via
第一圖顯示依據本發明第一實施例線路板結構的示意圖。 The first figure shows a schematic view of a circuit board structure according to a first embodiment of the present invention.
第二圖顯示依據本發明第二實施例線路板結構的示意圖。 The second figure shows a schematic view of a circuit board structure according to a second embodiment of the present invention.
以下配合圖示及元件符號對本發明之實施方式做更詳細的說明，俾使熟習該項技藝者在研讀本說明書後能據以實施。 The embodiments of the present invention will be described in more detail below with reference to the drawings and the reference numerals, which can be implemented by those skilled in the art after having studied this specification.
參閱第一圖，本發明第一實施例線路板結構的示意圖。如第一圖所示，本發明第一實施例線路板結構主要包括基板10、第一金屬層40、第二金屬層50以及第三金屬層60，具有細線寬/線距線路的特徵。基本上，基板10是由電氣絕緣材料所構成，並且包含位於基板10上由下而上堆疊的阻止層12及樹脂層20，其中阻止層12具有特定的圖案，且阻止層12的圖案包含至少一接觸區14，第一圖只顯示單一接觸區14，因而有部分的基板10是未被阻止層12覆蓋，而是由樹脂層20覆蓋未被阻止層12覆蓋的該部分基板10，同時樹脂層20覆蓋接觸區14以外的阻止層12。 Referring to the first figure, a schematic diagram of a circuit board structure of a first embodiment of the present invention. As shown in the first figure, the circuit board structure of the first embodiment of the present invention mainly includes a substrate 10, a first metal layer 40, a second metal layer 50, and a third metal layer 60, which have the characteristics of a thin line width/line line. Basically, the substrate 10 is composed of an electrically insulating material and includes a barrier layer 12 and a resin layer 20 stacked on the substrate 10 from the bottom up, wherein the barrier layer 12 has a specific pattern, and the pattern of the barrier layer 12 contains at least A contact region 14, the first figure shows only a single contact region 14, and thus a portion of the substrate 10 is covered by the unblocked layer 12, but the portion of the substrate 10 covered by the unprotected layer 12 is covered by the resin layer 20, while the resin Layer 20 covers the barrier layer 12 outside of the contact zone 14.
再者，第一金屬層40、第二金屬層50、第三金屬層60是依序由下而上堆疊在樹脂層20上以及在阻止層12的接觸區14上，其中第一金屬層40覆蓋接觸區14的部分為凹陷區41，如第一圖中的虛線所標示，亦即，凹陷區41的高度是低於第一金屬層40的其餘部分的高度。 Furthermore, the first metal layer 40, the second metal layer 50, and the third metal layer 60 are sequentially stacked from bottom to top on the resin layer 20 and on the contact region 14 of the blocking layer 12, wherein the first metal layer 40 The portion covering the contact region 14 is a recessed portion 41 as indicated by a broken line in the first figure, that is, the height of the recessed portion 41 is lower than the height of the remaining portion of the first metal layer 40.
此外，第一金屬層40在凹陷區41以外的部分是具有蝕刻圖案，且第二金屬層50、第三金屬層60也分別具有蝕刻圖案，尤其是，第一金屬層40的蝕刻圖案、第二金屬層50的蝕刻圖案以及第三金屬層60的蝕刻圖案是相互對齊，因而曝露出部分的樹脂層20。因此，第三金屬層60的蝕刻圖案可當作電氣線路的線路圖案。此外，第一金屬層40的蝕刻圖案、第二金屬層50的蝕刻圖案以及第三金屬層60的蝕刻圖案可利用一般的線路蝕刻而形成。 In addition, the portion of the first metal layer 40 outside the recessed region 41 has an etching pattern, and the second metal layer 50 and the third metal layer 60 also have an etching pattern, respectively, in particular, an etching pattern of the first metal layer 40, The etching pattern of the two metal layers 50 and the etching pattern of the third metal layer 60 are aligned with each other, thereby exposing a portion of the resin layer 20. Therefore, the etching pattern of the third metal layer 60 can be regarded as a wiring pattern of the electric wiring. Further, the etching pattern of the first metal layer 40, the etching pattern of the second metal layer 50, and the etching pattern of the third metal layer 60 may be formed by general line etching.
具體而言，第一金屬層40是利用濺鍍處理而形成，第二金屬層50是利用化學敷鍍處理或無電鍍處理而形成，而第三金屬層60是利用電鍍處理而形成，其中第一金屬層40、第二金屬層50、第三金屬層60之間具有較強的貼附強度而不易剝離，尤其是，經濺鍍處理而形成的第一金屬層40能與接觸區14、樹脂層20形成較佳的貼附作用。因此，本發明的線路板結構相當穩固，不易翹曲或變形，具有較佳的可靠度及耐用性。 Specifically, the first metal layer 40 is formed by a sputtering process, the second metal layer 50 is formed by a chemical plating process or an electroless plating process, and the third metal layer 60 is formed by a plating process, wherein The metal layer 40, the second metal layer 50, and the third metal layer 60 have strong adhesion strength and are not easily peeled off. In particular, the first metal layer 40 formed by the sputtering process can be in contact with the contact region 14. The resin layer 20 forms a preferred attachment effect. Therefore, the circuit board structure of the present invention is relatively stable, is not easy to warp or deform, and has better reliability and durability.
進一步而言，樹脂層20的上表面可覆蓋銅箔層(圖中未顯 示)，且銅箔層是經預先處理，而該預先處理可包含對銅箔層進行黑化處理或棕化處理，其中黑化處理或或棕化處理可氧化銅箔層的表面。 Further, the upper surface of the resin layer 20 may cover the copper foil layer (not shown in the figure) And the copper foil layer is pretreated, and the pretreatment may include blackening or browning the copper foil layer, wherein the blackening treatment or the browning treatment may oxidize the surface of the copper foil layer.
較佳的，樹脂層20主要是包含樹脂基材，而樹脂基材包含環氧樹脂、FR4、FR5、改質(Modified)FR4、矽膠(Silicon)、BT樹脂、聚苯醚樹脂(PPO)、聚醯亞胺(PI)、Ajinomoto內建膜(Ajinomoto build-up film，ABF)、聚丙烯或光可成像介電材料(Photo Imageable Dielectric Material，PIDM)，尤其是樹脂層20的表面具有Ra=0~1um及Rz=0~10um的粗糙度。 Preferably, the resin layer 20 mainly comprises a resin substrate, and the resin substrate comprises epoxy resin, FR4, FR5, modified FR4, silicone, BT resin, polyphenylene ether resin (PPO), Polyimine (PI), Ajinomoto build-up film (ABF), polypropylene or Photoimageable Dielectric Material (PIDM), especially the surface of the resin layer 20 has Ra= Roughness of 0~1um and Rz=0~10um.
此外，基板10的上表面上及/或下表面上可分別具有內層線路層(圖中未顯示)，而且第一金屬層40可包含上部金屬層(圖中未顯示)及下部金屬層(圖中未顯示)，其中上部金屬層是堆疊於下部金屬層上，而下部金屬層是堆疊於內層線路層的裸露部分上。較佳的，上部金屬層包含銅(Cu)，而下部金屬層包含鈦(Ti)、鉻(Cr)或鉭(Ta)，且第二金屬層50及第三金屬層60包含銅。 In addition, an upper layer circuit layer (not shown) may be respectively disposed on the upper surface and/or the lower surface of the substrate 10, and the first metal layer 40 may include an upper metal layer (not shown) and a lower metal layer ( Not shown in the drawing), wherein the upper metal layer is stacked on the lower metal layer, and the lower metal layer is stacked on the exposed portion of the inner wiring layer. Preferably, the upper metal layer comprises copper (Cu) and the lower metal layer comprises titanium (Ti), chromium (Cr) or tantalum (Ta), and the second metal layer 50 and the third metal layer 60 comprise copper.
第一金屬層40還可進一步包含底部金屬層(圖中未顯示)，是位於下部金屬層之下並接觸到內層線路層的裸露部分，其中底部金屬層包含氮化鈦(TiN)。 The first metal layer 40 may further comprise a bottom metal layer (not shown) that is under the lower metal layer and contacts the exposed portion of the inner wiring layer, wherein the bottom metal layer comprises titanium nitride (TiN).
為了進一步加強整體的機械強度，增加抗撓性的作用並避免發生撓曲、變形，樹脂層20可進一步包含均勻分佈於樹脂基材中的強化材料(圖中未顯示)，其中強化材料可包含多個玻璃纖維或碳纖維，藉以構成複合材料。 In order to further strengthen the overall mechanical strength, increase the flexibility and avoid deflection and deformation, the resin layer 20 may further include a reinforcing material (not shown) uniformly distributed in the resin substrate, wherein the reinforcing material may include A plurality of glass fibers or carbon fibers to form a composite material.
請參閱第二圖，本發明第二實施例線路板結構的示意圖。如第二圖所示，第二實施例的線路板結構係類似於第一圖的第一實施例，同樣是包括基板10、第一金屬層40、第二金屬層50以及第三金屬層60，並具有細線寬/線距線路的特徵，且第二實施例中基板10、第一金屬層40、第二金屬層50以及第三金屬層60的材料特徵及形成是相同於第一實施例，因此不再贅述。 Referring to the second figure, a schematic diagram of a circuit board structure according to a second embodiment of the present invention. As shown in the second figure, the circuit board structure of the second embodiment is similar to the first embodiment of the first figure, and also includes the substrate 10, the first metal layer 40, the second metal layer 50, and the third metal layer 60. And having the characteristics of a thin line width/line line, and the material characteristics and formation of the substrate 10, the first metal layer 40, the second metal layer 50, and the third metal layer 60 in the second embodiment are the same as in the first embodiment. Therefore, I will not repeat them.
要注意的是，第二實施例不同於第一實施例的差異點主要是在於第二實施例的基板10不包含第一實施例的阻止層12，而是只包含樹脂層20，而且樹脂層20是配置於基板10的上表面及下表面，而且在樹脂層 20上依序堆疊第一金屬層40、第二金屬層50以及第三金屬層60。另一差異點為，基板10還具有至少一導通孔H，其中導通孔H本質上是貫穿孔，是貫穿基板10的上表面及下表面，因此，第一金屬層40、第二金屬層50以及第三金屬層60依序覆蓋導通孔H的側壁，且由第三金屬層60填滿，亦即導通孔H中的第三金屬層60可形成栓塞狀結構。 It is to be noted that the difference between the second embodiment and the first embodiment is mainly that the substrate 10 of the second embodiment does not include the stopper layer 12 of the first embodiment, but only the resin layer 20, and the resin layer. 20 is disposed on the upper surface and the lower surface of the substrate 10, and is in the resin layer The first metal layer 40, the second metal layer 50, and the third metal layer 60 are sequentially stacked on the 20th. Another difference is that the substrate 10 further has at least one via hole H. The via hole H is substantially a through hole and penetrates the upper surface and the lower surface of the substrate 10 . Therefore, the first metal layer 40 and the second metal layer 50 . And the third metal layer 60 sequentially covers the sidewall of the via hole H and is filled by the third metal layer 60, that is, the third metal layer 60 in the via hole H can form a plug-like structure.
如同第一實施例，第二實施例的第一金屬層40、第二金屬層50以及第三金屬層60也具有個別的蝕刻圖案，是配置於導通孔H以外的區域，並相互對齊，因而曝露出部分的樹脂層20。因此，第三金屬層60的蝕刻圖案可當作電氣線路的線路圖案，進而達到線路板的功能。再者，第一金屬層40、第二金屬層50以及第三金屬層60的蝕刻圖案可分別藉線路蝕刻處理而實現。 As in the first embodiment, the first metal layer 40, the second metal layer 50, and the third metal layer 60 of the second embodiment also have individual etching patterns, which are disposed outside the via holes H, and are aligned with each other. A portion of the resin layer 20 is exposed. Therefore, the etching pattern of the third metal layer 60 can be regarded as a wiring pattern of the electric circuit, thereby achieving the function of the wiring board. Furthermore, the etching patterns of the first metal layer 40, the second metal layer 50, and the third metal layer 60 can be realized by line etching treatment, respectively.
本實施例的樹脂層20的上表面也可覆蓋銅箔層(圖中未顯示)，其中銅箔層是經預先處理，包含對銅箔層進行黑化處理或棕化處理，可用以氧化銅箔層的表面。 The upper surface of the resin layer 20 of the present embodiment may also cover a copper foil layer (not shown), wherein the copper foil layer is pretreated, including blackening or browning the copper foil layer, and may be used for copper oxide. The surface of the foil layer.
此外，基板10的上表面上及/或下表面上分別具有內層線路層(圖中未顯示)，且第一金屬層40包含上部金屬層(圖中未顯示)及下部金屬層(圖中未顯示)，而第一金屬層40還可進一步包含底部金屬層(圖中未顯示)，其中內層線路層、上部金屬層、下部金屬層及底部金屬層的特徵如同第一實施例，相關技術內容不再贅述。 In addition, the upper surface of the substrate 10 and/or the lower surface respectively have an inner layer circuit layer (not shown), and the first metal layer 40 includes an upper metal layer (not shown) and a lower metal layer (in the figure). Not shown), the first metal layer 40 may further include a bottom metal layer (not shown), wherein the inner layer, the upper metal layer, the lower metal layer and the bottom metal layer are characterized as in the first embodiment, The technical content will not be described again.
樹脂層20可包含均勻分佈於樹脂基材中的強化材料(圖中未顯示)，其中強化材料可包含多個玻璃纖維或碳纖維，以加強機械強度、抗撓性。 The resin layer 20 may include a reinforcing material (not shown) uniformly distributed in the resin substrate, wherein the reinforcing material may include a plurality of glass fibers or carbon fibers to enhance mechanical strength and flexibility.
綜上所述，本發明的主要特點在於將濺鍍形成的第一金屬層、化學膚鍍形成的第二金屬層、電鍍形成的第三金屬層依序堆疊在基板的樹脂層上，並藉第一金屬層提供較佳的表面特性，使得第二金屬層、第三金屬層更加穩固，可使得線路圖案具有線寬/線距小於10um的線路，因而確實滿足電子元件封裝及電子應用產品對線路板的細線寬/線距的要求。 In summary, the main feature of the present invention is that the first metal layer formed by sputtering, the second metal layer formed by chemical plating, and the third metal layer formed by electroplating are sequentially stacked on the resin layer of the substrate, and The first metal layer provides better surface characteristics, so that the second metal layer and the third metal layer are more stable, so that the line pattern has a line width/line spacing of less than 10 um, thus satisfying the electronic component packaging and the electronic application product pair. The thin line width/line spacing requirements of the board.
尤其是，第一金屬層包含由容易氧化的銅或鋁所構成的上部金屬層，還包含由用以提高活性的鈦、鉻或鉭所構成的下部金屬層，可改 善後續處理的加工性及品質。此外，第一金屬層還可進一步包含由氮化鈦所構成的底部金屬層，位於下部金屬層下，用以接觸內層線路層，使得第一金屬層的整體材料強度以及與內層線路層之間的結合力獲得大幅改善。因此，本發明的線路板確實具有較高的操作穩定性及可靠度，並有效解決習用技術的缺點。 In particular, the first metal layer comprises an upper metal layer composed of copper or aluminum which is easily oxidized, and further comprises a lower metal layer composed of titanium, chromium or ruthenium for enhancing activity, which can be modified. Good processing and quality of follow-up treatment. In addition, the first metal layer may further comprise a bottom metal layer composed of titanium nitride under the lower metal layer for contacting the inner circuit layer such that the overall material strength of the first metal layer and the inner layer layer The bond between them has been greatly improved. Therefore, the circuit board of the present invention does have high operational stability and reliability, and effectively solves the shortcomings of the conventional technology.
由於本發明的技術內並未見於已公開的刊物、期刊、雜誌、媒體、展覽場，因而具有新穎性，且能突破目前的技術瓶頸而具體實施，確實具有進步性。此外，本發明能解決習用技術的問題，改善整體使用效率，而能達到具產業利用性的價值。 Since the technology of the present invention is not found in published publications, periodicals, magazines, media, exhibition venues, and thus is novel, and can be implemented by breaking through the current technical bottlenecks, it is indeed progressive. In addition, the present invention can solve the problems of the conventional technology, improve the overall use efficiency, and can achieve the value of industrial utilization.
以上所述者僅為用以解釋本發明之較佳實施例，並非企圖據以對本發明做任何形式上之限制，是以，凡有在相同之發明精神下所作有關本發明之任何修飾或變更，皆仍應包括在本發明意圖保護之範疇。 The above is only a preferred embodiment for explaining the present invention, and is not intended to limit the present invention in any way, and any modifications or alterations to the present invention made in the spirit of the same invention. All should still be included in the scope of the intention of the present invention.
Claims (19)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104113950A TWI626863B (en) | 2015-04-30 | 2015-04-30 | Circuit board structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104113950A TWI626863B (en) | 2015-04-30 | 2015-04-30 | Circuit board structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201639421A TW201639421A (en) | 2016-11-01 |
| TWI626863B true TWI626863B (en) | 2018-06-11 |
Family
ID=57850454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW104113950A TWI626863B (en) | 2015-04-30 | 2015-04-30 | Circuit board structure |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI626863B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI605733B (en) * | 2016-11-10 | 2017-11-11 | 南亞電路板股份有限公司 | Printed circuit board and methods for forming the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200942105A (en) * | 2008-03-27 | 2009-10-01 | Phoenix Prec Technology Corp | Method of fabricating package substrate having semiconductor component embedded therein |
| TWI371830B (en) * | 2008-05-29 | 2012-09-01 | Advanced Semiconductor Eng | Circuit board process |
| TWI475693B (en) * | 2011-02-25 | 2015-03-01 | Fujitsu Ltd | Semiconductor device and method of manufacturing the same, and power supply apparatus |
-
2015
- 2015-04-30 TW TW104113950A patent/TWI626863B/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200942105A (en) * | 2008-03-27 | 2009-10-01 | Phoenix Prec Technology Corp | Method of fabricating package substrate having semiconductor component embedded therein |
| TWI371830B (en) * | 2008-05-29 | 2012-09-01 | Advanced Semiconductor Eng | Circuit board process |
| TWI475693B (en) * | 2011-02-25 | 2015-03-01 | Fujitsu Ltd | Semiconductor device and method of manufacturing the same, and power supply apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201639421A (en) | 2016-11-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7954234B2 (en) | Method of manufacturing a wiring board | |
| US20120006591A1 (en) | Wiring Substrate and Method for Manufacturing Wiring Substrate | |
| US9899235B2 (en) | Fabrication method of packaging substrate | |
| US20140054785A1 (en) | Chip package structure and method for manufacturing same | |
| JP2007324559A (en) | Multilayer circuit board with fine pitch and fabricating method thereof | |
| CN103681565A (en) | Semiconductor package substrates having pillars and related methods | |
| KR102069659B1 (en) | Method for manufacturing semiconductor package substrate and semiconductor package substrate manufactured using the same | |
| TWI626863B (en) | Circuit board structure | |
| EP2493274A1 (en) | Metal layer structure of multilayer flexible borad and making method thereof | |
| US9744624B2 (en) | Method for manufacturing circuit board | |
| US9398704B2 (en) | Manufacturing method of metal structure of flexible multi-layer substrate | |
| TWI691245B (en) | Manufacturing method of circuit board | |
| CN108172561B (en) | Bearing substrate, packaging structure thereof and manufacturing method of semiconductor packaging element | |
| TWI691244B (en) | Circuit board | |
| US10049976B2 (en) | Semiconductor substrate and manufacturing method thereof | |
| US11037869B2 (en) | Package structure and preparation method thereof | |
| US9204561B2 (en) | Method of manufacturing a structure of via hole of electrical circuit board | |
| JP4445778B2 (en) | Wiring board manufacturing method | |
| TWI626871B (en) | Circuit board manufacturing method | |
| KR20150107141A (en) | The printed circuit board and the method for manufacturing the same | |
| TWI425898B (en) | Method for fabricating wiring structure of circuit board | |
| US20160372409A1 (en) | Circuit board structure | |
| KR101067088B1 (en) | Printed circuit board and a fabricating method of the same | |
| TWI496243B (en) | Method for fabricating embedded component semiconductor package | |
| US8766102B2 (en) | Chip support board structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |