TW200917441A - Inter-connecting structure for semiconductor package and method of the same - Google Patents

Inter-connecting structure for semiconductor package and method of the same Download PDF

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Publication number
TW200917441A
TW200917441A TW97137322A TW97137322A TW200917441A TW 200917441 A TW200917441 A TW 200917441A TW 97137322 A TW97137322 A TW 97137322A TW 97137322 A TW97137322 A TW 97137322A TW 200917441 A TW200917441 A TW 200917441A
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Taiwan
Prior art keywords
layer
die
package
solder
semiconductor die
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TW97137322A
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English (en)
Inventor
Wen-Kun Yang
Hsien-Wen Hsu
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Advanced Chip Eng Tech Inc
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Publication date
Application filed by Advanced Chip Eng Tech Inc filed Critical Advanced Chip Eng Tech Inc
Publication of TW200917441A publication Critical patent/TW200917441A/zh

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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Description

200917441 六、發明說明： 【發明所屬之技術領域】 本發明係關於-種半導體封裝結構，特別是關於一種 用於半導體封裝結構之互連結構。 【先前技術】 曰曰片封裝之功能包含電源分配（p〇wer⑴价比加丨⑽）、訊 號分配（signal distributi〇n)、散熱（heat此咖如㈡、保護 與支撐等。當半導體變得更為複雜時，一般傳統封裝技術， 例如導線架封裝（lead frame package)、軟性封裝⑺以 package)、剛性封裝（rigidpackageHjUfi，已無法達成於晶 粒上產生具有高密度元件之小型晶粒的需求。一般來說， 陣列封裝技術例如球閘陣列封裝（Ball Grid Array，BGa) 提供一較封裝之表面密度更高之互連（interc〇nnects)結 構。典型的球閘陣列封裝包含一卷積訊號路徑（c〇nv〇luted signal path)，引起高阻抗與一無效率之散熱路徑（thermai path)進而導致不良的散熱表現。當封裝之密度增加時，散 佈元件所產生之熱將變得更為重要。為了符合新一代電子 產品之封裝需求，許多努力已被投入於製造可靠、符合成 本效益、小型及高效能的封裝。此類的需求，舉例來說包 括了縮短電性訊號（electrical signal)的傳播延遲 (propagation delay)，降低整體組件的面積，及在輸入/輪出 (I/O)連接塾的配置上具有更廣泛的自由度。為了符合上述 品求而發展出一種晶圓級封裝（Wafer Level Package， WLP)，其中一陣列的輸入/輸出端（I/〇 terminals)係分佈於 200917441 主動面（active surface)上方，而不是週邊引腳封裝 (peripherai_ieaded package)。此類終端（terminai)的分佈可 增：輸入/輸出端的數目並可改善元件的電性效能。再者， 架叹具有互連之積體電路（lntegrated circuit，ic)於印刷電 路板上時所佔狀面積僅為晶片的尺寸，而非封裝導線苹 的尺寸。因此，晶圓級封裝（WLP)之尺寸可做的非常小。、 可參考晶片尺寸封裝⑽ip seale paekage，csp)，其為此類 型的一種。 、 1C封裝之改良係由產業對增進散熱能力與電性效 能，以及縮;咸尺寸與降低製造成本之需求所推冑。在半導 體元件的領域中，it件密度係不斷的增加的而元件尺寸則 是：短的縮減。為了符合上述情形，在此類高密度元件中 進行封裝及互連技術之需求亦增加了。可利用—焊錫複合 材料而形成焊錫凸塊（SGlder bumps)。覆晶技術（fli卜咖P technology)係廣為熟悉此領域之技藝者所熟知，用於電性 連接一晶粒至一架設基底（m〇unting substra⑹，例如一印 刷電路板。晶粒之主動面通常係受被帶至晶粒邊緣之許多 電性耗合（eleetdW _plings)所制。電性連接係作為終端 而沈積於覆晶之主動面上。上述凸塊包含形成機械連接 及電性耦合至一基底之焊錫及/或塑膠。在重佈層（rdl)之 後的焊錫凸塊具有約略5(M⑻_之凸塊高度。晶粒係倒 置於-架設基底之上’其凸塊係與架設基底上之連接塾對 齊。假使上述凸塊係焊錫凸塊，則覆晶上之焊錫凸塊係焊 接至基底上之連接墊。焊錫接頭（s〇lder j〇ims)係相對的便 200917441 宜，但熱機械應力（thermo-mechanical stress)所帶來的疲乏 (fatigue)卻會顯示出增強電性抗性及隨著時間流逝而出現 的裂縫與空隙。再者，焊錫通常為一種錫鉛合金，而對有 毒材料的處理以及有毒材料可能濾入（leaching)地下水源 等環保上的考量，含鉛材料已變得較不受歡迎。 進一步來說，由於一般封裝技術必須先將晶圓上之晶 粒分割為個別晶粒，而後將晶粒分別封裝，因此上述技術 之製程十分費時。由於晶粒封裝技術受到積體電路之發展 高度影響，因此當電子元件之尺寸要求越來越高時，封裝 技術之要求也越來越高。基於上述理由，現今之封裝技術 已逐漸趨向採用球閘陣列封裝（BGA)、覆晶球閘陣列封裝 (flip chip ball grid array，FC-BGA)、晶片尺寸封裝（CSP)、 晶圓級封裝（WLP)之技術。應可理解「晶圓級封裝」（WLP) 指晶圓上所有封裝及互連結構，並包含於切割（singulation) 為個別晶粒前所進行之其他製程步驟。一般而言，在完成 所有封裝製程（assembling processes)或封裝製程 (packaging processes)之後，個別半導體封裝係由具有複數 半導體晶粒之晶圓中所分離出來的。上述晶圓級封裝具有 極小之尺寸及良好之電性。 美國專利第2004/0266162 A1號揭露了 一具有複數連 接墊及一純化層（passivation layer)之半導體晶圓。球下金 屬層（under bump metallurgy layers)係分別形成於個別連接 墊上。接著，複數凸塊係個別配置於開口中，其中每個凸 塊結構均具有一凸塊及一強化層（reinforced layer)覆蓋於 200917441 凸塊上。參考第一 a圖’半導體元件2〇〇具有連接墊2〇2、 一外露出連接墊2〇2之鈍化層2〇4以及複數球下金屬層 206形成於連接墊2〇2之上。焊錫凸塊2〇8係形成於球下 金屬層206之上。焊錫凸塊係由凸塊強化軸環 (bUmp-reinf0rced collars) 21〇所覆蓋或圍繞。美國專利第 6,271，469號揭露了 一具有重佈層124之封裝結構，如第一 b圖所*。上述微電子封裝結構包含一具有一主動面之微 電子晶粒102。-封裝材料112係配置於緊鄰微電子晶粒 102的側邊，其中封裝材料112包含至少―大體上與微電 子晶粒102之主動面呈平面⑻咖）的表面。一第一介電材 料層118可配置於至少上述微電子晶粒1〇2之主動面及封 裝材料112之表面的一部分上。接著，至少一導電佈線 (conductive trace)(即前述重佈層）124係配置於第一介電 材料層118上。上述導電佈、線124係與微電子晶粒⑽之 主動面形成電性連接。接著，一第二介電層126及一第三 介電層136作為防焊錫層（s〇lder mask u㈣而覆蓋於晶 粒上方。通孔（via holes) 132係形成於第二介電層i26 = 用以耦合至導電佈，線124。作為球下金屬層㈣以— metallurgy，UBM)功能之金屬墊134係連接至通孔⑴而焊 錫凸塊138則位於金屬藝134上。上述封裝結構包含一具 有-主動面及至少-側邊之微電子晶粒。一封裝材料係配 置於緊鄰微電子晶粒的側邊，其中封裝材料包含至少一 體上與微電子晶粒之主動面呈平面(plana〇的表面。二電佈 線係與微電子晶粒之主動面形成電性連接。至少一導電佈 200917441 線係垂直延伸至緊鄰於微電子晶粒之主動面並垂直緊鄰封 裝材料表面。 由於這些傳統設計包含了太多介電層之堆疊，再加上 製程中所考量之塑模複合物（molding compound)及晶粒之 熱膨脹係數（coefficient of thermal expansion, CTE) ’ 其機 械性質多為「塑性/硬性」（plastic/hardness)而非「彈性/軟 性」（elastic/softness);且錫球（solder ball)僅附著於重佈層 之上方，顯然的，上述設計並未考量到熱循環測試（thermal cycle test, TCT)、錫球剪力測試（ball shear test)及墜落測試 (drop test)等問題。當元件附者（藉由表面黏著技術（surface mount technology, SMT))於母板（印刷電路板（printed circuit board, PCB))上時，由於母板以及元件本身之間的熱 膨脹係數不匹配（CTE mismatching)的緣故，在溫度循環期 間錫球將承受最大的應力（stress)，因此防焊錫層（表面介 電層）或者凸塊強化軸環將無法穩固的鎖住錫球（太薄且易 碎-容易在熱循環期間裂開）。再者，上介電層（upper dielectric layer)之熱膨脹係數與印刷電路板之熱膨脹係數 的不匹配顯示出其内部並未有應力釋放緩衝層（stress releasing buffer layers)的存在。所以，此架構在熱循環及 封裝的操作期間將係不可靠的。 因此’本發明提供了一具有一覆晶架構之焊錫互連結 構，用以克服前述問題並提供更佳的元件效能。 【發明内容】 本發明之一目的係在於提供一晶粒及一導電佈線予一 200917441 ΐ =㈣裝結構(晶粒封裝⑻一_，其可提供 低成本、向效能及高可靠度之封裝。 播，=月之另—目的係在於提供—半導體元件封裝結 、、在熱循環以及操作期間均具有高可靠度。 的製3 =又：目的係在於提供-便利及符合成本效益 的h +導體凡件封裝結構之方法。 ，本發明之一觀點中’一半導體晶粒封裝之互連結 ’匕含-增層（bulld_up layer)，其具有重佈層形成於其 ’上述增層係形成於一晶粒上，而此晶粒具有晶粒墊形 成於其上方’*中上述重佈層係耦合至上述晶粒墊；一隔 離基座㈣lation base)，其具有球形開口（bau㈣他㈣（通 孔)附著於上述增層上方用以露出增層内之錫球墊；以及 導電球（conductive balls)配置於上述隔離罩 mask)(基座）之球形開口中並附著於上述增層内之錫球墊 上0 上述結構更包含了一球下金屬層形成於導電球墊 (conductive ball pads)之上方。或者’上述球下金屬層亦可 附著於球形開π之侧壁。上述結構之重佈層係由層合銅羯 (laminated copper foil)、濺鍍金屬及電鍍（E piated)銅 /鎳 / 金（CU/Ni/AU)所形成。上述隔離罩係由環氧類樹脂、fr4、 FR5、PI、有機材料或BT所形成。隔離罩包含玻璃纖維於 其中。上述結構更進一步包含一黏著層（adhesivelayer)位 於上述隔離罩（基座）之下方。 上述重佈層係設定為扇入（fan-in)形式或扇出 200917441 (fan-out)(擴散）形式的架構.此結構更進一步包含一基底形 成於晶粒之下。一核心膠（corepaste)係形成於晶粒旁。 種形成一用於半導體晶粒封裝之互連結構之方法， 包含形成增層於一晶粒或晶圓(或面板)之核心區域上方， 其中上述增層包含重佈層形成於其中；至少於增層之上層 開出開口’用以露出焊錫金屬墊；附著一具有球形開口‘ 式之隔離罩於增層上並露出上述焊錫金屬塾；及將锡球配 置於隔離罩之球形開口中並附著於增層之焊錫金屬墊上。 &方法更包含-形成-球下金屬層於錫球塾上 【實施方式】 在下列敘述巾’各柄定細節係用以提供本發明實施 例之通盤瞭解。本發明將配合其較佳實施例與後附之圖式 詳述於下，應理解的是本發明中所有較佳實施例僅為例示 之用，並非用以限制本發明。除了這些明叙敘述外，本 發明可以實施在其他廣泛範圍之實施例中。本發明之範圍 i不文限於上述實施例’其當視後述之申請專利範圍而定 本發月揭路了種半導體元件封I結構。本發明提供 二：半導體晶粒組件，如第二圖所示’其包含晶粒、導電 佈線及金屬互連結構。 基底201之剖面圖。基底2〇1可為 第二圖係 金屬 陶究、„、印刷電路板（pcB)或 聚亞胺(P°lyimide，PI)。上述基底之厚度係約為40至200 们1可為—早層或多層基底。—晶粒2Ό5係藉由一黏 者材枓2U而黏貼於基底2〇1之表面上。其可具有用以吸 200917441 收熱所產生的應力之彈性特性。互連結構（詳細細節將於下 文中敘述）215係耦合至晶粒205之晶粒墊203。上述晶粒 墊203可為鋁墊、銅墊或其他金屬墊。一堆疊增層架構 (stacked build-up scheme)216係形成於晶粒2〇5及核心膠 209之上，核心膠209係形成於晶粒2〇5旁以保護晶粒 205。增層架構216亦包含用以露出晶粒墊2〇3之開口。重 佈層207係形成於增層架構216之内。須注意的是，部份 重佈層2〇7係外露於增層架構216，用α配置導電球（導電 凸塊）225。導電凸塊225係輪合至重佈層2〇7。 -具有凸塊（球形）開口 3〇2之隔離基座（或罩係形 成於增層架構216上方，如第二圖及第三圖所示。凸塊開 口 302係與前述增層架構216之開口對齊的。舉例來說， 隔離基座300係由環氧類樹脂則fr5、bt所組成，而 在車乂佳的清况下’其係具有玻璃纖維形成於其中之Μ基 2 :實^例中’隔離罩300包含-黏著層304形成於 上。球下金屬層219係形成於錫球塾上並耦合至 重佈層207。 重佈層207係以電鑛（咖㈣ =(:叫 曰粒二:㈣具有理想的厚度。導電層延伸出容納 與扇出(擴散)架構相關。核心膠_將 二:；中並覆蓋於基底201之上方。其可由樹脂' 物夕膠或環氧類樹脂所形成。 第四圖顯示出本發明之另—實施例。除了基底結構之 10 200917441 外’此結構之絕大部分皆與上述實施例相似。請參照第四 圖’基底400包含一凹槽（或通孔）4〇2，用以容納晶粒2〇5。 本發明亦可應用至如第五圖所示之一扇入架構。重佈層 502並未延伸出晶粒區域，相反地，重佈層5〇2係由位於 晶粒205邊緣之晶粒墊504往晶粒205之中心區域延伸。 晶粒205之下表面及側表面係暴露在外的且其尺寸亦係經 過縮減的。此為一真正的晶圓級晶片尺寸封裝 level-chip scale package，WL_csp)。上述兩個實施例皆包 ^具有球形開口形成於其上之隔離罩（或基座）3〇〇。基底之 厚度係大幅度的縮;咸了且其可提供較傳統封裝結構更佳之 散熱架構。 請參照第六a圖，其顯示出本發明之互連結構，盆包 含一堆疊之增層，此增層具有至少一下介電層612及:上 ==於晶粒_及核心膠6〇2上。-導電層_係 填疊增層之開口並輕合至晶粒6〇〇之晶粒塾_。 -具有球形開口之隔離罩618係形成於上 黏著層621係形成於隔離罩 曰曰上 雹屮错祕勒 618之下。球形開口 619至少 置錫：61!:;:分，此物係，合至重佈層。用以配 罩6以七 620係稱為焊錫金屬墊620，結隔離 罩618之球形開口係對齊 ^離 之上，而球形開口下方内部係:::下成::一 配置上述錫球並具有隔離及黏著=了金屬層⑽，用以 墊之間出現問題。球下金屬層之構：：：防止錫球與錫球 等；原則上來說，在*+ 構成成分可為銅、鎳、金 兄在…將錫與錄谭接在-起將可建構 11 200917441 金屬間化合物（inter metallurgy compound, IMC)，其可避免 在銅區域（copper area)中的電子遷移（electr〇n migrad〇n)。 一般來s兒，與其他金屬區域相比，當金屬間化合物受到外 力之衝擊時’金屬間化合物區域較易破裂。 參照第六b及第六c圖，其顯示出球下金屬層覆蓋了 隔離罩618之球形開口的侧壁。另一例子則係隔離罩具有 一黏著層621形成於隔離罩之下方。由於隔離基座内部之 玻璃纖維使其具有軟質（flexible)特性，故可保護封裝結構 之側壁及邊緣（如虛線所構成之閉環所示），以防止增層、 錫球、核心或矽樹脂在處理時受到外力（如鑷子）所損壞。 一種形成一用於半導體晶粒封裝之互連結構之方法， 包含形成增層於一晶粒或晶圓(或面板)之核心區域上方之 步驟，其中上述增層包含重佈層形成於其中。下一步驟係 至：於增層之上層開出開口，用以露出焊錫金屬墊二妾著 附著-具有球形開口樣式之隔離罩於增層上並露出上述焊 錫金屬塾。之後將錫球配置於隔離罩之球形開口中並附著 於增層之焊錫金屬墊上。此方法更包含—形成—球下 層於錫球墊上方之步驟。 然後’在完成錫球的配置之後，執行紅外線回焊步驟 (IRre_fl〇W)以形成最後的終端。近來，t界多半採用了曰 圓或面板級的最終測試’之後再將晶粒或核心膠切割成； -晶0並個闕|。本發明提供了較傳財法更簡易之製 請參照第七圖 ，其顯示出架設於母板之組件。母板7〇〇 12 200917441 包含位於其兩邊表面及内部的電路佈線（circuit traces)702。電路佈線的採用係為了在元件間形成電性連 接。母板（印刷電路板）700之熱膨脹係數約為16 ;隔離基 座（或罩）704之熱膨脹係數約為16;核心膠7〇6、晶粒7〇8、 硬式基底710之熱膨脹係數係分別約為3〇至2〇〇、2.6、4 至16。由於印刷電路板700與隔離基座704之熱膨脹係數 係相同的且錫球714皆係鎖定於隔離基座（罩）7之開口 内，故錫球/凸塊714將不受應力所影響。具有彈性特性之 增層716將作為緩衝區以免除導線結構所產生之熱應力， 即增層716將藉其彈性特性吸收晶粒/核心與隔離基座/錫 球之間的熱機械應力（thermal mechanical stress)。具有橡膠 彈性特性之黏著層718亦可吸收熱應力，從而解決熱膨脹 係數不匹配之問題。在其他實施例中，黏著層7丨8可用來 替代（作為）增層716之上介電層。 本發明之優點及有利之處包含： 《 強化錫球/焊錫凸塊的強度：由於錫球係牢牢的固定於 隔離罩（基座）之口袋（洞）上而且隔離罩（基座）之熱膨脹係 數係與印刷電路板之熱膨脹係數相匹配，再加上增層之彈 性/延展（elongation)特性可吸收溫度循環期間之熱機械應 力，因此本發明可在溫度循環測試、墜落測試及錫球剪力 測試中提供較佳的可靠度。 強化扇入式與扇出（擴散）式之晶圓級封裝的頂部與侧 壁之強度：由於隔離罩（基座）内部具有玻璃纖維，隔離罩 .(BT/FR5/FR4/..)之強度係較表面介電層強，因此，其可避 13 200917441 特別是在封裝邊緣的 免增層在受到外力衝擊時遭到損壞 區域。 可輕易形成錫球/焊錫凸塊的製程:形成 層表面球塾區域將形成一「口袋」，此— 1二執士 (視錫球直徑而定），因此，當把錫球配置 於金屬墊％•錫球將可輕易落入「口袋」中。 可輕易替換錫球/痒錫凸金 其…W主 坪场凸塊-重工(rework) ··在形成隔離 土广、θ層表面之後，其表面將變得更加堅固，因此，一 般針對錫球的重I流程將不會損壞封裝的表面。 本發明由剖面圖之觀點來看提供了 一種夾層姓構 t—h S加㈣，根據本發明的半導體元件的機^性 為.上層具有軟質/硬性的特性並具有玻璃纖維於其中，·中 間層具有彈性/延展性/軟性的特性（增層）；而下層則且有硬 質/塑性/硬性的特性（晶粒/基底）。上述夾層結構可在埶機 械應力測試中提供更佳的可靠度。 本發明以較佳實施例說明如上，然其並非用以限定本 發明所主張之專利權利範圍。其專利保護範圍當視後附之 申凊專利範圍及其等同領域而定。凡熟悉此領域之技藝 者’在不脫離本專利精神或範_，所作之更動或潤飾， 均屬於本發明所揭示精神下所完成之等效改變或設計，且 應包含在下述之申請專利範圍内。 【圖式簡單說明】 第一 a圖及第一 組件之剖面圖； 圖係為根據習知技術之半導體晶粒 14 200917441 導體晶粒組件之實施例 第二圖係為根據本發明之 的剖面圖； 干 第三圖係為根據本發明之一丰 的剖面圖； f 導體 晶粒組件之實施例 第四圖係為根據本發明之一丰 的剖面圖； + 導體 晶粒組件之實施例 導體晶粒組件之實施例 第五圓係為根據本發明之— 的剖面圖； + 第六a圖至第六c圖係 組件之實_的剖_ ;根據本發明之—半導體晶粒 半導體晶粒組件架設於 第七圖係為根據本發明之 母板上之實施例的剖面圖。 【主要元件符號說明】 102微電子晶粒 112封裝材料 118介電材料層 124導電佈線 126第二介電層 13 2通孔 134金屬塾 136第三介電層 138焊錫凸塊 200半導體元件 201基底 202連接塾 203晶粒塾 204純化層 205晶粒 206球下金屬層 207重佈層 208焊錫凸塊 209核心膠 210凸塊強化轴環 211黏著材料 215互連結構 15 200917441 216增層架構 219球下金屬層 225導電球/導電凸塊 3〇〇隔離基座/隔離罩 302凸塊開口 304黏著層 400基底 402凹槽 502重佈層 504晶粒塾 6 0 0晶粒 602核心膠 604導電層 606晶粒塾 608球下金屬層 . 612介電層 614 上層 616 錫球 618 隔離罩 619 球形開口 620 焊錫金屬墊 621 黏著層 700 母板/印刷電路板 702 電路佈線 704 隔離基座/隔離罩 706 核心膠 708 晶粒 710 硬式基底 714 錫球/焊錫凸塊 716 增層 718 黏著層 16

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  1. 200917441 十、申請專利範圍： 1. 一種用於半導體晶粒封裝之互連結構，包含. -增層，該增層具有重佈層形成於其中，該增層係 於一晶粒上，而該晶粒具有晶粒签形成於其上方，= 該重佈層係耦合至該晶粒墊； 一 τ 座，其具有凸塊開"附著於該增層上方以露出 §亥增層内之錫球墊；及 :二::：肉配置於該隔離基座之該凸塊開口中，並附 者於该增層内之該錫球墊上。 2.如請求項1所述之用於半導曰 句会一抹™ 千㈣曰曰粒封裝之互連結構，更 '孟屬層結構形成於該導電錫球墊上方。 3·如請求項2所述之料半導體晶 令該球下金屬層係附著於該凸塊開口之側壁;J:構其 4.=Γ所述之用於半導體晶粒封裝之互連結構 中§亥重佈層#由人h » « /、 '、θ S銅治、〉賤鑛金屬及電 (Cu/Ni/Au)所形成。 ㉟及電鍍銅/鎳/金 之互連結構，其 FR5、Π、有機 5.如咕求項1所述之用於半導體晶粒封裝 中該隔離基座係由環氧類樹脂、_、 材料或BT所形成。 17 200917441 6 ·如請求項$所、中 、所达之用於半導體晶粒封裝之互連姓 中心離基料含坡_維於其中。連、、口構’其 I:求項1所述之用於半導體晶粒封裝之互連姓構承 包含—黏著層於該隔離基座下。 連、、，口構’更 8·如巧求項1所述之用於半導體Θ粒#驻 ㈣佈層係設定為扇=):互連結構’其 中今重=所述之用於半導體晶粒封裝之互連結構，並 佈層係設定為扇出（擴散）式（fan-out)架構。” 構，更 1〇‘如請求項1所述之心半導體晶粒封|之互連 包含—基底形成於該晶粒下。 包 12,一種形成一用於半導體 含： 晶粒封裝之互連結構的方法 '^區域上方，其 形成增層於一晶粒或晶圓（或面板）之核, 中該增層包含重佈層形成於其中； 用以露出焊錫金屬墊； 離基座於該增層上，並露 至少於增層之上層開出開口， 附著一具有凸塊開口樣式之隔 18 200917441 出δ玄焊锡金屬整；及 將焊錫凸塊配置於該隔離基座之該凸塊開口中並附著 於该增層之該焊錫金屬墊上。 於半導體晶粒封裝之互連 球下金屬層於該焊錫金屬 13.如請求項12所述之形成一用 結構的方法，更包含一形成一 墊上方之步驟。 14.^請求項13所述之形成-用於半導體晶粒封襄之互連 結構的方法’其中該球下金屬層係附著於該凸塊開口之 側壁上。 15=凊求項12所述之形成―用於半導體晶粒封裝之互連 結構的方法，其中該重佈層係由層合銅箔、濺鍍金屬及 電鑛鋼/鎳/金（Cu/Ni/Au)所形成。 ，屬及 16=明求項12所述之形成—用於半導體晶粒封|之互連 、”。構的方法，其中該隔離基座係由環氧類樹脂、FR4、 FR5 PI、有機材料或Βτ所形成。 ·=咕求項16所述之形成一用於半導體晶粒封裴之互連 的方法’其中該隔離基座包含玻璃纖維於其中。 18.如晴求項12所述之形成―用於半導體晶粒封|之互連 19 200917441 結構的方法，更包含一黏著層於該隔離基座下。 19_如請求項12所述之形成—用於半導體晶粒封裝之互連 結構的方法，其中該重佈層係設定為扇入式或扇出⑽ 散）式架構。 ' 20. 如請求〶12所述之形成—用於半導體 結構的方、本φ ^ 5 丁裝之互連 '’更I s —基底形成於該晶粒下。 21. 如請求項12 結構的方法，11形成一用於半導體晶粒封襄之互連 — Cess)之步驟。0 —實行紅外線回焊製程(IR — \ 20
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