TW200913075A - Method for manufacturing semiconductor device and display device - Google Patents

Method for manufacturing semiconductor device and display device Download PDF

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Publication number
TW200913075A
TW200913075A TW097119418A TW97119418A TW200913075A TW 200913075 A TW200913075 A TW 200913075A TW 097119418 A TW097119418 A TW 097119418A TW 97119418 A TW97119418 A TW 97119418A TW 200913075 A TW200913075 A TW 200913075A
Authority
TW
Taiwan
Prior art keywords
semiconductor film
film
display device
electrode
microcrystalline semiconductor
Prior art date
Application number
TW097119418A
Other languages
Chinese (zh)
Other versions
TWI479572B (en
Inventor
Shunpei Yamazaki
Original Assignee
Semiconductor Energy Lab
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Publication date
Application filed by Semiconductor Energy Lab filed Critical Semiconductor Energy Lab
Publication of TW200913075A publication Critical patent/TW200913075A/en
Application granted granted Critical
Publication of TWI479572B publication Critical patent/TWI479572B/en

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Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/511—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using microwave discharges
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/24—Deposition of silicon only
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45563—Gas nozzles
    • C23C16/45574—Nozzles for more than one gas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32192—Microwave generated discharge
    • H01J37/32211—Means for coupling power to the plasma
    • H01J37/32229—Waveguides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32192—Microwave generated discharge
    • H01J37/32211—Means for coupling power to the plasma
    • H01J37/32238—Windows
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/3244—Gas supply means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Analytical Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

It is an object to provide a method for manufacturing a display device suitable for mass production without complicating a manufacturing process of a thin film transistor. A microcrystalline semiconductor film is formed by use of a microwave plasma CVD apparatus with a frequency of greater than or equal to 1 GHz using silicon hydride or silicon halide as a source gas, and a thin film transistor using the microcrystalline semiconductor film and a display element connected to the thin film transistor are formed. Since plasma which is generated using microwaves with a frequency of greater than or equal to 1 GHz has high electron density, silicon hydride or silicon halide which is a source gas can be easily dissociated, so that mass productivity of the display device can be improved.

Description

200913075 九、發明說明 【發明所屬之技術領域】 本發明關於顯示裝置’其至少於像素部中包含薄膜電 晶體。 【先前技術】 近年來’藉由使用形成於具有絕緣表面的基底上的半 導體薄膜（厚度大約爲幾nm至幾百nm)來構成薄膜電晶 體的技術正受到關注。薄膜電晶體在如IC和電光學裝置 的電子裝置中獲得了廣泛應用，特別地，正在加快開發作 爲圖像顯示裝置的開關元件的薄膜電晶體。 使用非晶半導體膜的薄膜電晶體、使用多晶半導體膜 的薄膜電晶體等用作圖像顯示裝置的開關元件。 另外，使用微晶半導體膜的薄膜電晶體用作圖像顯示 裝置的開關元件（專利文件1以及專利文件2 )。 [專利文件1 ]日本專利申請公開 H e i 4 - 2 4 2 7 2 4號公 報 [專利文件2]日本專利申請公開 20〇5-4983 2號公報 使用多晶半導體膜的薄膜電晶體具有如下優點：與使 用非晶半導體膜的薄膜電晶體相比，其遷移度高2位數以 上；可以在同一個基底上集成地形成半導體顯示裝置的像 素部和其附近的驅動電路。然而，與使用非晶半導體膜時 相比，由於半導體膜的結晶化其製程複雜化’所以有降低 成品率且提高成本的缺點。 -4- 200913075 【發明內容】 鑒於上述問題，本發明的目的 體的製程複雜化而能夠批量生産的 微晶半導體膜（也被稱爲半結 導體膜不同，可以作爲微晶半導體 具體而言，可以藉由以氫化矽或鹵 1GHz以上的頻率的微波電漿CVD 膜。藉由使用上述方法製造的微晶 導體中含有 〇.5nm至 20nm的晶 此，與使用多晶半導體膜時不同， 需要結晶化的製程。可以減少在製 數，而提高顯示裝置的成品率，且 使用1 GHz以上的頻率的微波的電 可以容易分解原料氣體的氫化矽或 MHz至幾百MHz的頻率的微波電| 使用1 GHz以上的頻率的微波電漿 造微晶半導體膜，而可以提高成膜 顯不裝置的批量生産性。 另外’藉由使用微晶半導 (TFT )，而且將該薄膜晶體管用 路製造顯示裝置。使用微晶半導體 度爲 2cm2/V.sec 至 10cm2/V_sec， 導體膜的薄膜電晶體的2倍至2 0 在於提供不使薄膜電晶 顯示裝置的製造方法。 晶半導體膜）與多晶半 膜在基底上直接形成。 化矽爲原料氣體且使用 裝置來形成微晶半導體 半導體膜包括在非晶半 粒的微晶半導體膜。因 在形成半導體膜之後不 造薄膜電晶體時的製程 抑制製造成本。另外， 漿的電子密度高，因此 鹵化矽。因此，與幾十 褒CVD裝置相比，藉由 CVD裝置，可以容易製 速度。由此，可以提高 體膜製造薄膜電晶體 於像素部、以及驅動電 膜的薄膜電晶體的遷移 該遷移度是使用非晶半 倍的遷移度，因此可以 -5- 200913075 在與像素部同一個基底上集成地形成驅動電路的一部分或 整體，來形成系統面板（system-on-panel)。 注意，在本發明中，將微晶半導體膜至少使用於溝道 形成區域即可。 另外，作爲顯示裝置包括發光裝置或液晶顯示裝置。 發光裝置包括發光元件，並且液晶顯示裝置包括液晶元 件。發光元件其範疇內包括由電流或電壓控制亮度的元 件，具體而言，包括無機EL ( Electro Luminescence)、 有機 EL、或使用於 FED (Field Emission Display，即場 致發射顯示器）的電子源元件（electron source element) (電子發射元件）等。 另外，顯示裝置包括顯示元件被密封的狀態的面板、 該面板安裝有包括控制器的1C等的狀態的模組。而且本 發明涉及相當於在製造該發光裝置的製程中完成顯示元件 之前的一個方式的元件基底，該元件基底在多個像素中分 別具備對發光元件供給電流的方式。具體而言，元件基底 既可以是僅形成顯示元件的像素電極的狀態’又可以是在 形成成爲像素電極的導電膜之後且藉由蝕刻形成像素電極 之前的狀態，無論是任何狀態都可以。 注意，本說明書中的顯示裝置意味著圖像顯示裝置、 發光裝置、或光源（包括照明裝置）。顯示裝置還包括在 發光裝置安裝有連接器諸如FPC (柔性印刷電路）、TAB (載帶自動鍵合）帶或TCP (帶載封裝）的模組；印刷線 路板設置到TAB帶或TCP端部的模組；1C (積體電路） 200913075 藉由COG (玻璃上晶片）方式直接安裝在發光元件的模 組。 本發明藉由使用1GHz以上的頻率的微波電獎CVD裝 置可以提高微晶半導體膜的成膜速度’而可以提高使用該 微晶半導體膜的薄膜電晶體的顯示裝置的大量生産性。 另外，可以減少成膜之後的半導體膜的結晶化的製 程，可以不使薄膜電晶體的製程複雜化’而實現顯示裝置 的系統面板化。 【實施方式】 下面，將參照附圖說明本發明的實施方式。但是，本 發明可以藉由多種不同的方式來實施，所屬技術領域的普 通人員可以很容易地理解一個事實就是其形式及詳細內容 在不脫離本發明的宗旨及其範圍下可以被變換爲各種各樣 的方式。因此，本發明不應該被解釋爲僅限定在本實施方 式所記載的內容中。 實施方式1 對本發明的顯示裝置的製造方法進行說明。首先，作 爲顯示裝置的一個方式，使用發光裝置進行說明。在圖 1A至1C、圖2A至2C、圖3A至3C中表示用於驅動電路 的薄膜電晶體的截面圖、以及用於像素部的薄膜電晶體的 截面圖。注意，η型使用微晶半導體膜的薄膜電晶體的遷 移度比Ρ型闻，因此η型薄膜電晶體更適合用於驅動電 200913075 路。在本發明中，在使用具有η型及p型中的任一極性的 薄膜電晶體的情況下，優選使形成在同一個基底上的薄膜 電晶體的極性一致，以抑制製程數。 如圖1A所示，在基底5 0上形成閘電極5 1、閘電極 52。基底50可以使用藉由熔化方法或浮發方法（float method )製造的無城玻璃基底例如鋇硼矽酸鹽玻璃、鋁硼 矽酸鹽玻璃、鋁矽酸鹽玻璃等、或陶瓷基底，還可以使用 具有可承受本製造製程處理溫度的耐熱性的塑膠基底等。 此外，還可以使用在不銹鋼合金等金屬基底表面上設置絕 緣層的基底。基底 50的尺寸可以採用 320mmx400mm、 3 7 0 m m X 4 7 0 m m、550mmx650mm、600mmx720mm、6 8 0mm x 8 8 0mm、730mm x 920mm、lOOOmmx 1 200mm、1100mm x 1 25 0mm、1 1 5 0 m m x 1 3 0 0 m m、1 5 0 0 m m x 1 8 0 0 m m、1 9 0 0 mm x 2 2 0 0mm、2160mm x 2460mm、2400mm x 2800mm、或者 2 8 5 0 m m x 3 0 5 0 m m 等 ° 使用鈦、鉬、鉻、钽、鎢、鋁等金屬材料或它們的合 金材料來形成閘電極5 1、閘電極5 2。可以藉由濺射法或 真空沈積法在基底50上形成導電膜，藉由光刻技術或噴 墨法在該導電膜上形成光罩，使用該光罩鈾刻導電膜來形 成閘電極5 1、閘電極5 2。另外，也可以使用銀、金、銅 等導電奈米膏藉由噴墨法噴射而焙燒來形成閘電極51、閘 電極5 2。注意’爲了提高閘電極5 1、閘電極5 2的緊密 性’可以在基底5 0和閘電極5丨、閘電極5 2之間設置上述 金屬材料的氮化物膜。 -8- 200913075 注意，在閘電極5 1、閘電極5 2上形成半導體膜或佈 線，因此其端部優選加工爲錐形形狀’以便防止斷開。此 外，雖然未圖示，但是藉由形成閘電極的製程也可以同時 形成連接到閘電極的佈線。 其次，如圖1B所示，在閘電極5 1、閘電極5 2上按 順序形成用作閘極絕緣膜的絕緣膜5 3 (下面稱爲絕緣膜 53)、微晶半導體膜54、以及添加有賦予一導電型的雜質 元素的半導體膜55(下面稱爲半導體膜55)。注意，至 少連續形成絕緣膜5 3及微晶半導體膜5 4是優選的。進 而，連續形成絕緣膜53、微晶半導體膜54、以及半導體 膜5 5是優選的。藉由在不接觸大氣的狀態下至少連續形 成絕緣膜53及微晶半導體膜54，可以形成各個疊層介面 而不被大氣成分及懸浮在大氣中的污染雜質元素污染，因 此可以減少薄膜電晶體特性的不均勻。 絕緣膜5 3可以藉由CVD法或濺射法等，使用氧化矽 膜、氮化矽膜、氧氮化矽膜、或氮氧化矽膜的單層或疊層 而形成。另外，可以從基底一側按順序層疊氧化砂膜或氧 氮化矽膜與氮化矽膜或氮氧化矽膜而形成絕緣膜5 3。另 外，還可以從基底一側按順序層疊氮化矽膜或氮氧化矽 膜、氧化矽膜或氧氮化矽膜、及氮化矽膜或氮氧化規膜而 形成絕緣膜5 3。進而，藉由使用1 G Η z以上的頻率的微波 電漿CVD裝置形成絕緣膜5 3是優選的。使用微波電漿 CVD裝置形成的氧氮化矽膜的耐壓性高且可以提高之後所 形成的薄膜電晶體的可靠性。 -9- 200913075 在此，氧氮化矽膜是氧的含量多於氮’當使用盧瑟福 背散射光譜學法（RBS:Rutherford Backscattering Spectrometry )以及氣目丨J方散射法（HFS:Hydrogen Forward Scattering)測量時，作爲濃度範圍，其包含50 原子。/。至7 0原子％的氧、〇 · 5原子％至1 5原子％的氮' 2 5 原子％至3 5原子％的S i、0 . 1原子％至1 0原子％的氫。另 外，氮氧化砂膜是作爲其組成’氛的含量多於氧’當使用 RBS以及HFS測量時，作爲濃度範圍，其包含5原子％至 3 0原子％的氧、2 0原子％至5 5原子％的氮、2 5原子％至 3 5原子％的S i、1 0原子％至3 0原子％的氫。但是，在以 構成氧氮化矽或氮氧化矽的原子的總計設定爲1 〇〇原子％ 的情況下，氮、氧、s i以及氫的含有比率包括於上述範圍 內。 微晶半導體膜54是指具有非晶結構和結晶（包括單 晶、多晶）結構之間的中間結構的半導體的膜。該半導體 是具有在自由能方面上很穩定的第三狀態的半導體，並且 是具有短程有序且晶格畸變的結晶半導體，可以以其粒徑 爲0.5 nm至2 Onm使它分散存在於非晶半導體中。此外， 導入至少1原子％或其以上的氫或鹵素，以便終結懸空 鍵。再者，藉由將氦、氬、氪、氖等的稀有氣體元素包含 在微晶半導體膜中而進一步促進晶格畸變，可以獲得穩定 性提高的優質的微晶半導體膜。關於這種微晶半導體膜的 記述例如在美國專利文件4，4 0 9，1 3 4號中公開。 藉由使用頻率爲1GHz以上，優選爲2.45GHz以上， -10- 200913075 更優選爲8.3 GHz以上的微波的微波電漿CVD裝置可以形 成該微晶半導體膜54。代表地’可以使用SiH4、Si2H6等 的氫化矽形成。另外’也可以使用SiCl4、SiF4等的鹵化 矽形成。另外，可以氫化矽或鹵化矽藉由使用氫；選自 氦、Μ、氪、氣中的一種或多種稀有氣體元素；氫和選自 氦、氬、氪、氖中的一種或多種稀有氣體元素進行稀釋， 而形成微晶半導體膜。 以lnm以上且3 00nm以下，優選爲5nm以上且200 nm以下的膜厚度形成微晶半導體膜54。 也可以將CH4、C2H6等的碳化物氣體、或者GeH4、 G e F 4等的鍺化氣體混入在氫化砂或鹵化砂中，以將能帶寬 度調節爲1.5eV至2.4eV或者〇.9eV至l.leV。 另外，當以控制價電子爲目的的雜質元素未有意添加 時，微晶半導體膜5 4呈現較弱的η型導電性，因此對於 用作薄膜電晶體的溝道形成區域的微晶半導體膜，在成膜 同時或成膜之後添加賦予ρ型的雜質元素，來可以控制閾 値。作爲賦予ρ型的雜質元素以硼爲代表，將B2H6、BF3 等雜質氣體以lppm至lOOOppm，優選以1??01至i〇〇ppm 混入到氫化矽或鹵化矽即可。進而，優選地是，將硼的濃 度例如設定爲 lxl〇14atoms/cm3 至 6xlOl6atoms/cm3。 另外’優選地是將微晶半導體膜的氧濃度設定爲i χ 1019at〇mS/cm3以下，並且將氮及碳濃度分別設定爲1χ 1019atoms/cm3 以下。 關於半導體膜5 5 ’在形成η溝道型薄膜電晶體的情況 -11 - 200913075 下，作爲代表的雜質元素添加磷，並且將ph3等雜質氣體 添加到氫化矽或鹵化矽即可。另外，在形成p溝道型薄膜 電晶體的情況下，作爲代表的雜質元素添加硼，並且將 B2H6等雜質氣體添加到氫化矽或鹵化矽即可。可以由微晶 半導體膜、或非晶半導體膜形成半導體膜5 5。 在此，使用圖6示出可以從絕緣膜5 3到半導體膜5 5 連續形成的微波電漿CVD裝置。圖6是示出微波電漿 CVD裝置的俯視截面圖的示意圖。公共腔1 120夾著閘閥 1122至1127連接有裝載/卸載（L/UL ; Load/UnLoad)室 1 1 1〇、裝載/卸載（L/UL )室1 1 15、以及反應室（1 ) 1 1 1 1 至反應室（4) 1114。基底1130嵌入安裝於設置在裝載/ 卸載（L/UL)室1110、裝載/卸載（L/UL)室1115的匣 (cassette) 1128、匣1129，而利用公共腔1120的搬送機 構1121搬送到各反應室（1)至反應室（4)。 在每個反應室（1)至反應室（4)中，連續層疊絕緣 膜53、微晶半導體膜54、以及半導體膜55。在此情況 下，藉由原料氣體的交換，可以連續層疊多個不同種類的 膜。或者，在反應室（1)及反應室（3)中連續層疊絕緣 膜53及微晶半導體膜54，並且在反應室（2)及反應室 (4)中形成半導體膜55。藉由單獨地形成半導體膜55, 可以防止殘留在小室（chamber )內的雜質元素混入到其 他膜。 如此，藉由使用連接有多個小室的微波電漿CVD裝 置’可以同時形成絕緣膜53、微晶半導體膜54、以及半 -12- 200913075 導體膜5 5，因此可以提高批量生産性。另外，即 反應室進行維護或清洗，在其他反應室中也可以 處理，能夠高功率地成膜。另外，可以形成各個 而不被大氣成分及懸浮在大氣中的污染雜質元素 此可以減少薄膜電晶體特性的不均勻。 另外，在由氧化矽膜或氧氮化矽膜與氮化矽 化矽膜的兩層形成閘極絕緣膜5 3的情況下，可 室（1 )中形成絕緣膜53的氧化矽膜或氧氮化砂 應室（2 )中形成絕緣膜53的氮化矽膜或氮氧化 反應室（3)中形成微晶半導體膜54，在反應室 成半導體膜55。此時，優選由與成膜的膜相同種 上每個反應室的內側。當使用這種結構的微波1 裝置時，可以在每個反應室中形成一個種類的膜 觸大氣的方式連續形成，因此不被之前成膜的膜 或懸浮在大氣中的雜質元素污染，可以形成每 面。 注意，雖然圖6所示的微波電漿CVD裝置 個裝載/卸載（L/UL )室，但是也可以設置有 外’也可以在微波電漿CVD裝置中設置備用室 備用室中預熱基底，在反應室中可以縮短直到成 時間，因此可以提高生産率。 圖7是詳細說明這種微波電漿CVD裝置中 應室的結構的圖。微波電漿CVD裝置的反應室 理容器180、設置在處理容器180內的用於佈置 1使某一個 進行成膜 疊層介面 污染，因 膜或氮氧 以在反應 膜，在反 矽膜，在 (4 )中形 類的膜塗 電槳CVD 且以不接 的殘留物 個疊層介 設置有多 一個。另 。藉由在 膜的加熱 的一個反 設置有處 基底1 130 -13- 200913075 的支撐台181、將氣體引導於處理容器180內的氣 部1 8 2、連接到用於排出處理容器1 8 0內的氣體的 的排氣口 1 8 3、供給用於發生電漿的微波的微波產 1 8 4、從微波供給部到處理容器1 8 0引導微波的 185、接觸於波導管185且具有開口部187a的頂板 由安裝附件1 8 8設置在頂板1 8 7的多個電介質板] 外，在基底Π 3 0及電介質板1 8 6之間設置流過非 體的氣體管197 (下面稱爲氣體管197)、以及流 氣體的氣體管198(下面稱爲氣體管198)。氣體 和氣體管1 98連接到氣體供給部1 82。具體而言， 197通過閥門195及質量流量控制器193連接到非 體供給源1 9 1。另外，流過原料氣體的氣體管1 98 門1 96及質量流量控制器1 94連接到原料氣體 1 92。另外，藉由安裝用於支撐台1 8 1之溫度控制器 可以控制基底 Π 3 0的溫度。另外，也可以採用 構，即將高頻電源連接到支撐台1 8 1，而由從高頻 出的交流的電力將預定的偏壓施加到支撐台1 8 1。 氣體供給部182及微波產生單元184設置在反應容 部。 微波產生單元184供給頻率爲1GHz以上， 2.45GHz以上，更優選爲8_3GHz以上的微波。注 本發明中，藉由具有多個微波產生單元丨84，可以 定且大面積的電漿。因此’即使在使用一邊超過 的基底，尤其是一邊超過1 000mm的大面積基底 體供給 真空泵 生單元 波導管 187、 86。另 原料氣 過原料 管 197 氣體管 原料氣 通過閥 供給源 f 199 > 如下結 電源輸 注意’ 器的外 優選爲 意，在 生成穩 6 0 0mm 的情況 -14- 200913075 下，也可以形成均勻性高的膜，並且可以提高成膜速度。 處理容器180、以及頂板187由金屬如含有鋁的合金 形成，該金屬是其表面由礬土、氧化矽、或氟樹脂的絕緣 膜覆蓋的。此外，安裝附件1 8 8由金屬如含有鋁的合金形 成。 以緊密接觸於天板1 87的開口部的方式設置電介質板 186。在微波產生單元184中發生的微波經過波導管185 及頂板1 87的開口部1 87a傳播到電介質板1 86 ’而透過電 介質板1 8 6發射到處理容器內。由於發射到處理容器內的 微波的電場能量，非原料氣體電槳化。因爲在電介質板 186表面上該電漿200的密度更高，所以可以減少對於基 底1 1 3 0的損傷。此外，藉由設置多個電介質板1 8 6，可以 發生且維持均勻且大面積的電漿。電介質板186也可以由 陶瓷如藍寶石、石英玻璃、礬土、氧化矽、氮化矽等形 成。注意，電介質板1 8 6可以在電漿2 0 0發生一側形成有 凹部1 8 9。由於該凹部1 8 9，可以生成穩定的電漿。藉由 設置多個電介質板186，即使在使用一邊超過600mm的基 底，尤其是一邊超過1 000mm的大面積基底的情況下，也 可以形成均勻性高的膜，並且可以提高成膜速度。 氣體管197和氣體管198彼此交叉而設置。氣體管 197的噴出口設置在電介質板186 —側，且流過原料氣體 的氣體管198的噴出口設置在基底1130 —側。通過非原 料氣體噴出在電介質板186 —側，可以在電介質板186表 面上不形成膜且可以發生電漿200。另外，因爲氣體管 -15- 200913075 1 9 8的噴出口設置在基底1 1 3 0 —側’可以在進一步接近於 基底1 1 3 0的位置噴出原料氣體，所以可以提高成膜速 度。氣體管197、氣體管198由陶瓷如礬土、氮化鋁等形 成。因爲陶瓷的微波的透過率高，所以當由陶瓷形成氣體 管197、氣體管198，即使在電介質板186的正下方設置 氣體管，電場也不擾亂而可以使電漿的分佈均勻。 下面，對成膜處理進行說明。這些成膜處理根據其目 的選擇從氣體供給部1 8 2供給的氣體即可。 首先，對氧氮化矽膜的成膜處理方法將參照圖8及圖 7進行說明。首先，從圖8中的階段S1 70開始成膜處 理，在階段S 1 7 1中控制基底1 1 3 0的溫度。基底1 1 3 0的 溫度爲室溫或由溫度控制器199將基底1130加熱爲100°C 至5 5 0 °C。在階段S 1 7 2中使處理容器1 8 0內變成真空狀 態，並且導入氯、氬、氙、氪等中的稀有氣體的任一種以 上及氧作爲用於電漿發生的氣體。藉由與稀有氣體一起將 氧導入到處理容器180內，可以容易發火電漿。注意，基 底1 1 3 0和電介質板1 8 6之間的間隔大約爲1 0 mm至2 0 0 mm (優選爲 110mm至 160mm)。其次，在階段 S173 中，將處理容器180內的壓力變爲預定的壓力。處理容器 內的壓力爲IPa至200Pa，優選爲IPa至lOOPa，更優選 爲IPa至40Pa。其次，在階段S174中使微波產生單元 1 84的電源爲導通，微波產生單元1 84將微波供給給波導 管丨85，來在處理容器180內生成電漿。微波產生單元的 輸出爲500W至6000W、優選爲4000W至6000W。當藉由 -16- 200913075 微波的導入進行電漿的激發時，可以低電子溫度（0.7eV 以上且3ev以下，優選爲〇.7eV以上且1.5ev以下）且高 電子密度（1 X 1 0 1 1 atoms/cm3 至 1 χ 1 〇 1 3 atoms/cm3 )的電 漿。其次，在階段S 1 7 5中，從氣體管1 9 8將原料氣體導 入到處理容器180內。具體而言，藉由停止氧的供給而導 入一氧化二氮、稀有氣體、以及氫化矽或鹵化矽作爲原料 氣體，可以在基底1130上形成氧氮化矽膜。其次，在階 段S 1 7 6中，停止原料氣體的供給，且降低處理容器內的 壓力，並且將微波產生單元的電源爲關斷，然後在階段 S 1 7 7中結束成膜製程。 在上述氧氮化矽膜的成膜處理方法中，藉由採用如下 條件可以形成耐壓性高的氧氮化矽膜，即：基底溫度爲 3 0 0 °C至3 5 0 °C ; —氧化二氮的流量爲矽烷的流量的1 〇倍 以上且300倍以下，優選爲50倍以上且200倍以下；使 用2台至6台其功率爲5kW的微波產生單元：處理容器 內的壓力爲10Pa至lOOPa，優選爲10Pa至50Pa;在基底 1130和電介質板186之間的間隔爲110mm至160mm。 其次，對微晶半導體膜54的成膜處理方法說明。首 先，從圖8中的階段S 1 70開始成膜處理，在階段S 1 7 1中 控制基底1130的溫度。基底1130的溫度爲由室溫或溫度 控制器1 9 9將基底1 1 3 0加熱爲1 0 0 °C至5 5 〇t。在階段 S172中使處理容器內變成真空狀態，並且導入氦、氬、 氙、氪等的稀有氣體作爲用於電漿發火的氣體。注意，棊 底1130和電介質板186之間的間隔大約爲10mm至 -17- 200913075 2 0 0mm (優選爲π 〇mm至1 60mm )。其次，在階段s丨73 中，將處理容器180內的壓力變爲預定的壓力。處理容器 內的壓力爲IPa至200Pa’優選爲ipa至i〇〇pa。其次， 在階段S174中使微波產生單元184的電源成爲導通，微 波產生單元1 8 4將微波供給給波導管1 8 5，來在處理容器 180內生成電漿。微波產生單元的輸出功率爲50()w至 6000W、優選爲4000W至6000W。當藉由微波的導入進行 電漿的激發時，可以低電子溫度（0.7eV以上且3ev以 下，優選爲〇.7eV以上且1.5ev以下）且高電子密度（1χ 10" atoms/cm3cnT3 至 lxio13 atorns/cm3)的電槳。其次， 在階段S175中，從氣體管198將原料氣體導入到處理容 器180內。具體而言，藉由導入SiH4、ShH6等氫化矽或 SiH2Cl2、SiHCl3等鹵化矽’來可以形成微晶半導體膜。 或者，藉由導入SiH4、Si2H6等氫化5夕或SiH2Cl2、SiHCl3 等鹵化矽、氫，來可以形成微晶半導體膜。其次，在階段 S 1 7 6中，停止原料氣體的供給，且降低處理容器內的壓 力，並且將微波產生單元的電源成爲關斷，然後在階段 S177中結束成膜製程。 注意，爲了電漿的發火及電漿的維持，當混合氬等的 稀有氣體時’由於稀有氣體的激發種’可以有效地進行原 料氣體的分離及基（radicaI )的形成。 另外，由頻率爲1 GHz以上，優選爲2_45GHz、更優 選爲8.3GHzW上的微波電漿CVD裝置發生的電漿因爲其 電子密度高’並且由原料氣體形成多數基而供給給基底 -18 - 200913075 1130。因此促進在基底上的基的表面反應，可以提高微晶 半導體膜的成膜速度。進而，由多個微波產生單元、以及 多個電介質板構成的微波電漿CVD裝置可以生成穩定且 大面積的電漿。因此，即使在大面積基底上，也可以形成 提高膜質的均勻性的膜並且可以提高批量生産性。 在形成η溝道型薄膜電晶體的情況下，半導體膜5 5 可摻雜磷做爲典型之雜質元素，藉由使用氫化矽或鹵化石夕 及ΡΗ3等包含雜質元素的氣體的電漿CVD法而形成。另 外，在形成Ρ溝道型薄膜電晶體的情況下，作爲代表的雜 質元素添加硼即可，藉由使用氫化矽或鹵化矽及Β2Η6等 雜質元素的電漿CVD法而形成。藉由將磷或硼的濃度設 定爲 lxl019atoms/cm3 至 lxl021atoms/cm3，可以與之後形 成的半導體膜5 5與源電極及汲電極之間實現歐姆接觸。 可以由微晶半導體、或非晶半導體形成半導體膜5 5。以 2nm以上且50nm以下的膜厚度形成半導體膜55。藉由使 添加有賦予一導電型的雜質元素的半導體膜55的膜厚度 薄，可以提高生産率。 另外，也可以藉由使用如圖7所示的1 GHz以上的頻 率的微波電漿CVD裝置’並且使用圖8所示的階段與微 晶半導體膜54同樣地形成半導體膜5 5。在此情況下’在 階段S175中，藉由導入氫化矽或鹵化矽、PH3* B2H6、 以及氫作爲原料氣體，可以形成添加有賦予一導電型的雜 質元素的微晶半導體膜。 其次，在半導體膜55上形成光罩56、光罩57，將微 -19- 200913075 晶半導體膜5 4、半導體膜5 5蝕刻爲島狀而分離形成。其 結果’可以形成如圖1 C所不那樣的微晶半導體膜6 〇、微 晶半導體膜61、以及添加有賦予一導電型的雜質元素的半 導體膜58、添加有賦予一導電型的雜質元素的半導體膜 59(下面稱爲半導體膜58、半導體膜59)。 然後’在半導體膜58、半導體膜59及絕緣膜53上形 成源電極及汲電極62至65。優選使用銘、銅、或添加有 提高耐熱性的元素或防止小丘（hillock )的元素如5夕、 鈦、钕、銃、鉬等的鋁合金來形成源電極及汲電極6 2至 6 5。另外，也可以採用如下疊層結構，即由鈦、鉬、鉬、 鎢、或這些元素的氮化物形成與添加有賦予一導電型的雜 質元素的半導體膜接觸的一側的層，並且在其上形成銘或 鋁合金。進而，也可以採用由鈦、钽、鉬、鎢、或這些元 素的氣化物夾者錦或銘合金的上表面及下表面的疊層結 構。 藉由濺射法或真空沈積法’在半導體膜58、半導體膜 5 9、以及絕緣膜5 3上形成導電膜，在該導電膜上藉由光 刻技術或塗佈法形成光罩，然後使用該光罩蝕刻導電膜來 形成源電極及汲電極62至65。另外，也可以藉由使用 銀、金、銅等導電奈米膏藉由絲網印刷法、噴墨法等噴射 而焙燒來形成源電極及汲電極6 2至6 5。 其次，如圖2 A所示’藉由使用源電極及汲電極6 2至 6 5或未圖示的形成源電極及汲電極6 2至6 5的光罩，鈾刻 半導體膜5 8、半導體膜5 9來形成源極區域及汲極區域66 -20- 200913075 至6 9。另外’在該製程中’因爲不能獲得與用作基底的微 晶半導體膜60、用作基底的微晶半導體膜61的飽刻選擇 比，所以微晶半導體膜60、微晶半導體膜6 1也少許被蝕 刻，而形成用作溝道形成區域的微晶半導體膜7 0、用作溝 道形成區域的微晶半導體膜7 1。 注意，在本實施方式中，源電極及汲電極62至65和 源極區域及汲極區域66至69藉由使用同一抗蝕劑光罩， 並且使用幹蝕刻法蝕刻導電膜及添加有賦予一導電型的雜 質元素的半導體膜而形成。 藉由上述製程’可以形成溝道蝕刻型的薄膜電晶體 7 2、溝道蝕刻型的薄膜電晶體7 3。溝道蝕刻型的薄膜電晶 體的製造製程數目少’而可以降低成本。另外，藉由由微 晶半導體膜構成溝道形成區域，可以獲得2Cm2/V.SeC至 1 0cm2/V · sec的電場效應遷移率。因此，可以將該薄膜晶 體管用作像素部8 9的像素的開關用元件，進而用作形成 掃描線（閘極線）一側的驅動電路8 8的元件。 接下來，如圖2B所示，在薄膜電晶體72、薄膜電晶 體7 3上形成用於溝道形成區域的保護的絕緣膜8 1，在絕 緣膜8 1上作爲優選的方式形成具有接觸孔的平坦化膜 8 2，在平坦化膜8 2上形成在接觸孔中與源電極或汲電極 接觸的像素電極83。 作爲絕緣膜81，可以與絕緣膜5 3相同地形成。注 意，絕緣膜8 1用於防止從懸浮在大氣中的有機物、金屬 物、水蒸氣等污染雜質的浸入，因此優選爲緻密的膜。另 -21 - 200913075 外，藉由將氮化矽膜使用於絕緣膜8 1，可以將在用作溝道 形成區域的微晶半導體膜7 0、用作溝道形成區域的微晶半 導體膜71中的氧濃度設定爲5xl〇19at〇ms/cm3以下，優選 爲 lxl019atoms/cm3 以下。 平坦化膜82優選使用丙烯、聚醯亞胺、聚醯胺等有 機樹脂，或者矽烷聚合物，由絕緣膜形成。 在圖2B中’因爲像素的薄膜電晶體爲n型，所以作 爲像素電極83優選使用陰極材料，與此相反，像素的薄 膜電晶體爲Ρ型時，優選使用陽極材料。具體而言，作爲 陰極材料可以使用功函數小的已知的材料如Ca、Α1、 CaF、MgAg、AlLi 等。 其次’如圖2C所示’在平坦化膜82及像素電極83 的端部上形成隔壁84。隔壁84具有開口部，在該開口部 中露出像素電極83。隔壁84使用有機樹脂膜或無機絕緣 膜而形成。尤其是，藉由使用感光性的材料，在像素電極 上形成開口部，並且以該開口部的側壁具有連續的曲率的 傾斜面的方式形成，可以減少之後形成的發光層8 5的斷 開，這是優選的。 其次’以在隔壁84的開口部中接觸像素電極83的方 式形成發光層85。發光層85既可以由單獨層構成，又可 以由多層的疊層構成。 以覆蓋發光層85的方式形成使用陽極材料的^同電 極8 6。共同電極8 6可以使用具有透光性的導電材料如含 有氧化鎢的銦氧化物、含有氧化鎢的銦鋅氧化物、$胃胃 -22- 200913075 化鈦的銦氧化物、含有氧化鈦的銦錫氧化物、銦錫氧化物 (下面表示爲ITO)、銦鋅氧化物、添加有氧化矽的銦錫 氧化物等。作爲共同電極8 6，上述透明導電膜之外，還可 以使用氮化欽膜或欽膜。在圖2 C中，作爲共同電極8 6使 用ITO。在隔壁84的開口部中，藉由像素電極83、發光 層85、共同電極86彼此重疊，以形成發光元件90。然 後，優選在共同電極86及隔壁84上形成保護膜87，以便 防止氧、氫、水分、二氧化碳等浸入到發光元件90中。 作爲保護膜87，可以形成氮化矽膜、氮氧化矽膜、DLC (Diamond Like Carbon;類金剛石碳）膜等。 進而，實際上當完成圖2C的製程時，爲了不被暴露 於空氣，優選由氣密性高且脫氣少的保護薄膜（層壓薄 膜、紫外線硬化樹脂薄膜等）或覆蓋材料來封裝（密 封）。 注意，雖然圖1A至iC、2A至2C示出具有溝道蝕刻 型的薄膜電晶體的發光裝置的製造方法，但是也可以使用 溝道保護型的薄膜電晶體而形成。對該製造方法，使用圖 3 A至3 C進行說明。 如圖3A所示’在基底50上形成閘電極51、閘電極 52。接下來，在閘電極S1、閘電極52上形成絕緣膜53及 微曰η丰導體膜54使用1GHz以上的頻率的微波電榮CVD 裝置’因此可以容易形成微晶半導體膜54。 接下來，以與閘電極51、閘電極52重疊的方式在微 晶半導體膜54上形成溝道保護膜94 '溝道保護膜95。作 -23- 200913075 化 導 光 有 半 形 半 所 導 用 的 53 刻 極 護 表 電 保 爲溝道保護膜94、溝道保護膜95，使用氮化矽、氮氧 矽、氧化矽、氧氮化矽藉由濺射法、CVD法等在微晶半 體膜54上形成絕緣膜’在該絕緣膜上形成光罩，使用 罩蝕刻絕緣膜而形成。另外，也可以藉由噴射而焙燒含 聚醯亞胺、丙烯、或矽烷的組成物來形成溝道保護膜9 4 溝道保護膜95。 接下來，在溝道保護膜94、溝道保護膜95上形成 導體膜96(下面稱爲半導體膜96)，在半導體膜96上 成光罩97、光罩98。半導體膜96可以與圖1B所示的 導體膜55相同地形成。光罩97、光罩98可以與圖1B 示的光罩5 6、光罩5 7相同地形成。 接下來，藉由使用光罩97、光罩98蝕刻而分離半 體膜96及微晶半導體膜54，來如圖3 B所示那樣形成 作溝道形成區域的微晶半導體膜6 0、用作溝道形成區域 微晶半導體膜61、以及半導體膜58、半導體膜59。 接下來，在半導體膜58、半導體膜59以及絕緣膜 上形成源電極及汲電極62至65。 接下來，藉由以源電極及汲電極6 2至6 5爲光罩蝕 半導體膜5 8、半導體膜5 9，如圖3 C所示那樣，形成源 及汲極區域1 01至1 04。此時，溝道保護膜94、溝道保 膜9 5的一部分被蝕刻。將一部分被蝕刻的溝道保護膜 示爲溝道保護膜105、溝道保護膜106。 藉由上述製程，可以製造具有重疊於閘電極5 1、閘 極52、以及微晶半導體膜60、微晶半導體膜6 1的溝道 -24- 200913075 護膜1 05、溝道保護膜1 06的溝道保護型的薄膜電晶體。 藉由將溝道保護型的薄膜電晶體形成在元件基底上’可以 減少薄膜電晶體的元件特性的不均勻，並且降低關斷電 流。另外，藉由由微晶半導體膜構成溝道形成區域，可以 獲得2cm2/V.sec至10cm2/V.sec的電場效應遷移率。因 此，可以將該薄膜晶體管用作像素部89的像素的開關用 元件，進而用作形成掃描線（閘極線）一側的驅動電路8 8 的元件。 接下來，對發光元件的結構將參照圖4A至4C進行說 明。在此，舉出驅動T F T爲η型的情況作爲一例，對像素 的截面結構進行說明。 爲了提取發光，發光元件的陽極和陰極中的至少一個 是透明的即可。薄膜電晶體及發光元件形成在基底上。存 在具有頂部發射結構、底部發射結構和雙面發射結構的發 光元件，其中頂部發射結構通過與基底相對表面提取發射 的光，其中底部發射結構通過基底一側的表面提取發射的 光，其中雙面發射結構通過基底一側和與基底相對表面的 表面提取發射的光。本發明的像素結構可以應用於具有任 一種發射結構的發光元件。 對具有頂部發射結構的發光元件參照圖4Α進行說 明。 在圖4Α中示出當驅動TFT7001爲η型且從發光元件 7 002發射的光傳輸到陽極7005 —側時的像素的截面圖。 在圖4Α中，發光元件7002的陰極7003和驅動TFT7001 -25- 200913075 電連接，並且在陰極7003上按順序層疊有發光層7004、 陽極7005。陰極7003只要是功函數小且反射光的導電 膜，可以使用已知的材料。例如，優選使用Ca、A1、 CaF、MgAg、AlLi等。發光層7004既可以由單獨層構 成，又可以由多層的疊層構成。在由多層構成的情況下’ 在陰極7003上按順序層疊電子注入層、電子傳輸層、發 光層、空穴傳輸層、空穴注入層。注意，不一定必要設置 所有的這些層。陽極700 5使用透過光的透明導電膜而形 成，例如也可以使用具有透光性的導電膜如含有氧化鎢的 銦氧化物、含有氧化鎢的銦鋅氧化物、含有氧化鈦的銦氧 化物、含有氧化鈦的銦錫氧化物、銦錫氧化物（下面表示 爲ITO )、銦鋅氧化物、添加有氧化矽的銦錫氧化物等。 由陰極7003及陽極7005夾有發光層7004的區域相 當於發光元件7002。在圖4A所示的像素中，如空心箭頭 所示，從發光元件7002發射的光發射到陽極700 5 —側。 接下來，對具有底部發射結構的發光元件將參照圖 4B進行說明。圖4B示出當驅動TFT7011爲η型且從發光 元件7 0 1 2發射的光發射到陰極7 0 1 3 —側時的像素的截面 圖。在圖4Β中，在與驅動TFT701 1電連接的透明導電膜 7017上形成有發光元件7012的陰極7013，在陰極7〇13 上按順序層疊有發光層7014、陽極7015。注意，在陽極 70 1 5具有透光性的情況下，可以形成用於反射光或遮光的 遮光膜7016，以覆蓋陽極7015。與圖4Α相同，陰極 70 1 3只要是功函數小的導電膜，可以使用已知的材料。注 -26- 200913075 意’將其膜厚度設定爲透過光的膜厚度（優選大約爲5nm 至30nm)。例如，可以使用膜厚度爲20nm的A1作爲陰 極7013。而且’與圖4A相同，發光層7014既可以由單 獨層構成，又可以由多層的疊層構成。陽極7015不必要 透過光，但是與圖4A相同，可以使用透明導電膜而形 成。遮光膜7016可以使用如反射光的金屬等，但是不局 限於金屬膜。例如，也可以使用添加黑色顔料的樹脂等。 由陰極7013及陽極7015夾有發光層7014的區域相 當於發光元件7 0 1 2。在圖4 B所示的像素中，如空心箭頭 所示’從發光元件7 0 1 2發射的光發射到陰極7 0 1 3 —側。 其次，對具有雙面發射結構的發光元件，使用圖4C 進行說明。在圖4C中，在與驅動TFT7021電連接的透明 導電膜7027上形成有發光元件7022的陰極7023，在陰極 7〇23上按順序層疊有發光層7024、陽極7025。與圖4A 相同，陰極7023只要是功函數小的導電膜，可以使用已 知的材料。注意，將其膜厚度設定爲透過光的膜厚度。例 如，可以使用膜厚度爲20nm的A1作爲陰極7023。而 且，與圖4A相同，發光層7024既可以由單獨層構成，又 可以由多層的疊層構成。與圖4A相同，陽極7025可以使 用透過光的透明導電膜而形成。 陰極7023 '發光層7024、陽極7025彼此重疊的區域 相當於發光元件7 0 2 2。在圖4 C所示的像素中，如空心箭 頭所示，從發光元件7 0 2 2發射的光發射到陽極7 0 2 5 —側 和陰極7023 —側的雙方》 -27- 200913075 注意，雖然在本實施方式中示出驅動TFT和發光元 電連接的一例，但是也可以採用在驅動TFT和發光元件 間連接有控制流到發光元件的電流的電流控制TFT的 構。 注意，本實施方式所示的發光裝置不限於圖4A至 所示的結構，而基於本發明的技術思想可以實現各種各 的變形。 接下來，作爲顯示裝置對液晶顯示裝置的製造製程 用圖1A至1C、2A至2C、以及圖5進行說明。 經過圖1A至1 C以及圖2 A的製程，如圖5所示， 基底120上形成薄膜電晶體72、薄膜電晶體73。接 來，在薄膜電晶體72、薄膜電晶體73上形成用作保護 的絕緣膜8 1、平坦化膜82、與薄膜電晶體72、薄膜電 體7 3的源電極及汲電極6 2至6 5分別連接的佈線1 2 2 1 2 5。接下來’在平坦化膜8 2上形成連接到佈線丨2 5的 素電極1 3 0。 雖然在此示出由透明導電膜形成像素電極130來製 透過型的液晶顯示裝置的一例，但是本發明的液晶顯示 置不局限於該結構。藉由使用容易反射光的導電膜形成 素電極’可以形成反射型的液晶顯示裝置。在此情況下 可以將佈線1 25的一部分用作像素電極。 接下來，在佈線1 2 4或佈線1 2 5上由絕緣膜形成隔 物1 3 3。注意’在圖5中示出在佈線丨2 4上使用氧化砂 成隔離物1 3 3的一例。無論先形成像素電極丨3 〇還是隔 件 之 結 4C 樣 使 在 下 膜 晶 至 像 造 裝 像 離 形 離 -28 - 200913075 物1 3 3都可以。另外，作爲隔離物1 3 3雖然在此使用柱狀 隔離物，但是也可以散佈珠狀隔離物。 而且，以覆蓋佈線1 22至1 2 5、隔離物1 3 3、像素電 極1 3 0的方式形成定向膜1 3 1，而進行硏磨處理。 接下來，形成爲了密封液晶的密封劑162。另一方 面，準備形成有使用透明導電膜的相對電極1 4 1和進行了 硏磨處理的定向膜142的第二基底140。而且，在由密封 劑1 6 2圍繞的區域中滴落液晶1 6 1，使用密封劑1 6 2以相 對電極1 4 1和像素電極1 3 0相對的方式貼合第二基底 1 4 〇。注意，也可以在密封劑1 6 2中混合塡料。 注意’也可以在第二基底140上形成密封劑162，在 由密封劑1 6 2圍繞的區域中滴落液晶1 6 1之後，使用密封 劑162貼合第一基底120和第二基底140。 另外，雖然上述的液晶的注入使用分配器方式（滴落 方式），但是本發明不局限於此。也可以使用在由密封劑 162貼合第一基底120及第二基底140之後利用毛細現象 注入液晶的浸漬方式（汲上方式）。 另外’也可以在第一基底120或第二基底丨40上形成 有顔色爐光片、用来防止旋错（disclination)的屏蔽膜 (黑矩阵）等。另外’在與第一基底120的形成有薄膜電 晶體的面相反的面貼合偏振片15〇，在與第二基底〗4〇的 形成有相對電極1 4 1的面相反的面貼合偏振片1 5 j。 用於像素電極130或相對電極141的透明導電膜可以 適當地使用與圖2 B所示的像素電極相同的材料。藉由使 -29- 200913075 液晶1 6 1夾於像素電極1 3 0相對電極1 4 1之間，形成液晶 元件1 3 2。 藉由上述製程，可以製造顯示裝置。另外，由1GHz 以上的微波電槳CVD裝置發生的電漿因爲電子密度高， 所以藉由使用該裝置，可以提高微晶半導體膜的成膜速 度。因此，可以提高具有使用微晶半導體膜的薄膜電晶體 的顯示裝置的批量生産性。另外，由多個微波產生單元、 以及多個電介質板構成的微波電漿CVD裝置可以生成穩 定且大面積的電漿。因此，可以藉由使用大面積基底製造 顯示裝置，而提高批量生産性。 實施方式2 在本實施方式中，將使用圖1 2說明實施方式1所示 的薄膜電晶體的其他形狀。 如圖1 2所示，本實施方式所示的薄膜電晶體7 2、薄 膜電晶體7 3，其特徵在於源電極6 2 a、源電極6 4 a的端部 和源極區域6 6、源極區域6 8的端部不一致。另外’其特 徵還在於汲電極6 3 a、汲電極6 5 a的端部和汲極區域6 7、 汲極區域6 9的端部不一致。 在本實施方式中’藉由使用同一個抗蝕劑光罩，濕蝕 刻導電膜形成源電極及汲電極6 2 a至6 5 a ’並且幹蝕刻添 加有賦予一導電型的雜質元素的半導體膜形成源極區域及 汲極區域66至69°藉由本實施方式中之源電極及汲電極 62a至65a的結構，因爲相對的電極的間隔變大，所以可 -30- 200913075 以減少在源電極及汲電極之間的短路’因此可 率。 實施方式3 接下來，下面示出本發明的顯示裝置的一 示面板的結構。 在圖9中示出另外僅形成信號線驅動電路 在基底6011上形成的像素部6012連接的顯 式。像素部60 1 2及掃描線驅動電路60 1 4使用 導體膜的薄膜電晶體而形成。藉由由其遷移度 晶半導體膜的薄膜電晶體的遷移度的薄膜電晶 線驅動電路，可以使信號線驅動電路的工作穩 線驅動電路的驅動頻率被要求高於掃描線驅動 頻率。注意，信號線驅動電路6 0 1 3可以爲使 體的薄膜電晶體、使用多晶半導體的薄膜電晶 SOI的薄膜電晶體。電源的電位、各種f| FPC6015分別供給給像素部6012、信號親 6 0 1 3、掃描線驅動電路6 0 1 4。 注意，也可以將信號線驅動電路及掃描線 形成在與像素部相同的基底上。 此外’在另外形成驅動電路的情況下，不 形成有驅動電路的基底貼合到形成有像素部的 可以如貼合到F P C上。在圖1 〇 a中表示另外 線驅動電路6023，並且具有形成在基底6021 以提闻成品 個方式的顯 601 3且與 示面板的方 使用微晶半 高於使用微 體形成信號 定，該信號 電路的驅動 用單晶半導 體、或使用 •號等經由 丨驅動電路 驅動電路都 一定必要將 基底上，也 僅形成信號 上的像素部 -31 - 200913075 6 022及掃描線驅動電路6024的顯示面板的方式。像素部 6022及掃描線驅動電路6024藉由使用使用微晶半導體膜 的薄膜電晶體而形成。信號線驅動電路602 3經由 FPC6 025連接到像素部6022。電源的電位、各種信號等經 由F P C 6 0 2 5分別供給給像素部6 0 2 2、信號線驅動電路 6023、掃描線驅動電路6024。 另外，也可以使用使用微晶半導體膜的薄膜電晶體在 與像素部相同的基底上僅形成信號線驅動電路的一部分或 掃描線驅動電路的一部分，另外形成其他部分且與像素部 電連接。在圖1 0B中表示將信號線驅動電路所具有的類比 開關6 0 3 3 a形成在與像素部6 0 3 2、掃描線驅動電路6 0 3 4 相同的基底上，並且將信號線驅動電路所具有的移位暫存 器603 3 b另外形成在不同的基底603 1上，而彼此貼合的 顯示面板的方式。像素部6032及掃描線驅動電路6034使 用使用微晶半導體膜的薄膜電晶體而形成。信號線驅動電 路所具有的移位暫存器6 0 3 3 b經由FP C 6 0 3 5連接到像素部 603 2。電源的電位、各種信號等經由FPC603 5分別供給給 像素部603 2、信號線驅動電路、掃描線驅動電路6〇34。 如圖9、1 0A和1 0B所示，可以在與像素部相同的基 底上使用使用微晶半導體膜的薄膜電晶體形成本發明的顯 不裝置的驅動電路的一部分或全部。 注意’ 另外形成的基底的連接方法沒有特別的限 制，可以使用已知的COG方法、引線鍵合方法、或TAB 方法等。此外’連接的位置只要是能夠電連接，就不限於 -32- 200913075 圖9、10A和1〇B所示的位置。另外，也可以另 制器、CPU、記憶體等而連接。 '庄意’在本發明中使用的信號線驅動電路不 具有移位暫存器和類比開關的方式。除了移位暫 比開關之外’還可以具有緩衝器、電平轉移電路 隨器等其他電路。另外，不一定必要設置移位暫 比開關’例如既可以使用像解碼器電路的可以選 的另外電路而代替移位暫存器，又可以使用閂鎖 類比開關。 圖ΠΑ示出本發明的發光裝置的框圖。圖 的發光裝置包括具有多個具備顯示元件的像素 7 0 1、選擇每個像素的掃描線驅動電路7 〇 2、以及 信號輸入到被選擇的像素的信號線驅動電路703。 在圖1 1 A中信號線驅動電路7〇3具有移 704、類比開關705。對移位暫存器7〇4輸入有 (CLK )、起始脈衝信號（SP )。當輸入日ί (C L Κ )和起始脈衝信號（s ρ )時，在移位暫存| 生成定時信號，而輸入到類比開關705。 另外，將視頻信號（video signal )供給給 7 〇 5。根據輸入的定時信號，類比開關7 0 5取: 號，並供給給信號線。 接下來’對掃描線驅動電路702的結構進行 描線驅動電路702具有移位暫存器706、緩衝器 外，根據情況也可以具有電平轉移電路。在掃描 外形成控 局限於僅 存器和類 、源極跟 存器和類 擇信號線 等而代替 1 1 A所示 的像素部 控制視頻 位暫存器 時鐘信號 寺鐘信號 器704中 類比開關 樣視頻信 說明。掃 707 ° 此 線驅動電 -33- 200913075 路702中’藉由對移位暫存器706輸入有時鐘信號 (C L· K )及起始脈衝信號（s p )生成選擇信號。生成了的 選擇信號在緩衝器7 0 7中被緩衝放大，而供給給對應的掃 描線。一條線上的像素所具有的電晶體的閘極連接到掃描 線。而且’需要使一條線上的像素的電晶體同時導通，因 此採用能夠流過大電流的緩衝器7 〇 7。 全彩色顯示裝置中，在將對應於R (紅）、G (綠）、B (藍）的視頻信號按順序取樣而供給給對應的 信號線的情況下’用於連接移位暫存器704和類比開關 705的端子數目相當於用於連接類比開關705和像素部 701的信號線的端子數目的三分之一左右。因此，藉由將 類比開關7 0 5形成在與像素部7 0 1相同的基底上，與將類 比開關705形成在與像素部70丨不同的基底上時相比，可 以減少用於連接的端子數目，並且抑制連接不良的發生比 率，以可以提高成品率。 圖1 1 B示出與圖1 1 A不同的根據本發明的顯示裝置的 框圖。在圖1 1 B中，信號線驅動電路7 1 3具有移位暫存器 7 1 4、閂鎖A7 1 5、閂鎖B 7 1 6。掃描線驅動電路7 1 2具有與 圖11A的情況相同的結構。 移位暫存器714中輸入有時鐘信號（CLK)和起始脈 衝信號（SP )。當輸入時鐘信號（CLK )和起始脈衝信號 (SP )時，在移位暫存器714中生成定時信號，然後按順 序輸入到第一段閂鎖A 7 1 5中。當定時信號輸入到閂鎖a 7 1 5中時，與該定時信號同步，視頻信號按順序被寫入到 -34- 200913075 閂鎖A 7 1 5中並被存儲。注意，在圖1 1 B中雖然假定了視 頻信號按順序寫入到閂鎖A 7 1 5中，但是本發明並不限於 這種結構。也可以將閂鎖A 715的多個級（stage )分成幾 個組，然後給各組並行輸入視頻信號，即進行所謂分區驅 動。 向閂鎖A 7 1 5的所有閂鎖寫入視頻信號的周期被稱爲 線周期。實際上，有可能在上述線周期加上水平回掃周期 的周期包含在線周期中。 當一個線周期結束時，向第二段的閂鎖B 7 1 6供給閂 鎖信號（Latch Signal )。與該閂鎖信號的輸入同步，存 儲在閂鎖A 7 1 5中的視頻信號同時寫入並存儲在閂鎖b 7 1 6中。在將視頻信號傳輸到閂鎖B 7 1 6的閂鎖A 7 1 5 中，與從移位暫存器7 1 4輸入的定時信號同步，又按順序 進行下一個視頻信號的寫入。在第二一個線周期中，寫入 並存儲在閂鎖B 7 1 6中的視頻信號輸入到信號線。 注意，圖1 1 A、1 1 B所示的結構只不過是本發明的顯 示裝置的一個方式，信號線驅動電路和掃描線驅動電路的 結構不局限於此。 接下來，對相當於本發明的顯示裝置的一個方式的發 光顯示面板的外觀及截面，使用圖13A和13B進行說明。 圖13A是藉由使用密封劑將形成在第一基底上的使用微晶 半導體膜的薄膜電晶體及發光元件密封在第一基底與第二 基底之間的面板的俯視圖’圖1 3 B相當於沿圖丨3 A的A -A'的截面圖。 -35- 200913075 以圍繞在第一基底4001上設置的像素部4002和掃描 線驅動電路4004的方式設置有密封劑4005。另外，在像 素部4 0 0 2和掃描線驅動電路4 〇 〇 4上設置有第二基底 4 0 0 6。因此，像素部4 0 0 2和掃描線驅動電路4 0 0 4與塡料 4007 —起由第一基底4001、密封劑4005、以及第二基底 4〇〇6密封。另外，在第一基底400 1上的與由密封劑4005 圍繞的區域不同的區域中安裝有在另外準備的基底上由多 晶半導體膜形成的信號線驅動電路4 0 0 3。注意，雖然在本 實施方式中，對將具有使用多晶半導體膜的薄膜電晶體的 信號線驅動電路貼合到第一基底400 1的一例進行說明， 但是也可以由使用單晶半導體的電晶體形成信號線驅動電 路並貼合。圖1 3 B例示包含於信號線驅動電路4 0 0 3的由 多晶半導體膜形成的薄膜電晶體4009。 設置在第一基底400 1上的像素部4002和掃描線驅動 電路4004具有多個薄膜電晶體，圖13B例示包含於像素 部40 02的薄膜電晶體40 10。注意，在本實施方式中，雖 然假定了薄膜電晶體4010爲驅動TFT，但是薄膜電晶體 40 10既可以爲電流控制TFT，又可以爲擦除TFT。薄膜電 晶體40 1 0相當於使用微晶半導體膜的薄膜電晶體。 另外，發光元件4 0 1 1所具有的像素電極與薄膜電晶 體40 10的源電極或汲電極通過佈線40 17電連接。在本實 施方式中發光元件401 1的共同電極和透明導電膜4012電 連接。注意，發光元件40 1 1的結構不局限於本實施方式 所示的結構。根據從發光元件4011取出的光的方向或薄 -36- 200913075 膜電晶體4010的極性，可以適當地改變發光元件401 1的 結構。 此外，供給給另外形成的信號線驅動電路4003和掃 描線驅動電路4 〇 〇 4或像素部4 0 0 2的各種信號及電位，雖 然在圖13B的截面圖中未圖示，但是通過引導佈線4014 及引導佈線4015從FPC4018提供。 在本實施方式中，連接端子4016由與發光元件4011 所具有的像素電極相同的導電膜形成。另外，引導佈線 4〇14、引導佈線4015由與佈線4017相同的導電膜形成。 連接端子4016與FPC4018所具有的端子通過各向異 性導電膜4019電連接。 注意，作爲第一基底4001、第二基底4006，可以使 用玻璃、金屬（代表爲不銹鋼）、陶瓷、塑膠。作爲塑 膠，可以使用 FRP( Fiberglass-Reinforced Plastics，即纖 維增強塑膠）板、PVF (聚氟乙烯）薄膜、聚酯薄膜、聚 酯薄膜或丙烯酸樹脂薄膜。另外，也可以採用由PVF薄膜 或聚酯薄膜夾有鋁箔的結構的薄片。 但是’作爲位於從發光元件40 1 1的取出光的方向的 第二基底必須爲透明。在此情況下，使用玻璃板、塑膠 板、聚酯薄膜或丙烯酸薄膜等具有透光性的材料。 另外，作爲塡料4〇〇7除了氮或氬等惰性的氣體之 外’還可以使用紫外線硬化樹脂或熱硬化樹脂，即可以使 用PVC (聚氯乙烯）、丙烯、聚醯亞胺、環氧樹脂、矽酮 樹脂、PVB (聚乙嫌醇縮丁酉荃）'或EVA (ethylene vinyl -37- 200913075 acetate，即乙烯-醋酸乙烯酯）。在本實施方式中作爲塡 料使用氮。 另外’若有需要，也可以在發光元件的射出表面上適 當地提供諸如偏振片、圓偏振片（包括橋圓偏振片）、相 位差板（λ/4片、λ/2片）、以及顔色濾光片等的光學膜。 另外，也可以在偏振片或圓偏振片上提供抗反射膜。例 如，可以執行抗眩光處理，該處理是利用表面的凹凸來擴 散反射光並降低眩光的。 注意，圖1 3 Α和1 3 Β示出另外形成信號線驅動電路 4003並安裝到第一基底4001的一例，但是本實施方式不 局限於該結構。既可以另外形成掃描線驅動電路並安裝， 又可以另外僅形成信號線驅動電路的一部分或掃描線驅動 電路的一部分並安裝。 接下來，對相當於本發明的顯示裝置的一個方式的液 晶顯示面板的外觀及截面，使用圖1 4A和1 4B進行說明。 圖14A是藉由使用密封劑4005將形成在第一基底4001上 的具有微晶半導體膜的薄膜電晶體4010及液晶元件4013 密封在第一基底40 0 1與第二基底40 06之間的面板的俯視 圖，圖1 4 B相當於沿圖1 4 A的A - A'的截面圖。 以圍繞在第一基底400 1上設置的像素部4002和掃描 線驅動電路4004的方式設置有密封劑4005。另外，在像 素部4002和掃描線驅動電路4004上設置有第二基底 4 0 0 6。因此，像素部4 0 0 2和掃描線驅動電路4 0 0 4與液晶 4008 —起由第一基底4001、密封劑4005、以及第二基底 -38- 200913075 4006密封。另外，在第一基底400 1上的與由密封劑4005 圍繞的區域不同的區域中安裝有在另外準備的基底上由多 晶半導體膜形成的信號線驅動電路4 0 0 3。注意，雖然在本 實施方式中，對將具有使用多晶半導體膜的薄膜電晶體的 信號線驅動電路貼合到第一基底400 1的一例進行說明’ 但是也可以由使用單晶半導體的電晶體形成信號線驅動電 路並貼合。圖1 4 B例示包含於信號線驅動電路4 0 0 3的由 多晶半導體膜形成的薄膜電晶體4009。 設置在第一基底4 0 0 1上的像素部4 0 02和掃描線驅動 電路40 04具有多個薄膜電晶體，圖14B例示包含於像素 部4002的薄膜電晶體4010。薄膜電晶體4010相當於使用 微晶半導體膜的薄膜電晶體。 另外，液晶元件4013所具有的像素電極4030與薄膜 電晶體4010通過佈線404 1電連接。而且液晶元件4013 的相對電極 403 1形成在第二基底 4006上。像素電極 4〇3 0、相對電極403 1、液晶4008彼此重疊的部分相當於 液晶元件4 0 1 3。 另外，球狀的隔離物403 5用於控制像素電極4030和 相對電極403 1之間的距離（單元間隙）而設置。注意’ 也可以使用藉由對絕緣膜進行構圖獲得的隔離物。 此外，供給給另外形成的信號線驅動電路4003和掃 插線驅動電路4 0 0 4或像素部4 0 0 2的各種信號及電位，通 過引導佈線4014及引導佈線4015從FPC4018提供。 在本實施方式中，連接端子4016由與液晶元件4013 -39- 200913075 所具有的像素電極403 0相同的導電膜形成。另外’引導 佈線4 0 1 4、引導佈線4 0 1 5由與佈線4 0 4 1相同的導電膜形 成。 連接端子4〇16與FPC4018所具有的端子通過各向異 性導電膜4019電連接。 注意，雖然未圖示，本實施方式所示的液晶顯示裝置 具有定向膜、偏振片，進而也可以具有顔色濾光片、遮罩 膜。 注意，圖1 4 A和1 4 B示出另外形成信號線驅動電路 4003並安裝到第一基底4001的一例，但是本實施方式不 局限於該結構。既可以另外形成掃描線驅動電路並安裝， 又可以另外僅形成信號線驅動電路的一部分或掃描線驅動 電路的一部分並安裝。 本實施方式可以與其他實施方式所記載的結構組合而 實施。 實施方式4 根據本發明而獲得的顯示裝置如液晶顯示裝置等或發 光裝置可以用於各種模組（有源矩陣型液晶模組、有源矩 陣型EL模組）上。換句話說，其顯示部分安裝有上述各 種模組的所有電子設備均可以實施本發明。 作爲這種電子設備，可以舉出影像拍攝裝置如攝像機 和數位照相機等、頭戴式顯示器（護目鏡型顯示器）、汽 車導航系統、投影機、汽車音響、個人電腦、攜帶型資訊 -40 - 200913075 終端（移動電腦、移動電話或電子書籍等）等。圖1 5 A至 15C示出了其一例。 圖 15A表不電視裝置。如圖15A所不可以將顯示模 組組裝在框體中來完成電視裝置。將安裝了 FPC的顯示面 板還稱爲顯示模組。由顯示模組形成主畫面2 0 0 3，作爲其 他附屬器件還具有揚聲器單元2009、操作開關等。如上所 述，可以完成電視裝置。 如圖15A所示，在框體200 1中組裝利用了顯示元件 的顯示面板2002 ’並且可以由接收機2005接收普通的電 視廣播，而且通過介於數據機2 0 0 4連接到有線或無線方 式的通訊網絡，從而還可以進行單向（從發送者到接收 者）或雙向（在發送者和接收者之間’或者在接收者之 間）的資訊通訊。電視裝置的操作可以由組裝在框體中的 開關或另外的遙控裝置2006進行，並且該遙控裝置2006 也可以設置有顯示輸出資訊的顯示部分2〇〇7。 另外，電視裝置還可以附加有如下結構：除了主畫面 2〇03以外’使用第二顯示面板形成輔助畫面2008，並顯 示頻道或音量等。在這種結構中’也可以採用優越於視角 的發光顯示面板形成主畫面2 003，並且採用能夠以低耗電 量進行顯示的液晶顯示面板形成輔助畫面。另外，爲了優 先地減小耗電量’也可以採用如下結構：使用液晶顯示面 板形成主衋面20〇3，使用發光顯示面板形成輔助畫面，並 且輔助畫面能夠點亮和熄滅。 當然，本發明不局限於電視裝置’還可以應用於各種 -41 - 200913075 用途如個人電腦的監視器、鐵路的車站或飛機場等中的資 訊顯示幕、街頭上的廣告顯示幕等大面積顯示媒體。 圖15B表示攜帶型電話機23〇1的一例。該攜帶裂電 話機23 0 1包括顯示部23 02、操作開關2303等而構成。在 顯示部2 3 02中’應用上述實施方式所說明的顯示裝釐， 而可以提高批量生産性。 另外’圖15C所示的便攜型電腦包括主體240 1、顯 示部24〇2等。藉由對顯示部2402應用上述實施方式所示 的顯示裝置，可以提高大量生産性。 本申請基於2007年6月1日在日本專利局申請的日 本專利申請序列號2 0 0 7 - 1 4 7 3 8 6，在此引用其全部內容作 爲參考。 【圖式簡單說明】 圖1A至1C是說明本發明的顯示裝置的製造方法的截 面圖； 圖2A至2C是說明本發明的顯示裝置的製造方法的截 面圖； 圖3A至3C是說明本發明的顯示裝置的製造方法的截 面圖； 圖4A至4C是說明可以應用於本發明的發光裝置中的 像素的截面圖； 圖5是說明本發明的顯示裝置的製造方法的截面圖； 圖6是說明本發明的微波電漿CVD裝置的俯視圖； -42- 200913075 圖7是說明本發明的微波電漿CVD裝置的反應室的 截面圖； 圖8是說明本發明的成膜製程的圖； 圖9是說明本發明的顯示面板的立體圖； 圖10A和10B是說明本發明的顯示面板的立體圖； 圖11A和11B是說明可以應用於本發明的顯示裝置的 結構的方塊圖； 圖12是說明本發明的顯示裝置的截面圖； 圖1 3 A和1 3 B是說明本發明的發光顯示面板的俯視圖 及截面圖； 圖1 4 A和1 4 B是說明本發明的液晶顯示面板的俯視圖 及截面圖； 圖15A至15C是說明使用本發明的顯示裝置的電子設 備的立體圖。 【主要元件符號說明】 50 :基底 5 1 :閘電極 5 2 :閘電極 5 3 :絕緣膜 54 :微晶半導體膜 55 :半導體膜 56 :光罩 57 :光罩 -43- 200913075 5 8 :半導體膜 5 9 :半導體膜 60 :微晶半導體膜 61 :微晶半導體膜 62 :汲電極 6 2 a :源電極 63 :汲電極 6 3 a :汲電極 64 :汲電極 6 4 a :源電極 6 5 :汲電極 6 5 a :汲電極 6 6 :源極區域 67 :汲極區域 6 8 :源極區域 6 9 :汲極區域 70 :微晶半導體膜 71 :微晶半導體膜 72 :薄膜電晶體 73 :薄膜電晶體 8 1 :絕緣膜 8 2 :平坦化膜 8 3 :像素電極 8 4 :隔壁 -44 200913075 85 :發光層 8 6 :共同電極 8 7 :保護膜 8 8 :驅動電路 8 9 :像素部 90 :發光元件 94 :溝道保護膜 95 ·‘溝道保護膜 96 :半導體膜 97 :光罩 98 :光罩 1 0 1 :源極及汲極區域 102 :源極及汲極區域 1 〇 3 :源極及汲極區域 1 〇 4 :源極及汲極區域 105 :溝道保護膜 106 :溝道保護膜 120 :基底 1 2 2 :佈線 1 2 3 :佈線 1 2 4 :佈線 1 2 5 :佈線 1 3 0 :像素電極 1 3 1 :定向膜 -45 - 200913075 1 3 2 :液晶元件 1 3 3 :隔離物 140 :第二基底 1 4 1 :相對電極 1 4 2 :定向膜 1 5 0 :偏振片 1 5 1 :偏振片 1 6 1 :液晶 1 6 2 :密封劑 1 8 0 :處理容器 1 8 1 :支撐台 182 :氣體供給部 1 8 3 :排氣口 184 :微波產生單元 1 8 5 :波導管 1 8 6 :電介質板 1 8 7 :頂板 1 8 7 a :開口部 1 8 8 :安裝附件 1 8 9 :凹部 1 9 1 :非原料氣體供給源 192 :原料氣體供給源 193 :質量流量控制器 194 :質量流量控制器 -46 200913075 1 9 5 :閥門 1 9 6 :閥門 197 :氣體管 198 :氣體管 1 9 9 :溫度控制器 2 0 0 :電漿 7 0 1 :像素部 7 0 2 :掃描線驅動電路 7 〇 3 :信號線驅動電路 704 :移位暫存器 705 :類比開關 706 :暫存器 7 0 7 :緩衝器 7 1 2 :掃描線驅動電路 7 1 3 :信號線驅動電路 7 1 4 :移位暫存器 7 1 5 :閂鎖 7 1 6 :閂鎖 1 1 10 :裝載/卸載室 1 1 1 1 :反應室 1 1 1 2 :反應室 1 1 1 3 :反應室 1 1 1 4 :反應室 1 1 15 :裝載/卸載室 -47 200913075 1120： 公共腔 112 1： 搬送機構 1122： 閘閥 1123： 間閥 1124： 聞閥 1125： 間閥 1126： 閘閥 1127： 閘閥 1128： 匣 1129： 匣 113 0： 基底 200 1： 框體 20 02 ： 顯示面板 2003 ： 主畫面 2004 ： 數據機 200 5 ： 接收機 2006 ： 遙控裝置 2007 ： 顯示部分 200 8 ： 輔助畫面 2009 ： 揚聲器單元 23 0 1 ： 攜帶型電話機 23 02 ： 顯示部 23 03 ： 操作開關 240 1 ： 主體 200913075 2402 :顯示部 400 1:第一基底 4 0 0 2:像素部 4003 ：信號線驅動電路 4004 :掃描線驅動電路 4 0 0 5 :密封劑 4006:第二基底 4 0 0 7:塡料 4008 :液晶 4009 :薄膜電晶體 4010 :薄膜電晶體 4011:發光元件 4012 :透明導電膜 4 0 1 3 :液晶元件 4014 :引導佈線BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device which includes a thin film transistor in at least a pixel portion. [Prior Art] In recent years, a technique of forming a thin film transistor by using a semiconductor thin film (having a thickness of about several nm to several hundreds nm) formed on a substrate having an insulating surface is attracting attention. Thin film transistors are widely used in electronic devices such as ICs and electro-optical devices, and in particular, thin film transistors are being developed as switching elements of image display devices. A thin film transistor using an amorphous semiconductor film, a thin film transistor using a polycrystalline semiconductor film, or the like is used as a switching element of an image display device. In addition, a thin film transistor using a microcrystalline semiconductor film is used as a switching element of an image display device (Patent Document 1 and Patent Document 2). [Patent Document 1] Japanese Patent Application Publication No. Hei 4 - 2 4 2 7 2 4 [Patent Document 2] Japanese Patent Application Laid-Open No. Hei 20-5-5983 No. 2 discloses a thin film transistor using a polycrystalline semiconductor film having the following advantages : Compared with a thin film transistor using an amorphous semiconductor film, the mobility is two or more digits higher; the pixel portion of the semiconductor display device and the driving circuit in the vicinity thereof can be integrally formed on the same substrate. However, the process is complicated by the crystallization of the semiconductor film as compared with the case of using an amorphous semiconductor film, so that there is a disadvantage of lowering the yield and increasing the cost. -4-200913075 SUMMARY OF THE INVENTION In view of the above problems, a microcrystalline semiconductor film which can be mass-produced by a process of the object of the present invention (also referred to as a semi-junction conductor film, can be used as a microcrystalline semiconductor, specifically, The film can be CVD by microwave plasma at a frequency of 1 GHz or more with hydrogen hydride or halogen. The microcrystalline conductor produced by using the above method contains ruthenium. The crystal of 5 nm to 20 nm is different from the case of using a polycrystalline semiconductor film, and requires a process of crystallization. It is possible to reduce the number of devices and increase the yield of the display device, and it is possible to easily decompose the hydrogenation of the source gas or the microwave of the frequency of MHz to several hundred MHz using electricity of microwaves having a frequency of 1 GHz or more | using 1 GHz or more The microwave plasma of the frequency is used to form a microcrystalline semiconductor film, and the mass productivity of the film forming device can be improved. Further, by using a microcrystalline semiconductor (TFT), the thin film transistor is used to manufacture a display device. The degree of use of microcrystalline semiconductor is 2cm2/V. From sec to 10 cm2/V_sec, 2 to 20 of the thin film transistor of the conductor film is provided in a method of manufacturing a thin film electro-crystal display device. The crystalline semiconductor film) and the polycrystalline half film are formed directly on the substrate. The bismuth is a raw material gas and a device is used to form a microcrystalline semiconductor film including a microcrystalline semiconductor film in an amorphous half. The manufacturing process is suppressed because the process of forming a semiconductor film without forming a thin film transistor is suppressed. In addition, the pulp has a high electron density and is therefore halogenated. Therefore, the speed can be easily made by the CVD apparatus as compared with the tens of 褒 CVD apparatus. Thereby, the migration of the thin film transistor to the pixel portion and the thin film transistor for driving the electric film can be improved, and the mobility is half the mobility of the amorphous film, so that it can be the same as the pixel portion from -5 to 200913075. A part or the whole of the driving circuit is integrally formed on the substrate to form a system-on-panel. Note that in the present invention, the microcrystalline semiconductor film may be used at least in the channel formation region. Further, as the display device, a light-emitting device or a liquid crystal display device is included. The light emitting device includes a light emitting element, and the liquid crystal display device includes a liquid crystal element. The light-emitting element includes an element whose brightness is controlled by current or voltage, and specifically includes an inorganic EL (Electro Luminescence), an organic EL, or an electron source element used in an FED (Field Emission Display). Electron source element). Further, the display device includes a panel in a state in which the display element is sealed, and a module in which the panel is mounted with a state including 1C of the controller or the like. Further, the present invention relates to an element substrate corresponding to one mode before completion of a display element in a process of manufacturing the light-emitting device, wherein the element substrate has a mode in which a current is supplied to the light-emitting element in a plurality of pixels. Specifically, the element substrate may be in a state in which only the pixel electrode of the display element is formed, or may be in a state before the formation of the pixel electrode by etching as a conductive film of the pixel electrode, regardless of any state. Note that the display device in this specification means an image display device, a light emitting device, or a light source (including a lighting device). The display device further includes a module in which the light emitting device is mounted with a connector such as an FPC (Flexible Printed Circuit), a TAB (Tape Automated Bonding) tape or a TCP (Loaded Package); the printed wiring board is set to the TAB tape or the TCP end Module; 1C (integrated circuit) 200913075 Directly mounted on the module of the light-emitting element by COG (Chip On Glass). According to the present invention, it is possible to increase the film formation rate of the microcrystalline semiconductor film by using a microwave electron-accepting CVD apparatus having a frequency of 1 GHz or more, and it is possible to improve the mass productivity of a display device using a thin film transistor of the microcrystalline semiconductor film. Further, the process of crystallization of the semiconductor film after film formation can be reduced, and the system of the display device can be panelized without complicating the process of the thin film transistor. [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be embodied in a variety of different ways, and one of ordinary skill in the art can readily understand the fact that the form and details can be variously changed without departing from the spirit and scope of the invention. The way it is. Therefore, the present invention should not be construed as being limited to the contents described in the present embodiment. Embodiment 1 A method of manufacturing a display device of the present invention will be described. First, as one mode of the display device, a description will be made using a light-emitting device. Figs. 1A to 1C, Figs. 2A to 2C, and Figs. 3A to 3C show cross-sectional views of a thin film transistor for a driving circuit, and a cross-sectional view of a thin film transistor for a pixel portion. Note that the n-type thin film transistor using the microcrystalline semiconductor film has a higher mobility than the Ρ type, so the n-type thin film transistor is more suitable for driving the electric power 200913075. In the present invention, in the case of using a thin film transistor having any one of an n-type and a p-type, it is preferable to make the polarity of the thin film transistors formed on the same substrate uniform to suppress the number of processes. As shown in Fig. 1A, a gate electrode 51 and a gate electrode 52 are formed on the substrate 50. The substrate 50 may use a cityless glass substrate such as bismuth borate glass, aluminoborosilicate glass, aluminosilicate glass, or the like, or a ceramic substrate, which is manufactured by a melting method or a float method. A plastic substrate or the like having heat resistance which can withstand the processing temperature of the manufacturing process is used. Further, a substrate provided with an insulating layer on the surface of a metal substrate such as a stainless steel alloy can also be used. The size of the substrate 50 can be 320 mm x 400 mm, 370 mm X 4 70 mm, 550 mm x 650 mm, 600 mm x 720 mm, 680 mm x 880 mm, 730 mm x 920 mm, 1000 mm x 1 200 mm, 1100 mm x 1 25 0 mm, 1 1 5 0 mm x 1 3 0 0 mm, 1 5 0 0 mmx 1 8 0 0 mm, 1 9 0 0 mm x 2 2 0 0mm, 2160mm x 2460mm, 2400mm x 2800mm, or 2 8 5 0 mmx 3 0 5 0 mm etc. A metal material such as molybdenum, chromium, tantalum, tungsten or aluminum or an alloy thereof is used to form the gate electrode 51 and the gate electrode 52. A conductive film may be formed on the substrate 50 by a sputtering method or a vacuum deposition method, a photomask may be formed on the conductive film by a photolithography technique or an inkjet method, and the urethane engraved conductive film may be used to form the gate electrode 5 1 . , gate electrode 5 2 . Alternatively, the gate electrode 51 and the gate electrode 52 may be formed by firing by a jet-jet method using a conductive nano paste such as silver, gold or copper. Note that the nitride film of the above-described metal material may be provided between the substrate 50, the gate electrode 5A, and the gate electrode 52 in order to increase the tightness of the gate electrode 51 and the gate electrode 52. -8- 200913075 Note that a semiconductor film or wiring is formed on the gate electrode 51 and the gate electrode 52, and therefore its end portion is preferably processed into a tapered shape to prevent breakage. Further, although not shown, the wiring connected to the gate electrode can be simultaneously formed by the process of forming the gate electrode. Next, as shown in FIG. 1B, an insulating film 53 (hereinafter referred to as an insulating film 53) serving as a gate insulating film, a microcrystalline semiconductor film 54, and addition are sequentially formed on the gate electrode 51 and the gate electrode 52. There is a semiconductor film 55 (hereinafter referred to as a semiconductor film 55) which imparts an impurity element of one conductivity type. Note that it is preferable to form the insulating film 53 and the microcrystalline semiconductor film 504 at least continuously. Further, it is preferable to continuously form the insulating film 53, the microcrystalline semiconductor film 54, and the semiconductor film 55. By forming the insulating film 53 and the microcrystalline semiconductor film 54 at least continuously without contact with the atmosphere, each laminated interface can be formed without being contaminated by atmospheric constituents and contaminating impurity elements suspended in the atmosphere, thereby reducing the thin film transistor. Uneven characteristics. The insulating film 53 can be formed by a single layer or a laminate of a ruthenium oxide film, a tantalum nitride film, a hafnium oxynitride film, or a hafnium oxynitride film by a CVD method, a sputtering method, or the like. Further, an insulating film 53 may be formed by laminating an oxidized sand film or a hafnium oxynitride film, a tantalum nitride film or a hafnium oxynitride film in this order from the substrate side. Further, an insulating film 53 may be formed by sequentially laminating a tantalum nitride film or a hafnium oxynitride film, a hafnium oxide film or a hafnium oxynitride film, and a tantalum nitride film or an oxynitride film from the substrate side. Further, it is preferable to form the insulating film 53 by using a microwave plasma CVD apparatus having a frequency of 1 G Η z or more. The yttrium oxynitride film formed using the microwave plasma CVD apparatus has high pressure resistance and can improve the reliability of the thin film transistor which is formed later. -9- 200913075 Here, the yttrium oxynitride film has a higher oxygen content than nitrogen' when using Rutherford Backscattering Spectrometry (RBS) and the Hurricane J scattering method (HFS: Hydrogen Forward) Scattering) As a concentration range, it contains 50 atoms. /. Up to 70 atom% of oxygen, 〇·5 atom% to 15 atom% of nitrogen '25 atomic% to 35 atomic % of S i, 0.  1 atom% to 10 atom% hydrogen. In addition, the oxynitride film is used as its composition 'content more than oxygen' when measured using RBS and HFS as a concentration range, which contains 5 atom% to 30 atom% of oxygen, 20 atom% to 5 5 Atomic % nitrogen, 2 5 atom% to 35 atomic % of S i , 10 atomic % to 30 atomic % of hydrogen. However, in the case where the total of the atoms constituting the yttrium oxynitride or yttrium oxynitride is set to 1 〇〇 atomic%, the content ratio of nitrogen, oxygen, s i and hydrogen is included in the above range. The microcrystalline semiconductor film 54 refers to a film of a semiconductor having an amorphous structure and an intermediate structure between crystals (including single crystal, polycrystalline) structures. The semiconductor is a semiconductor having a third state which is very stable in terms of free energy, and is a crystalline semiconductor having short-range order and lattice distortion, which can have a particle diameter of 0. 5 nm to 2 Onm disperses it in the amorphous semiconductor. Further, at least 1 atom% or more of hydrogen or halogen is introduced to terminate the dangling bond. Further, by including a rare gas element such as helium, argon, neon or xenon in the microcrystalline semiconductor film to further promote lattice distortion, a high-quality microcrystalline semiconductor film having improved stability can be obtained. A description of such a microcrystalline semiconductor film is disclosed, for example, in U.S. Patent No. 4,409,134. By using the frequency of 1 GHz or more, preferably 2. 45 GHz or more, -10- 200913075 is more preferably 8. The microcrystalline semiconductor film 54 can be formed by a microwave plasma CVD apparatus of microwaves of 3 GHz or more. The representative ground can be formed using yttrium hydride of SiH4, Si2H6 or the like. Further, it may be formed using a hafnium halide such as SiCl4 or SiF4. In addition, hydrogen ruthenium or ruthenium halide may be used by using hydrogen; one or more rare gas elements selected from the group consisting of ruthenium, osmium, iridium, and gas; hydrogen and one or more rare gas elements selected from the group consisting of helium, argon, krypton, and xenon. Dilution is carried out to form a microcrystalline semiconductor film. The microcrystalline semiconductor film 54 is formed with a film thickness of 1 nm or more and 300 nm or less, preferably 5 nm or more and 200 nm or less. A carbide gas such as CH4 or C2H6 or a deuterated gas such as GeH4 or G e F 4 may be mixed in the hydride sand or the halogenated sand to adjust the energy band width to 1. 5eV to 2. 4eV or 〇. 9eV to l. leV. In addition, when the impurity element for the purpose of controlling the valence electron is not intentionally added, the microcrystalline semiconductor film 54 exhibits weak n-type conductivity, and therefore, for the microcrystalline semiconductor film used as the channel formation region of the thin film transistor, The threshold enthalpy can be controlled by adding an impurity element imparting a p-type at the same time as film formation or after film formation. The impurity element imparting the p-type is represented by boron, and an impurity gas such as B2H6 or BF3 may be mixed into the hydrazine hydride or the ruthenium halide at a concentration of from 1 ppm to 1,000 ppm, preferably from 1 to 0.01 ppm. Further, it is preferable to set the concentration of boron to, for example, lxl 〇 14 atoms/cm 3 to 6 x 10 6 atoms/cm 3 . Further, it is preferable to set the oxygen concentration of the microcrystalline semiconductor film to i χ 1019 at 〇 mS/cm 3 or less, and to set the nitrogen and carbon concentrations to 1 χ 1019 atoms/cm 3 or less, respectively. With regard to the semiconductor film 5 5 ' in the case of forming an n-channel type thin film transistor -11 - 200913075, phosphorus is added as a representative impurity element, and an impurity gas such as ph3 is added to the ruthenium hydride or the ruthenium halide. Further, in the case of forming a p-channel type thin film transistor, boron is added as a representative impurity element, and an impurity gas such as B2H6 may be added to the ruthenium hydride or the ruthenium halide. The semiconductor film 55 can be formed of a microcrystalline semiconductor film or an amorphous semiconductor film. Here, a microwave plasma CVD apparatus which can be continuously formed from the insulating film 53 to the semiconductor film 55 is shown using FIG. Fig. 6 is a schematic view showing a plan sectional view of a microwave plasma CVD apparatus. The common chamber 1 120 is connected to the gate valve 1122 to 1127 with a loading/unloading (L/UL; Load/UnLoad) chamber 1 1 1〇, a loading/unloading (L/UL) chamber 1 1 15 , and a reaction chamber (1 ) 1 1 1 1 to the reaction chamber (4) 1114. The substrate 1130 is embedded in a cassette 1128 and 1129 provided in a loading/unloading (L/UL) chamber 1110 and a loading/unloading (L/UL) chamber 1115, and is transported to each by a transport mechanism 1121 of the common chamber 1120. Reaction chamber (1) to reaction chamber (4). The insulating film 53, the microcrystalline semiconductor film 54, and the semiconductor film 55 are successively laminated in each of the reaction chambers (1) to the reaction chamber (4). In this case, a plurality of different types of films can be continuously laminated by the exchange of the material gases. Alternatively, the insulating film 53 and the microcrystalline semiconductor film 54 are continuously laminated in the reaction chamber (1) and the reaction chamber (3), and the semiconductor film 55 is formed in the reaction chamber (2) and the reaction chamber (4). By separately forming the semiconductor film 55, it is possible to prevent impurity elements remaining in the chamber from being mixed into other films. Thus, the insulating film 53, the microcrystalline semiconductor film 54, and the semi--12-200913075 conductor film 55 can be simultaneously formed by using the microwave plasma CVD apparatus to which a plurality of cells are connected, so that mass productivity can be improved. In addition, the reaction chamber can be maintained or cleaned, and can be processed in other reaction chambers to form a film with high power. In addition, it is possible to form contaminating impurity elements which are not trapped in the atmosphere and suspended in the atmosphere, which can reduce the unevenness of the characteristics of the thin film transistor. Further, in the case where the gate insulating film 53 is formed of two layers of a hafnium oxide film or a hafnium oxynitride film and a tantalum nitride film, the hafnium oxide film or oxygen nitrogen of the insulating film 53 may be formed in the chamber (1). The microcrystalline semiconductor film 54 is formed in the tantalum nitride film or the oxynitride reaction chamber (3) in which the insulating film 53 is formed in the sand chamber (2), and the semiconductor film 55 is formed in the reaction chamber. At this time, it is preferable to form the inside of each reaction chamber by the same film as the film formed. When the microwave 1 device of such a structure is used, one type of film can be formed in each reaction chamber to form an atmosphere continuously, and thus it can be formed without being contaminated by a film formed before or by an impurity element suspended in the atmosphere. Every side. Note that although the microwave plasma CVD apparatus shown in FIG. 6 has a load/unload (L/UL) chamber, it may be provided with an outer portion. It is also possible to provide a preheating substrate in the spare chamber spare chamber in the microwave plasma CVD apparatus. In the reaction chamber, it is possible to shorten the time until it is formed, so that productivity can be improved. Fig. 7 is a view for explaining in detail the structure of a chamber in the microwave plasma CVD apparatus. The reaction chamber 180 of the microwave plasma CVD apparatus is disposed in the processing container 180 for arranging 1 to cause a film deposition interface to be contaminated by a film or nitrogen oxide in the reaction film, in the ruthenium film, (4) The medium-sized film-coated electric paddle CVD is provided with one more than one layer of the remaining residue. Another. By means of a support table 181 having a substrate 1 130 -13- 200913075 disposed on the opposite side of the heating of the film, and a gas portion 18 2 for guiding the gas into the processing container 180, 2 is connected to the discharge processing container 1 8 0 The exhaust port of the gas 1 8 3, the microwave product 1 8 4 for supplying microwaves for generating plasma, the 185 for guiding the microwave from the microwave supply portion to the processing container 180, the contact with the waveguide 185, and the opening portion The top plate of the 187a is disposed outside the plurality of dielectric plates of the top plate 187 by the mounting attachment 18.8, and a gas pipe 197 flowing through the non-body is disposed between the substrate Π30 and the dielectric plate 186 (hereinafter referred to as gas) Tube 197), and gas tube 198 for flowing gas (hereinafter referred to as gas tube 198). The gas and gas pipe 1 98 is connected to the gas supply portion 1 82. Specifically, 197 is coupled to the non-body supply source 91 through valve 195 and mass flow controller 193. Further, a gas pipe 1 98 door 1 96 flowing through the material gas and a mass flow controller 1 94 are connected to the material gas 1 92. In addition, the temperature of the substrate Π 30 can be controlled by installing a temperature controller for the support stage 81. Alternatively, it is also possible to adopt a configuration in which a high-frequency power source is connected to the support stage 81, and a predetermined bias voltage is applied to the support stage 81 by electric power of alternating current from a high frequency. The gas supply unit 182 and the microwave generating unit 184 are disposed in the reaction volume. The microwave generating unit 184 supplies a frequency of 1 GHz or more. Above 45 GHz, more preferably, it is a microwave of 8_3 GHz or more. Note In the present invention, by having a plurality of microwave generating units 丨84, a large area of plasma can be determined. Therefore, the vacuum pumping unit waveguides 187, 86 are supplied even when the substrate is over used, in particular, a large-area substrate having a side exceeding 1 000 mm. In addition, the raw material gas passes through the raw material pipe 197. The gas pipe raw material gas passes through the valve supply source f 199 > The following is the preferred meaning of the power supply input, and it can be formed evenly under the condition of generating stable 60 mm -14-200913075. High film and can increase film formation speed. The processing container 180, and the top plate 187 are formed of a metal such as an alloy containing aluminum whose surface is covered with an insulating film of alumina, yttria, or fluororesin. Further, the mounting attachment 18 8 is formed of a metal such as an alloy containing aluminum. The dielectric plate 186 is provided in close contact with the opening of the top plate 187. The microwave generated in the microwave generating unit 184 is propagated through the waveguide 185 and the opening portion 87a of the top plate 187 to the dielectric plate 1 86' and transmitted through the dielectric plate 186 into the processing container. The non-feedstock gas is electrically padded due to the electric field energy of the microwaves emitted into the processing vessel. Since the density of the plasma 200 is higher on the surface of the dielectric plate 186, damage to the substrate 1 130 can be reduced. Furthermore, a uniform and large area of plasma can be generated and maintained by providing a plurality of dielectric plates 186. The dielectric plate 186 may also be formed of a ceramic such as sapphire, quartz glass, alumina, tantalum oxide, tantalum nitride or the like. Note that the dielectric plate 186 may be formed with a recess 889 on the side where the plasma 200 occurs. Due to the recess 18 8 , a stable plasma can be generated. By providing a plurality of dielectric plates 186, even in the case of using a substrate having a side exceeding 600 mm, particularly a large-area substrate exceeding one 1000 mm on one side, a film having high uniformity can be formed, and the film formation speed can be improved. The gas pipe 197 and the gas pipe 198 are disposed to cross each other. The discharge port of the gas pipe 197 is disposed on the side of the dielectric plate 186, and the discharge port of the gas pipe 198 flowing through the material gas is disposed on the side of the substrate 1130. By spraying the non-raw material gas on the side of the dielectric plate 186, a film can be formed on the surface of the dielectric plate 186 and the plasma 200 can be generated. Further, since the discharge port of the gas pipe -15 - 200913075 1 9 8 is disposed on the substrate 1 1 3 0 - side ', the material gas can be ejected at a position closer to the substrate 1 130, so that the film formation speed can be increased. The gas pipe 197 and the gas pipe 198 are formed of ceramics such as alumina, aluminum nitride, or the like. Since the microwave transmittance of the ceramic is high, when the gas tube 197 and the gas tube 198 are formed of ceramics, even if a gas tube is provided directly under the dielectric plate 186, the electric field is not disturbed, and the distribution of the plasma can be made uniform. Next, the film formation process will be described. These film forming processes may be selected from the gas supplied from the gas supply unit 182 according to the purpose. First, a method of forming a film of yttrium oxynitride film will be described with reference to Figs. 8 and 7 . First, the film formation process is started from the stage S1 70 in Fig. 8, and the temperature of the substrate 1 130 is controlled in the stage S 1 71. The temperature of the substrate 1 130 is room temperature or the substrate 1130 is heated by the temperature controller 199 to 100 ° C to 550 ° C. In the stage S 1 7 2, the inside of the processing vessel 1880 is brought into a vacuum state, and any one of rare gases such as chlorine, argon, helium, neon or the like is introduced and oxygen is used as a gas for plasma generation. The plasma can be easily ignited by introducing oxygen into the processing vessel 180 together with the rare gas. Note that the interval between the substrate 1 1 3 0 and the dielectric plate 1 8 6 is approximately 10 mm to 2 0 mm (preferably 110 mm to 160 mm). Next, in stage S173, the pressure in the processing container 180 is changed to a predetermined pressure. The pressure in the treatment vessel is from IPa to 200 Pa, preferably from IPa to 100 Pa, more preferably from IPa to 40 Pa. Next, in step S174, the power of the microwave generating unit 184 is turned on, and the microwave generating unit 184 supplies the microwave to the waveguide 85 to generate plasma in the processing container 180. The output of the microwave generating unit is from 500 W to 6000 W, preferably from 4000 W to 6000 W. When the plasma is excited by the introduction of microwave from -16- 200913075, the electron temperature can be lowered (0. 7 eV or more and 3 ev or less, preferably 〇. 7eV or more and 1. Plasma below 5 ev) and high electron density (1 X 1 0 1 1 atoms/cm3 to 1 χ 1 〇 1 3 atoms/cm3). Next, in the stage S 1 7 5, the material gas is introduced into the processing vessel 180 from the gas pipe 198. Specifically, a yttrium oxynitride film can be formed on the substrate 1130 by stopping the supply of oxygen to introduce nitrous oxide, a rare gas, and a lanthanum or lanthanum halide as a source gas. Next, in the stage S 1 7 6 , the supply of the material gas is stopped, the pressure in the processing container is lowered, and the power of the microwave generating unit is turned off, and then the film forming process is ended in the stage S 17 7 . In the above-described film forming treatment method of the yttrium oxynitride film, a yttrium oxynitride film having high pressure resistance can be formed by using the following conditions, that is, the substrate temperature is from 300 ° C to 350 ° C; The flow rate of nitrous oxide is 1 〇 or more and 300 times or less, preferably 50 times or more and 200 times or less, of the flow rate of decane; and 2 to 6 microwave generating units having a power of 5 kW are used: the pressure in the processing container is 10 Pa to 100 Pa, preferably 10 Pa to 50 Pa; the interval between the substrate 1130 and the dielectric plate 186 is 110 mm to 160 mm. Next, a method of forming a film of the microcrystalline semiconductor film 54 will be described. First, the film forming process is started from the stage S 1 70 in Fig. 8, and the temperature of the substrate 1130 is controlled in the stage S 1 71. The temperature of the substrate 1130 is such that the substrate 1 1 3 0 is heated to 100 ° C to 5 5 〇t by a room temperature or temperature controller 199. In the stage S172, the inside of the processing container is brought into a vacuum state, and a rare gas such as helium, argon, neon or xenon is introduced as a gas for plasma ignition. Note that the interval between the bottom 1130 and the dielectric plate 186 is approximately 10 mm to -17 - 200913075 2 0 0 mm (preferably π 〇 mm to 1 60 mm). Next, in the stage s 73, the pressure in the processing container 180 is changed to a predetermined pressure. The pressure in the treatment vessel is from IPa to 200 Pa', preferably from ipa to i〇〇pa. Next, in step S174, the power of the microwave generating unit 184 is turned on, and the microwave generating unit 184 supplies the microwave to the waveguide 185 to generate plasma in the processing container 180. The output power of the microwave generating unit is 50 () w to 6000 W, preferably 4000 W to 6000 W. When the plasma is excited by the introduction of microwaves, the electron temperature can be lowered (0. 7 eV or more and 3 ev or less, preferably 〇. 7eV or more and 1. An electric paddle with a high electron density (1χ 10" atoms/cm3cnT3 to lxio13 atorns/cm3). Next, in stage S175, the material gas is introduced into the processing container 180 from the gas pipe 198. Specifically, a microcrystalline semiconductor film can be formed by introducing ruthenium hydride such as SiH4 or ShH6 or ruthenium halide Si such as SiH2Cl2 or SiHCl3. Alternatively, a microcrystalline semiconductor film can be formed by introducing a halogenated ruthenium or hydrogen such as SiH4 or Si2H6 or SiH2Cl2 or SiHCl3. Next, in the stage S 1 7 6 , the supply of the material gas is stopped, the pressure in the processing container is lowered, and the power of the microwave generating unit is turned off, and then the film forming process is ended in the step S177. Note that in order to maintain the igniting of the plasma and the maintenance of the plasma, when a rare gas such as argon is mixed, the separation of the raw material gas and the formation of the radical (radicaI) can be efficiently performed due to the excited species of the rare gas. Further, the frequency is 1 GHz or more, preferably 2_45 GHz, and more preferably 8. The plasma generated by the microwave plasma CVD apparatus at 3 GHz W is supplied to the substrate -18 - 200913075 1130 because of its high electron density and formation of a majority by the material gas. Therefore, the surface reaction of the substrate on the substrate is promoted, and the film formation speed of the microcrystalline semiconductor film can be increased. Further, a microwave plasma CVD apparatus comprising a plurality of microwave generating units and a plurality of dielectric plates can generate a stable and large-area plasma. Therefore, even on a large-area substrate, a film which improves the uniformity of the film quality can be formed and mass productivity can be improved. In the case of forming an n-channel type thin film transistor, the semiconductor film 55 can be doped with phosphorus as a typical impurity element, and plasma CVD method using a gas containing an impurity element such as cesium hydride or a halogenated lanthanum and lanthanum 3 And formed. Further, in the case of forming a ruthenium channel type thin film transistor, boron may be added as a representative impurity element by a plasma CVD method using an impurity element such as ruthenium hydride or ruthenium halide or ruthenium 2 Η6. By setting the concentration of phosphorus or boron to lxl019atoms/cm3 to lxl021atoms/cm3, ohmic contact can be achieved with the semiconductor film 55 formed later and the source electrode and the germanium electrode. The semiconductor film 55 may be formed of a microcrystalline semiconductor or an amorphous semiconductor. The semiconductor film 55 is formed with a film thickness of 2 nm or more and 50 nm or less. The productivity can be improved by making the film thickness of the semiconductor film 55 to which the impurity element imparting one conductivity type is added thin. Further, the semiconductor film 5 may be formed in the same manner as the microcrystalline semiconductor film 54 by using the microwave plasma CVD apparatus ' at a frequency of 1 GHz or more as shown in Fig. 7 and using the stage shown in Fig. 8 . In this case, in the step S175, a microcrystalline semiconductor film to which a heterogeneous element imparting a conductivity type is added can be formed by introducing a hydrazine hydride or a ruthenium halide, PH3*B2H6, and hydrogen as a material gas. Then, a photomask 56 and a photomask 57 are formed on the semiconductor film 55, and the micro-19-200913075 crystal semiconductor film 504 and the semiconductor film 55 are etched into an island shape to be separated and formed. As a result, a microcrystalline semiconductor film 6 〇, a microcrystalline semiconductor film 61, and a semiconductor film 58 to which an impurity element imparting a conductivity type is added, and an impurity element imparting a conductivity type can be formed as shown in FIG. 1C. The semiconductor film 59 (hereinafter referred to as a semiconductor film 58 and a semiconductor film 59). Then, source electrodes and germanium electrodes 62 to 65 are formed on the semiconductor film 58, the semiconductor film 59, and the insulating film 53. It is preferable to form the source electrode and the ruthenium electrode 6 2 to 6 5 using an aluminum alloy to which an element which enhances heat resistance or an element which prevents hillocks such as a hillock, titanium, tantalum, niobium, molybdenum or the like is added. . In addition, it is also possible to adopt a laminated structure in which a layer of titanium, molybdenum, molybdenum, tungsten, or a nitride of these elements is formed on the side in contact with a semiconductor film to which an impurity element imparting one conductivity type is added, and Formed on the Ming or aluminum alloy. Further, a laminated structure of an upper surface and a lower surface of a vapor-formed alloy of titanium, tantalum, molybdenum, tungsten, or these elements may be used. A conductive film is formed on the semiconductor film 58, the semiconductor film 59, and the insulating film 53 by a sputtering method or a vacuum deposition method, and a photomask is formed on the conductive film by photolithography or coating, and then used. The photomask etches the conductive film to form source and drain electrodes 62 to 65. Alternatively, the source electrode and the ruthenium electrodes 6 2 to 65 may be formed by firing using a conductive nano paste such as silver, gold or copper by a screen printing method, an ink jet method or the like. Next, as shown in FIG. 2A, 'the uranium-etched semiconductor film 58 and the semiconductor are formed by using the source electrode and the germanium electrode 6 2 to 65 or a photomask which forms the source electrode and the germanium electrode 6 2 to 65 (not shown). The film 59 forms a source region and a drain region 66 -20- 200913075 to 69. Further, 'in the process', since the saturation selection ratio with the microcrystalline semiconductor film 60 serving as the substrate and the microcrystalline semiconductor film 61 serving as the substrate cannot be obtained, the microcrystalline semiconductor film 60 and the microcrystalline semiconductor film 6 1 are also A small amount is etched to form a microcrystalline semiconductor film 70 serving as a channel formation region, and a microcrystalline semiconductor film 71 serving as a channel formation region. Note that in the present embodiment, the source and drain electrodes 62 to 65 and the source and drain regions 66 to 69 are etched using dry etching by using the same resist mask and added with a given one. A semiconductor film of a conductive type impurity element is formed. A channel-etched thin film transistor 7 and a channel-etched thin film transistor 73 can be formed by the above process. The number of manufacturing processes of the channel-etched thin film transistor is small, and the cost can be reduced. Further, by forming the channel formation region from the microcrystalline semiconductor film, 2Cm2/V can be obtained. Electric field effect mobility of SeC to 10 cm2/V · sec. Therefore, the thin film transistor can be used as a switching element of the pixel of the pixel portion 89, and further used as an element for forming the driving circuit 8 8 on the scanning line (gate line) side. Next, as shown in FIG. 2B, an insulating film 8.1 for protecting the channel formation region is formed on the thin film transistor 72 and the thin film transistor 73, and a contact hole is formed as a preferable manner on the insulating film 81. The planarizing film 82 forms a pixel electrode 83 which is in contact with the source electrode or the germanium electrode in the contact hole on the planarizing film 82. The insulating film 81 can be formed in the same manner as the insulating film 53. Note that the insulating film 81 is used to prevent intrusion of contaminating impurities such as organic substances, metals, and water vapor suspended in the atmosphere, and therefore is preferably a dense film. Further, in addition to the use of the tantalum nitride film for the insulating film 8.1, the microcrystalline semiconductor film 70 serving as a channel formation region, and the microcrystalline semiconductor film 71 serving as a channel formation region can be used. The oxygen concentration in the medium is set to 5 x l 〇 19 at 〇 ms / cm 3 or less, preferably 1 x l 019 atoms / cm 3 or less. The planarizing film 82 is preferably formed of an insulating film using an organic resin such as propylene, polyimine or polyamine or a decane polymer. In Fig. 2B, since the thin film transistor of the pixel is n-type, it is preferable to use a cathode material as the pixel electrode 83. On the contrary, when the thin film transistor of the pixel is of a Ρ type, an anode material is preferably used. Specifically, as the cathode material, a known material having a small work function such as Ca, ruthenium 1, CaF, MgAg, AlLi or the like can be used. Next, as shown in Fig. 2C, a partition wall 84 is formed on the end portions of the planarizing film 82 and the pixel electrode 83. The partition wall 84 has an opening, and the pixel electrode 83 is exposed in the opening. The partition wall 84 is formed using an organic resin film or an inorganic insulating film. In particular, by using a photosensitive material, an opening is formed in the pixel electrode, and the side wall of the opening has an inclined surface having a continuous curvature, and the opening of the light-emitting layer 85 formed later can be reduced. This is preferred. Next, the light-emitting layer 85 is formed by contacting the pixel electrode 83 in the opening of the partition wall 84. The light-emitting layer 85 may be composed of a single layer or a laminate of a plurality of layers. The same electrode 8 6 using an anode material is formed to cover the light-emitting layer 85. The common electrode 8 6 may use a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide of stomach -22-200913075 titanium, indium containing titanium oxide. Tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with cerium oxide, or the like. As the common electrode 86, in addition to the above transparent conductive film, a nitrided film or a immersion film may be used. In Fig. 2C, ITO is used as the common electrode 86. In the opening portion of the partition wall 84, the pixel electrode 83, the light-emitting layer 85, and the common electrode 86 are overlapped with each other to form the light-emitting element 90. Then, a protective film 87 is preferably formed on the common electrode 86 and the partition wall 84 to prevent oxygen, hydrogen, moisture, carbon dioxide, or the like from entering the light-emitting element 90. As the protective film 87, a tantalum nitride film, a hafnium oxynitride film, a DLC (Diamond Like Carbon) film, or the like can be formed. Further, in actuality, when the process of FIG. 2C is completed, it is preferably encapsulated (sealed) by a protective film (laminated film, ultraviolet curable resin film, or the like) or a covering material which is high in airtightness and low in deaeration in order not to be exposed to air. . Note that although Figs. 1A to iC, 2A to 2C show a method of manufacturing a light-emitting device having a channel-etched thin film transistor, it may be formed using a channel-protected thin film transistor. This manufacturing method will be described using Figs. 3A to 3C. A gate electrode 51 and a gate electrode 52 are formed on the substrate 50 as shown in Fig. 3A. Then, the insulating film 53 and the micro-n-conductor film 54 are formed on the gate electrode S1 and the gate electrode 52 using a microwave gyro CVD apparatus having a frequency of 1 GHz or more. Therefore, the microcrystalline semiconductor film 54 can be easily formed. Next, a channel protective film 94' channel protective film 95 is formed on the microcrystalline semiconductor film 54 so as to overlap the gate electrode 51 and the gate electrode 52. -23- 200913075 The light guide has a half-shaped half-guided 53-step pole protection. The gate protection film 94 and the channel protection film 95 use tantalum nitride, ytterbium oxide, ytterbium oxide, and oxygen nitrogen. The insulating film is formed on the microcrystalline half film 54 by a sputtering method, a CVD method, or the like. A photomask is formed on the insulating film, and an insulating film is formed by using a cap. Alternatively, the channel protective film 94 protective film 95 may be formed by firing a composition containing polyfluorene iodide, propylene or decane by spraying. Next, a conductor film 96 (hereinafter referred to as a semiconductor film 96) is formed on the channel protective film 94 and the channel protective film 95, and a mask 97 and a mask 98 are formed on the semiconductor film 96. The semiconductor film 96 can be formed in the same manner as the conductor film 55 shown in Fig. 1B. The mask 97 and the mask 98 can be formed in the same manner as the mask 56 and the mask 57 shown in Fig. 1B. Next, the half film 96 and the microcrystalline semiconductor film 54 are separated by etching using the mask 97 and the mask 98 to form a microcrystalline semiconductor film 60 as a channel formation region as shown in FIG. 3B. A channel formation region microcrystalline semiconductor film 61, a semiconductor film 58, and a semiconductor film 59 are formed. Next, source and drain electrodes 62 to 65 are formed on the semiconductor film 58, the semiconductor film 59, and the insulating film. Next, the source and drain regions 01 to 104 are formed by photo-shielding the semiconductor film 58 and the semiconductor film 5, 9 as shown in Fig. 3C, with the source and drain electrodes 62 to 65 as the photo-etching semiconductor film 58. At this time, a part of the channel protective film 94 and the channel film 956 are etched. A part of the etched channel protective film is shown as a channel protective film 105 and a channel protective film 106. By the above process, the channel-24-200913075 film 105 and the channel protective film 106 having the overlap with the gate electrode 51, the gate 52, and the microcrystalline semiconductor film 60 and the microcrystalline semiconductor film 61 can be fabricated. A channel-protected thin film transistor. By forming the channel-protected thin film transistor on the element substrate, the unevenness of the element characteristics of the thin film transistor can be reduced, and the off current can be reduced. In addition, by forming the channel formation region from the microcrystalline semiconductor film, 2 cm 2 /V can be obtained. Sec to 10cm2/V. The electric field effect mobility of sec. Therefore, the thin film transistor can be used as a switching element of the pixel of the pixel portion 89, and further used as an element of the driving circuit 8 8 on the side of the scanning line (gate line). Next, the structure of the light-emitting element will be explained with reference to Figs. 4A to 4C. Here, a case where the driving T F T is an n-type is taken as an example, and a cross-sectional structure of the pixel will be described. In order to extract light, at least one of the anode and the cathode of the light-emitting element may be transparent. The thin film transistor and the light emitting element are formed on the substrate. There is a light-emitting element having a top emission structure, a bottom emission structure, and a double-sided emission structure, wherein the top emission structure extracts the emitted light by the opposite surface from the substrate, wherein the bottom emission structure extracts the emitted light through the surface on one side of the substrate, wherein the double-sided The emission structure extracts the emitted light through one side of the substrate and a surface opposite the surface of the substrate. The pixel structure of the present invention can be applied to a light-emitting element having any of the emission structures. A light-emitting element having a top emission structure will be described with reference to Fig. 4A. A cross-sectional view of a pixel when the driving TFT 7001 is of an n-type and light emitted from the light-emitting element 7 002 is transmitted to the side of the anode 7005 is shown in FIG. In FIG. 4A, the cathode 7003 of the light-emitting element 7002 and the driving TFTs 7001 to 25-200913075 are electrically connected, and a light-emitting layer 7004 and an anode 7005 are laminated in this order on the cathode 7003. As long as the cathode 7003 is a conductive film having a small work function and reflecting light, a known material can be used. For example, Ca, Al, CaF, MgAg, AlLi or the like is preferably used. The light-emitting layer 7004 may be composed of a single layer or a laminate of a plurality of layers. In the case of being composed of a plurality of layers, an electron injecting layer, an electron transporting layer, a light-emitting layer, a hole transporting layer, and a hole injecting layer are laminated in this order on the cathode 7003. Note that it is not necessary to set all of these layers. The anode 700 5 is formed using a transparent conductive film that transmits light. For example, a light-transmitting conductive film such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, or indium oxide containing titanium oxide may be used. Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide to which cerium oxide is added, or the like. A region where the light-emitting layer 7004 is sandwiched by the cathode 7003 and the anode 7005 is equivalent to the light-emitting element 7002. In the pixel shown in Fig. 4A, as shown by the open arrow, light emitted from the light-emitting element 7002 is emitted to the side of the anode 700 5 . Next, a light-emitting element having a bottom emission structure will be described with reference to Fig. 4B. Fig. 4B shows a cross-sectional view of a pixel when the driving TFT 7011 is of an n-type and light emitted from the light-emitting element 7 0 2 2 is emitted to the side of the cathode 7 0 1 3 . In Fig. 4A, a cathode 7013 of a light-emitting element 7012 is formed on a transparent conductive film 7017 electrically connected to a driving TFT 701 1, and a light-emitting layer 7014 and an anode 7015 are laminated on the cathode 7 〇 13 in this order. Note that in the case where the anode 70 15 is light transmissive, a light shielding film 7016 for reflecting light or shading may be formed to cover the anode 7015. Similarly to Fig. 4, the cathode 70 1 3 may be a known material as long as it is a conductive film having a small work function. Note -26- 200913075 means that the film thickness is set to the film thickness of the transmitted light (preferably about 5 nm to 30 nm). For example, A1 having a film thickness of 20 nm can be used as the cathode 7013. Further, as in Fig. 4A, the light-emitting layer 7014 may be composed of a single layer or a multilayer laminate. The anode 7015 does not have to transmit light, but like the one in Fig. 4A, it can be formed using a transparent conductive film. The light shielding film 7016 may use, for example, a metal that reflects light, but is not limited to a metal film. For example, a resin to which a black pigment is added or the like can also be used. The region where the light-emitting layer 7014 is sandwiched by the cathode 7013 and the anode 7015 is equivalent to the light-emitting element 7 0 1 2 . In the pixel shown in Fig. 4B, light emitted from the light-emitting element 7 0 1 2 is emitted to the side of the cathode 7 0 1 3 as indicated by a hollow arrow. Next, a light-emitting element having a double-sided emission structure will be described using FIG. 4C. In Fig. 4C, a cathode 7023 of a light-emitting element 7022 is formed on a transparent conductive film 7027 electrically connected to a driving TFT 7021, and a light-emitting layer 7024 and an anode 7025 are laminated on the cathode 7〇23 in this order. Similarly to Fig. 4A, as long as the cathode 7023 is a conductive film having a small work function, a known material can be used. Note that the film thickness is set to the film thickness of the transmitted light. For example, A1 having a film thickness of 20 nm can be used as the cathode 7023. Further, as in Fig. 4A, the light-emitting layer 7024 may be composed of a single layer or a laminate of a plurality of layers. As in Fig. 4A, the anode 7025 can be formed using a transparent conductive film that transmits light. The region where the cathode 7023 'the light-emitting layer 7024 and the anode 7025 overlap each other corresponds to the light-emitting element 7 0 2 2 . In the pixel shown in FIG. 4C, as shown by the open arrow, light emitted from the light-emitting element 7 0 2 2 is emitted to both sides of the anode 7 0 2 5 side and the cathode 7023 side -27- 200913075 Note that although In the present embodiment, an example in which the driving TFT and the light-emitting element are electrically connected is shown. However, a configuration in which a current controlling TFT that controls a current flowing to the light-emitting element is connected between the driving TFT and the light-emitting element may be employed. Note that the light-emitting device shown in the present embodiment is not limited to the structure shown in Fig. 4A, and various modifications can be realized based on the technical idea of the present invention. Next, a manufacturing process of the liquid crystal display device as a display device will be described with reference to Figs. 1A to 1C, 2A to 2C, and Fig. 5. Through the processes of FIGS. 1A to 1C and FIG. 2A, as shown in FIG. 5, a thin film transistor 72 and a thin film transistor 73 are formed on the substrate 120. Then, an insulating film 81 for protecting, a planarizing film 82, a thin film transistor 72, a source electrode of the thin film electric body 713, and a ytterbium electrode 6 2 to 6 are formed on the thin film transistor 72 and the thin film transistor 73. 5 separately connected wiring 1 2 2 1 2 5 . Next, a prime electrode 1 30 connected to the wiring layer 25 is formed on the planarizing film 82. Although an example of a liquid crystal display device in which a pixel electrode 130 is formed of a transparent conductive film to form a transmission type is shown here, the liquid crystal display device of the present invention is not limited to this configuration. A reflective liquid crystal display device can be formed by using a conductive film forming electrode 'which easily reflects light. A portion of the wiring 125 can be used as the pixel electrode in this case. Next, a spacer 133 is formed of an insulating film on the wiring 1 2 4 or the wiring 1 2 5 . Note that an example in which oxide sand is used as the spacer 13 3 on the wiring 丨 24 is shown in Fig. 5 . Whether the pixel electrode 丨3 先 is formed first or the junction 4C of the spacer is formed, the underlying film to the image can be separated from the image -28 - 200913075. Further, although a columnar spacer is used as the spacer 133, a bead spacer may be scattered. Further, the alignment film 133 is formed so as to cover the wirings 1 22 to 1 25, the spacers 133, and the pixel electrodes 1300, and the honing treatment is performed. Next, a sealant 162 for sealing the liquid crystal is formed. On the other hand, a second substrate 140 on which the opposite electrode 141 using the transparent conductive film and the alignment film 142 subjected to the honing treatment are formed is prepared. Further, the liquid crystal 169 was dropped in a region surrounded by the sealant 162, and the second substrate 14 〇 was attached in a manner to face the electrode 141 and the pixel electrode 1300 using the sealant 162. Note that it is also possible to mix the dip in the sealant 162. Note that the sealant 162 may also be formed on the second substrate 140, and after the liquid crystal 116 is dropped in the region surrounded by the sealant 162, the first substrate 120 and the second substrate 140 are bonded using the sealant 162. Further, although the above-described liquid crystal injection is performed by a dispenser method (drop method), the present invention is not limited thereto. It is also possible to use an immersion method in which liquid crystal is injected by capillary phenomenon after the first substrate 120 and the second substrate 140 are bonded together by the sealant 162. Further, a color oven sheet, a shielding film (black matrix) for preventing disclination, and the like may be formed on the first substrate 120 or the second substrate 40. Further, 'the polarizing plate 15' is bonded to the surface opposite to the surface on which the thin film transistor of the first substrate 120 is formed, and the polarizing surface is bonded to the surface opposite to the surface of the second substrate 4' which is formed opposite to the electrode 141. Slice 1 5 j. The transparent conductive film for the pixel electrode 130 or the opposite electrode 141 can be suitably made of the same material as the pixel electrode shown in Fig. 2B. The liquid crystal element 1 3 2 is formed by sandwiching -29-200913075 liquid crystal 161 between the pixel electrode 1 30 and the opposite electrode 1 4 1 . By the above process, a display device can be manufactured. Further, since the plasma generated by the microwave electric pulverizer CVD apparatus of 1 GHz or more has a high electron density, the film formation speed of the microcrystalline semiconductor film can be improved by using the apparatus. Therefore, the mass productivity of a display device having a thin film transistor using a microcrystalline semiconductor film can be improved. Further, a microwave plasma CVD apparatus comprising a plurality of microwave generating units and a plurality of dielectric plates can generate a stable and large-area plasma. Therefore, mass production can be improved by manufacturing a display device using a large-area substrate. (Embodiment 2) In this embodiment, another shape of the thin film transistor shown in Embodiment 1 will be described with reference to Fig. 1 . As shown in FIG. 12, the thin film transistor 7 and the thin film transistor 73 shown in the present embodiment are characterized by a source electrode 62 a, an end portion of the source electrode 64 4 a, and a source region 66, a source. The ends of the pole regions 6.8 are inconsistent. Further, the feature is that the end of the ytterbium electrode 63 3 a, the end of the ytterbium electrode 65 5 a, and the end of the drain region 67 and the drain region 609 do not coincide. In the present embodiment, the source electrode and the germanium electrode 6 2 a to 65 a are formed by wet etching the conductive film by using the same resist mask, and the semiconductor film to which the impurity element imparting one conductivity type is added is dry-etched. Forming the source region and the drain region 66 to 69° by the structure of the source electrode and the germanium electrode 62a to 65a in the present embodiment, since the interval between the opposing electrodes becomes large, it can be reduced to -30-200913075 at the source electrode and The short circuit between the electrodes is therefore 'rateful. (Embodiment 3) Next, the structure of a panel of the display device of the present invention is shown below. The display of the connection of the pixel portion 6012 formed on the substrate 6011 by only the signal line driver circuit is shown in Fig. 9 . The pixel portion 60 1 2 and the scanning line driving circuit 60 1 4 are formed using a thin film transistor of a conductor film. The driving frequency of the operating line driving circuit of the signal line driving circuit can be made higher than the scanning line driving frequency by the thin film transistor driving circuit from which the mobility of the thin film transistor of the crystalline semiconductor film is migrated. Note that the signal line driver circuit 601 may be a thin film transistor of a body, a thin film transistor of a thin film transistor SOI using a polycrystalline semiconductor. The potential of the power source and the various f| FPCs 6015 are supplied to the pixel portion 6012, the signal pro 6 0 1 3 , and the scanning line drive circuit 6 0 1 4, respectively. Note that the signal line driver circuit and the scanning line may be formed on the same substrate as the pixel portion. Further, in the case where the driving circuit is additionally formed, the substrate on which the driving circuit is not formed is attached to the pixel portion, and may be attached to the F P C as it is. An additional line driving circuit 6023 is shown in FIG. 1A, and has a display 601 3 formed on the substrate 6021 to improve the finished product, and the side of the display panel is formed using a microcrystal half higher than the micro-body forming signal. The single crystal semiconductor for driving the circuit or the driving circuit for driving the circuit via the • or the like must be formed on the substrate, and only the display panel of the pixel portion -31 - 200913075 6 022 and the scanning line driving circuit 6024 on the signal is formed. the way. The pixel portion 6022 and the scanning line driving circuit 6024 are formed by using a thin film transistor using a microcrystalline semiconductor film. The signal line driver circuit 602 3 is connected to the pixel portion 6022 via the FPC 6 025. The potential of the power source, various signals, and the like are supplied to the pixel portion 6 0 2 2, the signal line drive circuit 6023, and the scanning line drive circuit 6024 via F P C 6 0 2 5 , respectively. Further, a thin film transistor using a microcrystalline semiconductor film may be used to form only a part of the signal line driver circuit or a part of the scanning line driver circuit on the same substrate as the pixel portion, and another portion may be formed and electrically connected to the pixel portion. It is shown in FIG. 10B that the analog switch 6 0 3 3 a of the signal line driver circuit is formed on the same substrate as the pixel portion 6 0 2 2, the scanning line driving circuit 6 0 3 4 , and the signal line driving circuit is provided. The shift register 603 3 b is additionally formed on a different substrate 6031 in a manner of being attached to the display panel. The pixel portion 6032 and the scanning line driving circuit 6034 are formed using a thin film transistor using a microcrystalline semiconductor film. The shift register 6 0 3 3 b of the signal line drive circuit is connected to the pixel portion 603 2 via FP C 6 0 3 5 . The potential of the power source, various signals, and the like are supplied to the pixel portion 603 2, the signal line drive circuit, and the scanning line drive circuit 6〇34 via the FPC 603 5, respectively. As shown in Figs. 9, 10A and 10B, a part or all of the driving circuit of the display device of the present invention can be formed using a thin film transistor using a microcrystalline semiconductor film on the same substrate as the pixel portion. Note that the method of joining the additionally formed substrate is not particularly limited, and a known COG method, a wire bonding method, a TAB method, or the like can be used. Further, the position of the connection is not limited to the position shown in Figs. 9, 10A and 1B as long as it can be electrically connected. Alternatively, it can be connected by a separate device, CPU, memory, or the like. The signal line driver circuit used in the present invention does not have a shift register and an analog switch. In addition to shifting the temporary switch, there may be other circuits such as a buffer, a level shifting circuit follower, and the like. Further, it is not always necessary to provide a shift temporary switch. For example, it is possible to use an alternative circuit such as a decoder circuit instead of the shift register, and a latch analog switch. The figure shows a block diagram of a light-emitting device of the present invention. The light-emitting device of the figure includes a signal line drive circuit 703 having a plurality of pixels 707 having display elements, a scan line drive circuit 7 选择 2 for selecting each pixel, and a signal input to the selected pixel. In Fig. 11 A, the signal line drive circuit 7〇3 has a shift 704 and an analog switch 705. The shift register 7〇4 is input with (CLK) and a start pulse signal (SP). When the input day ί (C L Κ ) and the start pulse signal (s ρ ), the timing signal is generated in the shift temporary memory and input to the analog switch 705. In addition, a video signal is supplied to 7 〇 5. According to the input timing signal, the analog switch 7 0 5 takes the: number and supplies it to the signal line. Next, the structure of the scanning line driving circuit 702 is described. The line driving circuit 702 has a shift register 706 and a buffer, and may have a level shift circuit depending on the case. The control outside the scanning is limited to the memory and class, the source register and the analog signal line, etc. instead of the pixel portion shown in FIG. 1 A. Control the video bit register clock signal analog clock switch in the temple clock signal 704 Sample video letter description. The sweep 707 ° line drive -33- 200913075 way 702' generates a selection signal by inputting a clock signal (C L·K ) and a start pulse signal (s p ) to the shift register 706. The generated selection signal is buffer-amplified in the buffer 707 and supplied to the corresponding scan line. The gate of the transistor on the line of pixels has a gate connected to the scan line. Moreover, the transistors of the pixels on one line need to be turned on at the same time, so that the buffer 7 〇 7 capable of flowing a large current is used. In the full-color display device, when a video signal corresponding to R (red), G (green), and B (blue) is sequentially sampled and supplied to a corresponding signal line, 'for connection to the shift register 704 The number of terminals of the analog switch 705 is equivalent to about one third of the number of terminals for connecting the analog switch 705 and the signal line of the pixel portion 701. Therefore, by forming the analog switch 705 on the same substrate as the pixel portion 701, the terminal for connection can be reduced as compared with when the analog switch 705 is formed on a different substrate than the pixel portion 70? The number, and the occurrence ratio of the connection failure is suppressed, so that the yield can be improved. Fig. 1 1 B shows a block diagram of a display device according to the present invention which is different from Fig. 11A. In Fig. 1 1 B, the signal line drive circuit 7 1 3 has a shift register 7 14 , a latch A 7 15 , and a latch B 7 16 . The scanning line driving circuit 71 has the same configuration as that of the case of Fig. 11A. A clock signal (CLK) and a start pulse signal (SP) are input to the shift register 714. When the clock signal (CLK) and the start pulse signal (SP) are input, a timing signal is generated in the shift register 714, and then sequentially input to the first segment latch A 7 15 . When the timing signal is input to the latch a 7 15 , in synchronization with the timing signal, the video signal is sequentially written into the -34-200913075 latch A 7 1 5 and stored. Note that although it is assumed in Fig. 11B that the video signals are sequentially written into the latch A 7 15 , the present invention is not limited to this configuration. It is also possible to divide a plurality of stages of the latch A 715 into several groups, and then input video signals to the groups in parallel, that is, perform so-called partition driving. The period in which the video signal is written to all the latches of the latch A 7 15 is referred to as a line period. In fact, it is possible to include the period of the horizontal retrace period in the above line period including the online period. When the end of one line period, a latch signal (Latch Signal) is supplied to the latch B 7 16 of the second stage. In synchronization with the input of the latch signal, the video signal stored in latch A 7 15 is simultaneously written and stored in latch b 7 16 . In the latch A 7 15 that transmits the video signal to the latch B 7 16 , in synchronization with the timing signal input from the shift register 7 14 , the writing of the next video signal is performed in order. In the second one line cycle, the video signal written and stored in the latch B 7 16 is input to the signal line. Note that the structure shown in Figs. 1 1 and 1 1 B is only one mode of the display device of the present invention, and the configurations of the signal line driver circuit and the scanning line driver circuit are not limited thereto. Next, an appearance and a cross section of a light-emitting display panel which is one embodiment of the display device of the present invention will be described with reference to Figs. 13A and 13B. FIG. 13A is a plan view of a panel in which a thin film transistor and a light-emitting element using a microcrystalline semiconductor film formed on a first substrate are sealed between a first substrate and a second substrate by using a sealant. FIG. A section along A-A' of Figure 3A. -35- 200913075 A sealant 4005 is provided in such a manner as to surround the pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001. Further, a second substrate 4 0 0 6 is provided on the pixel portion 4 0 0 2 and the scanning line driving circuit 4 〇 〇 4 . Therefore, the pixel portion 420 and the scanning line driving circuit 604 are sealed from the first substrate 4001, the sealant 4005, and the second substrate 4?6. Further, a signal line drive circuit 403 formed of a polycrystalline semiconductor film on a separately prepared substrate is mounted in a region on the first substrate 400 1 different from the region surrounded by the sealant 4005. Note that, in the present embodiment, an example in which a signal line driver circuit having a thin film transistor using a polycrystalline semiconductor film is bonded to the first substrate 400 1 will be described, but a transistor using a single crystal semiconductor may be used. A signal line driver circuit is formed and bonded. Fig. 13B illustrates a thin film transistor 4009 formed of a polycrystalline semiconductor film included in the signal line driver circuit 403. The pixel portion 4002 and the scanning line driving circuit 4004 disposed on the first substrate 400 1 have a plurality of thin film transistors, and FIG. 13B illustrates the thin film transistor 40 10 included in the pixel portion 40 02. Note that in the present embodiment, although the thin film transistor 4010 is assumed to be a driving TFT, the thin film transistor 40 10 may be either a current controlling TFT or an erasing TFT. The thin film transistor 40 10 corresponds to a thin film transistor using a microcrystalline semiconductor film. Further, the pixel electrode of the light-emitting element 4101 and the source electrode or the germanium electrode of the thin film transistor 40 10 are electrically connected by a wiring 40 17 . In the present embodiment, the common electrode of the light-emitting element 401 1 and the transparent conductive film 4012 are electrically connected. Note that the structure of the light-emitting element 40 1 1 is not limited to the structure shown in the present embodiment. The structure of the light-emitting element 401 1 can be appropriately changed depending on the direction of light taken out from the light-emitting element 4011 or the polarity of the thin film - 36 - 200913075 film transistor 4010. Further, various signals and potentials supplied to the signal line driver circuit 4003 and the scanning line driver circuit 4 or the pixel portion 4 0 0 2 which are separately formed are not shown in the cross-sectional view of FIG. 13B, but are guided by the wiring. 4014 and boot wiring 4015 are provided from the FPC 4018. In the present embodiment, the connection terminal 4016 is formed of the same conductive film as the pixel electrode of the light-emitting element 4011. Further, the lead wiring 4〇14 and the lead wiring 4015 are formed of the same conductive film as the wiring 4017. The connection terminal 4016 and the terminal of the FPC 4018 are electrically connected by the anisotropic conductive film 4019. Note that as the first substrate 4001 and the second substrate 4006, glass, metal (represented as stainless steel), ceramic, or plastic can be used. As the plastic, FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride) film, polyester film, polyester film or acrylic film can be used. Further, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film or a polyester film may also be used. However, the second substrate, which is in the direction of the light taken out from the light-emitting element 40 1 1 , must be transparent. In this case, a light transmissive material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used. In addition, as the crucible 4〇〇7, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin may be used, that is, PVC (polyvinyl chloride), propylene, polyimine, epoxy may be used. Resin, fluorenone resin, PVB (polyethylene terephthalate) or EVA (ethylene vinyl -37-200913075 acetate, ie ethylene-vinyl acetate). In the present embodiment, nitrogen is used as a binder. Further, if necessary, it is also possible to appropriately provide, for example, a polarizing plate, a circularly polarizing plate (including a bridge circular polarizing plate), a phase difference plate (λ/4 film, λ/2 plate), and a color on the emitting surface of the light emitting element. An optical film such as a filter. Alternatively, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, an anti-glare treatment can be performed which utilizes the unevenness of the surface to diffuse the reflected light and reduce the glare. Note that Figs. 13 and 13 show an example in which the signal line driver circuit 4003 is additionally formed and mounted to the first substrate 4001, but the embodiment is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted. Next, the appearance and cross section of a liquid crystal display panel corresponding to one embodiment of the display device of the present invention will be described with reference to Figs. 14A and 14B. 14A is a panel in which a thin film transistor 4010 having a microcrystalline semiconductor film and a liquid crystal element 4013 formed on a first substrate 4001 are sealed between a first substrate 40 0 1 and a second substrate 40 06 by using a sealant 4005. In the top view, Fig. 14B corresponds to a cross-sectional view along A-A' of Fig. 14. A sealant 4005 is provided in such a manner as to surround the pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 400 1 . Further, a second substrate 4 0 0 6 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 420 and the scanning line driving circuit 604 are sealed from the liquid crystal 4008 by the first substrate 4001, the sealant 4005, and the second substrate -38-200913075 4006. Further, a signal line drive circuit 403 formed of a polycrystalline semiconductor film on a separately prepared substrate is mounted in a region on the first substrate 400 1 different from the region surrounded by the sealant 4005. Note that, in the present embodiment, an example in which a signal line driver circuit having a thin film transistor using a polycrystalline semiconductor film is bonded to the first substrate 400 1 will be described. However, it is also possible to use a transistor using a single crystal semiconductor. A signal line driver circuit is formed and bonded. Fig. 14B illustrates a thin film transistor 4009 formed of a polycrystalline semiconductor film included in the signal line driver circuit 403. The pixel portion 704 and the scanning line driving circuit 40 04 disposed on the first substrate 409 have a plurality of thin film transistors, and FIG. 14B exemplifies the thin film transistor 4010 included in the pixel portion 4002. The thin film transistor 4010 corresponds to a thin film transistor using a microcrystalline semiconductor film. Further, the pixel electrode 4030 of the liquid crystal element 4013 and the thin film transistor 4010 are electrically connected by a wiring 404 1 . Further, the opposite electrode 403 1 of the liquid crystal element 4013 is formed on the second substrate 4006. The portion where the pixel electrode 4〇3 0, the counter electrode 4031, and the liquid crystal 4008 overlap each other corresponds to the liquid crystal element 4 0 1 3 . Further, a spherical spacer 403 5 is provided for controlling the distance (cell gap) between the pixel electrode 4030 and the opposite electrode 4031. Note that a spacer obtained by patterning an insulating film can also be used. Further, various signals and potentials supplied to the separately formed signal line driver circuit 4003 and the zigzag line driver circuit 104 or the pixel portion 4 0 0 2 are supplied from the FPC 4018 through the pilot wiring 4014 and the pilot wiring 4015. In the present embodiment, the connection terminal 4016 is formed of the same conductive film as the pixel electrode 4030 of the liquid crystal element 4013-39-200913075. Further, the leading wiring 4 0 1 4 and the guiding wiring 4 0 1 5 are formed of the same conductive film as the wiring 4 0 4 1 . The connection terminals 4〇16 and the terminals of the FPC4018 are electrically connected by the anisotropic conductive film 4019. Note that the liquid crystal display device of the present embodiment has an alignment film and a polarizing plate, and may further have a color filter or a mask film. Note that Figs. 14A and 14B show an example in which the signal line driver circuit 4003 is additionally formed and mounted to the first substrate 4001, but the embodiment is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted. This embodiment can be implemented in combination with the structures described in the other embodiments. Embodiment 4 A display device such as a liquid crystal display device or the like which is obtained according to the present invention can be used for various modules (active matrix type liquid crystal module, active matrix type EL module). In other words, all of the electronic devices whose display portions are mounted with the above various modules can implement the present invention. As such an electronic device, an image capturing device such as a video camera and a digital camera, a head mounted display (goggle type display), a car navigation system, a projector, a car audio, a personal computer, and a portable information - 40 - 200913075 Terminal (mobile computer, mobile phone or e-book, etc.). An example of this is shown in Figs. 1 5 A to 15C. Figure 15A shows a television device. As shown in Fig. 15A, the display module cannot be assembled in the housing to complete the television device. The display panel on which the FPC is installed is also referred to as a display module. The main screen 2 0 0 3 is formed by the display module, and as other accessory devices, the speaker unit 2009, the operation switch, and the like are further provided. As described above, the television device can be completed. As shown in FIG. 15A, a display panel 2002' using a display element is assembled in a housing 2001 and can receive an ordinary television broadcast by the receiver 2005, and is connected to a wired or wireless mode by being connected to the data machine 2000. The communication network can thus perform information communication in one direction (from sender to receiver) or in both directions (between sender and receiver) or between receivers. The operation of the television device can be performed by a switch incorporated in the housing or another remote control device 2006, and the remote control device 2006 can also be provided with a display portion 2〇〇7 that displays output information. Further, the television device may have a configuration in which the auxiliary screen 2008 is formed using the second display panel except for the main screen 2〇03, and the channel or volume or the like is displayed. In this configuration, the main picture 2 003 can also be formed by using the light-emitting display panel superior to the viewing angle, and the auxiliary picture can be formed by the liquid crystal display panel capable of display with low power consumption. Further, in order to preferentially reduce the power consumption, it is also possible to adopt a configuration in which the main pupil plane 20〇3 is formed using the liquid crystal display panel, an auxiliary screen is formed using the light-emitting display panel, and the auxiliary screen can be turned on and off. Of course, the present invention is not limited to the television device' can also be applied to various types of -41 - 200913075 applications such as personal computer monitors, railway stations or airports, information display screens, street display screens, etc. media. Fig. 15B shows an example of the portable telephone 23〇1. The portable telephone 231 includes a display unit 323, an operation switch 2303, and the like. In the display unit 2 3 02, the display device described in the above embodiment is applied, and mass productivity can be improved. Further, the portable computer shown in Fig. 15C includes a main body 240 1 , a display unit 24 〇 2 and the like. By applying the display device described in the above embodiment to the display portion 2402, mass productivity can be improved. The present application is based on Japanese Patent Application Serial No. PCT Application No. No. No. No. No. No. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1C are cross-sectional views illustrating a method of fabricating a display device of the present invention; FIGS. 2A to 2C are cross-sectional views illustrating a method of fabricating the display device of the present invention; FIGS. 3A to 3C are diagrams illustrating the present invention FIG. 4A to FIG. 4C are cross-sectional views illustrating a pixel that can be applied to the light-emitting device of the present invention; FIG. 5 is a cross-sectional view illustrating a method of manufacturing the display device of the present invention; A plan view showing a microwave plasma CVD apparatus of the present invention; -42- 200913075; Fig. 7 is a cross-sectional view showing a reaction chamber of the microwave plasma CVD apparatus of the present invention; and Fig. 8 is a view for explaining a film forming process of the present invention; 10A and 10B are perspective views illustrating a display panel of the present invention; FIGS. 11A and 11B are block diagrams showing the structure of a display device which can be applied to the present invention; and FIG. 12 is a view for explaining the present invention. 1A and 1B are a plan view and a cross-sectional view illustrating a light-emitting display panel of the present invention; and FIGS. 1A and 1B are diagrams illustrating a liquid crystal display panel of the present invention. Top view and sectional view; Figs. 15A to 15C are perspective views illustrating an electronic device using the display device of the present invention. [Description of main component symbols] 50: Substrate 5 1 : Gate electrode 5 2 : Gate electrode 5 3 : Insulating film 54 : Microcrystalline semiconductor film 55 : Semiconductor film 56 : Photomask 57 : Photomask - 43 - 200913075 5 8 : Semiconductor Film 5 9 : semiconductor film 60 : microcrystalline semiconductor film 61 : microcrystalline semiconductor film 62 : germanium electrode 6 2 a : source electrode 63 : germanium electrode 6 3 a : germanium electrode 64 : germanium electrode 6 4 a : source electrode 6 5 : 汲 electrode 6 5 a : 汲 electrode 6 6 : source region 67 : drain region 6 8 : source region 6 9 : drain region 70 : microcrystalline semiconductor film 71 : microcrystalline semiconductor film 72 : thin film transistor 73 : Thin film transistor 8 1 : Insulating film 8 2 : Flattening film 8 3 : Pixel electrode 8 4 : Partition wall - 44 200913075 85 : Light-emitting layer 8 6 : Common electrode 8 7 : Protective film 8 8 : Driving circuit 8 9 : Pixel Portion 90: Light-emitting element 94: Channel protective film 95 - 'Channel protective film 96: Semiconductor film 97: Photomask 98: Photomask 1 0 1 : Source and drain region 102: Source and drain regions 1 〇 3: source and drain regions 1 〇 4 : source and drain regions 105 : channel protective film 106 : channel protective film 120 : substrate 1 2 2 : wiring 1 2 3 : wiring 1 2 4 : wiring 1 2 5 : wiring 1 3 0 : pixel electrode 1 3 1 : alignment film -45 - 200913075 1 3 2 : liquid crystal element 1 3 3 : spacer 140: second substrate 1 4 1 : opposite electrode 1 4 2 : alignment film 1 5 0 : polarizing plate 1 5 1 : polarizing plate 1 6 1 : liquid crystal 1 6 2 : sealing agent 1 8 0 : processing container 1 8 1 : support table 182 : gas supply portion 1 8 3 : exhaust port 184 : microwave generation Unit 1 8 5 : Waveguide 1 8 6 : Dielectric plate 1 8 7 : Top plate 1 8 7 a : Opening 1 8 8 : Mounting attachment 1 8 9 : Recess 1 1 1 : Non-material gas supply source 192 : Raw material gas supply Source 193: Mass Flow Controller 194: Mass Flow Controller - 46 200913075 1 9 5 : Valve 1 9 6 : Valve 197: Gas Tube 198: Gas Tube 1 9 9 : Temperature Controller 2 0 0 : Plasma 7 0 1 : pixel portion 7 0 2 : scan line drive circuit 7 〇 3 : signal line drive circuit 704 : shift register 705 : analog switch 706 : register 7 0 7 : buffer 7 1 2 : scan line drive circuit 7 1 3 : Signal line drive circuit 7 1 4 : Shift register 7 1 5 : Latch 7 1 6 : Latch 1 1 10 : Load/unload chamber 1 1 1 1 : Reaction chamber 1 1 1 2 : Reaction chamber 1 1 1 3 : Reaction chamber 1 1 1 4 : reverse Chamber 1 1 15 : Loading/unloading chamber - 47 200913075 1120: Common chamber 112 1: Transport mechanism 1122: Gate valve 1123: Interval valve 1124: Smell valve 1125: Interval valve 1126: Gate valve 1127: Gate valve 1128: 匣1129: 匣113 0 : Base 200 1: Frame 20 02 : Display Panel 2003 : Main Screen 2004 : Data Machine 200 5 : Receiver 2006 : Remote Control 2007 : Display Section 200 8 : Auxiliary Screen 2009 : Speaker Unit 23 0 1 : Portable Telephone 23 02 : Display portion 23 03 : Operation switch 240 1 : Main body 200913075 2402 : Display portion 400 1: First substrate 4 0 0 2: Pixel portion 4003: Signal line drive circuit 4004: Scan line drive circuit 4 0 0 5 : Sealant 4006: second substrate 4 0 0 7: tantalum 4008: liquid crystal 4009: thin film transistor 4010: thin film transistor 4011: light-emitting element 4012: transparent conductive film 4 0 1 3 : liquid crystal element 4014: boot wiring

401 5 :引導佈線 4016 :連接端子 4017:佈線 4018： FPC 4019 :各向異性導電膜 4030:像素電極 4 0 3 1 :相對電極 4 0 3 5 :隔離物 4 0 4 1 :佈線 -49 - 200913075401 5 : Guide wiring 4016 : Connection terminal 4017 : Wiring 4018 : FPC 4019 : Anisotropic conductive film 4030 : Pixel electrode 4 0 3 1 : Counter electrode 4 0 3 5 : Isolation 4 0 4 1 : Wiring -49 - 200913075

60 1 1 :基底 6 01 2 :像素 6 0 1 3 :信號 6 0 1 4 :掃描 6015： FPC 6021 ：基底 6022 ：像素 6 0 2 3 :信號 6024:掃描 6025 ： FPC 6031：基底 6032 ：像素 603 3 a ： II t 603 3 b ：移 f: 6034 ：掃描60 1 1 : Substrate 6 01 2 : Pixel 6 0 1 3 : Signal 6 0 1 4 : Scan 6015: FPC 6021 : Substrate 6022 : Pixel 6 0 2 3 : Signal 6024: Scan 6025 : FPC 6031 : Substrate 6032 : Pixel 603 3 a : II t 603 3 b : shift f: 6034 : scan

6035 ： FPC 7 0 0 1 :驅動 7002 :發光 7003 ：陰極 7004 :發光 7005 陽極 7 0 1 1 :驅動 7012 :發光 70 1 3 :陰極 部 線驅動電路 線驅動電路 部 線驅動電路 線驅動電路 部 ：開關 ί暫存器 線驅動電路6035 : FPC 7 0 0 1 : Drive 7002 : Light-emitting 7003 : Cathode 7004 : Light-emitting 7005 Anode 7 0 1 1 : Drive 7012 : Light-emitting 70 1 3 : Cathode line drive circuit line drive circuit line drive circuit line drive circuit section: Switch ί register line driver circuit

TFT 元件 層TFT element layer

TFT 元件 -50- 200913075 7014 :發光層 7 0 1 5 :陽極 7016 :遮光膜 7 0 1 7 :透明導電膜 702 1 ：驅動 TFT 7022 ·‘發光元件 7 0 2 3 :陰極 7024 :發光層 7025 ：陽極 7027 :透明導電膜TFT element-50-200913075 7014: light-emitting layer 7 0 1 5 : anode 7016: light-shielding film 7 0 1 7 : transparent conductive film 702 1 : driving TFT 7022 · 'light-emitting element 7 0 2 3 : cathode 7024: light-emitting layer 7025: Anode 7027: transparent conductive film

Claims (1)

200913075 十、申請專利範圍 1. 一種半導體裝置的製造方法，包括如下步驟： 形成薄膜電晶體的微晶半導體膜， 其中該微晶半導體膜係藉由使用1 GHz以上的頻率的 微波電漿CVD裝置而形成。 2. 根據申請專利範圍第1項之半導體裝置的製造方 法，其中該微晶半導體膜使用至少做爲該薄膜電晶體的溝 道形成區域。 3 .根據申請專利範圍第1項之半導體裝置的製造方 法，其中該微晶半導體膜是微晶矽膜。 4.一種半導體裝置的製造方法，包括如下步驟： 形成薄膜電晶體的微晶半導體膜， 其中該微晶半導體膜係藉由使用微波電漿CVD裝置 而形成，該微波電漿CVD裝置具有多個微波產生單元和 傳播在該多個微波產生單元中產生的微波的多個電介質 板，並且該微波電漿CVD裝置的頻率爲1 GHz以上。 5 ·根據申請專利範圍第4項之半導體裝置的製造方 法，其中該微晶半導體膜使用至少做爲該薄膜電晶體的溝 道形成區域。 6. 根據申請專利範圍第4項之半導體裝置的製造方 法，其中該微晶半導體膜是微晶矽膜。 7. —種顯示裝置的製造方法，包括如下步驟： 在基底上形成閘電極； 在該閘電極上形成閘極絕緣膜； -52- 200913075 在該閘極絕緣膜上形成第一微晶半導體膜； 在該第一微晶半導體膜上形成添加有賦予一導電型的 雜質元素之第一半導體膜； 蝕刻該第一微晶半導體膜以及添加有賦予一導電型的 雜質元素之該第一半導體膜，以形成用作溝道形成區域的 第二微晶半導體膜及添加有賦予一導電型的雜質元素的第 二半導體膜； 在添加有賦予一導電型的雜質元素的該第二半導體膜 上形成源電極及汲電極； 以該源電極及汲電極爲光罩，蝕刻添加有賦予一導電 型的雜質元素的該第二半導體膜，以形成添加有賦予一導 電型的雜質元素且用作源極區域及汲極區域的第三半導體 膜；以及 形成與該源電極或該汲電極接觸的像素電極， 其中該第一微晶半導體膜及添加有賦予一導電型的雜 質元素的該第一半導體膜係藉由使用微波電漿CVD裝置 而形成，該微波電漿CVD裝置具有多個微波產生單元和 傳播在該多個微波產生單元中產生的微波的多個電介質 板，並且該微波電漿CVD裝置的頻率爲1GHz以上。 8. 根據申請專利範圍第7項之顯示裝置的製造方法， 其中該第一及第二微晶半導體膜是微晶矽膜。 9. 根據申請專利範圍第7項之顯示裝置的製造方法， 其中該顯示裝置是液晶顯示裝置。 1 〇 .根據申請專利範圍第7項之顯示裝置的製造方 -53- 200913075 法，其中該顯示裝置是發光裝置。 1 1 . 一種顯示裝置的製造方法，包括如下步 在基底上形成閘電極； 在該閘電極上形成閘極絕緣膜； 在該閘極絕緣膜上形成第一微晶半導體膜 在該第一微晶半導體膜上形成溝道保護膜 在該第一微晶半導體膜及該溝道保護膜上 賦予一導電型的雜質元素的第一半導體膜； 蝕刻該第一微晶半導體膜以及添加有賦予 雜質元素的該第一半導體膜，以形成用作溝道 第二微晶半導體膜及添加有賦予一導電型的雜 二半導體膜； 在添加有賦予一導電型的雜質元素的該第 上形成源電極及汲電極； 以該源電極及汲電極爲光罩，蝕刻添加有 型的雜質元素的該第二半導體膜，以形成添加 電型的雜質元素且用作源極區域及汲極區域的 膜；以及 形成與該源電極或汲電極接觸的像素電極 其中該第一微晶半導體膜及添加有賦予一 質元素的該第一半導體膜係藉由使用微波電漿 而形成，該微波電漿CVD裝置具有多個微波 傳播在該多個微波產生單元中產生的微波的 板，並且該微波電槳CVD裝置的頻率爲1GHz 驟： 形成添加有 一導電型的 形成區域的 質元素的第 二半導體膜 賦予一導電 有賦予一導 第三半導體 5 導電型的雜 CVD裝置 產生單元和 多個電介質 以上。 -54- 200913075 1 2 .根據申請專利範圍第1 1項之顯示裝置的製造方 法，其中該第一及第二微晶半導體膜是微晶矽膜。 1 3 .根據申請專利範圍第1 1項之顯示裝置的製造方 法，其中該顯示裝置是液晶顯示裝置。 1 4 .根據申請專利範圍第1 1項之顯示裝置的製造方 法，其中該顯示裝置是發光裝置。 -55-200913075 X. Patent application scope 1. A method for manufacturing a semiconductor device, comprising the steps of: forming a microcrystalline semiconductor film of a thin film transistor, wherein the microcrystalline semiconductor film is a microwave plasma CVD device using a frequency of 1 GHz or higher And formed. 2. The method of fabricating a semiconductor device according to claim 1, wherein the microcrystalline semiconductor film uses at least a channel formation region of the thin film transistor. 3. The method of fabricating a semiconductor device according to the first aspect of the invention, wherein the microcrystalline semiconductor film is a microcrystalline germanium film. A method of fabricating a semiconductor device, comprising the steps of: forming a microcrystalline semiconductor film of a thin film transistor, wherein the microcrystalline semiconductor film is formed by using a microwave plasma CVD apparatus, the microwave plasma CVD apparatus having a plurality of a microwave generating unit and a plurality of dielectric plates that propagate microwaves generated in the plurality of microwave generating units, and the microwave plasma CVD device has a frequency of 1 GHz or more. The method of manufacturing a semiconductor device according to the fourth aspect of the invention, wherein the microcrystalline semiconductor film uses at least a channel forming region of the thin film transistor. 6. The method of fabricating a semiconductor device according to claim 4, wherein the microcrystalline semiconductor film is a microcrystalline germanium film. 7. A method of manufacturing a display device comprising the steps of: forming a gate electrode on a substrate; forming a gate insulating film on the gate electrode; -52- 200913075 forming a first microcrystalline semiconductor film on the gate insulating film Forming, on the first microcrystalline semiconductor film, a first semiconductor film to which an impurity element imparting a conductivity type is added; etching the first microcrystalline semiconductor film and adding the first semiconductor film to which an impurity element imparting a conductivity type is added Forming a second microcrystalline semiconductor film serving as a channel formation region and a second semiconductor film to which an impurity element imparting a conductivity type is added; forming on the second semiconductor film to which an impurity element imparting a conductivity type is added a source electrode and a germanium electrode; the second semiconductor film to which an impurity element imparting one conductivity type is added is etched by using the source electrode and the germanium electrode as a mask to form an impurity element to which a conductivity type is added and used as a source a third semiconductor film of the region and the drain region; and a pixel electrode that is in contact with the source electrode or the germanium electrode, wherein the first microcrystalline semiconductor film And the first semiconductor film to which an impurity element imparting a conductivity type is added is formed by using a microwave plasma CVD apparatus having a plurality of microwave generating units and propagating in the plurality of microwave generating units A plurality of dielectric plates of the generated microwaves, and the frequency of the microwave plasma CVD apparatus is 1 GHz or more. 8. The method of manufacturing a display device according to claim 7, wherein the first and second microcrystalline semiconductor films are microcrystalline germanium films. 9. The method of manufacturing a display device according to claim 7, wherein the display device is a liquid crystal display device. A method of manufacturing a display device according to the invention of claim 7, wherein the display device is a light-emitting device. A manufacturing method of a display device comprising the steps of: forming a gate electrode on a substrate; forming a gate insulating film on the gate electrode; forming a first microcrystalline semiconductor film on the gate insulating film at the first micro Forming a channel protective film on the crystalline semiconductor film, and providing a first semiconductor film of a conductive type impurity element on the first microcrystalline semiconductor film and the channel protective film; etching the first microcrystalline semiconductor film and adding an impurity The first semiconductor film of the element is formed to form a second microcrystalline semiconductor film for use as a channel and a hetero semiconductor film to which a conductivity type is added; and the first electrode is formed by adding an impurity element imparting a conductivity type And a drain electrode; the second semiconductor film to which a type impurity element is added is etched by using the source electrode and the germanium electrode as a mask to form a film in which an impurity element of an electric type is added and used as a source region and a drain region; And forming a pixel electrode in contact with the source electrode or the germanium electrode, wherein the first microcrystalline semiconductor film and the first semiconductor film to which a primary element is added are used by using microwave Formed by plasma, the microwave plasma CVD apparatus has a plurality of plates for microwave propagation of microwaves generated in the plurality of microwave generating units, and the frequency of the microwave electric paddle CVD apparatus is 1 GHz. The formation of a conductive type is formed. The second semiconductor film of the material element of the region is provided with a hetero-CVD device generating unit and a plurality of dielectrics which are electrically conductive and impart a conductivity to the third semiconductor 5. The method of manufacturing a display device according to the above aspect of the invention, wherein the first and second microcrystalline semiconductor films are microcrystalline germanium films. A method of manufacturing a display device according to the invention of claim 1, wherein the display device is a liquid crystal display device. A method of manufacturing a display device according to the invention of claim 1, wherein the display device is a light-emitting device. -55-
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JP5364293B2 (en) 2013-12-11
KR101482754B1 (en) 2015-01-14
CN101315884A (en) 2008-12-03
US20080299689A1 (en) 2008-12-04
JP2009010347A (en) 2009-01-15
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TWI479572B (en) 2015-04-01
US8647933B2 (en) 2014-02-11

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