200849456 九、發明說明： 【發明所屬之技術領域】 本發明係關於半導體測試設備’且更特定言之，係關於 將半導體積體電路封裝轉移至測試腔室中之測試板以將半 導體積體電路封裝緊密地黏著至測試板之半導體測試設 備。 本申請案主張2007年6月5曰向韓國智慧財產局申請之韓 國專利申請案第2007-0054986號之權利，該案之全文以引 用的方式併入本文中。 【先前技術】 半導體積體電路封裝在製造之最後階段經過測試過程以 檢查封裝是否正常操作。出於此原因，使用測試分類機作 為半導體測試設備中之一者。測試分類機將上面安裝有自 加載器供應之半導體積體電路封裝的托盤按壓至測試板 上，以使得半導體積體電路封裝之I/O端子接觸測試板。 日本專利特許公開案第H07-027637號揭示一種用於藉由 安裝於測試板上之複數個荷重元（load cell)來量測壓力及 移位之方法。在待測試之半導體積體電路封裝的標準改變 時’測試板亦由滿足改變之標準的新測試板替換。在日本 專利特許公開案第H07-027637號中所揭示之方法中，由於 荷重元女裝於測試板上，因此荷重元必須安裝於新的測試 板上’且因此半導體測試設備之價格上升。 韓國專利註冊案第10-0394215號揭示一種用於藉由安裝 於測试分類機上之荷重感應器（l〇ad sensor)(荷重元）來量測 壓力之方法。在韓國專利註冊案第10-039421 5號中所揭示 127748.doc 200849456 ;吏用單一荷重感應器（單一 不提供一用於識別托盤與測試 、… 積體電路封裝不接觸列η 卩0此-些半導體 【發明内容】収板’且校正托盤之位置的單元。 ^1月之1樣為提供—種半導體測試設備及-種用於控制該半導體 ^ m又備之方法，該半導體測試設備 牦加半導體積體電路封穿盘 了扃則试板之間的接觸之穩定性同 Ο 日、使用較小數目之零件（荷重感應器），從而為低價的。 本舍明之另-態樣為提供—種半導體測試^備及一種用 於控制該半導體測試設備之方法，該半導體測試設備經由 半導體積體電路封裝與測試板之間的平行控制而達成該等 半導體積體電路封裝與該測試板之間的正確接觸。 根據一態樣，本發明提供一種半導體測試設備，其包 含··複數個轉移單元，其分別連接至一板之複數個位置以 用於使該板朝向一測試板移動以使得將定位於該板與該測 試板之間的半導體積體電路封裝黏著至該測試板上；複數 個荷重感應器，其分別安裝於該複數個轉移單元上；及一 控制單元，其用於基於由該複數個荷重感應器所量測之荷 重而計异將該等半導體積體電路封裝黏著至該測試板上所 茜的該複數個轉移單元之轉移距離，且藉由調整該複數個 轉移單元之功率而以該等計算得之轉移距離來移動該板。 該板之正面接觸該等半導體積體電路封裝；且該複數個 轉移單元係藉由連桿部件而連接至該板之背面的不同位 置。 導螺 該複數個轉移單元中之每一者包括：一馬達； 127748.doc 200849456 桿，其藉由該馬達而旋 之兮滌錄移動部件，其基於該導螺桿 往ΐ;及於與該導螺桿之—螺桿部分的相互作用而 該板j 其與該移動部件之該往復-起往復以轉移 =數個荷重感應器中之每—者提供於該移動部件與該 ;件：二t該複數個荷重感應器中之每-者量測在該移動 口 IM牛彺设日守施加至該桿的荷重。200849456 IX. INSTRUCTIONS OF THE INVENTION: FIELD OF THE INVENTION The present invention relates to semiconductor test equipment 'and more particularly to transferring a semiconductor integrated circuit package to a test board in a test chamber to integrate a semiconductor integrated circuit The package is tightly bonded to the semiconductor test equipment of the test board. The present application claims the benefit of the Korean Patent Application No. 2007-0054986, filed on June 5, 2007, to the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. [Prior Art] The semiconductor integrated circuit package is subjected to a test process at the final stage of manufacture to check whether the package is operating normally. For this reason, a test classifier is used as one of the semiconductor test equipment. The test sorter presses the tray on which the semiconductor integrated circuit package supplied from the loader is mounted onto the test board so that the I/O terminals of the semiconductor integrated circuit package contact the test board. Japanese Patent Laid-Open Publication No. H07-027637 discloses a method for measuring pressure and displacement by a plurality of load cells mounted on a test board. When the standard of the semiconductor integrated circuit package to be tested changes, the test board is also replaced by a new test board that meets the changed standard. In the method disclosed in Japanese Laid-Open Patent Publication No. H07-027637, since the load cell is worn on the test board, the load cell must be mounted on a new test board' and thus the price of the semiconductor test equipment rises. Korean Patent Registration No. 10-0394215 discloses a method for measuring pressure by a load sensor (load cell) mounted on a test sorter. 127748.doc 200849456 is disclosed in Korean Patent Registration No. 10-039421 5; a single load sensor is used (a single one is not provided for identifying the tray and the test, ... the integrated circuit package does not contact the column η 卩 0 this - Some semiconductors [invention] a unit that closes the board and corrects the position of the tray. ^1 is a semiconductor test equipment and a method for controlling the semiconductor, the semiconductor test equipment牦When the semiconductor integrated circuit is sealed, the stability of the contact between the test boards is the same as that of the next day, and a smaller number of parts (load sensors) are used, which is low-priced. Providing a semiconductor test device and a method for controlling the semiconductor test device, the semiconductor test device achieving the semiconductor integrated circuit package and the test board via parallel control between a semiconductor integrated circuit package and a test board According to an aspect, the present invention provides a semiconductor testing apparatus comprising: a plurality of transfer units respectively connected to a plurality of positions of a board For moving the board toward a test board such that a semiconductor integrated circuit package positioned between the board and the test board is adhered to the test board; a plurality of load sensors respectively mounted to the plurality of And a control unit for adhering the semiconductor integrated circuit packages to the plurality of transfer units on the test board based on the load measured by the plurality of load sensors Transferring the distance, and moving the board by adjusting the power of the plurality of transfer units by the calculated transfer distance. The front side of the board contacts the semiconductor integrated circuit packages; and the plurality of transfer units are borrowed Connected to different positions on the back side of the board by the link member. Each of the plurality of transfer units includes: a motor; 127748.doc 200849456 rod, which is rotated by the motor a member that is based on the lead screw; and interacts with the screw portion of the lead screw to reciprocate the plate j and the moving member to transfer = several load sensations Each of the vessel - to provide the member with the movement; member: two t the plurality of load sensors in each - are applied to the measurement of the moving rod opening disposed day IM bovine Wang gatekeeper load.
一 制單元彳工制忒板與該測試板之相對位置以使得該等 半導體積體電路封裝之1/0端子電接觸該測試板之測試端 子0 /控制單元里測在该等半導體積體電路封裝之〗/〇端子 :接：該：試板之測試端子時施加至該板的荷重，儲存該 里測侍之何t ’且在測試該等半導體積體電路封裝時分別 亥複數個轉移單元之該等功帛以產生與該儲存之荷重 相同的荷重。 在待測試之該等半導體積體電路封裝之標準改變時，該 控制單兀重新量測在具有改變之標準的該等半導體積體電 路封I之I/O端子電接觸該測試板之測試端子時施加至該 板的荷重，儲存該重新量測得之荷重，且在測試具有改變 之祆準的该等半導體積體電路封裝時基於該儲存之荷重而 分別该控制複數個轉移單元之該等功率。 該複數個荷重感應器為複數個荷重元。 根據另一恶樣，本發明提供一種用於控制半導體測試設 備之方法，該半導體測試設備具有：複數個轉移單元，其 分別連接至一板之複數個位置以用於使該板朝向一測試板 127748.doc 200849456 矛夕動以使仔將疋位於該板與該測試板之間的半導體積體電 路封裝黏著至該測試板上；及複數個荷重感應器，其分別 安裝於該複數個轉移單元上，該方法包含：分別驅動該複 數個轉移單元以將該等半導體積體電路封裝黏著至該測試 板上，里測％加至s亥板之荷重；基於由該複數個荷重感應 器所量測之荷重而計算將該等半導體積體電路封裝黏著至 該測試板上所需的該複數個轉移單元之轉移距離；及藉由The unit is configured to be in a position relative to the test board such that the 1/0 terminal of the semiconductor integrated circuit package electrically contacts the test terminal 0 of the test board/control unit in the semiconductor integrated circuit Package 〗 / 〇 terminal: connect: the load applied to the board when the test terminal of the test board is stored, store what is in the test, and when the semiconductor integrated circuit package is tested, a plurality of transfer units are respectively The power is generated to produce the same load as the stored load. When the standard of the semiconductor integrated circuit package to be tested is changed, the control unit re-measures the test terminal of the test board with the I/O terminal of the semiconductor integrated circuit package having the changed standard. Loading the load applied to the board, storing the re-measured load, and controlling the plurality of transfer units based on the stored load when testing the semiconductor integrated circuit packages having the changed standards power. The plurality of load sensors are a plurality of load cells. According to another embodiment, the present invention provides a method for controlling a semiconductor test apparatus having: a plurality of transfer units coupled to a plurality of locations of a board for directing the board toward a test board 127748.doc 200849456 spear so that the semiconductor integrated circuit package between the board and the test board is adhered to the test board; and a plurality of load sensors respectively mounted to the plurality of transfer units The method includes: respectively driving the plurality of transfer units to adhere the semiconductor integrated circuit packages to the test board, and measuring the load added to the s-plate; based on the plurality of load sensors Calculating the transfer distance of the plurality of transfer units required to adhere the semiconductor integrated circuit packages to the test board; and
調整該複數個轉移單元之功率而以該等計算得之轉移距離 來移動該板。 在該板之移動中’該板與該測試板之相對位置經控制以 使得該等半導體積體電路封裝之1/〇端子電接觸該測試板 之測試端子。 該方法進-步包含：量測在料半導體積體電路封裝之 I/O端子電接㈣測試板之測試端子時施加至該板的荷 重；儲存該量測得之荷重；及在測試該等半導體積體電路 封裝時分別控㈣複數個轉移單元之料功㈣產生與該 儲存之荷重相同的荷重。 另外’在待測試之該等半導體積體電路封裝之標準改變 時，該方法進一步包含：重新量測在具有該改變之標準的 該等半導體積體電路封裝之1/0姓 ο鳊子電接觸該測試板之測 試端子時施加至該板的荷重；儲存該重新量測 及在測試具有該改變之標準的 重， 千π孩專+導體積體電路封裝時 :於該儲存之荷重而分別控制該複數個轉移單元之 率。 〜 127748.doc •10- 200849456 比較該等量測得> π ^ 之何重與一預定荷重，且在該等量測得 荷重…亥預定荷重之間的差異超過—預定可容許誤差範 圍時’重新調整由該複數個轉移單元產生的該等荷重以重 新設定該板之位置。 比車乂該等里測彳于之荷重與一預定荷重，且計算該等量測 付之何重與4預定荷重之間的差異；在該等量測得之荷重 舁名預疋何重之間的差異處於一預定可容許誤差範圍中 才將°亥板之备則位置設定為一最終位置；且在該等量測 得=荷重與該預定荷重之間的差異不處於該預定可容許誤 差範圍中％，考慮到該等差異而重新設定該板之位置。 該板之最終位置為在該等半導體積體電路封裝充分黏著 至該測試板以使得可測試該等半導體積體電路封裝時該板 的一位置。 【實施方式】 現將詳細參看本發明之實施例，在隨附圖式中說明其實 例，在全部隨附圖式中相似參考數字指代相似元件。下文 藉由參看附加圖式而描述實施例以闡述本發明。 圖1為說明根據本發明之一實施例之半導體測試設備的 不意圖。 如圖1所示，測試板1 〇4提供於測試腔室1 〇2中，且托盤 106疋位於測試板104前方。托盤106用以接納安裝於其上 的複數個半導體積體電路封裝1〇以。具備安裝於上面的半 導體積體電路封裝106a之托盤1〇6藉由單獨加載器轉移至 半導體製造過程中之必要步驟。在托盤丨〇6緊密地黏著至 127748.doc • 11 - 200849456 /貝J忒板1 04吟，半導體積體電路封裝丨〇6a插入至形成於測 试板104上之插口 104a中且電連接至插口 1〇牦。為了使托 盤1〇6緊密地黏著至測試板1〇4，提供板1〇8及複數個轉移 單兀110。圖1說明複數個轉移單元110中之每一者的一部 分，但圖2及圖3說明複數個轉移單元11〇中之每一者的所 有部分。複數個轉移單元110及板1〇8將托盤1〇6轉移至測 試板104，且接著將托盤ι〇6按壓至測試板ι〇4上。 被稱為高精度定位（hi_fix)板之測試板1〇4為用於電連接 半導體積體電路封裝l〇6a及測試電路U2之單元。測試電 路112在半導體積體電路封裝1〇6a插入至測試板1〇4之情況 下發射及接收測試信號，且因此判定半導體積體電路封裝 l〇6a是否正常操作。測試電路112安裝於測試腔室1〇2外 部。 為了正確測試安裝於托盤106上之半導體積體電路封裝 l〇6a ’必須將所有半導體積體電路封裝1〇6a正確插入至測 試板104之插口 i〇4a中。因此，托盤ι〇6與測試板ι〇4之間 的平行對準為重要的。在板108與測試板1〇4之間的距離L1 及L2如圖1所示彼此不同（Li关[2)之情況下，托盤1〇6之具 備距離L1及L2中之較大者的一側無法充分接近測試板 104’且因此一些半導體積體電路封裝1〇6a無法插入至插 口 104a中。既而，不可能測試相應半導體積體電路封裝 l〇6a’或者可能獲得相應半導體積體電路封裝1〇6a的不可 靠測試結果。 另外’複數個轉移單元110及板108按壓托盤106之程度 127748.doc -12- 200849456 亦為重要的。在施加過大荷重以按壓托盤1〇6時，可能會 損壞半導體積體電路封裝106a或其他裝備，且在施加過小 荷重以按壓托盤1〇6時，半導體積體電路封裝1〇^無法充 分插入至插口 l〇4a中。 圖2為根據本發明之實施例之半導體測試設備的透視 圖。圖3為圖2之半導體測試設備之轉移單元的剖視圖，且 特別說明複數個轉移單元中之每一者的構成。如圖2及圖3 所示，複數個轉移單元110具有相同構成，複數個轉移單 元U〇中之每一者的大體上相同之一些部分由相同參考數 字表不。下文將描述一個轉移單元11〇之構成。 用於產生功率的馬達2〇2之旋轉力經由第一滑輪2〇4 '皮 帶206及第二滑輪208傳輸至導螺桿210。導螺桿210藉由旋 轉力而旋轉。移動部件212連接至導螺桿21〇。導螺桿21〇 之旋轉運動轉化為移動部件212之往復運動。移動部件Η] 之往復運動經由桿214而傳輸至板108，且因此與板1〇8之 轉移有關。因此’板1()8由於馬達逝之旋轉力而在箭頭A 之方向上往復。由於桿214與板⑽經由連桿部件2i6而機 械連接，因此有可能藉由不同地調整由複數個轉移單元 11〇所施加之壓力而控制板108與測試板1〇4之間的平行對 準。 在圖2中參考數字218表示測試腔室丨02之膜板，且僅 說明膜板218之部分。桿214及板1()8中之每—者的一部分 定位於膜板218内部（亦#，測試腔室102中），且複數個轉 移單元no定位於膜板218外部（亦即，測試腔室ι〇2外部）。 127748.doc -13- 200849456 環繞桿214之中間部分的熱絕緣材料22〇用以防止測試腔室 1 〇2令之熱經由桿214而損失。 在圖3中，荷重元302安裝於移動部件212與桿214之間。 移動部件212與桿214藉由單向制動器304而連接。在移動 口P件2 12朝向板1 〇 8移動時，壓力經由移動部件2 12、荷重 元3 02及杯214而傳輸至板1 〇8。此處，藉由荷重元3 〇2量測 壓力（亦即，荷重）。亦即，荷重元302偵測在板1〇8將圖 托盤106按壓至測試板104上時所施加的荷重。 圖4為圖2之半導體測試設備之控制系統的方塊圖。如圖 4所不’控制單元402分別經由複數個驅動電路404而控制 複數個轉移單元11 〇。特定言之，控制單元4〇2分別基於由 分別提供於複數個轉移單元11〇上之荷重元3〇2所量測的荷 重而控制複數個轉移單元110，且因此控制控制板1〇8與測 4板104之相對位置以使得半導體積體電路封裝 端子電接觸形成於測試板1〇4之插口 1〇乜中的測試端子。 另外，控制單元402量測在半導體積體電路封裝1〇以之 I/O端子電接觸測試板104之測試端子時施加至板的荷 重，將量測得之荷重儲存於記憶體4〇6中，且在測試半導 體積體電路封裝l〇6a時分別控制複數個轉移單元丨1〇之功 率以產生與儲存於記憶體1〇6中之荷重相同的荷重。 在待測試之半導體積體電路封裝l〇6a之標準（例如，插 腳頌型或插腳數目）改變時，控制單元4〇2重新量測在具有 改變之標準的半導體積體電路封裝l〇6a之I/O端子電接觸 測試板104之測試端子時施加至板1〇8的荷重，將重新量測 127748.doc -14- 200849456 得之荷重儲存於記憶體406中，且在測試具有改變之標準 的半導體積體電路封裝l〇6a時基於儲存於記憶體4〇6中之 荷重而分別控制複數個轉移單元11〇之功率。 圖5為說明根據本發明之實施例之控制半導體測試設備 之方法的流程圖。如圖5所示，在藉由使用板1〇8及複數個 轉移單元110而將具有安裝於上面的半導體積體電路封裝 106a之托盤106按壓至測試板104上時，分別量測施加至複 數個荷重元3 02的荷重（W丨及W2)(5〇2)。比較量測得之荷重 與預疋何重，且计异3：測得之荷重與預定荷重之間的差 異，亦即，絕對值（dl及d2)(504)。 此處，預定荷重為在將托盤1〇6完全黏著至測試板1〇4且 因此半導體積體電路封裝l〇6a完全插入至插口 1〇4a中時的 荷重。因此，在量測得之荷重（W1及W2)小於預定荷重 時’判定托盤1 06未完全黏著至測試板丨〇4。然而，準備了 可容許誤差範圍，且在絕對值（dl及d2)處於可容許誤差範 圍中時，承認托盤106充分黏著至測試板1〇4，且因此可正 常測试半導體積體電路封裝1 〇 6 a。 判定絕對值（dl及d2)是否處於可容許誤差範圍中，且在 判定絕對值（dl及d2)處於可容許誤差範圍中時（在5〇6處為 疋）’將板108之當前位置設定為最終位置（5〇8)。此處 最終位置意謂在板108將托盤106按壓至測試板ι〇4上以將 半導體積體電路封裝106a充分插入至插口 1〇4a中且因此可 正常測試半導體積體電路封裝l〇6a時板1〇8的位置。在板 108未接近最終位置之情況下，半導體積體電路封裴Μ。 127748.doc -15- 200849456The power of the plurality of transfer units is adjusted to move the board by the calculated transfer distance. The relative position of the board to the test board during movement of the board is controlled such that the 1/〇 terminals of the semiconductor integrated circuit packages electrically contact the test terminals of the test board. The method further comprises: measuring a load applied to the board when the I/O terminal of the semiconductor integrated circuit package is electrically connected to the test terminal of the test board; storing the measured load; and testing the same When the semiconductor integrated circuit package is packaged, the material of the plurality of transfer units is controlled (4) to generate the same load as the stored load. In addition, when the standards of the semiconductor integrated circuit packages to be tested are changed, the method further comprises: re-measuring the 1/0 first-order electrical contact of the semiconductor integrated circuit packages having the standard of the change The load applied to the board when the test terminal of the test board is stored; the re-measurement and the weight of the test having the change are stored, and the package is controlled by the load of the load. The rate of the plurality of transfer units. ~ 127748.doc •10- 200849456 Compares the weight of the measured > π ^ with a predetermined load, and when the difference between the measured load and the predetermined load exceeds the predetermined allowable error range 'Re-adjusting the loads generated by the plurality of transfer units to reset the position of the board. Calculating the difference between the load and the predetermined load, and calculating the difference between the weight of the equal amount and the predetermined load; the weight of the load measured in the equal amount The difference between the predetermined tolerances is set to a final position; and the difference between the measured value = the load and the predetermined load is not within the predetermined allowable error % in the range, resetting the position of the board in consideration of these differences. The final position of the board is a position of the board when the semiconductor integrated circuit packages are sufficiently adhered to the test board to enable testing of the semiconductor integrated circuit packages. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments The embodiments are described below by way of additional figures to illustrate the invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic diagram illustrating a semiconductor test apparatus in accordance with an embodiment of the present invention. As shown in FIG. 1, the test board 1 〇 4 is provided in the test chamber 1 〇 2, and the tray 106 疋 is located in front of the test board 104. The tray 106 is for receiving a plurality of semiconductor integrated circuit packages 1 mounted thereon. The trays 1 to 6 having the semiconductor body package 106a mounted thereon are transferred to a necessary step in the semiconductor manufacturing process by a separate loader. After the tray 丨〇 6 is tightly adhered to 127748.doc • 11 - 200849456 / 忒 J 忒 1 10 04 , the semiconductor integrated circuit package 丨〇 6a is inserted into the socket 104a formed on the test board 104 and electrically connected to Socket 1 〇牦. In order to make the tray 1〇6 tightly adhere to the test board 1〇4, the board 1〇8 and the plurality of transfer sheets 110 are provided. Figure 1 illustrates a portion of each of a plurality of transfer units 110, but Figures 2 and 3 illustrate all portions of each of a plurality of transfer units 11A. A plurality of transfer units 110 and plates 1〇8 transfer the trays 1〇6 to the test panel 104, and then press the tray 〇6 onto the test panel 〇4. The test board 1〇4, which is called a high-precision positioning (hi_fix) board, is a unit for electrically connecting the semiconductor integrated circuit package 16a and the test circuit U2. The test circuit 112 transmits and receives a test signal in the case where the semiconductor integrated circuit package 1〇6a is inserted into the test board 1〇4, and thus determines whether or not the semiconductor integrated circuit package 106a is operating normally. The test circuit 112 is mounted outside the test chamber 1〇2. In order to properly test the semiconductor integrated circuit package 1?6a' mounted on the tray 106, all of the semiconductor integrated circuit packages 1?6a must be correctly inserted into the sockets i?4a of the test board 104. Therefore, parallel alignment between the tray 〇6 and the test panel 〇4 is important. The distances L1 and L2 between the board 108 and the test board 1〇4 are different from each other as shown in FIG. 1 (Li off [2), and the tray 1〇6 has one of the larger of the distances L1 and L2. The side cannot sufficiently approach the test board 104' and thus some of the semiconductor integrated circuit packages 1〇6a cannot be inserted into the socket 104a. However, it is impossible to test the corresponding semiconductor integrated circuit package 10?' or it is possible to obtain an unreliable test result of the corresponding semiconductor integrated circuit package 1?6a. Further, the degree to which the plurality of transfer units 110 and the plates 108 press the tray 106 is also important. 127748.doc -12- 200849456 is also important. When the excessive load is applied to press the tray 1〇6, the semiconductor integrated circuit package 106a or other equipment may be damaged, and when a small load is applied to press the tray 1〇6, the semiconductor integrated circuit package 1〇 cannot be sufficiently inserted into Socket l〇4a. 2 is a perspective view of a semiconductor test apparatus in accordance with an embodiment of the present invention. 3 is a cross-sectional view of the transfer unit of the semiconductor test apparatus of FIG. 2, and specifically illustrating the configuration of each of a plurality of transfer units. As shown in Figures 2 and 3, the plurality of transfer units 110 have the same configuration, and substantially the same portions of each of the plurality of transfer units U are represented by the same reference numerals. The configuration of a transfer unit 11A will be described below. The rotational force of the motor 2〇2 for generating power is transmitted to the lead screw 210 via the first pulley 2〇4' belt 206 and the second pulley 208. The lead screw 210 is rotated by a rotational force. The moving member 212 is coupled to the lead screw 21A. The rotational motion of the lead screw 21 is converted into a reciprocating motion of the moving member 212. The reciprocating motion of the moving member 传输] is transmitted to the board 108 via the lever 214, and thus is related to the transfer of the board 1〇8. Therefore, the panel 1 () 8 reciprocates in the direction of the arrow A due to the rotational force of the motor. Since the rod 214 and the plate (10) are mechanically coupled via the link member 2i6, it is possible to control the parallel alignment between the plate 108 and the test plate 1〇4 by differently adjusting the pressure applied by the plurality of transfer units 11A. . Reference numeral 218 in Fig. 2 denotes a diaphragm of the test chamber 丨02, and only a portion of the diaphragm 218 is illustrated. A portion of each of the rod 214 and the plate 1 () 8 is positioned inside the diaphragm 218 (also #, in the test chamber 102), and a plurality of transfer units no are positioned outside the diaphragm 218 (ie, the test chamber) Room ι〇2 outside). 127748.doc -13- 200849456 The thermal insulation material 22 around the middle portion of the rod 214 is used to prevent the test chamber 1 〇 2 from losing heat via the rod 214. In FIG. 3, the load cell 302 is mounted between the moving member 212 and the rod 214. The moving member 212 and the rod 214 are connected by a one-way brake 304. As the moving port P member 2 12 moves toward the plate 1 〇 8, the pressure is transmitted to the plate 1 〇 8 via the moving member 2 12, the load cell 312 and the cup 214. Here, the pressure (i.e., the load) is measured by the load cell 3 〇2. That is, the load cell 302 detects the load applied when the board 1 〇 8 presses the tray 106 onto the test board 104. 4 is a block diagram of a control system of the semiconductor test equipment of FIG. 2. The control unit 402 controls a plurality of transfer units 11 经由 via a plurality of drive circuits 404, respectively, as shown in FIG. Specifically, the control unit 4〇2 controls the plurality of transfer units 110 based on the loads measured by the load cells 3〇2 respectively provided on the plurality of transfer units 11〇, and thus controls the control panel 1〇8 and The relative positions of the 4 plates 104 are measured such that the semiconductor integrated circuit package terminals electrically contact the test terminals formed in the sockets 1 of the test board 1〇4. In addition, the control unit 402 measures the load applied to the board when the I/O terminal of the semiconductor integrated circuit package 1 is electrically contacted with the test terminal of the test board 104, and stores the measured load in the memory 4〇6. And controlling the power of the plurality of transfer units 以1〇 to test the semiconductor integrated circuit package 〇6a to generate the same load as the load stored in the memory 〇6. When the standard (for example, the pin type or the number of pins) of the semiconductor integrated circuit package 16a to be tested is changed, the control unit 4〇2 re-measures the semiconductor integrated circuit package 10 6a having the changed standard. When the I/O terminal electrically contacts the test terminal of the test board 104, the load applied to the board 1〇8 is stored in the memory 406, and the load is re-measured in the memory 406, and the test has a change standard. The semiconductor integrated circuit package 100a controls the power of the plurality of transfer units 11 基于 based on the load stored in the memory 4 〇 6 . Figure 5 is a flow chart illustrating a method of controlling a semiconductor test device in accordance with an embodiment of the present invention. As shown in FIG. 5, when the tray 106 having the semiconductor integrated circuit package 106a mounted thereon is pressed onto the test board 104 by using the board 1〇8 and the plurality of transfer units 110, the measurement is applied to the plural The load of the load cell 3 02 (W丨 and W2) (5〇2). The measured load is compared with the preload and the difference is 3, and the difference between the measured load and the predetermined load, that is, the absolute value (dl and d2) (504). Here, the predetermined load is the load when the tray 1〇6 is completely adhered to the test board 1〇4 and thus the semiconductor integrated circuit package 16a is fully inserted into the socket 1〇4a. Therefore, when the measured load (W1 and W2) is less than the predetermined load, it is judged that the tray 106 is not completely adhered to the test board 丨〇4. However, an allowable error range is prepared, and when the absolute values (dl and d2) are in the allowable error range, the tray 106 is sufficiently adhered to the test board 1〇4, and thus the semiconductor integrated circuit package 1 can be normally tested. 〇 6 a. Determine whether the absolute values (dl and d2) are within the allowable error range, and when determining that the absolute values (dl and d2) are within the allowable error range (疋 at 5〇6), set the current position of the board 108. For the final position (5〇8). The final position here means that the tray 106 is pressed onto the test board ι 4 at the board 108 to sufficiently insert the semiconductor integrated circuit package 106a into the socket 1 4a and thus the semiconductor integrated circuit package 16a can be normally tested. The position of the board 1〇8. In the case where the board 108 is not near the final position, the semiconductor integrated circuit is sealed. 127748.doc -15- 200849456
未充分插入至插口 104a中。另一方面，在板108以過度大 於對應於最終位置之荷重的荷重而按壓托盤106之情況 下，半導體積體電路封裝l〇6a過度插入至插口 l〇4a中，且 因此可能會損壞。因此，為了達成正常測試半導體積體電 路封裝106a，複數個轉移單元11〇向板1〇8施加適當荷重以 使得板108到達最終位置。出於此原因，絕對值（dl&d2)較 佳處於可容許誤差範圍内。在絕對值（dl及d2)中之僅一者 處於可容許誤差範圍内且絕對值（dl及d2)中之另一者偏離 可容許誤差範圍的情況下，判定托盤106之具有偏離可容 許誤差範圍之絕對值的部分未充分黏著至測試板1〇4。因 此’在此情況下，定位於托盤1〇6之具有偏離可容許誤差 範圍之絕對值的位置處之轉移單元110產生較大荷重，藉 此使托盤106之相應部分較為緊密地黏著至測試板1〇4。 判定絕對值（dl及d2)是否處於可容許誤差範圍中，且在 判定絕對值（dl及d2)不處於可容許誤差範圍中時（在5〇6處 為"否π)，重新調整複數個轉移單元i i 〇的荷重以允許絕對 值（dl及d2)處於可容許誤差範圍中，且因此重新設定板1〇8 之位置（510)。 圖6為說明根據本發明之另一實施例之半導體測試設備 的透視圖。如圖6所示，提供四個轉移單元61〇，且該四個 轉移單元610獨立地控制施加至板6〇8之四個位置的荷重 因此較為精密地控制托盤1〇6至測試板1〇4上之黏著程度 部件216的連桿部件 向上、向下、向右及 此處，較佳使用不同於圖2之連桿 616，其可在所有方向上移動（亦即， 127748.doc -16 - 200849456 向左）。 自以上描述顯而易見，本發明提供一種半導體測試設備 及一種用於控制该半導體測試設備之方法，在該半導體測 試設備中荷重感應器（荷重元）分別安裝於轉移單元上而並 非測試板或托盤上，以使得轉移單元即使在待測試之半導 體積體電路封裝的標準改變且因此使用新托盤或新測試板 時仍可使用，從而為低價的。 另外，由於荷重元分別安裝於複數個轉移單元上，因此 有可能經由半導體積體電路封裝與測試板之間的平行控制 而達成半導體積體電路封裝與測試板之間的正確接觸。 雖然已展示並描述了本發明之實施例，但熟習此項技術 者將瞭解可在不脫離本發明之原理及精神的情況下對此等 實&例進行改變，其中本發明之範嗜界定於申請專利範圍 及其等效物中。 【圖式簡單說明】 圖1為說明根據本發明之一實施例之半導體測試設備的 示意圖； 圖2為根據本發明之實施例之半導體測試設備的透視 圖， 圖3為圖2之半導體測試設備之轉移單元的剖視圖； 圖4為圖2之半導體測試設備之控制系統的方塊圖； 圖5為說明根據本發明之實施例之控制半導體測試設備 之方法的流程圖；且 圖6為《兒明根據本發明之另一實施例之半導體測試設備 127748.doc •17- 200849456 的透視圖。 【主要元件符號說明】 102 測試腔室 104 測試板 104a 插口 106 托盤 106a 半導體積體電路封裝 108 板 110 轉移單元 112 測試電路 202 馬達 204 第一滑輪 206 皮帶 208 第二滑輪 210 導螺桿 212 移動部件 214 桿 216 連桿部件 218 膜板 220 熱絕緣材料 302 何重元 304 單向制動器 402 控制單元 404 驅動電路 127748.doc -18 - 200849456 406 記憶體 608 板 610 轉移單元 616 連桿部件 A 箭頭 LI 距離 L2 距離Not fully inserted into the socket 104a. On the other hand, in the case where the board 108 presses the tray 106 with a load excessively larger than the load corresponding to the final position, the semiconductor integrated circuit package 16a is excessively inserted into the socket 10a, and thus may be damaged. Therefore, in order to achieve normal testing of the semiconductor integrated circuit package 106a, a plurality of transfer units 11 施加 apply an appropriate load to the board 1 〇 8 to bring the board 108 to the final position. For this reason, the absolute value (dl & d2) is preferably within the allowable error range. In the case where only one of the absolute values (dl and d2) is within the allowable error range and the other of the absolute values (dl and d2) deviates from the allowable error range, the determination tray 106 has a deviation tolerance The portion of the absolute value of the range is not sufficiently adhered to the test board 1〇4. Therefore, in this case, the transfer unit 110 positioned at the position of the tray 1〇6 having an absolute value that deviates from the allowable error range generates a larger load, whereby the corresponding portion of the tray 106 is more closely adhered to the test board. 1〇4. Determine whether the absolute values (dl and d2) are within the allowable error range, and when determining that the absolute values (dl and d2) are not within the allowable error range ("no π at 5〇6), re-adjust the complex number The load of the transfer unit ii 〇 is such that the absolute values (dl and d2) are allowed to be in the allowable error range, and thus the position of the plate 1〇8 is reset (510). Figure 6 is a perspective view illustrating a semiconductor testing apparatus in accordance with another embodiment of the present invention. As shown in FIG. 6, four transfer units 61A are provided, and the four transfer units 610 independently control the load applied to the four positions of the plates 6〇8, thereby controlling the trays 1〇6 to the test board 1 more precisely. 4, the link member of the adhesive degree member 216 is upward, downward, rightward, and here, preferably using a link 616 different from that of FIG. 2, which is movable in all directions (ie, 127748.doc -16) - 200849456 to the left). As apparent from the above description, the present invention provides a semiconductor test apparatus and a method for controlling the semiconductor test apparatus in which load sensors (load cells) are respectively mounted on a transfer unit instead of a test board or a tray In order to make the transfer unit usable even when the standard of the semiconductor integrated circuit package to be tested is changed and thus a new tray or a new test board is used, it is inexpensive. In addition, since the load cells are respectively mounted on the plurality of transfer units, it is possible to achieve proper contact between the semiconductor integrated circuit package and the test board via parallel control between the semiconductor integrated circuit package and the test board. While the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art In the scope of patent application and its equivalent. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a semiconductor test apparatus according to an embodiment of the present invention; FIG. 2 is a perspective view of a semiconductor test apparatus according to an embodiment of the present invention, and FIG. 3 is a semiconductor test apparatus of FIG. Figure 4 is a block diagram of a control system of the semiconductor test equipment of Figure 2; Figure 5 is a flow chart illustrating a method of controlling a semiconductor test equipment in accordance with an embodiment of the present invention; and Figure 6 is A perspective view of a semiconductor test apparatus 127748.doc • 17-200849456 in accordance with another embodiment of the present invention. [Main component symbol description] 102 Test chamber 104 Test board 104a Socket 106 Pallet 106a Semiconductor integrated circuit package 108 Board 110 Transfer unit 112 Test circuit 202 Motor 204 First pulley 206 Belt 208 Second pulley 210 Lead screw 212 Moving part 214 Rod 216 Link member 218 Membrane plate 220 Thermal insulation material 302 Heavy element 304 One-way brake 402 Control unit 404 Drive circuit 127748.doc -18 - 200849456 406 Memory 608 Board 610 Transfer unit 616 Link member A Arrow LI Distance L2 Distance
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