200848754 九、發明說明： 【發明所屬之技術領域】 本發明係有關連接器介面的測試裝置及方法，尤I是有關主 機板的擴充座插接介面的測試裝置及方法。 【先前技術】 主機板製作完成之後，需經過各種測試，以確定其品質是否 合於需求。有各種測試主機板的專利技術，例台灣專利第126〇417 號揭示的自動化電路板測試致動器系統；台灣專利公告第59〇219 號揭不的主機板測試機；台灣專利公告第55684〇號揭示的主機 板測試治具等。 傳統測試主機板的擴充座插介面（D〇cking c〇nnect〇r)的 方式，係使主機板的擴充座插接介面連接擴充座（D〇cking)底 座，置於擴充座功能測試治具（俗稱黑金剛治具），來測試擴充 座插接介面的品質是否合於需求；測試時需約需細秒。 舰測試域板的齡錄齡面需要制賴充底座及 擴充触能_絲具，其赋設備的_甚乡，且細試所需時 間長達300秒，甚為花費時間。 【發明内容】 本發明的主要目的，在提供_種主機板的擴充細接介面的 測試裝置及方法，可雜測試所需的時間，提高職效率。 本發明的另-目的’在提供—種主機板的擴充座插接介面的 測试裝置及方法，可使用-般的測試治具，可減少測試設備所需 的費用。 5 200848754 本發明主機板的擴充座插接介面的測試裝置，係供利用自動 測試設備進行測試者，包括： 一測試板，具有一導接端部、複數訊號線及複數接地線；該導接 端部具有複數端子分別電連接該等訊號線及該等接地線；該每一 訊號線分別電連接至一該接地線； 其中，該導接端部係與一主機板的擴充座插接介面相對應，俾當 该導接端部與該擴充座插接介面電連接後，該擴充座插接介面的 每一訊號線分別透過與該測試板電的一訊號線、一接地線及該擴 充座插接介面的一接地線構成一測試迴路，藉由該阻抗值得知該 擴充座插接介面的品質狀況資料。 其中該測试板之各訊號線及一接地線之間串接有一電阻。 其中该測試板的訊號線中至少有兩訊號線共同電連接至一接地 線。 其中該擴充座插接介面的每一訊號線分別電連接至該主機板上 相對應的各訊號測試點，且該擴充座插接介面的各接地線分別電 連接至該主機板上相對應的各接地測試點。 本發明主機板的擴充座插接介面的測試方法，係用以節省測 試時間提升測試效率者，包括如下步驟·· ⑴使-測試板電連接-主機板的擴充座插接介面，而使該擴充 座插接介面的每—訊號線與該擴充座插接介面的—接地線構成 一測試迴路； ⑵使-自_敢備賴數探針分卿連接至制試迴路的 6 200848754 兩端的訊號測試點及接地測試點； (3) 使該自動測試設備量測每一該測試迴路的阻抗值； (4) 藉由该阻抗值得知該擴充座插接介面之品質狀況。 本發明的其他目的、功效，請參關式及實施例，詳細說明 如下。 【實施方式】. 圖1所示者，係為本發明主機板的擴充座插接介面的測試裝 置。本發_測試裝置_以節社量測試_而得以測得擴^ 座插接介面之接腳品質者，本實施财，包括—測試板1〇具有 一導接端部Π、複數訊號線s (I)、s (2)、s (3) ."S (η)及 複數接地線G (1) ...G (m);導接端部u具有複數端子⑴分別 電連接複數减線S⑴、S⑵、s⑶."s⑷及複數接地線 G (1) ...G (m);各訊號線s ⑴、S (2)、s ⑶...s (n)與接 地線連接端G⑴(m)之間係分別串接有—⑴、R (2)、R (3) ...R (n)〇 在本實施例中，是由每三條訊號nS(1)、s⑵、s⑶共 同連接至-接地線，例如三訊號線s⑴、s⑵、s⑶分別串 接-電阻R(1)、R⑵、R⑶後，共同連接至一接地線G⑴。 設計上’訊號線連接端S⑴、S⑵、s⑶...s⑷的數量為 η，而接地線連接端G (1) ...G (m)的數量為m，n>m，㈣ 時，可使a條訊麟連接端制連接—條接地線連接端。 本實施例中，轉接端部11係為一公插接座U1;而主機板 200848754 20的擴充座插接介面21具有-可與導接端部u相對應插接之母 插接座21卜擴充座插接介面21另具有複數訊號線&⑴、& (2)、& (3) “.S丨(η)、複數接地線線Gi⑴…G丨⑷及複數 接腳212;複數獅212分別連接訊號線&⑴、&⑵、Si(3)〜S| (η)及接地線線G, (1) ··.& (m)。複數接腳212分別電連接至 主機板20上相對應的訊號測試點&⑴、3。（2)、S(j(3)..s 〇 (η)及接地測試點 G。（1)、G。（2)、G。（3)…G。（m)。 當測試板10與擴充麵接介面21 _電連接時，各訊號線 S(1)、S(2)、S(3) ...S (η)分別電連接至主機板2〇上相對 應的各訊號測試點SQ(1)、&(2)、&(3)…&(η)，且各接 地線G (1) ."G (m)分別電連接至主機板2〇上相對應的各接地 測試點G〇 (1)、G〇 (2)、G。（3)…G。（m);各訊號測試點s〇 (1)、 S〇(2)、S〇(3)…S〇(n)即分別與一接地測試點(^(丨）、^。）、 Go (3)…Go (m)之間構成一測試迴路。例如訊號測試點& (】） 經由擴充座插接介面21的訊號線& (1 )、測試板1〇的訊號線s (1)、電阻R(l)、接地線G(l)及擴充座插接介面21的接地線卩! (1)電連接至接地測試點G〇 (1 )，而構成一測試迴路。 測試之前，需先將主機板20上原本個別電連接至擴充座接 介面21的接地線線Gi (1)…Gi (m)的接地線，斷開成個別電連 接至接地線G(r"G。（m)的接地線。 接著需求得測試板10上各端點之阻抗值，其係藉由一自動 測試設備（ATE，Automatic Test Equipment)30 取得，其方式係 200848754 藉ATE 30之複數探針分別連接主機板2〇的各個訊號測試點& (1 )、s。（2)、S〇(3) ···&(!〇 及各個接地測試點 G|)(1)、Gq(2)、 G〇(3)*"GG(m)’以測量各訊號測試點 Sg(1)、&(2)、 〇 (η)分別與一接地測試點G0 (1)、G。（2)、G。（3)…仏之 間構成的測試迴路的阻抗值。 本實施例，是以擴充座插接介面21的訊號線& (丨）、& (2)、 S! (3) "A (η)約有91個，而接地線線Gl (1)(m)僅有 33個，故使用約3條訊號線共同與一條接地線連接構成一測試迴 路之方式，涵蓋财的減賴接崎制試，進_免使單條 接地線連接端上的電流過大。 藉由ATE 30測量各個測試迴路的阻抗值，再由各測試迴路 的阻抗值，即可判斷擴充座插接介面21的那一條訊號線、那一 個訊號線的接腳、那-條接地線、那—健地線的接腳有問題。 明參考圖1、3所示，圖3為本發明以三個測試點對應不同 條件之測試阻抗值及實際測得之阻抗值及減的對關；在本圖 中係以訊號測試點SQ (1)、S。（2)、S。（3)舉例說明，其中， 則1是訊號點S〇( 1)在主機板20端之阻抗值；R02是訊號點s。⑵ 在主機板20端之阻抗值；則3是訊號點s〇 (3)在主機板端之阻 抗值。請-併參考圖丨所示，擴充座插接介面21上三條訊號線 端& (1)、& (2)、& (3)，分別串接測試板10上的三個電阻R (1)、R (2)、R (3)(電阻值分別為R1、R2、R3)及共同電連接 至其-條接鱗G (1)，並電連接至擴紐齡面21的接地線 200848754 G, (1)’且訊號線Sl (1)、Si (2)、Si (3)及接地線& (u分別 電連接至主機板20的訊號測試點&(〗）、&(2)、&(3)及 接地測試點G。（ 1)，構成三條測試迴路。利用腿3〇的四支探 針为別連接主機板20的訊號測試點& (丨）、& ( 2 )、& ( 3 ) 與接地測試點G。⑴’職擴充座插接介面21的三條訊號線& ⑴、S丨（2)、S丨（3)分別與一個接地線Gi⑴構成的三條測 试迴路之阻抗值’可獲得如圖3所賴結果。若該等訊號線& ⑴、Si (2)、S丨(3)，電阻R⑴、R⑵、R⑶與接地線G丨 (1)構成的三條測試迴路無任何導接上的問題，則各測試迴路 被測得的阻抗值分別為R01// R1、R〇2// R2及R〇3//肋；若各 測试迴路被測得的阻抗值分別為R(n、R〇2及R〇3，則表示各測試 迴路應有導接上的問題。 若僅測量訊號線& (1)、電阻R (1)及接地線^ (1)構成 的測試迴路的電阻值，可獲得下列可能的數值： (A)若該擴充座插接介面21的訊號線& (1)、訊號線Si (1)的 接腳、接地線G! (1)及接地線G! (1)的接腳均良好時，測 到的阻抗值為R01及R1並聯之值； (B)若該擴充座插接介面21的訊號線Si (1)的接腳空焊不良時 該測試迴路是斷開的狀態，測到的阻抗值為訊號測試點別1 在主機板上之阻抗R01; (C)右§亥擴充座插接介面21的接地線Gi (1)的接腳空禪不戸時 該測試迴路是斷開的狀態，測到的阻抗值為訊號測試點 200848754 在主機板上之阻抗R〇l ; ⑻若該擴充錢接介面21的訊號線&⑴與其他的訊號線短 路，例如，訊號線&⑴與訊號線Si⑵爾，而該擴充 座插接介面21的接地線&⑴的接腳焊接良好時，測到的 阻抗值為肋卜即2與耵及咫並聯之值； (E)若該擴充座插接介面21的訊號線&⑴與該擴充座插接介 面21的接地線&⑴短路時，_的阻抗值為〇，· 利用上述該’可建立各測試迴路的各種阻抗值變化表。下 次測試時，將腿30量測各測試迴路獲得的阻抗值，與相對應已 知的阻抗值變化表相比較，即可得知擴充座插接介面21的各訊號 線、各訊麟連接端、各接地線及各接地線連接端導接上是否良 好，或者各訊麟及各祕線之間衫餘關航、各訊號線 連接端及各接地線連接端衫有冷焊的航等各翻壞狀況。 請參考圖1、2所示。本發明主機板的擴充座插接介面的測 試方法’係用以節省測試時間提升測試效率者，包括如下步驟： (1) 將-測试板10電連接至-主機板20的擴充座插接介面21， 令該擴充座插接介面21的每一訊號線Si(1)、Si(2)、Si(3). .Si (幻分別透過該測試板切上之一電阻!^)、^^、^^·^ (η)與該擴充座插接介面21的一接地線線& (1) ···& (m)構 成一測試迴路； (2) 使一自動測忒設備(ATE)30的複數探針分別電連接該主機板 20上之各sil號測试點Sg (1)、S〇 (2)、s〇 (3)…S〇 (η)及接 11 200848754 地測試點 G〇 (1)、G〇 (2)、G。（3)…G〇 (m); (3) 使該自動測試設備量3〇測得到每一測試迴路的阻抗值· (4) 比對原本所量測得知之主機板2〇各測試點& (丨彡、^0、 S〇 (3)…S。（η)之阻抗值，與量測該測試迴路所得的阻抗值， 而分析得知該擴充座插接介面21的品質狀況。 其中該各測試迴路的詳細結構係如前述本發明的測試裝置 中所揭示者。亦可如前述本發明關試裝置巾所揭示的方式建立 該各測試迴路良好狀態下_抗絲，作為與量獅測試迴路所 得的阻抗值的比較依據，而分析得知該擴充座插接介面21的品 質狀況。 ασ 本發明利卿m板使主機板的擴充座插接介面的各訊號線 與一接地線之間串接一電阻構成一測試迴路，再利用畑量晦 -測試迴路錄抗值，再使雜抗贿縣所量娜知之主機板 各測試點之阻抗值、或預鍵立的阻抗值表比對，即可得知該擴 充座插接介_品質狀況。測試所需時間僅為2秒，較傳統的測 試所需_的時間節省298秒。因此本發明可簡化測試流程大 幅提高測試效率。又本發明使用的測試板結構簡單製作費用便 且且利用叙吊用的ATE做為測量各測試迴路的阻抗值的設 備，不需如傳統的戦方式，需購買特別的擴充座底座及擴充座 功能測❹具，13此可降麵買顺設備的成本。 以上所讀’僅為_本翻技術内容之實_，任何孰采 本項技藝_本翻所為之修飾、變化，·發_= 200848754 利範圍，而不限於實施例所揭示者。 13 200848754 【圖式簡單說明】 圖1為本發明的測試裝置的實施例示意圖。 圖2為本發明主機板的測試方法的流程圖。 圖3為本發明以三個測試點對應不同條件之測試阻抗及實際測得之阻 抗值及意義對照圖。 【主要元件符號說明】 10測試板 11導接端部 111端子 20主機板 21擴充座插接介面 211母插接座 212接腳200848754 IX. Description of the Invention: [Technical Field] The present invention relates to a test device and method for a connector interface, and more particularly to a test device and method for a docking connector interface of a main board. [Prior Art] After the motherboard is manufactured, various tests are required to determine whether the quality meets the requirements. There are various patented test board technologies, such as the automated circuit board test actuator system disclosed in Taiwan Patent No. 126〇417; the motherboard test machine disclosed in Taiwan Patent Notice No. 59〇219; Taiwan Patent Notice No. 55684〇 No. reveals the motherboard test fixtures and so on. The traditional test board expansion socket interface (D〇cking c〇nnect〇r) is such that the expansion board socket interface of the motherboard is connected to the docking base (D〇cking) base, and is placed in the expansion seat function test fixture. (commonly known as the black diamond fixture), to test whether the quality of the docking interface of the docking station is in line with the demand; the test takes about a fine second. The age-old age of the ship test domain board needs to be based on the base and the expansion of the touch energy _ silk, which gives the device a very good time, and the time required for the fine test is up to 300 seconds, which is very time consuming. SUMMARY OF THE INVENTION The main object of the present invention is to provide a test apparatus and method for expanding the fine interface of a motherboard, which can improve the efficiency of the job by the time required for the test. Another object of the present invention is to provide a test apparatus and method for a docking interface of a motherboard, which can use a general test fixture to reduce the cost of the test equipment. 5 200848754 The test device for the expansion plug connector interface of the motherboard of the present invention is for testing by using automatic test equipment, comprising: a test board having a conductive end portion, a plurality of signal lines and a plurality of ground lines; the guiding The terminal has a plurality of terminals electrically connected to the signal lines and the ground lines; each of the signal lines is electrically connected to a ground line; wherein the guiding end is connected to a docking station of a motherboard Correspondingly, after the guiding end is electrically connected to the docking connector interface, each signal line of the docking station plugging interface transmits a signal line, a grounding line and the extension respectively connected to the test board. A grounding wire of the socket interface constitutes a test loop, and the quality information of the docking interface of the docking station is obtained by the impedance value. A resistor is connected in series between each signal line and a ground line of the test board. At least two of the signal lines of the test board are electrically connected to a ground line. Each of the signal lines of the docking station is electrically connected to a corresponding signal test point on the motherboard, and each grounding line of the docking station is electrically connected to the corresponding board. Each ground test point. The test method for the expansion socket insertion interface of the motherboard of the invention is used to save the test time and improve the test efficiency, and includes the following steps: (1) electrically connecting the test board to the expansion socket of the motherboard, and Each of the signal lines of the docking station interface and the grounding line of the docking station of the docking station constitute a test loop; (2) the signal of the two ends of the 200848754 connecting the test probe to the test circuit The test point and the grounding test point; (3) causing the automatic test equipment to measure the impedance value of each test circuit; (4) by using the impedance value, the quality status of the docking station interface is known. Other objects and effects of the present invention are described in detail in the following description. [Embodiment] The one shown in Fig. 1 is a test device for the docking station of the motherboard of the present invention. In the present invention, the test device has been tested for the quality of the pin of the plug-in interface. In this implementation, the test board 1 has a lead end and a complex signal line. (I), s (2), s (3) ."S (η) and complex grounding wire G (1) ... G (m); the conducting end u has a plurality of terminals (1) electrically connected to the complex number Lines S(1), S(2), s(3)."s(4) and complex ground lines G (1) ... G (m); each signal line s (1), S (2), s (3)...s (n) is connected to the ground line The terminals G(1)(m) are respectively connected in series - (1), R (2), R (3) ... R (n) 〇 in this embodiment, by every three signals nS (1), s (2), s(3) is commonly connected to the ground line. For example, the three signal lines s(1), s(2), and s(3) are connected in series to the resistors R(1), R(2), and R(3), and are connected to a ground line G(1). The number of signal line connection terminals S(1), S(2), s(3)...s(4) is η, and the number of ground wire connection terminals G (1) ... G (m) is m, n > m, (4) Connect a link to the ground connection. In this embodiment, the adapter end portion 11 is a male connector socket U1; and the docking station connector interface 21 of the motherboard 200848754 20 has a female socket 21 that can be inserted corresponding to the guiding terminal portion u. The docking station plug-in interface 21 further has a plurality of signal lines & (1), & (2), & (3) ".S 丨 (η), a plurality of grounding lines Gi (1) ... G 丨 (4) and a plurality of pins 212; The plurality of lions 212 are respectively connected to the signal lines & (1), & (2), Si (3) to S | (η), and the grounding wire G, (1) ···& (m). The plurality of pins 212 are electrically connected Corresponding signal test points & (1), 3. (2), S (j (3)..s 〇 (η) and ground test points G on the motherboard 20 (1), G. (2), G. (3)...G. (m) When the test board 10 is electrically connected to the expansion interface interface 21 _, each signal line S(1), S(2), S(3) ... S (η) ) respectively electrically connected to corresponding signal test points SQ(1), &(2), &(3)...&(n) on the motherboard 2, and each ground line G (1) . ; G (m) is electrically connected to the corresponding ground test points G 〇 (1), G 〇 (2), G (3) ... G (m); each signal test point s on the motherboard 2 〇(1), S〇(2), S〇( 3)...S〇(n) forms a test loop with a ground test point (^(丨), ^.), Go (3)...Go (m) respectively. For example, signal test point & (]) The signal line & (1) through the expansion plug connector interface 21, the signal line s (1) of the test board 1 、, the resistor R (l), the ground line G (l), and the ground line of the docking station plug-in interface 21 1! (1) Electrically connected to the grounding test point G〇(1) to form a test loop. Before testing, the main board 20 should be electrically connected to the grounding wire Gi of the expansion mating interface 21 (1). )...Gi (m) ground wire, disconnected into a ground wire that is electrically connected to ground wire G (r"G.(m). Then the impedance value of each end point on test board 10 is required. An automatic test equipment (ATE, Automatic Test Equipment) 30 is obtained by the method of 200848754. The multiple probes of the ATE 30 are respectively connected to the respective signal test points & (1), s. (2), S〇 of the motherboard 2〇. (3) ···&(!〇 and each grounding test point G|)(1), Gq(2), G〇(3)*"GG(m)' to measure each signal test point Sg(1 ), & (2), 〇 (η) and a ground test point G0 (1), G. (2), G. (3) The impedance value of the test loop formed between 仏. In this embodiment, there are about 91 signal lines & (丨), & (2), S! (3) " A (η) of the docking connector 21, and the grounding line G1 (1) (m) only 33, so the use of about 3 signal lines together with a ground line to form a test loop, covering the cost of the reduction of the Qisaki test, into the single ground wire connection Overcurrent. The ATE 30 measures the impedance value of each test circuit, and then the impedance value of each test circuit can determine the signal line of the expansion socket interface 21, the pin of the signal line, the ground line of the signal line, That - there is a problem with the pin of the ground wire. Referring to Figures 1 and 3, Figure 3 is a comparison of the test impedance values corresponding to different conditions of the three test points and the actual measured impedance values and subtraction; in this figure, the signal test point SQ ( 1), S. (2), S. (3) For example, where 1 is the impedance value of the signal point S〇(1) at the end of the motherboard 20; R02 is the signal point s. (2) The impedance value at the end of the motherboard 20; then 3 is the impedance value of the signal point s 〇 (3) at the motherboard end. Please - as shown in the figure ,, the three signal line ends & (1), & (2), & (3) on the expansion socket interface 21 are respectively connected to the three resistors R on the test board 10 (1), R (2), R (3) (resistance values are R1, R2, R3, respectively) and are electrically connected to the strip-connected scale G (1), and are electrically connected to the ground of the expanded age face 21 Line 200848754 G, (1) 'and signal line Sl (1), Si (2), Si (3) and ground line & (u signal connection point & (), & respectively, electrically connected to the motherboard 20 (2), & (3) and ground test point G. (1), constitutes three test loops. The four probes using the legs 3〇 are signal test points & (丨), which are connected to the motherboard 20 & ( 2 ), & ( 3 ) and ground test point G. (1) Three signal lines & (1), S丨 (2), S丨 (3) of the expansion connector plug interface 21 and a ground wire The impedance values of the three test loops formed by Gi(1) can be obtained as shown in Fig. 3. If the signal lines & (1), Si (2), S (3), resistors R (1), R (2), R (3) and ground line G三(1) consists of three test loops without any problems on the lead, then each test loop is tested The impedance values are R01// R1, R〇2// R2 and R〇3//rib; if the measured impedance values of each test loop are R(n, R〇2 and R〇3, respectively) Indicates that each test circuit should have a problem with the conduction. If only the resistance value of the test circuit composed of the signal line & (1), the resistor R (1) and the ground line ^ (1) is measured, the following possible values can be obtained: (A) If the signal line & (1) of the docking station connector 21, the pin of the signal line Si (1), the grounding wire G! (1), and the grounding wire G! (1) are all good. The measured impedance value is a value of R01 and R1 in parallel; (B) if the pin of the signal line Si (1) of the expansion plug connector interface 21 is poorly soldered, the test loop is disconnected. The impedance value is the signal test point 1 on the motherboard R01; (C) the right § hai expansion plug connector 21 ground wire Gi (1) pin is empty when the test circuit is broken In the open state, the measured impedance value is the impedance of the signal test point 200848754 on the motherboard R〇l; (8) if the signal line & (1) of the expansion interface 21 is short-circuited with other signal lines, for example, the signal line &;(1) and signal line Si(2) When the pins of the grounding wire & (1) of the docking connector interface 21 are soldered well, the measured impedance value is the value of the ribs, that is, the parallel connection of 耵 and 咫; (E) if the docking station is inserted into the interface When the signal line of 21 & (1) is short-circuited with the ground line & (1) of the docking connector interface 21, the impedance value of _ is 〇, and various impedance value change tables for each test loop can be established by using the above. In the next test, the leg 30 is measured for the impedance value obtained by each test circuit, and compared with the corresponding known impedance value change table, the signal lines of the expansion docking interface 21 and the respective communication lines are known. Whether the end, the grounding wire and the grounding wire are connected at the connection end, or the air between the Xunlin and the secret lines, the connection ends of the signal lines, and the grounding wires of the grounding wires are cold-welded. Each situation is broken. Please refer to Figure 1 and Figure 2. The test method for the expansion socket interface of the motherboard of the present invention is used to save the test time and improve the test efficiency, and includes the following steps: (1) electrically connecting the test board 10 to the expansion socket of the motherboard 20 The interface 21 is such that each of the signal lines Si(1), Si(2), Si(3).Si of the expansion socket is inserted into the interface 21 (the phantom is respectively cut through the test board to cut a resistance! ^), ^ ^, ^^·^ (η) and a grounding wire of the expansion docking interface 21 & (1) ···& (m) constitute a test loop; (2) an automatic measuring device ( The plurality of probes of the ATE) 30 are electrically connected to the respective sil test points Sg (1), S〇(2), s〇(3), ...S〇(η) and the connection test of 200848754 on the motherboard 20, respectively. Point G〇(1), G〇(2), G. (3)...G〇(m); (3) Make the automatic test equipment amount 3 to measure the impedance value of each test loop. (4) Compare the original test panel 2 test points andamps (丨彡, ^0, S〇(3)...S. (η) the impedance value, and the impedance value obtained by measuring the test loop, and the quality condition of the docking connector interface 21 is analyzed. The detailed structure of each test circuit is as disclosed in the above-mentioned test device of the present invention. The test circuit can also be established in the manner disclosed in the above-mentioned test device to prevent the wire from being in a good state. Based on the comparison of the impedance values obtained by the test loop, the quality of the docking connector interface 21 is analyzed. ασ The invention is used to make the signal lines of the expansion board of the motherboard into a grounding line and a grounding wire. A series of resistors are connected to form a test loop, and then the measured value of the 晦-test circuit is recorded, and then the impedance value of each test point of the motherboard of the miscellaneous anti-bribery county or the impedance value of the pre-key is compared. Yes, you can know the expansion socket _ quality status. Test time required It takes 2 seconds to save 298 seconds compared with the time required for the traditional test. Therefore, the invention can simplify the test process and greatly improve the test efficiency. Moreover, the test board used in the invention has a simple structure and is easy to use and uses the ATE for the suspension. In order to measure the impedance value of each test circuit, it is not necessary to purchase a special expansion base and a docking function test cooker as in the conventional cymbal mode, and the cost of purchasing the shun equipment can be reduced. For the purpose of this _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 1 is a schematic view of an embodiment of a test apparatus according to the present invention. Fig. 2 is a flow chart of a test method of a motherboard according to the present invention. Fig. 3 is a test impedance corresponding to different conditions of three test points according to the present invention and an actual measured impedance value. And the meaning of the figure. [Main component symbol description] 10 test board 11 lead end 111 terminal 20 motherboard 21 expansion socket plug interface 211 female socket 212 pin
S (1)、S (2)、S (3)、S (η)訊號線 S! (1)、Si (2)、Si (3)、& (η)訊號線 G (1)、G (m)、Gi (l)、Gi (m)接地線 S〇(l)、S〇(2)、S〇(3)、S〇(n)訊號測試點 G〇 (1)、G〇 (2)、G〇 (3)、G〇 (m)接地測試點 30 ATE (1)、（2)、（3)、（4)分別為各步驟之編號S (1), S (2), S (3), S (η) signal line S! (1), Si (2), Si (3), & (η) signal line G (1), G (m), Gi (l), Gi (m) grounding wire S〇(l), S〇(2), S〇(3), S〇(n) signal test points G〇(1), G〇( 2), G〇(3), G〇(m) grounding test point 30 ATE (1), (2), (3), (4) are the number of each step