TW200832542A - Semiconductor structure and method for forming the same - Google Patents

Semiconductor structure and method for forming the same Download PDF

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TW200832542A
TW200832542A TW096102740A TW96102740A TW200832542A TW 200832542 A TW200832542 A TW 200832542A TW 096102740 A TW096102740 A TW 096102740A TW 96102740 A TW96102740 A TW 96102740A TW 200832542 A TW200832542 A TW 200832542A
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semiconductor structure
forming
layer
barrier layer
underlying metal
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TW096102740A
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Wen-Yung Fu
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Chipmos Technologies Inc
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Priority to TW096102740A priority Critical patent/TW200832542A/zh
Priority to US11/907,276 priority patent/US20080174011A1/en
Publication of TW200832542A publication Critical patent/TW200832542A/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0236—Shape of the insulating layers therebetween
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/024—Material of the insulating layers therebetween
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

200832542 九、發明說明： 【發明所屬之技術領域】 本發明係一種導電結構；特別是一種用於一半導體積體電路 之導電結構及其成形方法。 【先前技術】 凸塊電鍵於微電子(microelectronics)及微系統(micro system) Γ
專領域已發展出許多技術’諸如平面顯示器(f|at panei displays, FPD)與驅動晶片（driver ICs)的連接、砷化鎵晶片上的傳導線與^ 橋(air bridges)技術、以及LIGA技術中X-ray光罩的製作等，'均 於不同階段使用到該凸塊電鍍技術。 以電路板與1C晶片的連接為例，ic晶片可利用各種方式與電 路板連接，而其封裝方式主要便是利用凸塊（特別是金凸塊）電 鍍技術，將1C晶片中的襯墊與電路板電性連接。此技術不僅可大 幅縮小1C晶片的體積，亦使其可直接崁入電路板上，具有節省空 間、低感應及散熱能力佳等特性，加上電鍍製程的低成本優勢， 致使凸塊電鑛技術得以蓬勃發展。 典型的凸塊電鍍製程，例如金凸塊電鑛製程，需要在襯塾 (pad )上先行形成一底層金屬(un(jer ㈤技奶，底 為接合凸塊與襯塾之黏著料，亦於電鍍形成凸塊後，作為^電 =之用’使凸塊可以順獅成於底層金屬上方，並透過底層金 ，：、j塾紐賴，此在紐開始之前 面，除 他地方’形成至少-導電層，在凸塊電=後 再利用蝕刻方式，將該導電層去除。 導雷表面可能會具有部分粗糖表面’因此當 口各處料不-，而導致導電層的電阻增加。為解決上述問題者 200832542 習知技術形成平均厚度較厚之底層金屬或其他導電層，以改 ，層形成能產生斷點的缺失。但厚度增加的底I金屬或其他 層，其等，電阻會增加，且由於底層金屬主要功能係作為凸 塊”襯墊之麟層，其阻抗本身即較高，因此底層金屬若具有較 大之厚度，將使得凸塊與襯墊之間的阻抗更嚴重增加，不利 片與電路板之電性連結。上述情況皆會影響電鑛效果，使凸塊電 錢的良率降低，而需要進行後加卫重整或者廢棄該晶片。 有鑑於上舰失，本發明乃提供如τ之觀突破，以解決上 述問題。 、【發明内容】 本發明之-目的在於提供—種轉體結構，該半導體結構包 含一基材以及佈局於該基材上之一積體電路，藉由該半導體結構 上方形成一阻隔層，以構成一平坦的表面，使得一底層金屬可以 成形於該阻隔層之上，避免該由底層金屬所形成之導電層，產生 造成阻抗增加或不均勻之斷點。為達上述目的，本發明揭露一種 半，體結構，包含-鈍化層、-阻隔層及—底層金屬。該鈍化層 覆蓋於設有該積體電路之該基材上，形成實質上非平坦之一第一 上表面。該阻隔層成形於該鈍化層之上，形成實質上平坦之一第 二表面。而後該底層金屬（under-bumpmetal)，再成形於該阻隔層 ’ 之該第二表面上。 本發明更揭露一種形成上述半導體結構之方法，包含下列步 驟·於已佈局一積體電路之基材上，成形實質上具有一非平坦第 一表面之一鈍化層(passivationlayer);成形具有一實質上平坦第二 表面之阻隔層，以使該鈍化層平坦化；以及成形一底層金屬，於 該阻隔層之弟二表面上，以構成一電鑛程序之一導電介面。 為讓本發明之上述目的、技術特徵、和優點能更明顯易懂， 下文係以較佳實施例配合所附圖式進行詳細說明。 200832542 【實施方式】 、第1(a)圖至第ι(φ圖係顯示本發明之較佳實施例，以呈現一 具導電結構之半導體結構10之製造流程。 如第1(a)圖所示，該半導體結構1〇，包含一基材u以及一設 ?，基材11上方之鈍化層12，因基材u ±有積體電路佈局，^ =鈍化層12的表面並不平整；如糊所示，齡層12且有 ΐΐί平坦之第—上表面1G1。若直接於該第—上表面1〇1上形成 ^電之底層金屬’卿底層金屬將可能在第—上表面1〇 點’導致阻抗不均，使導電性不良。由於具有積體以 之基f 11於製造完成時，亦已一併形成純化層12 ’同時鈍化 地ΐ向性形成祕材U之上，無法騎各區域之不 同而求’對應形成各種不同之鈍化層，因此該第一上表面1〇 不平坦情況’無法藉由調整純化層12之形成來加以克服。 一甲明於該第一上表面101上先形成-阻隔層，例如 :认亞胺（Polyunide，ΡΙ)層13，利用該ρι層13之具 料特性’故將其覆蓋於該第一上表自1〇1，將可形成^有一定 之Η層13，並構成一實質上平坦之第二表面1〇2，： 圖所不。阻隔層亦可由其他具有絕緣 (） (Si02)等氧化物。 貝表风如一虱化矽 ，著，在該Π層13上方形成一底層金屬14，如 底層金屬M為鈦鶴合金所製成。由於P^13 、第一上表面101的不平整處，同時pi層η且右绍給 果，因此PI層所成形之第二表面1〇2係為一 ^緣效 金屬14可以連續地成形於該第二表面ϋ上，忐吏得底層 同時底層金屬14亦可成形為具有柄厚度之 ，^斷，。 相同或相異材料特性之導電層，使其導電性更為穩、他
著’在該底層金屬14上，成形—覆蓋層15，並於-頻定F 域成形-凸塊.如第1(_所示。凸塊16可藉由紐㈣H 200832542 由該覆蓋層is，成形於該該預定區域之底層金屬M上。 之揭露，本發明之半導體結構丨。，顧於鈍化層12 層阻隔層13之設計，可確保底層金屬14成形時不 供紐時之觀導電雜；㈣，基於上述設 Ρ声θ屬14無需為可能產生斷點的問題，而大幅增加Α 塊16與其接觸之部分所受到之導電阻抗，亦將大i 亡述之實施例僅用來例舉本發明之實施態樣，以及 =好ί徵’並非用來限制本發明之保護範疇。任何孰 ί 完成之改變或均等性之安排均屬於本發日^主'ίίϊ 圍本么明之權利保護範圍應以申請專利範圍為準。 、耗 【圖式簡單說明】 第1(a)圖至第1(d)係為本發明較佳實施例 立 揭露出本發明較佳實施例之結構示意圖。 衣杠不思圖，其亦 【主要元件符號說明】 1〇半導體結構 π基材 12鈍化層 U阻隔層 14底層金屬 U覆蓋層 16凸塊

Claims (1)

  1. 200832542 十、申請專利範圍： 1· 一種半導體結構，包含： 一基材； 一積體電路，佈局於該基材上； 一鈍化層（passivation layer)，覆蓋於設有該積體電路之該 基材上，成形實質上非平坦之一第一上表面；、 ^ 一阻隔層，成形於該鈍化層之上，成形實質上平坦之一第 二表面；以及 一底層金屬（under bump metal)，成形於該阻隔層之該第 二表面上。 2·如明求項1之半導體結構，更包含一凸塊（bump)，成形於該 底層金屬之上 3.如請求項1之半導體結構，其中該阻隔層係由聚醢亞胺 (Polyimide，PI)所製成。 4·如請求項1之半導體結構，其中該阻隔層係由氧化物所製成。 5·如凊求項1之半導體結構，其中該底層金屬係由鈦鎢合金所製 V, 成。 6· —種半導體結構之成形方法，包含下列步驟： 於已佈局一積體電路之基材上，成形實質上具有一非平坦 第一表面之一純化層(passivation layer); 成形具有一實質上平坦第二表面之阻隔層，以使該鈍化層 平坦化；以及 成形一底層金屬，於該阻隔層之第二表面上，以構成一電 鍍程序之一導電介面。 7·如請求項6之方法，其中於該構成導電介面之步驟後，更包含 200832542 下列步驟：電錢一凸塊於該底層金屬上，以成形一導電結構。
TW096102740A 2007-01-24 2007-01-24 Semiconductor structure and method for forming the same TW200832542A (en)

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US11/907,276 US20080174011A1 (en) 2007-01-24 2007-10-10 Semiconductor structure and method for forming the same

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KR100874588B1 (ko) * 2007-09-05 2008-12-16 성균관대학교산학협력단 전기적 특성 평가가 가능한 플립칩 및 이것의 제조 방법
USRE48422E1 (en) * 2007-09-05 2021-02-02 Research & Business Foundation Sungkyunkwan Univ. Method of making flip chip
US10217644B2 (en) * 2012-07-24 2019-02-26 Infineon Technologies Ag Production of adhesion structures in dielectric layers using photoprocess technology and devices incorporating adhesion structures

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EP0734059B1 (en) * 1995-03-24 2005-11-09 Shinko Electric Industries Co., Ltd. Chip sized semiconductor device and a process for making it
US5844317A (en) * 1995-12-21 1998-12-01 International Business Machines Corporation Consolidated chip design for wire bond and flip-chip package technologies
JP3523746B2 (ja) * 1996-03-14 2004-04-26 株式会社東芝 半導体記憶装置の製造方法
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